ISD9100 Series Datasheet
Publication Release Date: January 8, 2016
- 1 - Revision V1.41
ISD Cortex™-M0 ChipCorder
ISD9100 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of ISD ChipCorder microcontroller
based system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 2 - Revision V1.41
Table of Contents-
TABLE OF CONTENTS- ......................................................................................................................... 2
1 GENERAL DESCRIPTION ......................................................................................................... 3
2 FEATURES ................................................................................................................................. 4
3 PART INFORMATION AND PIN CONFIGURATION ................................................................. 7
3.1 Pin Configuration ............................................................................................................ 7
3.1.1 ISD9100 LQFP 48 pin ....................................................................................................... 7
3.1.2 ISD9100 QFN 33 pin ......................................................................................................... 8
3.1.3 Pin Description .................................................................................................................. 9
4 BLOCK DIAGRAM .................................................................................................................... 13
5 APPLICATION DIAGRAM ......................................................................................................... 14
6 ELECTRICAL CHARACTERISTICS ......................................................................................... 15
6.1 Absolute Maximum Ratings .......................................................................................... 15
6.2 DC Electrical Characteristics ........................................................................................ 16
6.3 AC Electrical Characteristics ........................................................................................ 20
6.3.1 External 32kHz XTAL Oscillator ...................................................................................... 20
6.3.2 Internal 49.152MHz Oscillator ......................................................................................... 20
6.3.3 Internal 16 kHz Oscillator ................................................................................................ 20
6.3.4 Reset Characteristics ...................................................................................................... 20
7 PACKAGE DIMENSIONS ......................................................................................................... 22
7.1.1 48L LQFP (7x7x1.4mm footprint 2.0mm) ........................................................................ 22
7.1.2 33-pin QFN (5x5 mm^2, Thickness 0.8mm ,Pitch 0.5 mm)................................................... 23
8 ORDERING INFORMATION ..................................................................................................... 24
9 REVISION HISTORY ................................................................................................................ 25
IMPORTANT NOTICE........................................................................................................................... 26
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 3 - Revision V1.41
1 GENERAL DESCRIPTION
The ISD9100 is a system-on-chip product optimized for low power, audio record and playback with an
embedded ARM® Cortex™-M0 32-bit microcontroller core.
The ISD9100 embeds a Cortex™-M0 core running up to 49 MHz with 68/100/145K-byte of non-volatile
flash memory and 12K-byte of embedded SRAM. It also comes equipped with a variety of peripheral
devices, such as Timers, Watchdog Timer (WDT), Real-time Clock (RTC), Peripheral Direct Memory
Access (PDMA), a variety of serial interfaces (UART, SPI/SSP, I2C, I2S), PWM modulators, GPIO,
Analog Comparator, Low Voltage Detector and Brown-out detector.
The ISD9100 comes equipped with a rich set of power saving modes including a Deep Power Down
(DPD) mode drawing less than 1A. A micro-power 16KHz oscillator can periodically wake up the
device from deep power down to check for other events. A Standby Power Down (SPD) mode can
maintain a real time clock function at less than 10A.
For audio functionality the ISD9100 includes a Sigma-Delta ADC with 92dB SNR performance coupled
with a Programmable Gain Amplifier (PGA) capable of a maximum gain of 61dB to enable direct
connection of a microphone. Audio output is provided by a Differential Class D amplifier (DPWM) that
can deliver 1W
1
of power to an 8Ω speaker.
The ISD9100 provides eight analog enabled general purpose IO pins (GPIO). These pins can be
configured to connect to an analog comparator, can be configured as analog current sources or can
be routed to the SDADC for analog conversion. They can also be used as a relaxation oscillator to
perform capacitive touch sensing.
1
We suggest implementing thermal protection by utilizing the Temperature Alarm; for details please
refer to Temperature Alarm in Design Guide.
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 4 - Revision V1.41
2 FEATURES
Core
– ARM® Cortex™-M0 core runs up to 49MHz.
– One 24-bit System tick timer for operating system support.
– Supports a variety of low power sleep and power down modes.
– Single-cycle 32-bit hardware multiplier.
– NVIC (Nested Vector Interrupt Controller) for 32 interrupt inputs, each with 4-levels of priority.
– Serial Wire Debug (SWD) support with 2 watchpoints/4 breakpoints.
Power Management
– Wide operating voltage range from 2.4V to 5.5V.
– Power management Unit (PMU) providing four levels of power control.
– Deep Power Down (DPD) mode with sub micro-amp leakage (<1µA).
– Wakeup from Deep Power Down via dedicated WAKEUP pin or timed operation from internal
low power 16kHz oscillator.
– Standby mode with limited RAM retention and RTC operation (<10µA).
– Wakeup from Standby can be from any GPIO interrupt, RTC or BOD.
– Sleep mode with minimal dynamic power consumption.
– 3V LDO for operation of external 3V devices such as serial flash.
Flash EPROM Memory
– 68/100/145K bytes Flash EPROM for program code and data storage.
– 4KB of flash can be configured as boot sector for ISP loader.
– Support In-system program (ISP) and In-circuit program (ICP) application code update
– 1K byte page erase for flash
– Configurable boundary to delineate code and data flash.
– Support 2 wire In-circuit Programming (ICP) update from SWD ICE interface
SRAM Memory
– 12K bytes embedded SRAM.
Clock Control
– One high speed and two low speed oscillators providing flexible selection for different
applications. No external components necessary.
– Built-in trimmable oscillator with range of 16-49MHz. Factory trimmed within 1% to settings of
49.152MHz and 32.768MHz. User trimmable with in-built frequency measurement block
(OSCFM) using reference clock of 32kHz crystal or external reference source.
– Ultra-low power (<1uA) 16kHz oscillator for watchdog and wakeup from power-down or sleep
operation.
– External 32kHz crystal input for RTC function and low power system operation.
GPIO
– Four I/O modes:
Quasi bi-direction
Push-Pull output
Open-Drain output
Input only with high impendence
– TTL/Schmitt trigger input selectable.
– I/O pin can be configured as interrupt source with edge/level setting.
– Switchable pull-up.
Audio Analog to Digital converter
– Sigma Delta ADC with configurable decimation filter and 16 bit output.
– 92dB Signal-to-Noise (SNR) performance.
– Programmable gain amplifier with 32 steps from -12 to 35.25dB in 0.75dB steps.
– Boost gain stage of 26dB, giving maximum total gain of 61dB.
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 5 - Revision V1.41
– Input selectable from dedicated MIC pins or analog enabled GPIO.
– Programmable biquad filter to support multiple sample rates from 8-32kHz.
– DMA support for minimal CPU intervention.
Differential Audio PWM Output (DPWM)
– Direct connection of speaker
– 1W drive capability into 8Ω load.
– High efficiency 88%
– Configurable up-sampling to support sample rates from 8-32kHz.
– DMA support for minimal CPU intervention.
Timers
– Two timers with 8-bit pre-scaler and 24-bit resolution.
– Counter auto reload.
Watch Dog Timer
– Default ON/OFF by configuration setting
– Multiple clock sources
– 8 selectable time out period from micro seconds to seconds (depending on clock source)
– WDT can wake up power down/sleep.
– Interrupt or reset selectable on watchdog time-out.
RTC
– Real Time Clock counter (second, minute, hour) and calendar counter (day, month, year)
– Alarm registers (second, minute, hour, day, month, year)
– Selectable 12-hour or 24-hour mode
– Automatic leap year recognition
– Time tick and alarm interrupts.
– Device wake up function.
– Supports software compensation of crystal frequency by compensation register (FCR)
PWM/Capture
– Built-in up to two 16-bit PWM generators provide two PWM outputs or one complementary
paired PWM outputs.
– The PWM generator equipped with a clock source selector, a clock divider, an 8-bit pre-scaler
and Dead-Zone generator for complementary paired PWM.
– PWM interrupt synchronous to PWM period.
– 16-bit digital Capture timers (shared with PWM timers) provide rising/falling capture inputs.
– Support Capture interrupt
UART
– UART ports with flow control (TX, RX, CTS and RTS)
– 8-byte FIFO.
– Support IrDA (SIR) and LIN function
– Programmable baud-rate generator up to 1/16 of system clock.
SPI
– Master up to 20 Mbps / Slave up to 10 Mbps.
– Support MICROWIRE/SPI master/slave mode (SSP)
– Full duplex synchronous serial data transfer
– Variable length of transfer data from 1 to 32 bits
– MSB or LSB first data transfer
– 2 slave/device select lines when used in master mode.
– Hardware CRC calculation module available for CRC calculation of data stream.
– DMA support for burst transfers.
I2C
– Master/Slave up to 1Mbit/s
– Bidirectional data transfer between masters and slaves
– Multi-master bus (no central master).
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 6 - Revision V1.41
– Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
– Serial clock synchronization allows devices with different bit rates to communicate via one
serial bus.
– Serial clock synchronization can be used as a handshake mechanism to suspend and resume
serial transfer.
– Programmable clock allowing versatile rate control.
– I2C-bus controller supports multiple address recognition.
I2S
– Interface with external audio CODEC.
– Operate as either master or slave.
– Capable of handling 8, 16, 24 and 32 bit word sizes
– Mono and stereo audio data supported
– I2S and MSB justified data format supported
– Two 8 word FIFO data buffers are provided, one for transmit and one for receive
– Generates interrupt requests when buffer levels cross a programmable boundary
– Supports DMA requests, for transmit and receive
Brown-out detector
– With 8 levels: 2.1V, 2.2V, 2.4V, 2.5V, 2.625V, 2.8V, 3.0V, and 4.6V
– Supports time-multiplex operation to minimize power consumption.
– Supports Brownout Interrupt and Reset option
Built in Low Dropout Voltage Regulator (LDO)
– Capable of delivering 30mA load current.
– Configurable for output voltage of 1.8V, 2.4V, 3.0V and 3.3V
– Eight GPIO (GPIOA<7:0>) operate from LDO voltage domain allowing direct interface to, for
example, 3V SPI Flash.
– Can be bypassed and voltage domain supplied directly from system power.
Additional Features
– Over temperature alarm. Can generate interrupt if device exceeds safe operating temperature.
– Temperature proportional voltage source which can be routed to ADC for temperature
measurements.
– Digital Microphone interface.
Operating Temperature: -40C~85C
Package:
– All Green package (RoHS)
LQFP 48-pin
QFN 33-pin
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 7 - Revision V1.41
3 PART INFORMATION AND PIN CONFIGURATION
3.1 Pin Configuration
3.1.1 ISD9100 LQFP 48 pin
LQFP 48-pin
38
37
40
39
42
41
44
43
46
45
47
48
32
36
30
29
28
27
26
25
34
35
31
33
20
21
18
19
16
17
14
15
13
22
23
24
1
2
3
4
6
7
8
9
10
5
11
12
VCCLDO
PA.14/TM0/SDCLK/SDCLKn
PA.4/I2S_FS
PA.6/I2S_SDI
PA.3/SPI_MISO0/I2C_SDA
VSSD
PA.5/I2S_BCLK
PA.7/I2S_SDO
PA.1/SPI_SCLK/I2C_SCL
PA.2/SPI_SSB0
PA.0/SPI_MOSI0/MCLK
VDD33
I2C_SCL/CMP2/SPI_SCLK/PB.2
VCCD
NC
VREG
SPI_SSB1/CMP0/SPI_SSB0/PB.0
MCLK/CMP1/SPI_SSB1/PB.1
I2C_SDA/CMP3/SPI_MISO0/PB.3
PWM0B/CMP4SPI_MOSI0/PB.4
I2S_SDI/CMP6/SPI_MOSI1/PB.6
PWM1B/CMP5/SPI_MISO1/PB.5
WAKEUP
I2S_SDO/CMP7/PB.7
PA.8/UART_TX/I2S_FS
SPK+
VCCSPK
VSSSPK
RESETN
SPK-
VCCSPK
PA.9/UART_RX/I2S_BCLK
PA.15/TM1/SDIN
NC
ICE_DAT
ICE_CLK
MIC+
I2C_SCL/I2S_SDO/UART_CTSn/PA.11
XO32K
XI32K
VSSA
VMID
I2C_SDA/I2S_SDI/UART_RTSn/PA.10
PWM0/SPKP/I2S_FS/PA.12
MIC-
MICBIAS
VCCA
PWM1/SPKM/I2S_BCLK//PA.13
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 8 - Revision V1.41
3.1.2 ISD9100 QFN 33 pin
PB.4
PB.5
PA.8
I9160YI
PB.3
PB.2
PA.9
VREG
VCCSPK
SPK+
VSSSPK
SPK-
VCCSPK
VDD33
PA.3
MIC+
XO32K
XI32K
VCCLDO
VMID
PA.11
VCCA
MICBIAS
PA.0
PA.1
PA.2
WAKEUP
VCCD
PA.10
MIC-
RESETN
ICE_DAT
ICE_CLK
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25
QFN-33 Pin
33 VSS
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 9 - Revision V1.41
3.1.3 Pin Description
The ISD9100 is a low pin count device where many pins are configurable to alternative functions. All
General Purpose Input/Output (GPIO) pins can be configured to alternate functions as described in
the table below.
Pin No.
Pin Name
Pin Type
Description
LQFP
48
QFN
33
1
2
WAKEUP
I
Pull low to wake part from deep power down
2
-
PB.7
A/I/O
General purpose input/output pin, analog capable; Port B, bit 7
I2S_SDO
O
Serial Data Output for I2S interface
CMP7
AIO
Configure as relaxation oscillator for capacitive touch sensing
3
-
PB.6
A/I/O
General purpose input/output pin, analog capable; Port B, bit 6
I2S_SDI
I
Serial Data Input for I2S interface
CMP6
AIO
Configure as relaxation oscillator for capacitive touch sensing
SPI_MOSI1
O
Master Out, Slave In channel 1 for SPI interface
4
3
PB.5
A/I/O
General purpose input/output pin, analog capable; Port B, bit 5
PWM1B
O
PWM channel 1 complementary output pin
CMP5
AIO
Configure as relaxation oscillator for capacitive touch sensing
SPI_MISO1
I
Master In, Slave Out channel 1 for SPI interface
5
4
PB.4
A/I/O
General purpose input/output pin, analog capable; Port B, bit 4
PWM0B
O
PWM channel 0 complementary output pin
CMP4
AIO
Configure as relaxation oscillator for capacitive touch sensing
SPI_MOSI0
O
Master Out, Slave In channel 0 for SPI interface
6
5
PB.3
A/I/O
General purpose input/output pin, analog capable; Port B, bit 3
I2C_SDA
I/O
Serial Data, I2C interface
CMP3
AIO
Configure as relaxation oscillator for capacitive touch sensing
SPI_MISO0
I
Master In, Slave Out channel 0 for SPI interface
7
6
PB.2
A/I/O
General purpose input/output pin, analog capable; Port B, bit 2
I2C_SCL
I/O
Serial Clock, I2C interface
CMP2
AIO
Configure as relaxation oscillator for capacitive touch sensing
SPI_SCLK
I/O
Serial Clock for SPI interface
8
-
PB.1
A/I/O
General purpose input/output pin, analog capable; Port B, bit
1. Triggers external interrupt 1 (EINT1/IRQ3)
MCLK
O
Master clock output for synchronizing external device
CMP1
AIO
Configure as relaxation oscillator for capacitive touch sensing
SPI_SSB1
O
Slave Select Bar 1 for SPI interface
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 10 - Revision V1.41
Pin No.
Pin Name
Pin Type
Description
LQFP
48
QFN
33
9
-
PB.0
A/I/O
General purpose input/output pin, analog capable; Port B, bit
0. Triggers external interrupt 0 (EINT0/IRQ2)
SPI_SSB1
O
Slave Select Bar 1 for SPI interface
CMP0
AIO
Configure as relaxation oscillator for capacitive touch sensing
SPI_SSB0
I/O
Slave Select Bar 0 for SPI interface
10
7
VCCD
P
Main Digital Supply for Chip. Supplies all IO except analog,
Speaker Driver and PA<7:0>
11
8
VREG
P
Logic regulator output decoupling pin. A 1µF capacitor
returning to VSSD must be placed on this pin.
12
-
NC
Should remain unconnected.
13
-
NC
Should remain unconnected.
14
-
PA.15
I/O
General purpose input/output pin; Port A, bit 15
TM1
I
External input to Timer 1
SDIN
I
Sigma Delta bit stream input for digital MIC mode
15
9
PA.9
I/O
General purpose input/output pin; Port A, bit 9
UART_RX
I
Receive channel of UART
I2S_BCLK
I/O
Bit Clock for I2S interface
16
10
PA.8
I/O
General purpose input/output pin; Port A, bit 8
UART_TX
O
Transmit channel of UART
I2S_FS
I/O
Frame Sync Clock for I2S interface
17
11
VCCSPK
P
Power Supply for PWM Speaker Driver
18
12
SPK+
O
Positive Speaker Driver Output
19
13
VSSSPK
P
Ground for PWM Speaker Driver
20
14
SPK-
O
Negative Speaker Driver Output
21
15
VCCSPK
P
Power Supply for PWM Speaker Driver
22
16
RESETN
I
External reset input. Pull this pin low to reset device to initial
state. Has internal weak pull-up.
23
17
ICE_DAT
I/O
Serial Wire Debug port data pin. Has internal weak pull-up.
24
18
ICE_CLK
I
Serial Wire Debug port clock pin. Has internal weak pull-up.
25
-
VSSD
P
Digital Ground.
26
-
PA.7
I/O
General purpose input/output pin; Port A, bit 7
I2S_SDO
O
Serial Data Out for I2S interface
27
-
PA.6
I/O
General purpose input/output pin; Port A, bit 6
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 11 - Revision V1.41
Pin No.
Pin Name
Pin Type
Description
LQFP
48
QFN
33
I2S_SDI
I
Serial Data In for I2S interface
28
-
PA.5
I/O
General purpose input/output pin; Port A, bit 5
I2S_BCLK
I/O
Bit Clock for I2S interface
29
-
PA.4
I/O
General purpose input/output pin; Port A, bit 4
I2S_FS
I/O
Frame Sync Clock for I2S interface
30
19
PA.3
I/O
General purpose input/output pin; Port A, bit 3
SPI_MISO0
I
Master In, Slave Out channel 0 for SPI interface
I2C_SDA
I/O
Serial Data, I2C interface
31
20
PA.2
I/O
General purpose input/output pin; Port A, bit 2
SPI_SSB0
I/O
Slave Select Bar 0 for SPI interface
32
21
VDD33
P
LDO Regulator Output. If used, a 1µF capacitor must be
placed to ground. If not used then tie to VCCD.
33
22
PA.1
I/O
General purpose input/output pin; Port A, bit 1
SPI_SCLK
I/O
Serial Clock for SPI interface
I2C_SCL
I/O
Serial Clock, I2C interface
34
23
PA.0
I/O
General purpose input/output pin; Port A, bit 2
SPI_MOSI0
O
Master Out, Slave In channel 0 for SPI interface
MCLK
O
Master clock output.
35
24
VCCLDO
P
Power Supply for LDO, should be connected to VCCD
36
-
PA.14
I/O
General purpose input/output pin; Port A, bit 14
SDCLK
O
Clock output for digital microphone mode.
SDCLKn
O
Inverse Clock output for digital microphone mode.
37
-
PA.13
I/O
General purpose input/output pin; Port A, bit 13
PWM1
O
PWM1 Output.
SPKM
O
Equivalent to SPK-.
I2S_BCLK
I/O
Bit Clock for I2S interface
38
-
PA.12
I/O
General purpose input/output pin; Port A, bit 12
PWM0
O
PWM0 Output.
SPKP
O
Equivalent to SPK+
I2S_FS
I/O
Frame Sync Clock for I2S interface
39
25
XO32K
O
32.768kHz Crystal Oscillator Output
40
26
XI32K
I
32.768kHz Crystal Oscillator Input. Max Voltage 1.8V
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 12 - Revision V1.41
Pin No.
Pin Name
Pin Type
Description
LQFP
48
QFN
33
41
VSSA
AP
Ground for analog circuitry.
42
27
VMID
O
Mid rail reference. Connect 4.7µF to VSSA.
43
28
MIC+
AI
Positive microphone input.
44
29
MIC-
AI
Negative microphone input.
45
30
MICBIAS
AO
Microphone bias output.
46
31
VCCA
AP
Analog power supply.
47
32
PA.11
I/O
General purpose input/output pin; Port A, bit 11
I2C_SCL
I/O
Serial Clock, I2C interface
I2S_SDO
O
Serial Data Out I2S interface
UART_CTSn
I
UART Clear to Send Input.
48
-
PA.10
I/O
General purpose input/output pin; Port A, bit 10
I2C_SDA
I/O
Serial Data, I2C interface
I2S_SDI
I
Serial Data In I2S interface
UART_RTSn
O
UART Request to Send Output.
-
33
VSS
P
Ground for both digital and analog. Center pad underneath.
Note:
Pin Type I=Digital Input, O=Digital Output; AI=Analog Input; P=Power Pin; AP=Analog Power
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 13 - Revision V1.41
4 BLOCK DIAGRAM
AHB Lite
Cortex M0 RAM
12KB
Embedded
Flash
145KB
AHB to APB bridge
Flash Mem ControllerI2C
PWM Speaker Driver
SPI
Timers/PWM
Debug interface
System Control/PMU
GPIO
CLK CTRL 50MHz Internal Osc.
32kHz RTC Osc
Audio ADC
UART
WDT
I2S
LDO 3.0V
LDO 1.8V
BOD
PDMA
POR
10kHz low power
Osc
Peripherals with PDMA
Figure 4-1 ISD9100 Block Diagram
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 14 - Revision V1.41
5 APPLICATION DIAGRAM
MIC+
MIC-
VSSD
VCCD
VCCD
0.1
uF
47
uF
VCCD
17
21
19
VSSSPK
VCCSPK
VCCSPK
43
44
: Digital ground; : Analog ground;
4.7uF
2.2 K
0.1uF
2.2 K
0.1uF
MIC
SPK+
SPK-
18
20
46
VSSA
VCCA 0.1
uF
47
uF
VCCA
41
CSB
DO
WPB
GND
VCC
HOLDB
CLK
DIO
W25Q
PA.3/SPI_MISO0
PA.2/SPI_SSB0
PA.1/SPI_SCLK
PA.0/SPI_MOSI0
30
31
33
34
10
25
0.1
uF
47
uF
ISD9160
LQFP48 XI32K
XO32K 39
40
20pF 20pF
32.768K
45 MICBIAS
4.7uF
VMID
42
VREG 11
1uF
32 VDD33
35 VCCLDO
1uF
0.1uF
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 15 - Revision V1.41
6 ELECTRICAL CHARACTERISTICS
6.1 Absolute Maximum Ratings
SYMBOL
PARAMETER
MIN
MAX
UNIT
DC Power Supply
VDDVSS
-0.3
+6.0
V
Input Voltage
VIN
VSS-0.3
VDD+0.3
V
Oscillator Frequency
1/tCLCL
0
40
MHz
Operating Temperature
TA
-40
+85
C
Storage Temperature
TST
-55
+150
C
Maximum Current into VDD
-
120
mA
Maximum Current out of VSS
120
mA
Maximum Current sunk by a
I/O pin
35
mA
Maximum Current sourced by
a I/O pin
35
mA
Maximum Current sunk by
total I/O pins
100
mA
Maximum Current sourced by
total I/O pins
100
mA
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the
device.
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 16 - Revision V1.41
6.2 DC Electrical Characteristics
(VDD-VSS=3.3V, TA = 25C, FOSC = 49.152 MHz unless otherwise specified.)
PARAMETER
SYM.
SPECIFICATION
TEST CONDITIONS
MIN.
TYP.
MAX.
UNI
T
Operation voltage
VDD
2.4
5.5
V
VDD =2.4V ~ 5.5V up to 49 MHz
Power Ground
VSS
AVSS
-0.3
V
Analog Operating Voltage
AVDD
0
VDD
V
Analog Reference Voltage
Vref
0
AVDD
V
Operating Current
Normal Run Mode
@ 49.152 MHz
IDD1
24.8
mA
VDD= 5.5V,
Enable all IP.
IDD2
19.7
mA
VDD=5.5V,
disable all IP
IDD3
23.6
mA
VDD = 3V,
enable all IP
IDD4
18.3
mA
VDD = 3V,
disable all IP
Operating Current
Normal Run Mode
@ 32.768Mhz
IDD5
18.8
mA
VDD = 5.5V,
Enable all IP.
IDD6
15.0
mA
VDD = 5.5V,
Disable all IP.
IDD7
17.6
mA
VDD = 3V,
Enable all IP.
IDD8
13.8
mA
VDD = 3V,
Disable all IP.
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 17 - Revision V1.41
Operating Current
Normal Run Mode
@ 12.288MHz
IDD9
12.5
mA
VDD = 5.5V
enable all IP
IDD10
10.3
mA
VDD = 5.5V,
disable all IP
IDD11
11.4
mA
VDD = 3V
enable all IP
IDD12
9
mA
VDD = 3V,
disable all
Operating Current
Normal Run Mode
@ 4.9152Mhz
IDD13
9.7
mA
VDD = 5.5V,
Enable all IP.
IDD14
8.1
mA
VDD = 5.5V,
Disable all IP.
IDD15
8.7
mA
VDD = 3V,
Enable all IP.
IDD16
7.0
mA
VDD = 3V,
Disable all IP.
Operating Current
Sleep Mode
IIDLE1
10
mA
VDD= 5.5V
IIDLE1
9
mA
VDD= 3.3V
Operating Current
Deep Sleep Mode
IIDLE1
10
mA
VDD=5.5V
IIDLE1
8
mA
VDD= 3.3V
Standby Power down
mode(SPD)
IIDLE1
3
uA
VDD=3.3V 32K running with RTC
IIDLE1
1
uA
VDD= 3.3V 16K running
Operating Current
Deep Power down mode(DPD)
IIDLE1
500
nA
VDD=3.3V Wakeup with16K
IIDLE1
nA
VDD= 3.3V wakeup with wakeup pin
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 18 - Revision V1.41
Input Current PA, PB
(Quasi-bidirectional mode)
IIN1
-60
-
+15
A
VDD = 5.5V, VIN = 0V or VIN=VDD
Input Current at /RESET [1]
IIN2
-55
-45
-30
A
VDD = 3.3V, VIN = 0.45V
Input Leakage Current PA, PB
ILK
-2
-
+2
A
VDD = 5.5V, 0<VIN<VDD
Logic 1 to 0 Transition Current
PA~PB (Quasi-bidirectional
mode)
ITL [3]
-650
-
-200
A
VDD = 5.5V, VIN<2.0V
Input Low Voltage PA, PB (TTL
input)
VIL1
-0.3
-
0.8
V
VDD = 4.5V
-0.3
-
0.6
VDD = 2.5V
Input High Voltage PA, PB (TTL
input)
VIH1
2.0
-
VDD
+0.2
V
VDD = 5.5V
1.5
-
VDD
+0.2
VDD =3.0V
Input Low Voltage XT1[*2]
VIL3
0
-
0.8
V
VDD = 4.5V
0
-
0.4
VDD = 3.0V
Input High Voltage XT1[*2]
VIH3
3.5
-
VDD
+0.2
V
VDD = 5.5V
2.4
-
VDD
+0.2
VDD = 3.0V
Input Low Voltage X32I[*2]
VIL4
0
-
0.4
V
Input High Voltage X32I[*2]
VIH4
1.7
2.5
V
Negative going threshold
(Schmitt input), /REST
VILS
-0.5
-
0.3VDD
V
Positive going threshold
(Schmitt input), /REST
VIHS
0.7VDD
-
VDD+0.
5
V
Hysteresis voltage of
PA~PB(Schmitt input)
VHY
0.2VDD
V
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 19 - Revision V1.41
Source Current PA, PB
Quasi-bidirectional Mode)
ISR11
-300
-370
-450
A
VDD = 4.5V, VS = 2.4V
ISR12
-50
-70
-90
A
VDD = 2.7V, VS = 2.2V
ISR12
-40
-60
-80
A
VDD = 2.5V, VS = 2.0V
Source Current PA, PB (Push-
pull Mode)
ISR21
-20
-24
-28
mA
VDD = 4.5V, VS = 2.4V
ISR22
-4
-6
-8
mA
VDD = 2.7V, VS = 2.2V
ISR22
-3
-5
-7
mA
VDD = 2.5V, VS = 2.0V
Sink Current PA, PB
(Quasi-bidirectional and Push-
pull Mode)
ISK1
10
16
20
mA
VDD = 4.5V, VS = 0.45V
ISK1
7
10
13
mA
VDD = 2.7V, VS = 0.45V
ISK1
6
9
12
mA
VDD = 2.5V, VS = 0.45V
Brownout voltage with
BOV_VL [2:0] =000b
VBO2.1
2.15
V
Brownout voltage with
BOV_VL [2:0] =001b
VBO2.2
2.25
V
Brownout voltage with
BOV_VL [2:0] =010b
VBO2.4
2.45
V
Brownout voltage with
BOV_VL [2:0] =011b
VBO2.5
2.55
V
Brownout voltage with
BOV_VL [2:0] =100b
VBO2.7
2.7
V
Brownout voltage with
BOV_VL [2:0] =101b
VBO2.8
2.8
V
Brownout voltage with
BOV_VL [2:0] =110b
VBO3.0
3.0
V
Brownout voltage with
BOV_VL [2:0] =111b
VBO4.5
4.55
V
Notes:
1. /REST pin is a Schmitt trigger input.
2. Crystal Input is a CMOS input.
3. Pins of P0, P1, P2, P3 and P4 can source a transition current when they are being externally driven from 1 to 0. In the condition of
VDD=5.5V, 5he transition current reaches its maximum value when Vin approximates to 2V.
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 20 - Revision V1.41
6.3 AC Electrical Characteristics
6.3.1 External 32kHz XTAL Oscillator
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
Input clock frequency
External crystal
-
32.768
-
kHz
Temperature
-
-40
-
85
℃
VDD
-
2.4
-
5.5
V
6.3.2 Internal 49.152MHz Oscillator
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
Supply voltage[1]
-
2.4
-
5.5
V
Center Frequency
-
-
49.152
MHz
Calibrated Internal Oscillator
Frequency
+25C; VDD =5V
-1
-
1
%
-40C~+85C;
VDD=2.5V~5.5V
-4
-
4
%
6.3.3 Internal 16 kHz Oscillator
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
Supply voltage
-
2.4
-
5.5
V
Center Frequency
-
-
10
-
kHz
Calibrated Internal Oscillator
Frequency
+25C; VDD =5V
-10
-
10
%
-40C~+85C;
VDD=2.5V~5.5V
-20
-
20
%
Notes:
*1. Internal operation voltage comes from LDO.
6.3.4 Reset Characteristics
(VDD-VSS=5V, TA = 25C, FOSC = 49.152 MHz unless otherwise specified.)
Parameter
No.
Parameter
Parameter Name
Min
Typ
Max
Unit
R1
VTH
Reset threshold
1
1.7
2
V
R2
TVDDRISE
Supply voltage (VDD) rise time (0V-5V),
power on reset
-
-
100
ms
R3
TPOR
Power-On Reset timeout
-
-
12
µs
R4
TIRPOR
Internal reset timeout after POR
-
-
45
µs
R5
TMIN
Minimum RESETN pulse width
100
-
-
ns
R6
TIRHWR
Internal reset timeout after hardware reset
(RESETN pin)
-
-
20
µs
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 21 - Revision V1.41
R7
TIRSWR
Internal reset timeout after software-initiated
system reset
-
-
2
µs
R8
TIRWDR
Internal reset timeout after watchdog reset
-
-
3 *2
µs
*Notes:
2. It will be 6500us when use OSC_10K as the WDG clock.
6.3.4.1 Power-On Reset Timing
R3
R4
R1
VCCD
POR
(Internal)
Reset
(Internal)
R2
6.3.4.2 External Reset Timing (RESETN)
Reset
(Internal)
RESETN
R5 R6
6.3.4.3 Software Reset Timing
Reset
(Internal)
SW Reset
R7
6.3.4.4 Watchdog Reset Timing
Reset
(Internal)
WDOG Reset
(Internal)
R8
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 22 - Revision V1.41
7 PACKAGE DIMENSIONS
7.1.1 48L LQFP (7x7x1.4mm footprint 2.0mm)
112
48
H
H
Controlling dimension : Millimeters
0.10
070
0.004
1.00
0.75
0.600.45
0.039
0.030
0.024
0.018
9.109.00
8.90
0.358
0.354
0.350
0.50
0.20
0.25
1.45
1.40
0.10
0.15
1.35
0.008
0.010
0.0570.055
0.026
7.10
7.00
6.90
0.280
0.276
0.272
0.004
0.006
0.053
Symbol Min Nom Max Max
Nom
Min
Dimension in inch Dimension in mm
A
b
c
D
e
HD
HE
L
Y
0
A
A
L1
1
2
E
0.008
0.006 0.15
0.20
7
0.020 0.35 0.65
0.100.050.002 0.004 0.006 0.15
9.109.00
8.90
0.358
0.354
0.350
7.10
7.00
6.90
0.280
0.276
0.272
0.014
37
36 25
24
13
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 23 - Revision V1.41
7.1.2 33-pin QFN
5x5 mm2, Thickness 0.8mm (MAX), Pitch 0.5 mm (SAW Type), EP SIZE 3.5X3.5 mm
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 24 - Revision V1.41
8 ORDERING INFORMATION
ISD Audio Product Family
Product Series
91: Cortex-M0
Flash ROM
0: 12KB
3: 68KB
4: 100KB
6: 145KB
SRAM SW Feature
Temperature
I: -40°C ~ +85°C
Package
Blank: Standard
C: Voice Recognition
I 9 1 x x x x I
F: LQFP-48
Y: QFN-33
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 25 - Revision V1.41
9 REVISION HISTORY
VERSION
DATE
PAGE/
CHAP.
DESCRIPTION
V0.1
May 25, 2011
-
First Release.
V1.01
Sep 6, 2011
-
Add better description of EINT0/1 and PB0/1 interrupts.
Unify the naming of capacitive touch sensing.
V1.10
Sep 30, 2011
-
Revise the level value of Brown-out detector in Feature.
Correct the maximum voltage of DC Power Supply in section
6.1 Absolute Maximum Ratings
V1.22
Nov 17, 2011
-
Update DC spec.
Add ordering information.
V1.23
Sep 10, 2012
Remove “Preliminary”
Change internal oscillation 10K to 16K
Change minimum voltage (to 2.4V) in chapter 9 Electrical
Characteristics
V1.24
July 17,2013
Change SNR to 92dB
Add RESET low specification in DC characteristic.
V1.25
July 31, 2013
Update RESET timing spec.
V1.30
Oct 24, 2014
Add ISD9130 and ISD9140 into the ISD9100 series.
V1.40
July 20, 2015
Add QFN-33 pin package.
V1.41
Jan 8, 2016
Fix ordering info, QFN-33 pin dimension data.
ISD9100 Series Datasheet
Release Date: January 8, 2016
- 26 - Revision V1.41
Important Notice
Nuvoton products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Furthermore, Nuvoton products are not intended for applications wherein failure of
Nuvoton products could result or lead to a situation where personal injury, death or severe
property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper
use or sales.
Please note that all data and specifications are subject to change without notice. All the
trademarks of products and companies mentioned in this datasheet belong to their respective
owners.