Atmel-0299J-PEEPROM-AT28BV64B-Datasheet_072013
Features
•Single 2.7V to 3.6V Supply
•Hardware and Software Data Protection
•Low Power Dissipation
– 15 mA Active Current
– 20µA CMOS Standby Current
•Fast Read Access Time – 200 ns
•Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
•Fast Write Cycle Times
– Page Write Cycle Time: 10 ms Maximum
– 1 to 64 Byte Page Write Operation
•DATA Polling for End of Write Detection
•High-reliability CMOS Technology
– Endurance: 100,000 Cycles
– Data Retention: 10 Years
•JEDEC Approved Byte-wide Pinout
•Industrial Temperature Ranges
•Green (Pb/Halide-free) Packaging Only
1. Description
The AT28BV64B is a high-performance electrically erasable programmable read only-
memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manu-
factured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 200 ns with power dissipation of just 54 mW. When the device is
deselected, the CMOS standby current is less than 20µA.
The AT28BV64B is accessed like a static RAM for the read or write cycle without the
need for external components. The device contains a 64 byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to
64 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.
Atmel’s AT28BV64B has additional features to ensure high quality and manufactur-
ability. A software data protection mechanism guards against inadvertent writes. The
device also includes an extra 64 bytes of EEPROM for device identification or
tracking.
64K (8K x 8)
Battery-Voltage
Parallel
EEPROM
with Page Write
and Software
Data Protection
AT28BV64B
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AT28BV64B
2. Pin Configurations
2.1 28-lead SOIC Top View
Pin Name Function
A0 - A12 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
2.2 32-lead PLCC Top View
Note: PLCC package pins 1 and 17 are Don’t Connect.
2.3 28-lead TSOP Top View
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
4
3
2
1
32
31
30
14
15
16
17
18
19
20
I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5
A7
A12
NC
DC
VCC
WE
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
A11
A9
A8
NC
WE
VCC
NC
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
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AT28BV64B
3. Block Diagram
4. Device Operation
4.1 Read
The AT28BV64B is accessed like a static RAM. When CEandOE are low and WEishigh,the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CEorOE is high. This dual-line
control gives designers flexibility in preventing bus contention in their systems.
4.2 Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write
cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Once a byte write has been started, it will automati-
cally time itself to completion. Once a programming operation has been initiated and for the
duration of tWC, a read operation will effectively be a polling operation.
4.3 Page Write
The page write operation of the AT28BV64B allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 63 additional
bytes. Each successive byte must be written within 100µs (tBLC) of the previous byte. If the tBLC
limit is exceeded, the AT28BV64B will cease accepting data and commence the internal pro-
gramming operation. All bytes during a page write operation must reside on the same page as
defined by the state of the A6 to A12 inputs. For each WE high to low transition during the page
write operation, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be
loaded in any order and may be altered within the same load period. Only bytes which are spec-
ified for writing will be written; unnecessary cycling of other bytes within the page does not occur.
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AT28BV64B
4.4 DATA Polling
The AT28BV64B features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O7. Once the write cycle has been completed, true data is valid
on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the
write cycle.
4.5 Toggle Bit
In addition to DATA Polling, the AT28BV64B provides another method for determining the end of
a write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-
gling and valid data will be read. Reading the toggle bit may begin at any time during the write
cycle.
4.6 Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel®has incorporated both hardware and software features that will protect the
memory against inadvertent writes.
4.6.1 Hardware Protection
Hardware features protect against inadvertent writes to the AT28BV64B in the following ways:
(a) VCC power-on delay – once VCC has reached 1.8V (typical) the device will automatically time
out 10 ms (typical) before allowing a write; (b) write inhibit–holding any one of OE low, CE high
or WE high inhibits write cycles; and (c) noise filter–pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a write cycle.
4.6.2 Software Data Protection
A software-controlled data protection feature has been implemented on the AT28BV64B. Soft-
ware data protection (SDP) helps prevent inadvertent writes from corrupting the data in the
device. SDP can prevent inadvertent writes during power-up and power-down as well as any
other potential periods of system instability.
The AT28BV64B can only be written using the software data protection feature. A series of three
write commands to specific addresses with specific data must be presented to the device before
writing in the byte or page mode. The same three write commands must begin each write opera-
tion. All software write commands must obey the page mode write timing specifications. The
data in the 3-byte command sequence is not written to the device; the addresses in the com-
mand sequence can be utilized just like any other location in the device.
Any attempt to write to the device without the 3-byte sequence will start the internal write timers.
No data will be written to the device; however, for the duration of tWC, read operations will effec-
tively be polling operations.
4.7 Device Identification
An extra 64 bytes of EEPROM memory are available to the user for device identification. By rais-
ing A9 to 12V ± 0.5V and using address locations 0000H to 003FH, the additional bytes may be
written to or read from in the same manner as the regular memory array.
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AT28BV64B
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH= 12.0V ± 0.5V.
5. DC and AC Operating Range
AT28BV64B-20
Operating Temperature (Case) -40C-85C
VCC Power Supply 2.7V to 3.6V
6. Operating Modes
Mode CE OE WE I/O
Read VIL VIL VIH DOUT
Write(2) VIL VIH VIL DIN
Standby/Write Inhibit VIH X(1) XHighZ
Write Inhibit X X VIH
Write Inhibit X VIL X
Output Disable X VIH XHighZ
Chip Erase VIL VH(3) VIL High Z
7. Absolute Maximum Ratings*
Temperature Under Bias ............................... -55C to +125C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Storage Temperature..................................... -65C to +150C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
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AT28BV64B
10. AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC -t
CE after the address transition without impact on tACC.
2. OE may be delayed up to tCE -t
OE after the falling edge of CE without impact on tCE or by tACC -t
OE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL= 5 pF).
4. This parameter is characterized and is not 100% tested.
8. DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN =0VtoV
CC +1V 10 µA
ILO Output Leakage Current VI/O =0VtoV
CC 10 µA
ISB VCC Standby Current CMOS CE = VCC -0.3VtoV
CC +1V 50 µA
ICC VCC Active Current f = 5 MHz; IOUT =0mA 15 mA
VIL Input Low Voltage 0.6 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 1.6 mA 0.45 V
VOH Output High Voltage IOH = -100µA 2.0 V
9. AC Read Characteristics
Symbol Parameter
AT28BV64B-20
UnitsMin Max
tACC Address to Output Delay 200 ns
tCE(1) CE to Output Delay 200 ns
tOE(2) OE to Output Delay 0 80 ns
tDF(3)(4) CE or OE to Output Float 0 55 ns
tOH Output Hold from OE, CE or Address, Whichever Occurred First 0 ns
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AT28BV64B
11. Input Test Waveforms and Measurement Level
12. Output Test Load
Note: 1. This parameter is characterized and is not 100% tested.
tR,t
F<20ns
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol Typ Max Units Conditions
CIN 46pFV
IN =0V
COUT 812pFV
OUT =0V
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AT28BV64B
Notes: 1. NR = No Restriction
2. All byte write operations must be preceded by the SDP command sequence.
15. AC Write Waveforms
15.1 WE Controlled
15.2 CE Controlled
14. AC Write Characteristics
Symbol Parameter Min Max Units
tAS,t
OES Address, OE Set-up Time 0 ns
tAH Address Hold Time 100 ns
tCS Chip Select Set-up Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE) 200 ns
tDS Data Set-up Time 100 ns
tDH,t
OEH Data, OE Hold Time 0 ns
tDV Time to Data Valid NR(1)
tWPH Write Pulse Width High 100 ns
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17. Write Algorithm(1)
Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A12 - A0 (Hex).
2. Data protect state will be re-activated at the end of the write cycle.
3. 1 to 64 bytes of data are loaded.
16. Page Mode Characteristics
Symbol Parameter Min Max Units
tWC Write Cycle Time 10 ms
tAS Address Set-up Time 0 ns
tAH Address Hold Time 100 ns
tDS Data Set-up Time 100 ns
tDH Data Hold Time 0 ns
tWP Write Pulse Width 200 ns
tBLC Byte Load Cycle Time 100 µs
tWPH Write Pulse Width High 100 ns
LOAD DATA AA
TO
ADDRESS 1555
LOAD DATA 55
TO
ADDRESS 0AAA
LOAD DATA A0
TO
ADDRESS 1555
LOAD DATA XX
TO
AN ADDRESS
(3)
LOAD LAST B TE
TO
LAST ADDRESS ENTER DATA
PROTECT STATE
WRITES ENABLED
(2)
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AT28BV64B
18. Software Data Protection Write Cycle Waveforms(1)(2)(3)
Notes: 1. A0 - A12 must conform to the addressing sequence for the first three bytes as shown above.
2. A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after the software
code has been entered.
3. OE must be high only when WE and CE are both low.
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
20. Data Polling Waveforms
19. Data Polling Characteristics(1)
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 0 ns
tOEH OE Hold Time 0 ns
tOE OE to Output Delay(2) ns
tWR Write Recovery Time 0 ns
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AT28BV64B
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
22. Toggle Bit Waveforms
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used, but the address should not vary.
21. Toggle Bit Characteristics(1)
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay(2) ns
tOEHP OE High Pulse 150 ns
tWR Write Recovery Time 0 ns
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23. Ordering Information
23.2 Die Products
23.1 Green Package Option (Pb/Halide-free)
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
200 15 0.05 AT28BV64B-20JU
AT28BV64B-20SU
AT28BV64B-20TU
32J
28S
28T
Industrial
(-40Cto85C)
Contact Atmel Sales in regards to die and wafer sales.
Package Type
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
28S 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
28T 28-lead, Plastic Thin Small Outline Package (TSOP)
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24. Packaging Information
24.1 32J – PLCC
DRAWING NO. REV.
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B
32J
10/04/01
1.14(0.045) X 45° PIN NO. 1
IDENTIFIER
1.14(0.045) X 45°
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45° MAX (3X)
A
A1
B1 E2
B
e
E1 E
D1
D
D2
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MA NOTE
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 3.175 – 3.556
A1 1.524 – 2.413
A2 0.381 – –
D 12.319 – 12.573
D1 11.354 – 11.506 Note 2
D2 9.906 – 10.922
E 14.859 – 15.113
E1 13.894 – 14.046 Note 2
E2 12.471 – 13.487
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 T P
Package Drawing Contact:
packagedrawings atmel.com
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Atmel-0299J-PEEPROM-AT28BV64B-Datasheet_072013
AT28BV64B
24.2 28S – SOIC
TITLE DRAWING NO. REV.
Package Drawing Contact:
packagedrawings@atmel.com
28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC)
JEDEC Standard MS-013 B
28S
8/4/03
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
TOP VIEW
SIDE VIEWS
0.51(0.020)
0.33(0.013)
7.60(0.2992)
7.40(0.2914)
10.65(0.419)
10.00(0.394)
1.27(0.50) BSC
2.65(0.1043)
2.35(0.0926)
18.10(0.7125)
17.70(0.6969)
0.30(0.0118)
0.10(0.0040)
0.32(0.0125)
0.23(0.0091)
1.27(0.050)
0.40(0.016)
0º ~ 8º
PIN 1
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Atmel-0299J-PEEPROM-AT28BV64B-Datasheet_072013
AT28BV64B
24.3 28T – TSOP
DRAWING NO. REV.
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B
32J
10/04/01
1.14(0.045) X 45° PIN NO. 1
IDENTIFIER
1.14(0.045) X 45°
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45° MAX (3X)
A
A1
B1 E2
B
e
E1 E
D1
D
D2
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MA NOTE
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 3.175 – 3.556
A1 1.524 – 2.413
A2 0.381 – –
D 12.319 – 12.573
D1 11.354 – 11.506 Note 2
D2 9.906 – 10.922
E 14.859 – 15.113
E1 13.894 – 14.046 Note 2
E2 12.471 – 13.487
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 T P
Package Drawing Contact:
packagedrawings atmel.com
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AT28BV64B
25. Revision History
Doc. Rev. Date Comments
0299J 04/2013 Correct Device ID addressing.
Update Atmel branding and disclaimer page.
X
XXX
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© 2013 Atmel Corporation / Rev.: Atmel-0299J-PEEPROM-AT28BV64B-Datasheet_072013
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