EMIF03SIM02M8 - STMICROELECTRONICS

October 2007 Rev 1 1/10

EMIF03-SIM02M8

3 line IPAD™, EMI filter for SIM card applications

Features

■SIM card EMI low-pass filter

■High efficiency in EMI filtering

■Very low PCB space consumption:

1.7 mm x 1.5 mm

■Very thin package: 0.6 mm max

■High efficiency in ESD suppression on external

pins (IEC 61000-4-2 level 4).

■High reliability offered by monolithic integration

■High reduction of parasitic elements through

integration and wafer level packaging.

■Lead free package

■Easy layout and flexibility thanks to I/O

topology

■Low clamping voltage

Complies with following standards

■IEC 61000-4-2 level 4 external pins

– 15 kV (air discharge)

– 8 kV (contact discharge)

■IEC 61000-4-2 level 2 internal pins

– 2 kV (air discharge)

– 2 kV (contact discharge)

■MIL STD 883G - Method 3015-7 Class 3A (all

pins)

Applications

Where EMI filtering in ESD sensitive equipment is

required:

■Keyboard for mobile phones

■Computers and printers

■Communication systems

■MCU boards

TM: IPAD is a trademark of STMicroelectronics

Figure 1. Pin configuration (top view)

Figure 2. Device configuration

Description

The EMIF03-SIM02M8 is a 3 line highly

integrated device designed to suppress EMI/RFI

noise in all systems exposed to electromagnetic

interference.

This filter includes ESD protection circuitry, which

prevents damage to the application when

subjected to ESD surges up to 15 kV on the

external pins.

7GND

GND

Micro QFN 1.7 mm x 1.5 mm

(bottom view)

GND

Vcc Vcc

RST

CLK

Data

RST

EXT

CLK

EXT

Data

EXT

Maximum line capacitance = 20 pF

100 Ω

47 Ω

100 Ω

RST ext

RST in

CLK ext

CLK in

Data ext

Data in

GND

Vcc

www.st.com

Characteristics EMIF03-SIM02M8

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1 Characteristics

Table 1. Absolute ratings (limiting values at Tamb = 25 °C unless otherwise specified)

Symbol Parameter Value Unit

VPP

Internal pins

ESD discharge IEC 61000-4-2 air discharge

ESD discharge IEC 61000-4-2 contact discharge

External pins and VCC

ESD discharge IEC 61000-4-2 air discharge

ESD discharge IEC 61000-4-2 contact discharge

All pins

MIL STD 883G - Method 3015-7 Class 3A (human body model)

TjJunction temperature 125 °C

Top Operating temperature range -40 to + 85 °C

Tstg Storage temperature range -55 to +150 °C

Table 2. Electrical characteristics (Tamb = 25 °C)

Symbol Parameter

VBR Breakdown voltage

IRM Leakage current @ VRM

VRM Stand-off voltage

VCL Clamping voltage

IPP Peak pulse current

RI/O Series resistance between input and output

Cline Input capacitance per line

Symbol Test conditions Min. Typ. Max. Unit

VBR IR = 1 mA 6 7.9 V

IRM VRM = 3 V 0.2 µA

R1, R3Tolerance ± 20% 100 Ω

R2Tolerance ± 20% 47 Ω

Cline VR= 0 V, F = 1 MHz, VOSC = 30 mV 17 20 pF

VBR

IPP

VRM

IRM

VCL

EMIF03-SIM02M8 Characteristics

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Figure 3. S21(db) attenuation (RST line) Figure 4. S21(db) attenuation (CLK line)

300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G

-35.00

-30.00

-25.00

-20.00

-15.00

-10.00

-5.00

0.00

F (Hz)

300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G

-35.00

-30.00

-25.00

-20.00

-15.00

-10.00

-5.00

0.00

F (Hz)

Figure 5. S21(db) attenuation (DATA line) Figure 6. Analog cross talk measurements

300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G

-35.00

-30.00

-25.00

-20.00

-15.00

-10.00

-5.00

0.00

F (Hz)

300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G

-120.00

-110.00

-100.00

-90.00

-80.00

-70.00

-60.00

-50.00

-40.00

-30.00

-20.00

-10.00

0.00

ClkIn- RstExt DataIn-Rst/Clk

F (Hz)

Figure 7. ESD response to IEC 61000-4-2

(+15 kV air discharge) applied to

external pin

Figure 8. ESD response to IEC 61000-4-2

(-15 kV air discharge) applied to

external pin

200 ns/div

5 V/div

2 V/div

200 ns/div

5 V/div

2 V/div

Application schematic EMIF03-SIM02M8

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2 Application schematic

Figure 11. Application schematic

3 Ordering information scheme

Figure 12. Ordering information scheme

Figure 9. ESD response to IEC 61000-4-2

(+2 kV air discharge) applied to

internal pin

Figure 10. ESD response to IEC 61000-4-2

(-2 kV air discharge) applied to

internal pin

20 ns/div

5 V/div

2 V/div

20 ns/div

5 V/div

2 V/div

GND

Vcc Vcc

RST in

CLK in

Data in

RST EXT

CLK EXT

Data EXT

SIM PROCESSOR

SIM CONNECTOR

EMIF yy - xxx zz Mx

EMI Filter

Number of lines

Information

Package

xxx = application

zz = version

Mx = Micro QFN x leads

EMIF03-SIM02M8 Package information

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4 Package information

●Epoxy meets UL94, V0

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a lead-free second level interconnect. The category of

second level interconnect is marked on the inner box label, in compliance with JEDEC

Standard JESD97. The maximum ratings related to soldering conditions are also marked on

the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available

at: www.st.com.

Table 3. QFN 1.7 x 1.5 package dimensions

Ref

Dimensions

Millimeters inches

MIN TYP MAX MIN TYP MAX

A 0.50 0.55 0.60 0.20 0.22 0.24

A1 0.00 0.02 0.05 0.00 0.01 0.02

b 0.15 0.18 0.25 0.06 0.07 0.10

D 1.70 0.67

D2 0.9 1.00 1.10 0.35 0.39 0.43

E 1.50 0.59

E2 0.30 0.40 0.50 0.12 0.16 0.24

e 0.40 0.16

k 0.20 0.08

L 0.25 0.30 0.35 0.10 0.12 0.14

Figure 13. Footprint (dimensions in mm) Figure 14. Marking

Dot: Pin 1 Identification

Package information EMIF03-SIM02M8

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Figure 15. Tape and reel specification

Note: Product marking may be rotated by 90° for assembly plant differentiation. In no case should

this product marking be used to orient the component for its placement on a PCB. Only pin

1 mark is to be used for this purpose.

4.00+/-0.1

1.75 +/- 0.1

4.00

φ1.5 +/- 0.1

3.5 +/- 0.03

User direction of unreeling

8.0 +/- 0.3

0.75 1.70

1.90

2.0+/-0.05

4.00+/-0.1

1.75 +/- 0.1

4.00

φ1.5 +/- 0.1

3.5 +/- 0.03

User direction of unreeling

8.0 +/- 0.3

0.75 1.70

1.90

2.0+/-0.05

EMIF03-SIM02M8 Recommendation on PCB assembly

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5 Recommendation on PCB assembly

5.1 Stencil opening design

1. General recommendation on stencil opening design

a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).

Figure 16. Stencil opening dimensions

b) General Design Rule

Stencil thickness (T) = 75 ~ 125 µm

2. Reference design

a) Stencil opening thickness: 100 µm

b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%.

Example: Stencil opening L = 680 µm, W = 300 µm

Footprint (see Figure 13) L = 1000 µm, W = 400 µm

c) Stencil opening for leads: Opening to footprint ratio is 90%.

Example: Stencil opening L = 570 µm, W = 190 µm

Footprint (see Figure 13) L = 600 µm, W = 200 µm

5.2 Solder paste

1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004.

2. “No clean” solder paste is recommended.

3. Offers a high tack force to resist component movement during high speed

4. Solder paste with fine particles: powder particle size is 20-45 µm.

Aspect Ratio W

----- 1.5≥=

Aspect Area LW×

2T L W+()

----------------------------0.66≥=

Recommendation on PCB assembly EMIF03-SIM02M8

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5.3 Placement

1. Manual positioning is not recommended.

2. It is recommended to use the lead recognition capabilities of the placement system, not

the outline centering

3. Standard tolerance of ± 0.05 mm is recommended.

4. 3.5 N placement force is recommended. Too much placement force can lead to

squeezed out solder paste and cause solder joints to short. Too low placement force

can lead to insufficient contact between package and solder paste that could cause

open solder joints or badly centered packages.

5. To improve the package placement accuracy, a bottom side optical control should be

performed with a high resolution tool.

6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is

recommended during solder paste printing, pick and place and reflow soldering by

using optimized tools.

5.4 PCB design preference

1. To control the solder paste amount, the closed via is recommended instead of open

vias.

2. The position of tracks and open vias in the solder area should be well balanced. The

symmetrical layout is recommended, in case any tilt phenomena caused by

asymmetrical solder paste amount due to the solder flow away.

5.5 Reflow profile

Figure 17. ST ECOPACK® recommended soldering reflow profile for PCB mounting

Note: Minimize air convection currents in the reflow oven to avoid component movement.

01234567

Time (min)

Temperature (°C)

2°C/s recommended

6°C/s max

220°C

125 °C

260°C max

255°C

180°C

90 sec max

10-30 sec

90 to 150 sec

3°C/s max

01234567

Time (min)

Temperature (°C)

2°C/s recommended

6°C/s max

220°C

125 °C

260°C max

255°C

180°C

90 sec max

10-30 sec

90 to 150 sec

3°C/s max

EMIF03-SIM02M8 Ordering information

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6 Ordering information

7 Revision history

Table 4. Ordering information

Part number Marking Package Weight Base qty Delivery mode

EMIF03-SIM02M8 HA Micro QFN 4 mg 3000 Tape and reel (7”)

Table 5. Document revision history

Date Revision Changes

07-Oct-2007 1Initial release.

EMIF03-SIM02M8

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