K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Document Title 128M x 8 Bit NAND Flash Memory Revision History Revision No. History 0.0 0.1 Initial issue. 1. Note 1 ( Program/Erase Characteristics) is added( page 13 ) 2. NAND Flash Technical Notes is changed. -Invalid block -> initial invalid block ( page 15 ) -Error in write or read operation ( page 16 ) -Program Flow Chart ( page 16 ) 3. Vcc range is changed -1.7V~1.95V ->1.65V~1.95V 4. 2.7V device is added 5. Multi plane operation and Copy-Back Program are not supported with 1.8V Draft Date Remark Mar. 17th 2003 Oct. 11th 2004 Advance Advance May 6th. 2005 Preliminary device. 0.2 1. The flow chart to creat the initial invalid block table is changed. 1.0 May 30th 2005 Final Note : For more detailed features and specifications including FAQ, please refer to Samsung's Flash web site. http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office. 1 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY 128M x 8 Bit Bit NAND Flash Memory PRODUCT LIST Part Number Vcc Range K9K1G08R0B-G,J 1.65 ~ 1.95V K9K1G08B0B-G,J 2.5 ~ 2.9V K9K1G08U0B-G,J 2.7 ~ 3.6V Organization PKG Type X8 FBGA FEATURES * Command/Address/Data Multiplexed I/O Port * Hardware Data Protection - Program/Erase Lockout During Power Transitions * Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles - Data Retention : 10 Years * Command Register Operation * Intelligent Copy-Back * Unique ID for Copyright Protection * Package - K9K1G08X0B-GCB0/GIB0 63- Ball FBGA - K9K1G08X0B-JCB0/JIB0 63- Ball FBGA - Pb-free Package * Voltage Supply - 1.8V device(K9K1G08R0B) : 1.65 ~ 1.95V - 2.7V device(K9K1G08B0B) : 2.5 ~ 2.9V - 3.3V device(K9K1GXXU0B) : 2.7 ~ 3.6 V * Organization - Memory Cell Array -128M + 4096K)bit x 8 bit - Data Register - (512 + 16)bit x 8bit * Automatic Program and Erase - Page Program - (512 + 16)Byte - Block Erase : - (16K + 512)Byte * Page Read Operation - Page Size - (512 + 16)Byte - Random Access : 15s(Max.) - Serial Page Access : 50ns(Min.)* * K9K1G08R0B : 60ns * Fast Write Cycle Time - Program time : 200s(Typ.) - Block Erase Time : 2ms(Typ.) GENERAL DESCRIPTION The K9K1G08X0B is a 128M(134,217,728)x8bit NAND Flash Memory with a spare 4.096K(4,194,304)x8bit. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typically 200s on the 528-byte page and an erase operation can be performed in typically 2ms on a 16K-byte block. Data in the data register can be read out at 50ns(1.8V device : 60ns) cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verify and margining of data. Even the write-intensive systems can take advantage of the K9K1G08X0Bs extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K1G08X0B is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. 2 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY PIN CONFIGURATION (FBGA) K9K1G08X0B-GCB0,JCB0/GIB0,JIB0 1 2 3 4 5 6 N.C N.C N.C N.C A B C D E F G H N.C N.C N.C /WP ALE Vss /CE /WE R/B NC /RE CLE NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC I/O0 NC NC Vcc VccQ I/O5 NC I/O7 NC I/O1 NC Vss I/O2 I/O3 I/O4 I/O6 Vss N.C N.C N.C N.C N.C N.C N.C N.C Top View 3 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Top View Bottom View #A1 INDEX MARK(OPTIONAL) 8.500.10 6 #A1 8.500.10 0.80 x 9= 7.20 0.80 x 5= 4.00 0.80 5 4 3 2 A B 1 0.80 (Datum A) A D 2.80 E F G H 63-0.450.05 0.20 M A B 0.25(Min.) Side View 13.500.10 0.10MAX 0.450.05 4 1.20(Max) 2.00 13.500.10 0.80 x 7= 5.60 13.500.10 C 0.80 x 11= 8.80 B (Datum B) K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY PIN DESCRIPTION Pin Name Pin Function I/O0 ~ I/O7 (K9K1G08X0B) DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled. CLE COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ALE ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CE CHIP ENABLE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation. Regarding CE control during read operation, refer to 'Page read' section of Device operation . RE READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WE WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WP WRITE PROTECT The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. R/B READY/BUSY OUTPUT The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. VccQ OUTPUT BUFFER POWER VccQ is the power supply for Output Buffer. VccQ is internally connected to Vcc, thus should be biased to Vcc. Vcc POWER VCC is the power supply for device. Vss GROUND N.C NO CONNECTION Lead is not internally connected. DNU DO NOT USE Leave it disconnected. NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected. 5 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Figure 1-1. Functional Block Diagram VCC VSS A9 - A26 X-Buffers Latches & Decoders A 0 - A7 Y-Buffers Latches & Decoders 1,024M + 32M Bit NAND Flash ARRAY (512 + 16)Byte x 262,144 Page Register & S/A A8 Y-Gating Command Command Register CE RE WE VCC VSS I/O Buffers & Latches Control Logic & High Voltage Generator Output Driver Global Buffers I/0 0 I/0 7 CLE ALE WP Figure 2-1. Array Organization 1 Block = 32 Pages (16K + 512) Byte 256K Pages (=8,192 Blocks) 1st half Page Register 2nd half Page Register (=256 Bytes) (=256 Bytes) 1 Page = 528 Bytes 1 Block = 528 B x 32 Pages = (16K + 512) Bytes 1 Device = 528B x 32Pages x 8,192 Blocks = 1,056 Mbits 8 bit 512B Bytes 16 Bytes I/O 0 ~ I/O 7 Page Register 512 Bytes I/O 0 I/O 1 16 Bytes I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16 3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24 4th Cycle A25 A26 *L *L *L *L *L *L NOTE : Column Address : Starting Address of the Register. 00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. * A8 is set to "Low" or "High" by the 00h or 01h Command. * L must be set to "Low". 6 Column Address Row Address (Page Address) K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Product Introduction The K9K1G08X0B is a 1,026Mbit(1,107,296,436 bit) memory organized as 262,144 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 8,192 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K1G08X0B. The K9K1G08X0B has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 128M byte physical space requires 27 addresses, thereby requiring four cycles for byte-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9K1G08X0B. The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into eight 128Mbit separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining the conventional 512 byte structure. The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block out of selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document. In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another of the same plane without the need for transporting the data to and from the external buffer memory. Since the time-consuming burstreading and data-input cycles are removed, system performance for solid-state disk application is significantly increased. Table 1. Command Sets Function 1st. Cycle Read 1 00h/01h Read 2 (1) 50h 2nd. Cycle 3rd. Cycle - - - - Read ID 90h - - Reset FFh - - Page Program (True) 80h 10h - Page Program (Dummy)(2) 80h 11h - 00h 8Ah 10h (2) Copy-Back Program(True) (2) Acceptable Command during Busy O Copy-Back Program(Dummy) 03h 8Ah 11h Block Erase 60h D0h - 60h---60h D0h - 70h - - O - - O (2) Multi-Plane Block Erase Read Status Read Multi-Plane Status 71h (3) NOTE : 1. The 00h command defines starting address of the 1st half of registers. The 01h command defines starting address of the 2nd half of registers. After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle. 2. Page Program(True) and Copy-Back Program(True) are available on 1 plane operation. Page Program(Dummy) and Copy-Back Program(Dummy) are available on the 2nd,3rd,4th plane of multi plane operation. 3. The 71h command should be used for read status of Multi Plane operation. 4. Multi plane operation and Copy-Back Program are not supported with 1.8V device. Caution : Any undefined command inputs are prohibited except for above command set of Table 1. 7 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Memory Map The device is arranged in eight 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is configured so that multi-plane program/erase operations can be executed for every four sequential blocks by dividing the memory array into plane 0~3 or plane 4~7 separately. For example, multi-plane program/erase operations into plane 2,3,4 and 5 are prohibited. Figure 3. Memory Array Map Plane 0 (1024 Block) Block 0 Plane 2 (1024 Block) Plane 1 (1024 Block) Block 2 Block 1 Plane 3 (1024 Block) Block 3 Page 0 Page 0 Page 0 Page 0 Page 1 Page 1 Page 1 Page 1 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Block 4092 Block 4094 Block 4093 Block 4095 Page 0 Page 0 Page 0 Page 0 Page 1 Page 1 Page 1 Page 1 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 528byte Page Registers 528byte Page Registers 528byte Page Registers 528byte Page Registers Plane 4 (1024 Block) Plane 5 (1024 Block) Plane 6 (1024 Block) Plane 7 (1024 Block) Block 4096 Block 4098 Block 4097 Block 4099 Page 0 Page 0 Page 0 Page 0 Page 1 Page 1 Page 1 Page 1 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Block 8188 Block 8190 Block 8189 Block 8191 Page 0 Page 0 Page 0 Page 0 Page 1 Page 1 Page 1 Page 1 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 528byte Page Registers 528byte Page Registers 528byte Page Registers 528byte Page Registers 8 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY ABSOLUTE MAXIMUM RATINGS Parameter 1.8V Device 2.7V/3.3V Device VIN/OUT -0.6 to + 2.45 -0.6 to + 4.6 VCC -0.2 to + 2.45 -0.6 to + 4.6 VCCQ -0.2 to + 2.45 -0.6 to + 4.6 Voltage on any pin relative to VSS Temperature Under Bias Storage Temperature Rating Symbol K9K1G08X0B-XCB0 K9K1G08X0B-XCB0 K9K1G08X0B-XIB0 Short Circuit Current V -10 to +125 TBIAS K9K1G08X0B-XIB0 Unit C -40 to +125 TSTG -65 to +150 C Ios 5 mA NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, K9K1G08X0B-XCB0 :TA=0 to 70C, K9K1G08X0B-XIB0 :TA=-40 to 85C) Parameter Symbol Supply Voltage K9K1G08R0B(1.8V) K9K1G08B0B(2.7V) K9K1G08U0B(3.3V) Unit Min Typ. Max Min Typ. Max Min Typ. Max VCC 1.65 1.8 1.95 2.5 2.7 2.9 2.7 3.3 3.6 V Supply Voltage VCCQ 1.65 1.8 1.95 2.5 2.7 2.9 2.7 3.3 3.6 V Supply Voltage VSS 0 0 0 0 0 0 0 0 0 V 9 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.) K9K1G08X0B Parameter Sequential Operating Read Current Program Erase Symbol Test Conditions 1.8V 2.7V 3.3V Unit Min Typ Max Min Typ Max Min Typ Max ICC1 tRC=50ns (K9K1G08R0B:60ns), CE=VIL IOUT=0mA - 10 20 - 10 20 - 15 30 ICC2 - - 10 20 - 10 20 - 15 30 ICC3 - - 10 20 - 10 20 - 15 30 Stand-by Current(TTL) ISB1 CE=VIH, WP=0V/VCC - - 1 - - 1 - - 1 Stand-by Current(CMOS) ISB2 CE=VCC-0.2, WP=0V/VCC - 20 100 - 10 50 - 20 100 Input Leakage Current ILI VIN=0 to Vcc(max) - - 20 - - 10 - - 20 Output Leakage Current ILO VOUT=0 to Vcc(max) - - 20 - - 10 - - 20 2.0 - 2.0 - -0.3 - VCCQ I/O pins Input High Voltage -0.4 VIH* VCC- Except I/O pins Input Low Voltage, All inputs Output High Voltage Level 0.4 - VIL* -0.3 VCCQ K9K1G08B0B :IOH-100A Level - +0.3 -0.4 VCC VCC +0.3 -0.4 0.4 -0.3 - - - - 0.1 3 4 - -0.1 K9K1G08U0B :IOH-400A Output Low Voltage - VCCQ VCCQ - VCCQ +0.3 VCC +0.3 0.5 A VCCQ +0.3 VCC+ 0.3 0.8 V K9K1G08R0B :IOH-100A VOH - mA VCCQ - - 2.4 - - - - 0.4 - - 0.4 3 4 - 8 10 - -0.4 K9K1G08R0B :IOL=100uA VOL K9K1G08B0B :IOH=100A K9K1G08U0B :IOL=2.1mA K9K1G08R0B :VOL=0.1V Output Low Current(R/B) IOL(R/B) K9K1G08B0B :VOL=0.1V mA K9K1G08U0B :VOL=0.4V NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less Valid Block Parameter Valid Block Number Symbol Min Typ. Max Unit NVB 8,052 - 8,192 Blocks NOTE : 1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid blocks for program and erase. Refer to the attached technical notes for an appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles. 3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space. 10 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY AC TEST CONDITION (K9K1G08X0B-XCB0 :TA=0 to 70C, K9K1G08X0B-XIB0 :TA=-40 to 85C K9K1G08R0B : Vcc=1.65V~1.95V , K9K1G08B0B : Vcc=2.5V~2.9V, K9K1G08U0B : Vcc=2.7V~3.6V unless otherwise noted) Parameter K9K1G08R0B K9K1G08B0B K9K1G08U0B 0V to VccQ 0V to VccQ 0.4V to 2.4V Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels 5ns 5ns 5ns VccQ/2 VccQ/2 1.5V K9K1G08R0B:Output Load (VccQ:1.8V +/-10%) K9K1G08B0C:Output Load (VccQ:2.7V +/-10%) 1 TTL GATE and CL=30pF 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF K9K1G08U0B:Output Load (VccQ:3.0V +/-10%) K9K1G08U0B:Output Load (VccQ:3.3V +/-10%) - - 1 TTL GATE and CL=100pF Capacitance(TA=25C, VCC=1.8V/2.7V/3.3V, f=1.0MHz) Item Symbol Test Condition Min Max Unit Input/Output Capacitance CI/O VIL=0V - 20 pF Input Capacitance CIN VIN=0V - 20 pF NOTE : Capacitance is periodically sampled and not 100% tested. MODE SELECTION CLE ALE CE H L L H H L L L WE RE WP L H X L H X L L H H H L H H L H H Mode Read Mode Write Mode Command Input Address Input(4clock) Command Input Address Input(4clock) Data Input L L L H X Data Output X X X X H X During Read(Busy) on the devices X X X X X H During Program(Busy) X X X X X H During Erase(Busy) X X X L Write Protect H X X 0V/V X X X (1) X CC(2) Stand-by NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby. Program / Erase Characteristics Parameter Program Time Dummy Busy Time for Multi Plane Program Number of Partial Program Cycles in the Same Page Block Erase Time Symbol Min Typ Max Unit tPROG(1) - 200 500 s 1 10 s - - 1 cycle - - 2 cycles - 2 3 ms tDBSY Main Array Spare Array Nop tBERS NOTE : 1.Typical program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and 25'C 11 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY AC Timing Characteristics for Command / Address / Data Input Parameter Symbol Min 1.8V Max 3.3V 2.7V 1.8V Unit 3.3V 2.7V CLE Set-up Time tCLS 0 0 0 - - - ns CLE Hold Time tCLH 10 10 10 - - - ns CE Setup Time tCS 0 0 0 .- .- .- ns CE Hold Time tCH 10 10 10 - - - ns WE Pulse Width tWP 40 25(1) 25(1) - - - ns ALE Setup Time tALS 0 0 0 - - - ns ALE Hold Time tALH 10 10 10 - - - ns Data Setup Time tDS 20 20 20 - - - ns Data Hold Time tDH 10 10 10 - - - ns Write Cycle Time tWC 60 50 50 - - - ns WE High Hold Time tWH 20 15 15 - - - ns NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns. AC Characteristics for Operation Parameter Symbol Min 1.8V 2.7V Max 3.3V 1.8V 2.7V 3.3V Unit Data Transfer from Cell to Register tR 0 - - 15 15 15 s ALE to RE Delay tAR 10 10 10 - - - ns CLE to RE Delay tCLR 10 10 10 - - - ns Ready to RE Low tRR 20 20 20 - - - ns RE Pulse Width tRP 40 25 25 - - - ns WE High to Busy tWB - - - 100 100 100 ns Read Cycle Time tRC 60 50 50 - - - ns RE Access Time tREA - - - 40 30 30 ns CE Access Time tCEA - - - 55 45 45 ns RE High to Output Hi-Z tRHZ - - - 30 30 30 ns CE High to Output Hi-Z tCHZ - - - 20 20 20 ns RE or CE High to Output hold tOH 15 15 15 - - - ns RE High Hold Time tREH 20 15 15 - - - ns tIR 0 0 0 - - - ns WE High to RE Low Output Hi-Z to RE Low tWHR 60 60 60 - - - ns Device Resetting Time(Read/Program/Erase) tRST - - - NOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us. 12 5/10/500(1) 5/10/500(1) 5/10/500(1) s K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles. Identifying Initial Invalid Block(s) All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 517. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 4). Any intentional erasure of the initial invalid block information is prohibited. Start Set Block Address = 0 Increment Block Address No Create (or update) Initial Invalid Block(s) Table * Check "FFh" at the column address 517 of the 1st and 2nd page in the block Check "FFh" ? Yes No Last Block ? Yes End Figure 4. Flow chart to create initial invalid block table. 13 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block failure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read failure due to single bit error should be reclaimed by ECC without any block replacement. The block failure ratein the qualification report does not include those reclaimed blocks. Failure Mode Write Read ECC Detection and Countermeasure sequence Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement Single Bit Failure Verify ECC -> ECC Correction : Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection Program Flow Chart Start Write 80h Write Address Write Data Write 10h Read Status Register I/O 6 = 1 ? or R/B = 1 ? * Program Error No Yes No I/O 0 = 0 ? Yes Program Completed * 14 : If program operation results in an error, map out the block including the page in error and copy the target data to another block. K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY NAND Flash Technical Notes (Continued) Erase Flow Chart Read Flow Chart Start Start Write 60h Write 00h Write Block Address Write Address Write D0h Read Data Read Status Register ECC Generation I/O 6 = 1 ? or R/B = 1 ? * Erase Error No Reclaim the Error Verify ECC Yes Yes No No Page Read Completed I/O 0 = 0 ? Yes Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. Block Replacement Buffer memory error occurs Page a Block A Block B 15 When the error happens with page "a" of Block "A", try to write the data into another Block "B" from an external buffer. Then, prevent further system access to Block "A" (by creating a "invalid block" table or other appropriate scheme.) K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Pointer Operation of K9K1G08X0B Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. '00h' command sets the pointer to 'A' area(0~255byte), '01h' command sets the pointer to 'B' area(256~511byte), and '50h' command sets the pointer to 'C' area(512~527byte). With these commands, the starting column address can be set to any of a whole page(0~527byte). '00h' or '50h' is sustained until another address pointer command is inputted. '01h' command, however, is effective only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with '01h' command, the address pointer returns to 'A' area by itself. To program data starting from 'A' or 'C' area, '00h' or '50h' command must be inputted before '80h' command is written. A complete read operation prior to '80h' command is not necessary. To program data starting from 'B' area, '01h' command must be inputted right before '80h' command is written. Table 2. Destination of the pointer Command Pointer position Area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(A) 2nd half array(B) spare array(C) "A" area (00h plane) "B" area (01h plane) 256 Byte 256 Byte "A" "B" "C" area (50h plane) 16 Byte "C" Internal Page Register Pointer select commnad (00h, 01h, 50h) Pointer Figure 5. Block Diagram of Pointer Operation (1) Command input sequence for programming 'A' area The address pointer is set to 'A' area(0~255), and sustained Address / Data input 00h 80h Address / Data input 10h 00h 'A','B','C' area can be programmed. It depends on how many data are inputted. 80h 10h '00h' command can be omitted. (2) Command input sequence for programming 'B' area The address pointer is set to 'B' area(256~511), and will be reset to 'A' area after every program operation is executed. Address / Data input 01h 80h Address / Data input 10h 01h 'B', 'C' area can be programmed. It depends on how many data are inputted. 80h 10h '01h' command must be rewritten before every program operation (3) Command input sequence for programming 'C' area The address pointer is set to 'C' area(512~527), and sustained Address / Data input 50h 80h Address / Data input 10h 50h Only 'C' area can be programmed. 80h '50h' command can be omitted. 16 10h K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY System Interface Using CE don't-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption. Figure 6. Program Operation with CE don't-care. CLE CE don't-care WE CE ALE I/OX 80h Start Add.(4Cycle) tCS Data Input tCH Data Input 10h tCEA CE CE RE tWP tREA WE I/OX out Figure 7. Read Operation with CE don't-care. CLE CE don't-care CE RE ALE tR R/B WE I/OX 00h Data Output(sequential) Start Add.(4Cycle) 17 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY I/O DATA I/Ox Data In/Out I/O 0 ~ I/O 7 ~528byte Device K9K1G08X0B Command Latch Cycle CLE tCLS tCLH tCS tCH CE tWP WE tALH tALS ALE tDH tDS Command I/O0~7 Address Latch Cycle tCLS CLE tCS tWC tWC tWC CE tWP tWP WE tWH tALH tALS tWH tALH tALS tALS tWP tWP tWH tALH tALS tALH ALE tDS I/O0~7 tDH A0~A7 tDS tDH A9~A16 18 tDS tDH A17~A24 tDS tDH A25,,A26 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Input Data Latch Cycle tCLH CLE tCH CE tWC tALS ALE tWP tWH tDH tDS tDH tDS tDH tDS tWP tWP WE I/O0~7 DIN 511 DIN 1 DIN 0 Serial access Cycle after Read(CLE=L, WE=H, ALE=L) tRC CE tREA tREA tREH tCHZ* tOH tREA RE tRHZ* tRHZ* I/Ox Dout Dout tOH Dout tRR R/B NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 19 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Status Read Cycle tCLR CLE tCLS tCLH tCS CE tCH tWP WE tCEA tCHZ tOH tWHR RE tDH tDS I/OX tRHZ tREA tIR tOH Status Output 70h Read1 Operation(Read One Page) CLE CE tCHZ tWC tOH WE tWB tAR2 ALE tR tRHZ tOH tRC RE I/O0~7 00h or 01h A0 ~ A7 A9 ~ A16 Column Address R/B A17 ~ A24 Dout N A25,A26 Page(Row) Address Busy 20 Dout N+1 Dout N+2 tRR Dout 527 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Read1 Operation(Intercepted by CE) CLE CE WE tWB tCHZ tAR ALE tRC tR RE tRR I/O0~7 00h or 01h A9 ~ A16 A0 ~ A7 A17 ~ A24 Dout N A25,A26 Dout N+1 Dout N+2 Page(Row) Address Column Address R/B Busy Read2 Operation(Read One Page) CLE CE WE tR tWB ALE tAR RE I/O0~7 50h A0 ~ A7 A9 ~ A16 A17 ~ A24 Dout 511+M A25,A26 R/B tRR Dout 527 Selected Row M Address A0~A3 : Valid Address A4~A7 : Dont care 512 16 Start address M 21 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Page Program Operation CLE CE tWC tWC tWC WE tWB tPROG ALE I/O0~7 A0 ~ A7 A9 ~ A16 A17 ~ A24 A25,A26 80h Sequential Data Column Input Command Address Page(Row) Address RE Din Din 10h N 527 1 up to 528 Byte Data Program Command Serial Input R/B 70h I/O0 Read Status Command I/O0=0 Successful Program I/O0=1 Error in Program BLOCK ERASE OPERATION (ERASE ONE BLOCK) CLE CE tWC WE tBERS tWB ALE RE I/O0~7 60h A9 ~ A16 A17 ~ A24 A25,A26 DOh 70h I/O 0 Busy R/B Auto Block Erase Setup Command Erase Command 22 Page(Row) Address Read Status Command I/O0=0 Successful Erase I/O0=1 Error in Erase R/B I/O0~7 RE ALE WE Sequential Data Input Command 80h tWC 23 Max. three times repeatable Page(Row) Address Din 527 tDBSY : typ. 1us max. 10us tDBSY 80h I/O0~7 R/B 80h A0 ~ A7 & A9 ~ A26 528 Byte Data Address & Data Input 11h tDBSY 80h A0 ~ A7 & A9 ~ A26 528 Byte Data Address & Data Input 11h 80h Din N A0 ~ A7 & A9 ~ A26 528 Byte Data Address & Data Input 11h tDBSY Last Plane Input & Program A0 ~ A7 A9 ~ A16 A17 ~ A24 A25,A26 tDBSY Ex.) Four-Plane Page Program into Plane 0~3 or Plane 4~7 Column Address Din N 11h Program 1 up to 528 Byte Data Command (Dummy) Serial Input A0 ~ A7 A9 ~ A16 A17 ~ A24 A25,A26 tWB CE CLE tPROG A0 ~ A7 & A9 ~ A26 528 Byte Data Address & Data Input 10h Program Confirm Command (True) 80h Din 527 tWB Multi-Plane Page Program Operation 71h tPROG 10h I/O 71h Read Multi-Plane Status Command K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Multi-Plane Block Erase Operation into Plane 0~3 or Plane 4~7 CLE CE tWC WE tBERS tWB ALE RE I/O0~7 60h A9 ~ A16 A17 ~ A24 A25,A26 DOh 71h I/O 0 Busy R/B Block Erase Setup Command Page(Row) Address Erase Confirm Command Read Multi-Plane Status Command Max. 4 times repeatable * For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command. Ex.) Four-Plane Block Erase Operation tBERS R/B I/O0~7 60h Address 60h Address 60h Address 60h A9 ~ A26 24 Address D0h 71h K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Read ID Operation CLE CE WE ALE RE tREAD I/O 0 ~ 7 90h Read ID Command 00h ECh Address. 1cycle Maker Code Device* Code Device Device Code K9K1G08R0B 78h K9K1G08B0B 79h K9K1G08U0B 79h 90 ID : Access command = 90H Value Description ECh 79h A5h C0h Maker Code Device Code Must be don't -cared Supports Multi Plane Operation (Must be don't-cared for 1.8V device) 25 C0h Multi Plane Code ID Defintition Table 1st Byte 2nd Byte 3rd Byte 4th Byte A5h K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Copy-Back Program Operation CLE CE tWC WE tWB tWB tPROG ALE tR RE R/B 8Ah A0~A7 A9~A16 A17~A24 A25,A26 Column Address A0~A7 A9~A16 A17~A24 A25,A26 Column Address Page(Row) Address 10h 70h I/O0 Read Status Command Page(Row) Address 00h I/O0~7 Busy Busy Copy-Back Data Input Command 26 I/O0=0 Successful Program I/O0=1 Error in Program K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Device Operation PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, serial page read and sequential row read. The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 15s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns(1.8V device : 60ns) cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column address. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to 527 may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command(00h/01h) is needed to move the pointer back to the main area. Figures 9 to 12 show typical sequence and timings for each read operation. 27 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Figure 8. Read1 Operation CLE CE WE ALE tR R/B RE I/O0~7 00h Data Output(Sequential) Start Add.(4Cycle) A0 ~ A7 & A9 ~ A26 (00h Command) 1st half array (01h Command)* 2st half array Data Field Spare Field 1st half array 2st half array Data Field Spare Field * After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. 28 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Figure 9. Read2 Operation CLE CE WE ALE tR R/B RE I/O0~7 50h Data Output(Sequential) Start Add.(4Cycle) Spare Field A0 ~ A3 & A9 ~ A26 (A4 ~ A7 : Dont Care) 1st half array 2nd half array Data Field Spare Field 29 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 for main array and 2 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached technical notes. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state control automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 10. Program & Read Status Operation tPROG R/B I/O0~7 80h Address & Data Input 10h 70h A0 ~ A7 & A9 ~ A26 528 Byte Data I/O0 Pass Fail BLOCK ERASE The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A14 to A26 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 11 details the sequence. Figure 11. Block Erase Operation tBERS R/B I/O0~7 60h Address Input(3Cycle) 70h D0h I/O0 Block Add. : A14 ~ A26 Fail 30 Pass K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Multi-Plane Page Program into Plane 0~3 or Plane 4~7 Multi-Plane Page Program is an extension of Page Program, which is executed for a single plane with 528 byte page registers. Since the device is equipped with eight memory planes, activating the four sets of 528 byte page registers into plane 0~3 or plane 4~7 enables a simultaneous programming of four pages. Partial activation of four planes is also permitted. After writing the first set of data up to 528 byte into the selected page register, Dummy Page Program command (11h) instead of actual Page Program (10h) is inputted to finish data-loading of the current plane and move to the next plane. Since no programming process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate 71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for one of the other planes is inputted with the same command and address sequences. After inputting data for the last plane, actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages into plane 0~3 or plane 4~7 are programmed simultaneously, pass/fail status is available for each page when the program operation completes. The extended status bits (I/O1 through I/O 4) are checked by inputting the Read Multi-Plane Status Register. Status bit of I/O 0 is set to "1" when any of the pages fails. Multi-Plane page Program with "01h" pointer is not supported, thus prohibited. Figure 12. Four-Plane Page Program tDBSY R/B I/O0~7 Data input 80h Address & 11h Data Input A0 ~ A7 & A9 ~ A26 528 Byte Data 80h 11h tDBSY 80h Address & 11h Data Input A0 ~ A7 & A9 ~ A26 528 Byte Data Address & 11h Data Input A0 ~ A7 & A9 ~ A26 528 Byte Data 80h 80h 80h 11h tPROG tDBSY 11h Address & 10h Data Input A0 ~ A7 & A9 ~ A26 528 Byte Data 80h 80h 10h Plane 3 (1024 Block) Plane 0 (1024 Block) Plane 1 (1024 Block) Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 4088 Block 4092 Block 4089 Block 4093 Block 4090 Block 4094 Plane 2 (1024 Block) 31 Block 4091 Block 4095 71h K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Restirction in addressing with Multi Plane Page Program While any block in each plane may be addressable for Multi-Plane Page Program, the four least significant addresses(A9-A13) for the selected pages at one operation must be the same. Figure 13 shows an example where 2nd page of each addressed block is selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure17. Figure 13. Multi-Plane Program & Read Status Operation Block 0 Plane 3 (1024 Block) Plane 2 (1024 Block) Plane 1 (1024 Block) Plane 0 (1024 Block) Block 2 Block 1 Block 3 Page 0 Page 0 Page 0 Page 0 Page 1 Page 1 Page 1 Page 1 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Figure 14. Addressing Multiple Planes 80h Plane 2 11h 80h Plane 0 11h 80h Plane3 80h 11h Plane 1 10h Figure 15. Multi-Plane Page Program & Read Status Operation tPROG R/B Last Plane input I/O0~7 80h Address & Data Input 10h Pass I/O 71h A0 ~ A7 & A9 ~ A26 528 Byte Data Fail Multi-Plane Block Erase into Plane 0~3 or Plane 4~7 Basic concept of Multi-Plane Block Erase operation is identical to that of Multi-Plane Page Program. Up to four blocks, one from each plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command followed by three address cycles) may be repeated up to four times for erasing up to four blocks. Only one block should be selected from each plane. The Erase Confirm command initiates the actual erasing process. The completion is detected by analyzing R/B pin or Ready/Busy status (I/O 6). Upon the erase completion, pass/fail status of each block is examined by reading extended pass/fail status(I/O 1 through I/O 4). Figure 16. Four Block Erase Operation R/B I/O0~7 tBERS 60h Address (3 Cycle) 60h Address (3 Cycle) 60h Address (3 Cycle) 60h Address (3 Cycle) D0h 71h I/O A0 ~ A7 & A9 ~ A26 Fail 32 Pass K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Copy-Back Program The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within the same plane without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with "00h" command and the address of the source page moves the whole 528byte data into the internal buffer. As soon as the device returns to Ready state, Page-Copy Data-input command (8Ah) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to actually begin the programming operation. Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. A14, A15 and A26 must be the same between source and target page. Figure20 shows the command sequence for single plane operation. "When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But if the soure page has a bit error for charge loss, accumulated copy-back operations could also accumulate bit errors. For this reason, two bit ECC is recommended for copy-back operation. " Figure 17. One Page Copy-Back program Operation tR R/B I/O0~7 00h Add.(4Cycles) A0 ~ A7 & A9 ~ A26 Source Address tPROG 8Ah Add.(4Cycles) A0 ~ A7 & A9 ~ A26 Destination Address 33 10h 70h I/O0 Fail Pass K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Multi-Plane Copy-Back Program Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device is equipped with four memory planes, activating the four sets of 528 bytes page registers enables a simultaneous Multi-Plane CopyBack programming of four pages. Partial activation of four planes is also permitted. First, normal read operation with the "00h"command and address of the source page moves the whole 528 byte data into internal page buffers. Any further read operation for transferring the addressed pages to the corresponding page register must be executed with "03h" command instead of "00h" command. Any plane may be selected without regard to "00h" or "03h". Up to four planes may be addressed. Data moved into the internal page registers are loaded into the destination plane addresses. After the input of command sequences for reading the source pages, the same procedure as Multi-Plane Page programming except for a replacement address command with "8Ah" is executed. Since no programming process is involved during data loading at the destination plane address , R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate 71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). After inputting data for the last plane, actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmed simultaneously, pass/fail status is available for each page when the program operation completes. No pointer operation is supported with Multi-Plane Copy-Back Program. Once the Multi-Plane Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase once the Multi-Plane Copy-Back Program is finished. Figure 18. Four-Plane Copy-Back Program Max Three Times Repeatable Source Address Input 00h Plane 0 (1024 Block) 03h 03h 03h Plane 3 (1024 Block) Plane 2 (1024 Block) Plane 1 (1024 Block) Block 0 Block 4 Block 1 Block 5 Block 2 Block 3 Block 6 Block 7 Block 4088 Block 4092 Block 4089 Block 4093 Block 4090 Block 4094 Block 4091 Block 4095 Max Three Times Repeatable Destination Address Input 8Ah 11h 8Ah 11h 8Ah 11h 8Ah 10h Plane 3 (1024 Block) Plane 0 (1024 Block) Plane 1 (1024 Block) Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 4088 Block 4092 Block 4089 Block 4093 Block 4090 Block 4094 34 Plane 2 (1024 Block) Block 4091 Block 4095 I/OX R/B 00h 03h tR A0 ~ A7 & A9 ~ A25 Source Address Add.( 4Cyc.) 03h Add.( 4Cyc.) tR 8Ah tDBSY A0 ~ A7 & A9 ~ A25 Source Address Add.(4Cyc.) 11h tDBSY A0 ~ A7 & A9 ~ A25 Destination Address 8Ah Add.(4Cyc.) tPROG 10h A0 ~ A7 & A9 ~ A25 Destination Address 8Ah Max. 4 times (4 Cycle Destination Address Input) repeatable tDBSY : Typical 1us, Max 10us A0 ~ A7 & A9 ~ A25 Destination Address Add.(4Cyc.) 11h Max. 4 times ( 4 Cycle Source Address Input) repeatable tR : Normal Read Busy A0 ~ A7 & A9 ~ A25 Source Address Add.(4Cyc.) tR Figure 19. Four-Plane Copy-Back Page Program (Continued) 71h K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY 35 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle. For Read Status of Multi Plane Program/Erase, the Read Multi-Plane Status command(71h) should be used to find out whether multi-plane program or erase operation is completed, and whether the program or erase operation is completed successfully. The pass/fail status data must be checked only in the Ready condition after the completion of Multi-Plane program or erase operation. Table4. Read Staus Register Definition I/O No. Status I/O 0 Total Pass/Fail Definition by 70h Command I/O 1 Plane 0 Pass/Fail Must be don't -cared Pass : "0"(2) Fail : "1" I/O 2 Plane 1 Pass/Fail Must be don't -cared Pass : "0" (2) Fail : "1" I/O 3 Plane 2 Pass/Fail Must be don't -cared Pass : "0"(2) Fail : "1" I/O 4 Plane 3 Pass/Fail Must be don't -cared Pass : "0" Fail : "1" I/O 5 Reserved Must be don't -cared Must be don't-cared I/O 6 Device Operation I/O 7 Write Protect Pass : "0" Fail : "1" Busy : "0" Protected : "0" Ready : "1" Not Protected : "1" Definition by 71h Command Pass : "0"(1) (2) Busy : "0" Protected : "0" Fail : "1" Ready : "1" Not Protected : "1" NOTE : 1. I/O 0 describes combined Pass/Fail condition for all planes. If any of the selected multiple pages/blocks fails in Program/ Erase operation, it sets "Fail" flag. 2. The pass/fail status applies only to the corresponding plane. 36 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Read ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacture code(ECh), and the device code*, Reserved(A5h), Multi plane operation code(C0h) respectively. A5h must be don't-cared. C0h means that device supports Multi Plane operation but must be don't-cared for 1.8V device. The command register remains in Read ID mode until further commands are issued to it. Figure 20 shows the operation sequence. Figure 20. Read ID Operation 1 CLE tCEA CE WE tAR ALE RE I/O0~7 tWHR 90h 00h Address. 1cycle tREA ECh Device* Code A5h C0h Maker code 37 Multi-Plane code Device Device Code K9K1G08R0B 78h K9K1G08B0B 79h K9K1G08U0B 79h K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer to Figure 21 below. Figure 21. RESET Operation tRST R/B I/O0~7 FFh Table5. Device Status Operation Mode After Power-up After Reset Read 1 Waiting for next command 38 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 25). Its value can be determined by the following guidance. Rp ibusy VCC Ready Vcc 1.8V device - VOL : 0.1V, VOH : VccQ-0.1V 2.7V device - VOL : 0.4V, VOH : VccQ-0.4V 3.3V device - VOL : 0.4V, VOH : 2.4V R/B open drain output VOH CL VOL Busy tf GND Device Figure 22. Rp vs tr ,tf & Rp vs ibusy 39 tr K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Ibusy 300n 200n 1.7 2m tr 100n 3m 30 0.85 90 60 1.7 tf 1K 120 0.57 1.7 1.7 2K 3K Rp(ohm) 0.43 Ibusy [A] tr,tf [s] @ Vcc = 1.8V, Ta = 25C , CL = 30pF 1m 1.7 4K 300n 3m 2.3 Ibusy 200n 100n 2m 1.1 tr 30 2.3 tf 1K 0.75 2.3 2.3 2K 120 90 60 Ibusy [A] tr,tf [s] @ Vcc = 2.7V, Ta = 25C , CL = 30pF 1m 2.3 0.55 4K 3K Rp(ohm) @ Vcc = 3.3V, Ta = 25C , CL = 100pF tr,tf [s] Ibusy 300n 1.2 300 3m 200 0.8 2m 3.6 tf 3.6 3.6 3.6 1K 2K 3K Rp(ohm) 4K 200n tr 100n 100 0.6 Rp value guidance Rp(min, 1.8V part) = Rp(min, 2.7V part) = Rp(min, 3.3V part) = 1.85V VCC(Max.) - VOL(Max.) IOL + IL = 2.5V VCC(Max.) - VOL(Max.) IOL + IL = 3mA + IL 3.2V VCC(Max.) - VOL(Max.) IOL + IL 3mA + IL = 8mA + IL where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr 40 1m Ibusy [A] 400 2.4 K9K1G08R0B K9K1G08B0B K9K1G08U0B FLASH MEMORY Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.7V device), 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down and recovery time of minimum 10s is required before internal circuit gets ready for any command sequences as shown in Figure 23. The two step command sequence for program/erase provides additional software protection. Figure 23. AC Waveforms for Power Transition 1.8V device : ~ 1.5V 2.7V device : ~ 2.0V 3.3V device : ~ 2.5V VCC High WP 10s WE 41 1.8V device : ~ 1.5V 2.7V device : ~ 2.0V 3.3V device : ~ 2.5V