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July 2012
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FXLA104 • Rev. 1.0.9
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
FXLA104
Low-Voltage Dual-Supply 4-Bit Voltage Translator with
Configurable Voltage Supplies and Signal Levels,
3-State Outputs, and Auto Direction Sensing
Features
Bi-Directional Interface between Two Levels:
from 1.1V to 3.6V
Fully Configurable: Inputs and Outputs Tr ack VCC
Non-Preferential Power-Up; Either VCC May Be
Powered Up First
Outputs Switch to 3-State if Either VCC is at GND
Power-Off Protection
Bus-Hold on Data Inputs Eliminates the Need for
Pull-Up Resistors; Do Not Use Pull-Up Res istors on
A or B Ports
Control Input (/OE) Referenced to VCCA Voltage
Available in 16-Terminal UMLP (1.8mm x 2.6mm)
and 12-Terminal, Quad UMLP, 1.8 x 1.8mm
Packages
Direction Control Not Necessary
100Mbps Throughput when Translating Between
1.8V and 2.5V
ESD Protection Exceeds:
- 8kV HBM (per JESD22-A114 & Mil Std 883e
3015.7)
- 2kV CDM (per ESD STM 5.3)
Applications
Cell Phone, PDA, Digital Camera, Portable GPS
Description
The FXLA104 is a configurable dual-voltage supply
translator for both uni-directional and bi-directional
voltage translation bet we en two logic levels. The device
allows translation between voltages as high as 3.6V to
as low as 1.1V. The A port tracks the VCCA level and the
B port tracks the VCCB level. This allows for bi-directi onal
voltage translation over a vari ety of voltage levels: 1.2V,
1.5V, 1.8V, 2.5V, and 3.3V.
The device remains in three-state as long as either
VCC=0V, allowing either VCC to be powered up first.
Internal power-down control circuits place the device in
3-state if either VCC is removed.
The /OE input, when HIGH, disables both the A and B
ports by placing them in a 3-state condition. The /OE
input is supplied by VCCA.
The FXLA104 supports bi-directional translation without
the need for a directi on control pin. The t wo ports of the
device have auto-direction sense capability. Either port
may sense an input signal and transfer it as an output
signal to the other port.
Ordering Information
Part Number Operating
Temperature
Range Top Mark Package Packing
Method
FXLA104UMX -40 to 85°C XJ 16-Terminal UMLP 1.8 x 2.6mm Package 5K Units Tape
and Reel
FXLA104UM12X XJ 12-Terminal, Quad UMLP, 1.8 x 1.8mm Package
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 2
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
Pin Configuration
Figure 1. 16-Pin UMLP (Top Through View) Figure 2. 12-Pin UMLP (Top Through View)
Pin Definitions
16 Pin # 12 Pin # Name Description
1 3 A0 A-Side Inputs or 3-State Outputs
2 4 A1 A-Side Inputs or 3-State Outputs
3 5 A2 A-Side Inputs or 3-State Outputs
4 6 A3 A-Side Inputs or 3-State Outputs
5 NC No Connect
6,7 7 GND Ground
8 8 /OE Output Enable Input
9 9 B3 B-Side Inputs or 3-State Outputs
10 10 B2 B-Side Inputs or 3-State Outputs
11 11 B1 B-Side Inputs or 3-State Outputs
12 12 B0 B-Side Inputs or 3-State Outputs
13 1 VCCB B-Side Power Supply
14,15 NC No Connect
16 2 VCCA A-Side Power Supply
VCCB
NC
NC
VCCA
A
0
A
1
A
2
A
3
NC
GND
GND
/OE
B3 B2 B1 B0
12 11 10 9
8
7
6
5
4321
16
15
14
13
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 3
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
Functional Diagram
Figure 3. Functional Diagram
Function Table
Control Outputs
/OE
LOW Logic Level Normal Operation
HIGH Logic Level 3-State
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 4
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable abov e the recommended operating con ditions and stressin g the parts to these levels is not recommended.
In addition, extended e xposur e to stresses above th e rec omm end ed oper ating c onditio ns may affect de vice relia bil it y.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Conditions Min. Max. Unit
VCC Supply Voltage VCCA -0.5 4.6
V
VCCB -0.5 4.6
VI DC Input Voltage I/O Ports A and B -0.5 4.6 V
Control Input (/OE) -0.5 4.6
VO Output Voltage(2) Output 3-State -0.5 4.6 V Output Active (An) -0.5 VCCA +0.5
Output Active (Bn) -0.5 VCCB +0.5
IIK DC Input Diode Current VIN<0V -50 mA
IOK DC Output Diode Current VO<0V -50
mA
VO>VCC +50
IOH/IOL DC Output Source/Sink Current -50 +50 mA
ICC DC VCC or Ground Current (per Supply Pin) ±100 mA
TSTG Storage Temperature Range -65 +150 °C
PD Power Dissipation 17 mW
ESD Electrostatic Discharge
Capability
Human Body Model (per JESD22-
A114 & Mil Std 883e 3015.7) 8
kV
Charged Device Mode l
(per ESD STM 5.3) 2
Notes:
1. IO absolute maximum ratings must be observed.
2. All unused inputs and input/outputs must be held at VCCi or GND.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designi ng to Absolute Maximum Ratings.
Symbol Parameter Conditions Min. Max. Unit
VCC Power Supply Operating VCCA or VCCB 1.1 3.6 V
VIN Input Voltage Ports A and B 0 3.6 V
Control Input (/OE) 0 VCCA V
TA Operating Temperature, Fr ee Air -40 +85 °C
dt/dV Minimum Input Edge Rate VCCA/B = 1.1 to 3.6V 10 ns/V
ΘJA Thermal Resistance:
Junction-to-Ambient UMLP-16 315
°C/W
UMLP-12 300
ΘJC Thermal Resistance:
Junction-to-Case UMLP-16 155
°C/W
UMLP-12 165
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 5
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
Power-Up/Power-D own Sequence
FXL translators offer an advantage in that either VCC
may be powered up first. This benefit derives from the
chip design. When either VCC is at 0V, outputs are in a
high-impedance state. The control input (/OE) is
designed to track the VCCA supply. A pull-up resistor
tying /OE to VCCA should be used to ensure that bus
contention, excessive currents, or oscillations do not
occur during power-up or power-down. The size of the
pull-up resistor is based upon the current-sinking
capability of the device driving the /OE pin.
The recommended power-up sequence is:
1. Apply power to the first VCC.
2. Apply power to the second VCC.
3. Drive the /OE input LOW to enable the device.
The recommended power-down sequence is:
1. Drive /OE input HIGH to disable the device.
2. Remove power from either VCC.
3. Remove power from other VCC.
Pull-Up/Pull-Down Resistors
Do not use pull-up or pull-down resistors. This device
has bus-hold circuits: pull-up or pull-down resistors are
not recommended because they interfere with the
output state. The current through these resistors may
exceed the hold drive, II(HOLD) and/or II(OD) bus-hold
currents, resulting in data transition and/or auto-
direction sensing failures. The bus-hold feature
eliminates the need for extra resistors.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 6
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
DC Electrical Characteristics
TA=-40 to 85°C
Symbol Parameter Conditions VCCA (V) VCCB (V) Min. Typ. Max. Units
VIHA
High-Level Input Voltage
Data Inputs An
Control Pin /OE
2.70 to 3.60
1.10 to 3.60
2.00
V
2.30 to 2.70 1.60
1.65 to 2.30 .65xVCCA
1.40 to 1.65 .65xVCCA
1.10 to 1.40 .90xVCCA
VIHB Data Inputs Bn 1.10 to 3.60
2.70 to 3.60 2.00
V
2.30 to 2.70 1.60
1.65 to 2.30 .65xVCCB
1.40 to 1.65 .65xVCCB
1.10 to 1.40 .90xVCCB
VILA
Low-Level Input Voltage
Data Inputs An
Control Pin /OE
2.70 to 3.60
1.10 to 3.60
.80
V
2.30 to 2.70 .70
1.65 to 2.30 .35xVCCA
1.40 to 1.65 .35xVCCA
1.10 to 1.40 .10xVCCA
VILB Data Inputs Bn 1.10 to 3.60
2.70 to 3.60 .80
V
2.30 to 2.70 .70
1.65 to 2.30 .35xVCCB
1.40 to 1.65 .35xVCCB
1.10 to 1.40 .10xVCCB
VOHA High-Level Output
Voltage(3) IOH=-4µA 1.10 to 3.60 1.10 to 3.60 VCCA -.4 V
VOHB I
OH=-4µA 1.10 to 3.60 1.10 to 3.60 VCCB - .4
VOLA Low-Level Output
Voltage(3) IOL=4µA 1.10 to 3.60 1.10 to 3.60 .4 V
VOLB I
OL=4µA 1.10 to 3.60 1.10 to 3.60 .4
II(HOLD) Bus-Hold Input Minimum
Drive Current
VIN=0.8V 3.00 3.00 75.0
µA
VIN=2.0V 3.00 3.00 -75.0
VIN=0.7V 2.30 2.30 45.0
VIN=1.6V 2.30 2.30 -45.0
VIN=0.57V 1.65 1.65 25.0
VIN=1.07V 1.65 1.65 -25.0
VIN=0.49V 1.40 1.40 11.0
VIN=0.91V 1.40 1.40 -11.0
VIN=0.11V 1.10 1.10 4.0
VIN=0.99V 1.10 1.10 -4.0
Note:
3. This is the output voltage for static conditions. Dynamic drive specifications are given in the Dynamic Output
Electrical Characteristics table.
Continued on following page…
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 7
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
DC Electrical Characteristics (Continued)
TA=-40 to 85°C.
Symbol Parameter Conditions VCCA (V) VCCB (V) Min. Max. Units
II(ODH) Bus-Hold Input
Overdrive High
Current(4) Data Inputs An, Bn
3.60 3.60 450.0
µA
2.70 2.70 300.0
1.95 1.95 200.0
1.60 1.60 120.0
1.40 1.40 80.0
II(ODL) Bus-Hold Input
Overdrive Low
Current(5) Data Inputs An, Bn
3.60 3.60 -450.0
µA
2.70 2.70 -300.0
1.95 1.95 -200.0
1.60 1.60 -120.0
1.40 1.40 -80.0
II Input Leakage Current Control Inputs /OE,
VI=VCCA or GND 1.10 to 3.60 3.60 ±1.0 µA
IOFF Power-Off Leakage
Current An VO=0V to 3.6V 0 3.60 ±2.0 µA
Bn VO=0V to 3.6V 3.60 0 ±2.0
IOZ 3-State Output
Leakage
An, Bn VO=0V or 3.6V,
/OE=VIH 3.60 3.60 ±5.0
µA
An VO=0V or 3.6V,
/OE=GND 3.60 0 ±5.0
Bn VO=0V or 3.6V,
/OE=GND 0 3.60 ±5.0
ICCA/B Quiescent Supply
Current(6, 7)
VI=VCCI or GND; IO=0,
/OE=GND 1.10 to 3.60 1.10 to 3.60 10.0 µA
ICCZ VI=VCCI or GND; IO=0,
/OE=VIH 1.10 to 3.60 1.10 to 3.60 10.0 µA
ICCA
Quiescent Supply
Current
VI=VCCB or GND; IO=0
B-to-A Direction,
/OE=GND 0 1.10 to 3.60 -10.0 µA
VI=VCCA or GND; IO=0
A-to-B Direction 1.10 to 3.60 0 10.0
ICCB
VI=VCCA or GND; IO=0,
A-to-B Direction,
/OE=GND 1.10 to 3.60 0 -10.0 µA
VI=VCCB or GND; IO=0
B-to-A Direction 0 1.10 to 3.60 10.0
Notes:
4. An external drive must source at least the specified current to switch LOW-to-HIGH.
5. An external drive must source at least the specified current to switch HIGH-to-LOW.
6. VCCI is the VCC associated with the input side.
7. Reflects current per supply, VCCA or VCCB.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 8
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
Dynamic Output Electrical Characteristic
A Port (An)
Output Load: CL=15pF, RL ≥ MΩ (CI/O=4pF), TA=-40 to 85°C
Symbol Parameter VCCA=3.0V
to 3.6V VCCA=2.3V
to 2.7V VCCA=1.65V
to 1.95V VCCA=1.4V
to 1.6V VCCA=1.1V
to 1.3V Units
Typ. Max. Typ. Max. Typ. Max Typ. Max. Typ.
trise Output Rise
Time A Port(9) 3.0 3.5 4.0 5.0 7.5 ns
tfall Output Fall
Time A
Port(10) 3.0 3.5 4.0 5.0 7.5 ns
IOHD
Dynamic
Output
Current
High(9)
-11.4 -7.5 -4.7 -3.2 -1.7 mA
IOLD
Dynamic
Output
Current
Low(10)
+11.4 +7.5 +4.7 +3.2 +1.7 mA
B Port (Bn)
Output Load: CL=15pF, RL ≥ MΩ (CI/O=5pF), TA=-40 to 85°C
Symbol Parameter VCCB=3.0V
to 3.6V VCCB=2.3V
to 2.7V VCCB=1.65V
to 1.95V VCCB=1.4V
to 1.6V VCCB=1.1V
to 1.3V Units
Typ. Max. Typ. Max. Typ. Max Typ. Max. Typ.
trise Output Rise
Time B Port(9) 3.0 3.5 4.0 5.0 7.5 ns
tfall Output Fall
Time B
Port(10) 3.0 3.5 4.0 5.0 7.5 ns
IOHD
Dynamic
Output
Current
High(9)
-12.0 -7.9 -5.0 -3.4 -1.8 mA
IOLD
Dynamic
Output
Current
Low(10)
+12.0 +7.9 +5.0 +3.4 +1.8 mA
Notes:
8. Dynamic output characteristics are guaranteed, but not tested.
9. See Figure 8.
10. See Figure 9.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 9
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
AC Characteristics
VCCA = 3.0V to 3.6V, TA=-40 to 85°C
Symbol Parameter VCCB=3.0V
to 3.6V VCCB=2.3V
to 2.7V VCCB=1.65V
to 1.95V VCCB=1.4V
to 1.6V VCCB=1.1V
to 1.3V Units
Min. Max. Min. Max. Min. Max Min. Max. Typ.
tPLH,tPHL A to B 0.2 4.0 0.3 4.2 0.5 5.4 0.6 6.8 6.9 ns
B to A 0.2 4.0 0.2 4.1 0.3 5.0 0.5 6.0 4.5 ns
tPZL,tPZH /OE to A,
/OE to B 1.7 1.7 1.7 1.7 1.7 µs
tSKEW A Port,
B Port(11) 0.5 0.5 0.5 1.0 1.0 ns
VCCA = 2.3V to 2.7V, TA=-40 to 85°C
Symbol Parameter VCCB=3.0V
to 3.6V VCCB=2.3V
to 2.7V VCCB=1.65V
to 1.95V VCCB=1.4V
to 1.6V VCCB=1.1V
to 1.3V Units
Min. Max. Min. Max. Min. Max Min. Max. Typ.
tPLH,tPHL A to B 0.2 4.1 0.4 4.5 0.5 5.6 0.8 6.9 7.0 ns
B to A 0.3 4.2 0.4 4.5 0.5 5.5 0.5 6.5 4.8 ns
tPZL,tPZH /OE to A,
/OE to B 1.7 1.7 1.7 1.7 1.7 µs
tSKEW A Port,
B Port(11) 0.5 0.5 0.5 1.0 1.0 ns
VCCA = 1.65V to 1.95V, TA=-40 to 85°C
Symbol Parameter VCCB=3.0V
to 3.6V VCCB=2.3V
to 2.7V VCCB=1.65V
to 1.95V VCCB=1.4V
to 1.6V VCCB=1.1V
to 1.3V Units
Min. Max. Min. Max. Min. Max Min. Max. Typ.
tPLH,tPHL A to B 0.3 5.0 0.5 5.5 0.8 6.7 0.9 7.5 7.5 ns
B to A 0.5 5.4 0.5 5.6 0.8 6.7 1.0 7.0 5.4 ns
tPZL,tPZH /OE to A,
/OE to B 1.7 1.7 1.7 1.7 1.7 µs
tSKEW A Port,
B Port(11) 0.5 0.5 0.5 1.0 1.0 ns
Note:
11. Skew is the variation of propagatio n delay between output signals an d applies only to output signals on th e
same port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 11).
Skew is guaranteed, but not tested.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 10
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
AC Characteristics (Continued)
VCC=1.4V to 1.6V, TA=-40 to 85°C
Symbol Parameter VCCB=3.0V
to 3.6V VCCB=2.3V
to 2.7V VCCB=1.65V
to 1.95V VCCB=1.4V
to 1.6V VCCB=1.1V
to 1.3V Units
Min. Max. Min. Max. Min. Max Min. Max. Typ.
tPLH,tPHL A to B 0.5 6.0 0.5 6.5 1.0 7.0 1.0 8.5 7.9 ns
B to A 0.6 6.8 0.8 6.9 0.9 7.5 1.0 8.5 6.1 ns
tPZL,tPZH /OE to A,
/OE to B 1.7 1.7 1.7 1.7 1.7 µs
tSKEW A Port,
B Port(12) 1.0 1.0 1.0 1.0 1.0 ns
VCCA=1.1V to 1.3V, TA=-40 to 85°C
Symbol Parameter VCCB=3.0V
to 3.6V VCCB=2.3V
to 2.7V VCCB=1.65V
to 1.95V VCCB=1.4V
to 1.6V VCCB=1.1V
to 1.3V Units
Typ. Typ. Typ. Typ. Typ.
tPLH,tPHL A to B 4.6 4.8 5.4 6.2 9.2 ns
B to A 6.8 7.0 7.4 7.8 9.1 ns
tPZL,tPZH /OE to A, /OE to B 1.7 1.7 1.7 1.7 1.7 µs
tSKEW A Port, B Port(12) 1.0 1.0 1.0 1.0 1.0 ns
Note:
12. Skew is the variation of propagatio n delay between output signals an d applies only to output signals on th e
same port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 11).
Skew is guaranteed, but not tested.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 11
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
Maximum Data Rate(13, 14)
TA=-40 to 85°C
VCCA VCCB=3.0V
to 3.6V VCCB=2.3V
to 2.7V VCCB=1.65V
to 1.95V VCCB=1.4V
to 1.6V VCCB=1.1V to
1.3V Units
Min. Min. Min. Min. Typ.
VCCA=3.00V to 3.60V 140 120 100 80 40 Mbps
VCCA=2.30V to 2.70V 120 120 100 80 40 Mbps
VCCA=1.65V to 1.95V 100 100 80 60 40 Mbps
VCCA=1.40V to 1.60V 80 80 60 60 40 Mbps
VCCA=1.10V to 1.30V Typ. Typ. Typ. Typ. Typ.
40 40 40 40 40 Mbps
Notes:
13. Maximum data rate is guaranteed, but not tested.
14. Maximum data rate is specified in megabits per second (see Figure 10). It is equivalent to t wo times the
F-toggle frequency, specified i n megahertz. For example, 100Mbps is equivalent to 50MHz.
Capacitance
Symbol Parameter Conditions TA=+25°C
Typical Units
CIN Input Capacitance Control Pin (/OE) VCCA=VCCB=GND 3 pF
CI/O Input/Output Capacitance
An VCCA=VCCB=3.3V, /OE=VCCA 4 pF
Bn 5
Cpd Power Dissipation Capacitance VCCA=VCCB=3.3V, VI=0V or VCC, f=10MHz 25 pF
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 12
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
I/O Architecture Benefit
The FXLA104 I/O architecture benefits the end user,
beyond level transl ation, in the following three ways:
Auto Direction without an external direction pin.
Drive Capacitive Loads. Automatically shifts to a
higher current drive mode only during “Dynamic Mode”
or HL / LH transitions.
Lower Power Consumption. Automatically shifts to
low-power mode during “Static Mode” (no transitions),
lowering power consumption.
The FXLA104 does not require a direction pin. Instead,
the I/O architecture detects input transitions on both
side and automatically transfers the data to the
corresponding output. For e xample, for a given chan nel,
if both A and B side are at a static LOW, the direction
has been established as A B, and a LH transition
occurs on the B port; the FXLA104 internal I/O
architecture automaticall y changes dir ection from A B
to B A.
During HL / LH transitions, or “D ynamic Mode,” a strong
output driver drives the outpu t channel in parallel with a
weak output driver. After a typical delay of
approximately 10ns – 50ns, the strong driver is turned
off, leaving the weak driver enabled for holding the logic
state of the channel. This weak driver is called the “bus
hold.” “Static Mode” is when only the bus h old drives th e
channel. The bus hold can be over ridden in the event
of a direction change. The strong driver allows the
FXLA104 to quickly charge and discharge capacitive
transmission lines during dynamic mode. Static mode
conserves power, where ICC is typically < 5µA.
Bus Hold Minimum Drive Current
Specifies the minimum amount of current the bus hold
driver can source/sink. The bus hold minimum drive
current (IIHOLD) is VCC dependent and guaranteed in the
DC Electrical tables. The intent is to maintain a valid
output state in a static m ode, but that can b e overridden
when an input data transition occurs.
Bus Hold Input Overdrive Drive Current
Specifies the minimum amount of current required (by
an external device) to overdrive the bus hold in the
event of a direction change. The bus hold overdrive
(IIODH, IIODL) is VCC dependent and gu aranteed in the DC
Electrical tables.
Dynamic Output Current
The strength of the output driver during LH / HL
transitions is referenced on page 8, Dynamic Output
Electrical Characteristics, IOHD, and IOLD.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 13
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
Test Diagrams
Figure 4. Test Circuit
Table 1. AC Test Conditions
Test Input Signal Output Enable Control
tPLH, tPHL Data Pulses 0V
tPZL 0V HIGH to LOW Switch
tPZH V
CCI HIGH to LOW Switch
Table 2. AC Load
Figure 5. Waveform for Inverting and Non-Inverting Functions
Notes:
15. Input tR = tF = 2.0ns, 10% to 90%.
16. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only.
V
CC
DUT
C1 R1
TEST
SIGNAL
V
CCI
V
CCO
GND
DATA
IN
DATA
OUT
t
pxx
t
pxx
V
mi
V
mo
VCCo C1 R1
1.2V± 0.1V 15pF 1MΩ
1.5V± 0.1V 15pF 1MΩ
1.8V ± 0.15V 15pF 1MΩ
2.5V ± 0.2V 15pF 1MΩ
3.3V ± 0.3V 15pF 1MΩ
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 14
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
Figure 6. 3-State Output Low Enable Time for Low Voltage Logic
Notes:
17. Input tR = tF = 2.0ns, 10% to 90%.
18. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only.
Figure 7. 3-State Output High Enable Time fo r Low Voltage Logic
Notes:
19. Input tR = tF = 2.0ns, 10% to 90%.
20. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only.
Table 3. Test Measure Points
Symbol VDD
VMI(21) V
CCI /2
VMO V
CCo /2
VX 0.9 x VCCo
VY 0.1 x VCCo
Note:
21. VCCI=VCCA for control pin /OE or VMI(VCCA/2).
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 15
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
RISE
CCO
OIL
OUT
OILOHD tV
CC
t
V
CCI •−
×+=
Δ
Δ
×+≈ %)80%20(
)()( //
Figure 8. Active Output Rise Time and Dynamic Output Current High
FALL
CCO
OIL
OUT
OILOLD tV
CC
t
V
CCI •−
×+=
Δ
Δ
×+≈ %)20%80(
)()( //
Figure 9. Active Output Fall Time and Dynamic Output Current Low
Figure 10. Maximum Data Rate
Figure 11. Output Skew Time
Note:
22. tSKEW = (tpHLmax – tpHLmin) or (tpLHmax – tpLHmin)
t
rise
80% x V
CCO
20% x V
CCO
V
OH
V
OL
V
OUT
Time
t
fall
80% x V
CCO
20% x V
CCO
V
OL
V
OH
V
OUT
Time
VCCI
VCCI/2 VCCI/2 GND
DATA
IN
tW
Maximum Data Rate, f = 1/tW
V
CCO
V
mo
t
skew
t
skew
V
mo
GND
DATA
OUTPUT
V
CCO
V
mo
V
mo
GND
DATA
OUTPUT
© 2009 Fairchild Semiconductor Corporat ion www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 16
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
Physical Dimensions
Figure 12. 16-Lead, UMLP, QUAD, Ultra-Thin MLP, 1.8 X 2.6mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’ s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
RECOMMENDED
LAND PATTERN
NOTES:
A. PACKAGE DOES NOT FULLY CONFORM TO
JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY.
E. DRAWING FILENAME: MKT-UMLP16Arev4.
F. TERMINAL SHAPE MAY VARY ACCORDING
TO PACKAGE SUPPLIER, SEE TERMINAL
SHAPE VARIANTS.
SCALE : 2X
LEAD
OPTION 1 SCALE : 2X
LEAD
OPTION 2
PIN#1 IDENT
PIN#1 IDENT
PACKAGE
EDGE
TOP VIEW
BOTTOM VIEW
0.10 C
0.08 C
2.60
1.80
0.10 C
2X
2X
SIDE VIEW
0.10 C
0.05
0.00
0.10 C A B
0.05 C
0.55 MAX.
0.40
1
5
9
13
16
2.10
2.90
0.40
0.663 0.563
0.225
1
(15X)
(16X)
0.152
0.40
0.60
0.10 0.30
0.50
0.10
TERMINAL SHAPE VARIANTS
0.15
0.25 15X
PIN 1 NON-PIN 1
0.15
0.25
15X
0.30
0.50
0.15
0.25 0.30
0.50
0.15
0.25 15X
15X
Supplier 1
Supplier 2
PIN 1 NON-PIN 1
AB
C
SEATING
PLANE
0.45
0.35
0.55
0.45 0.25
0.15
R0.20
© 2009 Fairchild Semiconductor Corporat ion www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 17
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
Physical Dimensions
Figure 13. 12-Lead, UMLP, QUAD, JEDEC MO-252 1.8 x 1.8mm Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’ s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
AB
C
SEATING
PLANE
RECOMMENDED
LAND PATTERN
NOTES:
A. PACKAGE DOES NOT FULLY CONFORM TO
JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY.
E. DRAWING FILENAME: MKT-UMLP12Arev4.
SCALE : 2X
LEAD
OPTION 1 SCALE : 2X
LEAD
OPTION 2
DETAIL A
SCALE : 2X
PIN#1 IDENT
TOP VIEW
BOTTOM VIEW
0.10 C
0.08 C
0.10 C
2X
2X
SIDE VIEW
0.10 C
0.05
0.00
36
1
0.10 CAB
0.05 C
0.55 MAX.
12
1.80
1.80
0.40
0.25
0.15(12X)
0.35
0.45
2.10
2.10
0.40
0.563
(11X)
0.20
(12X)
1
0.152
9
0.588
DETAIL A
PIN#1 IDENT
(11X)
PACKAGE
EDGE
0.10
0.10
0.45
0.35
0.10
© 2009 Fairchild Semiconductor Corporat ion www.fairchildsemi.com
FXLA104 • Rev. 1.0.9 18
FXLA104 — Low-Voltage Dual-Supply 4-Bit Voltage Translator
www.onsemi.com
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