MOTOROLA MC1445 TECHNICAL DATA Gate Controlled Two Channel GATE CONTROLLED Input Wideband Amplifier TWO CHANNEL INPUT The MC 1445/1545 was designed for use as a general purpose gated wideband WIDEBAND AMPLIFIER amplifier, video switch, sense amplifier, multiplexer, modulator, FSK circuit, limiter, AGC circuit, or pulse amplifier. SILICON MONOLITHIC Large Bandwidth: 50 MHz Typical INTEGRATED CIRCUIT Channel Select Time of 20 ns Typical Differential Inputs and Differential Output Typical Applications we Video Switch or Multiplex or FSK 14 Differential Amplifier with AGC 1 Vec Ve a . = L SUFFIX Signal Input & Channel CERAMIC PACKAGE i eout input out CASE 632 + Channel 2 Gat Input AGC Input np panne Select Amplitude Modulator Pulse Width Modulator PIN CONNECTIONS RF ee Vee m Vv V ce EE input Pua Output [7 | Ly NC Cout me Gate f2} [13] NC gout Noninv. | [3] [72] NC Input B Inv. Audio input m [4] i] NC Modulation Agjust Open Iman | [5H ji] NC = Inv. [6 F [2] Vee Output [7 [2] Vee Balanced Modulator Analog Switch (Top View) Voc Vee Voc VEE ee ~~ Signal Carrier out Input Sout Input 51 ORDERING INFORMATION = + ov Device Temperature Range Package Inost Blas Aust LM1445L 0 to +75C Ceramic DIP LM1545L 55 to +125C Ceramic DIP MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-95MC1445, MC1545 MAXIMUM RATINGS (Ta = +25C, unless otherwise noted.) Rating Symbol Value Unit Power Supply Voltage Voc +12 Vde VEE -12 Input Differential Voltage Range VIDR +5.0 v Load Current IL 25 mA Power Dissipation (Package Limitation) Pp Ceramic Dual In-Line Package 625 mw Derate above Ta = +25C 5.0 mw/ec Operating Ambient Temperature Range MC1445 TA 0 to +75 C MC 1545 55 to +125 Storage Temperature Range Tstg -65 to +150 C ELECTRICAL CHARACTERISTICS (Vcc = +5.0 Vdc, Veg = -5.0 Vdc, @ Ta = +25C, specifications apply to both input channels, unless otherwise noted.) MC 1545 MC1445 Characteristics Fig. No. Symbol Min Typ Max Min Typ | Max Unit Single-Ended Voltage Gain 1,12 AVS 16 19 21 16 19.5 23 dB Bandwidth 1,12 BW 40 50 _ _ 50 _ MHz Input Impedance 5, 14 Zj 4.0 10 _ 3.0 10 _ kQ (f = 50 kHz) Output Impedance 6, 15 Zo _ 25 _ 25 _ Q (f = 50 kHz) Output Differential Voltage Range 4,13 VopoR 15 25 _ 15 25 _ Vp-p (RL = 1.0 kQ, f = 50 kHz) Input Bias Current 16 \B _ 15 25 - 15 30 pAdc Input Offset Current 16 lio 2.0 _ _ 2.0 _ pAdc Input Offset Voltage 17 VIO _ 1.0 5.0 _ _ 7.5 mVdc Quiescent Output de Level 17 Vo - 0.1 _ _ 0.1 _ Vde Output de Level Change 17 AVO _ +15 _ _ +15 _ mv (Gate Input Voltage Change: +5.0 V to 0 V) Common Mode Rejection 9, 18 CMR _ 85 _ _ 85 dB (f = 50 kHz) Input Common Mode Voltage Range 18 VICR _ 42.5 _ _ +2.5 _ Vpk Gate Characteristics 8 Vde Gate Input Voltage Low Logic State (Note 1) VIL(G) 0.40 | 0.70 _ 0.2 0.4 _ Gate Input Voltage High Logic State (Note 2) VIH(G) _ 15 2.2 1.3 3.0 Gate Input Current Low Logic State 18 liLa@) _ _ 2.5 _ _ 4.0 mA (ViL(G) = 9 V) Gate Input Current High Logic State 18 NH(G) _ 2.0 _ _ 4.0 hA (VIH(G) = +5.0 V) Step Response 19 tPLH - 6.5 10 _ 6.5 _ ns (ein = 20 mV) {PHL _ 6.3 10 _ 6.3 _ tTLH _ 6.5 15 _ 6.5 _ tTHL _ 7.0 15 _ 7.0 _ Wideband Input Noise 10, 20 en _ 25 _ _ 25 _ uVi(rms) (5.0 Hz 10 MHz, Rg = 50 9) DC Power Consumption 11, 20 Pc _ 70 110 - 70 150 mW NOTES: 1. ViL(q) is the gate voltage which results in channel A gain of unity or less and channel B gain of 16 dB or greater. 2. ViH(G) is the gate voltage which results in channel B gain of unity or less and channel A gain of 16 dB or greater. MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-96Ayg, SINGLE-ENDED VOLTAGE GAIN (dB) Avg, SINGLE-ENDED VOLTAGE GAIN (dB) Rp PARALLEL INPUT RESISTANCE (k Q) MC1445, MC1545 Figure 1. Single-Ended Voltage Gain Figure 2. Single-Ended Voltage Gain versus Frequency versus Temperature 25 2 a 2 20 2 <= wy 20 15 , 5 a (15 ly 10 | 9 a Ww oe 10 5.0 g a wn 0 59 0.01 0.1 1.0 10 100 1000 55-25 0 25 50 75 100 125 f, FREQUENCY (kHz} Ta, AMBIENT TEMPERATURE (C) Figure 3. Voltage Gain versus Figure 4. Output Voltage Swing Power Supply Voltages versus Load Resistance 25 LS | Lee | 20 RANGE (Vp-p ) f= 50 kHz 10 VODR, OUTPUT DIFFERENTIAL VOLTAGE 4.0 50 60 70 80 90 10 i 12 0.1 0.2 05 10 2.0 5.0 10 20 Voc; Vee, POWER SUPPLY VOLTAGE (+ Vdc) Ri, LOAD RESISTANCE (kQ) Figure 5. Input Cp and Rp versus Frequency (Both Channels) Figure 6. Output Impedance versus Frequency 14 7.0 200 Cp & _ 180 12 60 w S$ Q S 16 to 50 & 2 140 <x a a 5 5 10 80 2 a0 204 8 60 = 4 1 & Virms) = 30 mV "= 20 a 0 0 1.0 50 10 50100 0.01 01 1.0 10 100 f, FREQUENCY (kHz} , FREQUENCY (kHz} MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-97MC1445, MC1545 Figure 7. Channel Separation versus Frequency Figure 8. Gate Characteristics 140 TTT 1111 a 20 ae Channel Sepration = * a @ 120 ~~ A Vo H = +10 z= NJ = 20logAy-20log ~ o z be Vi Ww 0 J O1 ++ fe 100 & -10 7 e N 3 = 80F = -20 4 & ne a 3 a 60+ ~ a7 0 7 z NN uy 49 J = 4b 3 / oO = -50 4 i a oO 20F % -60 4 < 0 L Lits -70 1 J 1 192 106 107 198 0 0.5 1.0 15 2.0 25 fin, INPUT FREQUENCY (Hz) Vg, GATE VOLTAGE (V) Figure 9. Common Mode Rejection Ratio Figure 10. Input Wideband Noise versus Frequency versus Source Resistance g 33 Q = TUM TT Term i} & E Bandwidth = 5.0 Hz to 10 MHz Y z = 3 Y = a | e lu 5 o "4 w < uw E23 6 [oa o Lar wi > LY a Wy on Qo n 97 = 3 Cae z 2 Le Z 2 rT 9 Zz 2 oO < oc o 3 23 0.01 Ot 1.0 10 100 10 100 1.0k 10k 100k f, FREQUENCY (MHz) Rg, SOURCE RESISTANCE (Q) Figure 12. Single-Ended Voltage Gain Figure 11. Circuit Schematic and Bandwidth Test Circuit e 0 Voc 45.0V -5.0V C t r im t - Output + .0k $9.0 $5.0k 3 5.0K Signal Generator CL = 15 pF and includes jig i. = = and voltmeter capacitance. wr Boonton RF Voltmeter Vj = 20 mV(mns) . or Equivalent 4.0k 500 Vv , ore MOTOROLA LINEAR/INTERFACE iCs DEVICE DATA 2-98MC1445, Figure 13. Output Voltage Swing Test Circuit +5.0V -5.0V f= 50 kHz Vj = 200 mV(rms) Figure 15. Output Impedance Test Circuit To AC MC1545 Figure 14. Input Impedance Test Circuit f= 50 kHz +6.0V -5.0V Vj = 50 mV(rms) To AC Voltmeter 5.1k = = 5.0k (41%) = Voltmeter Figure 16. Input Bias Current and Input Offset Current Test Circuit +5.0V -5.0V Voltmeter +5.0V 0 | b O 50k (+1%) 51 | - + L | Lis f = 50 kHz tL lio is the difference Vj = 50 mV(rms) ~ | in current reading when either S1 or S2 Open a is switched. Figure 17. Input Offset Voltage and Quiescent Output Level Test Circuit Adjust R1 until Vi reads OV then tead Ege. Ri 5.1k (1%) 9 100k 10 Tums r | Voide) = V2 -5.0V | _ Ede | MiO = jog AVo = change in reading 1 switch S; and readjust Ry for Vy = 0 +5.0V t 1 +5.0V Figure 18. Gate Current (High and Low), Common Mode Rejection and Common Mode Input Range Test Circuit -.0V MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-99MC1445, MC1545 Figure 19. Propagation Delay, Rise and Fall Times Test Circuit To A Channel of Scope +5.0V -5.0V Scope Tektronix 567 or equivalent Pulse Gen. T To B channel of scope rT 4 Cy.= 15 pF including probe and Vj =20mV jig capacitance tTLH = tTHL < 5.0 ns Open Vop , DIFFERENTIAL OUTPUT VOLTAGE (Vp-p) Figure 20. Power Dissipation and Wideband Input Noise Test Circuit True rms voltmeter with bandwidth of 5.0 Hz to 10 MHz. 0 Vo + n Avs Pp = 5.0 V (icc +lEE) Figure 21. Limiting Characteristic Voc = +5.0V 10k Vo 0 100 200 300 400 500 Vj, SINGLE ENDED INPUT VOLTAGE (mVp_p) MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-100