VTD48EF015T115A00 - Vicor Corporation

FEATURES

•48 Vdc to 1.5 Vdc 115 A current multiplier

- Operating from standard 48 V or 24 V PRM™ regulators

•High efficiency (>94%) reduces system power

consumption

•High density (392 A/in3)

•“Full Chip” VI Chip®package enables surface mount,

low impedance interconnect to system board

•Contains built-in protection features against:

- Overvoltage

- Overcurrent

•Provides enable / disable control,

internal temperature monitoring

•ZVS / ZCS resonant Sine Amplitude Converter topology

•Less than 50 ºC temperature rise at full load

in typical applications

TYPICAL APPLICATIONS

•High End Computing Systems

•Automated Test Equipment

•High Density Power Supplies

•Communications Systems

DESCRIPTION

The VI Chip®current multiplier is a high efficiency (>94%) Sine

Amplitude Converter™ (SAC™) operating from a 26 to 55 Vdc

primary bus to deliver an isolated output. The Sine Amplitude

Converter offers a low AC impedance beyond the bandwidth

of most downstream regulators; therefore capacitance normally

at the load can be located at the input to the Sine Amplitude

Converter. Since the K factor of the VTM48EF015T115A00 is

1/32, the capacitance value can be reduced by a factor of 1024,

resulting in savings of board area, materials and total system cost.

The VTM48EF015T115A00 is provided in a VI Chip®package

compatible with standard pick-and-place and surface mount

assembly processes. The co-molded VI Chip®package provides

enhanced thermal management due to a large thermal

interface area and superior thermal conductivity. The high

conversion efficiency of the VTM48EF015T115A00 increases

overall system efficiency and lowers operating costs compared

to conventional approaches.

The VTM48EF015T115A00 enables the utilization of Factorized

Power Architecture™ which provides efficiency and size

benefits by lowering conversion and distribution losses and

promoting high density point of load conversion.

NRTL

CUS

VTM Current Multiplier

High Efficiency, Sine Amplitude Converter™

VTM®Current Multiplier Rev 3.5 vicorpower.com

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CUS

VTM48EF015T115A00

VIN = 26 to 55 V

VOUT = 0.8 to 1.7 V(NO LOAD)

IOUT = 115 A(NOM)

K = 1/32

PART NUMBER DESCRIPTION

VTM48EF015T115A00 -40°C to 125°C TJ

PRMTM

Regulator

PRPC TM

+IN

-IN

IF RE SG VC

-OUT

+OUT

Load

38 to 55

Vdc Input

Current

Sense

Enable/

Disable

Feedback

Voltage

Reference

Voltage

Control

+IN

-IN

+OUT1

+OUT2

-OUT1

-OUT2

+IN

-IN

+OUT1

+OUT2

-OUT1

-OUT2

Constant

TYPICAL APPLICATION

VTM48EF015T115A00

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VTM48EF015T115A00

ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT

Input voltage range VIN No external VC applied 26 55 VDC

VC applied 055

VIN slew rate dVIN /dt 1V/µs

VIN UV turn off VIN_UV Module latched shutdown, 18 26 V

No external VC applied, IOUT = 115A

No Load power dissipation PNL

VIN = 48 V 1.5 5.8

VIN = 26 V to 55 V 6.5

VIN = 48 V, TC= 25 ºC 2.2 4.2

VIN = 26 V to 55 V, TC= 25 ºC 5.5

Inrush current peak IINRP VC enable, VIN = 48 V, COUT = 64400 µF, 7.2 11 A

RLOAD = 12 mΩ

DC input current IIN_DC 4.5 A

Transfer ratio K K = VOUT /V

IN, IOUT = 0 A 1/32 V/V

Output voltage VOUT VOUT = VIN •K - IOUT •ROUT, Section 11 V

30°C < Tc< 100°C, 115

Output current (average) IOUT_AVG Iout_max = - (3/14) * Tc + 136.43 A

TC= 30 ºC 130

Output current (peak) IOUT_PK TPEAK < 10 ms, IOUT_AVG ≤115 A 200 A

Output power (average) POUT_AVG IOUT_AVG ≤115 A 185 W

Efficiency (ambient) hAMB

VIN = 48 V, IOUT = 115 A 90.0 91.7

VIN = 26 V to 55 V, IOUT = 115 A 84.0 %

VIN = 48 V, IOUT = 57.5 A 91.5 94.0

VIN = 48 V, IOUT = 130 A 89.5 90.9

Efficiency (hot) hHOT VIN = 48 V, TC= 100°C, IOUT = 115 A 89.0 90.7 %

Efficiency (over load range) h20% 23 A < IOUT < 115 A 80 %

Output resistance (cold) ROUT_COLD TC= -40°C, IOUT = 115 A 0.35 0.67 1.0 mΩ

Output resistance (ambient) ROUT_AMB TC= 25°C, IOUT = 115 A 0.50 0.84 1.08 mΩ

Output resistance (hot) ROUT_HOT TC= 100°C, IOUT = 115 A 0.64 1.00 1.18 mΩ

Switching frequency FSW 1.30 1.40 1.50 MHz

Output ripple frequency FSW_RP 2.60 2.80 3.00 MHz

Output voltage ripple VOUT_PP COUT = 0 F, IOUT = 115 A, VIN = 48 V, 150 200 mV

20 MHz BW, Section 11

Output inductance (parasitic) LOUT_PAR Frequency up to 30 MHz, 150 pH

Simulated J-lead model

Output capacitance (internal) COUT_INT Effective Value at 1.5 VOUT 420 µF

Output capacitance (external) COUT VTM Standalone Operation. 64400 µF

VIN pre-applied, VC enable

PROTECTION

Overvoltage lockout VIN_OVLO+Module latched shutdown 55.1 58.2 60 V

Overvoltage lockout TOVLO Effective internal RC filter 0.2 µs

response time constant

Output overcurrent trip IOCP 138 190 250 A

Short circuit protection trip current ISCP 250 A

Output overcurrent TOCP Effective internal RC filter (Integrative). 9.1 ms

response time constant

Short circuit protection response time TSCP From detection to cessation 1µs

of switching (Instantaneous)

Thermal shutdown setpoint TJ_OTP 125 130 135 ºC

Reverse inrush current protection Reverse Inrush protection enabled for this product

1.0 ABSOLUTE MAXIMUM VOLTAGE RATINGS

The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent

damage to the device.

2.0 ELECTRICAL CHARACTERISTICS

Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature

range of -40°C < TJ< 125°C (T-Grade); All other specifications are at TJ= 25 ºC unless otherwise noted.

MIN MAX UNIT

+ IN to - IN . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 60 VDC

PC to - IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 20 VDC

TM to -IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 7 VDC

VC to - IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 20 VDC

MIN MAX UNIT

IM to - IN......................................................... 0 3.15 VDC

+ IN / - IN to + OUT / - OUT (hipot)................ 1500 VDC

+ IN / - IN to + OUT / - OUT (working)........... 60 VDC

+ OUT to - OUT............................................... -1.0 5.5 VDC

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VTM48EF015T115A00

SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT

External VC voltage VVC_EXT Required for start up, and operation 11.5 16.5 V

below 26 V. See Section 7.

VC = 11.5 V, VIN = 0 V 115 150

VC current draw IVC

VC = 11.5 V, VIN > 26 V 0 mA

VC = 16.5 V, VIN > 26 V 0

Steady Fault mode. VC > 11.5 V 60

ANALOG

VC internal diode rating DVC_INT 100 V

INPUT

VC internal resistor RVC-INT N/A kΩ

VC internal resistor TVC_COEFF N/A ppm/°C

temperature coefficient

Start Up

VC start up pulse VVC_SP Tpeak <18 ms 20 V

VC slew rate dVC/dt Required for proper start up; 0.02 0.25 V/µs

VC inrush current IINR_VC VC = 16.5 V, dVC/dt = 0.25 V/µs 1A

VC to VOUT turn-on delay TON VIN pre-applied, PC floating, 500 µs

VC enable, CPC = 0 µF

Transitional VC to PC delay Tvc_pc VC = 11.5 V to PC high, VIN = 0 V, 75 125 µs

dVC/dt = 0.25 V/µs

Internal VC capacitance CVC_INT VC = 0 V 3.2 µF

• Used to wake up powertrain circuit.

• A minimum of 11.5 V must be applied indefinitely for VIN < 26 V

to ensure normal operation.

• VC slew rate must be within range for a successful start.

• PRM™ module VC can be used as valid wake-up signal source.

• Internal Resistance used in “Adaptive Loop” compensation

• VC voltage may be continuously applied

VTM CONTROL : VC

3.0 SIGNAL CHARACTERISTICS

Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature

range of -40°C < TJ< 125°C (T-Grade); All other specifications are at TJ= 25°C unless otherwise noted.

SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT

PC voltage VPC 4.7 55.3 V

ANALOG Steady PC source current IPC_OP 2mA

OUTPUT PC resistance (internal) RPC_INT Internal pull down resistor 50 150 400 kΩ

Start Up

PC source current IPC_EN 50 100 300 µA

PC capacitance (internal) CPC_INT Section 7 1000 pF

PC resistance (external) RPC_S60 kΩ

Enable PC voltage VPC_EN 22.5 3V

DIGITAL Disable PC voltage (disable) VPC_DIS 2V

INPUT / OUPUT

PC pull down current IPC_PD 5.1 mA

Transitional PC disable time TPC_DIS_T5µs

PC fault response time TFR_PC From fault to PC = 2 V 100 µs

• The PC pin enables and disables the VTM™ module.

When held below 2 V, the VTM module will be disabled.

• PC pin outputs 5 V during normal operation. PC pin is equal to 2.5 V

during fault mode given VIN > 26 V or VC > 11.5 V.

• After successful start up and under no fault condition, PC can be used as

a 5 V regulated voltage source with a 2 mA maximum current.

• Module will shutdown when pulled low with an impedance

less than 400 Ω.

• In an array of VTM modules, connect PC pin to synchronize start up.

• PC pin cannot sink current and will not disable other modules

during fault mode.

PRIMARY CONTROL : PC

SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT

IM Voltage (No Load) VIM_NL TJ= 25 ºC, VIN = 48 V, IOUT = 0 A 0.2 0.07 0.3 V

IM Voltage (50%) VIM_50% TJ= 25 ºC, VIN = 48 V, IOUT = 57.5 A 0.28 V

ANALOG Steady IM Voltage (Full Load) VIM_FL TJ= 25 ºC, VIN = 48 V, IOUT = 115 A 0.61 V

OUTPUT IM Gain AIM TJ= 25 ºC, VIN = 48 V, IOUT > 57.5 A 6 mV/A

IM Resistance (External) RIM_EXT 2.5 MΩ

• The IM pin voltage varies between 0.2 V and 0.61 V representing the

output current within ±25% under all operating line temperature

conditions between 50% and 100%.

• The IM pin provides a DC analog voltage proportional to

the output current of the VTM module.

CURRENT MONITOR : IM

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VTM48EF015T115A00

SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT

TM voltage VTM_AMB TJcontroller = 27°C 2.95 3.00 3.05 V

ANALOG TM source current ITM 100 µA

OUTPUT Steady TM gain ATM 10 mV/°C

TM voltage ripple VTM_PP CTM = 0 F, VIN = 48 V, 120 200 mV

IOUT = 115 A

Disable TM voltage VTM_DIS 0V

DIGITAL OUTPUT TM resistance (internal) RTM_INT Internal pull down resistor 25 40 50 kΩ

Transitional TM capacitance (external) CTM_EXT 50 pF

(FAULT FLAG) TM fault response time TFR_TM From fault to TM = 1.5 V 10 µs

• The TM pin monitors the internal temperature of the VTM controller IC

within an accuracy of ±5°C.

• Can be used as a "Power Good" flag to verify that

the VTM module is operating.

• The TM pin has a room temperature setpoint of 3 V

and approximate gain of 10 mV/°C.

• Output drives Temperature Shutdown comparator

TEMPERATURE MONITOR : TM

4.0 TIMING DIAGRAM

VPRI

1. Initiated VC pulse

2. Controller start

3. VPRI ramp up

4. VPRI = VOVLO

5. VPRI ramp down no VC pulse

6. Overcurrent, Secondary

7. Start up on short circuit

8. PC driven low

VSEC

3 V

5 V

VOVLO

VTM-AMB

Notes:

– Timing and voltage is not to scale

– Error pulse width is load dependent

a: VC slew rate (dVC/dt)

b: Minimum VC pulse rate

c: TOVLO_PIN

d: TOCP_SEC

e: Secondary turn on delay (TON)

f: PC disable time (TPC_DIS_T)

g: VC to PC delay (TVC_PC)

ISEC

VVC-EXT

345

≥ 26 V

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VTM48EF015T115A00

5.0 APPLICATION CHARACTERISTICS

The following values, typical of an application environment, are collected at TC= 25 ºC unless otherwise noted. See associated

figures for general trend data.

ATTRIBUTE SYMBOL CONDITIONS / NOTES TYP UNIT

No load power dissipation PNL VIN = 48 V, PC enabled 2.1 W

Efficiency (ambient) hAMB VIN = 48 V, IOUT = 115 A 91.8 %

Efficiency (hot) hHOT VIN = 48 V, IOUT = 115 A, TC= 100 ºC 90.3 %

Output resistance (cold) ROUT_COLD VIN = 48 V, IOUT = 115 A, TC= -40 ºC 0.7 mΩ

Output resistance (ambient) ROUT_AMB VIN = 48 V, IOUT = 115 A 0.9 mΩ

Output resistance (hot) ROUT_HOT VIN = 48 V, IOUT = 115 A, TC= 100 ºC 1.0 mΩ

Output voltage ripple VOUT_PP COUT = 0 F, IOUT = 115 A, VIN = 48 V, 116 mV

20 MHz BW, Section 12

VOUT transient (positive) VOUT_TRAN+IOUT_STEP = 0 A TO 115A, VIN = 48 V, 40 mV

ISLEW = 36 A /us

VOUT transient (negative) VOUT_TRAN-IOUT_STEP = 115 A to 0 A, VIN = 48 V 60 mV

ISLEW = 23 A /us

No Load Power Dissipation vs. Line Voltage

Input Voltage (V)

Power Dissipation (W)

-40 °C 25 °C 100 °C

T :

CASE

1.0

1.5

2.0

2.5

3.0

3.5

4.0

26 29 32 35 38 41 43 46 49 52 55

-40 -20 0 20 40 60 80 100

Full Load Efficiency vs. TCASE

Case Temperature (°C)

Full Load Efficiency (%)

26 V 48 V 55 V

V :

Efficiency & Power Dissipation -40 °C Case

Load Current (A)

Efficiency (%)

Power Dissipation (W)

26 V 48 V 55 V

V :

IN 26 V 48 V 55 V

0 13 26 39 52 65 78 91 104 117 130

Efficiency & Power Dissipation 25 °C Case

Load Current (A)

Efficiency (%)

Power Dissipation (W)

26 V 48 V 55 V

V :

IN 26 V 48 V 55 V

0 13 26 39 52 65 78 91 104 117 130

Figure 1 — No load power dissipation vs. VIN Figure 2 — Full load efficiency vs. temperature

Figure 3 — Efficiency and power dissipation at –40°C Figure 4 — Efficiency and power dissipation at 25°C

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VTM48EF015T115A00

Figure 10 — Start up from application of VIN ;

VC pre-applied COUT = 64400 µF

100

120

140

160

180

200

220

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2

Output Current (A)

Safe Operating Area

Output Voltage (V)

< 10 ms, 200 A Maximum Current

< 30°C TCASE, 130 A Maximum Current

115 A Maximum Current Region

Limited by Power

Limited by ROUT

Figure 8 — Safe operating area

Figure 9 — Full load ripple, 100 µF CIN; No external COUT.Board

mounted module, scope setting : 20 MHz analog BW

Output Voltage Ripple vs. Load

Load Current (A)

RIPPLE

(mV

PK-PK

)

V :

IN 26 V 48 V 55 V

100

125

150

175

200

0 12 23 35 46 58 69 81 92 104 115

Figure 7 — VRIPPLE vs. IOUT ; No external COUT.Board mounted

module, scope setting: 20 MHz analog BW

Efficiency & Power Dissipation 100 °C Case

Load Current (A)

Efficiency (%)

Power Dissipation (W)

26 V 48 V 55 V

V :

IN 26 V 48 V 55 V

0 12 23 35 46 58 69 81 92 104 115

Case Temperature (ºC)

OUT

(mΩ)

ROUT vs. TCASE at VIN = 48 V

I :

OUT 57.5 A 115 A

0.0

0.5

1.0

1.5

2.0

-40 -20 0 20 40 60 80 100

Figure 5 — Efficiency and power dissipation at 100°C Figure 6 — ROUT vs. temperature

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VTM48EF015T115A00

Figure 13 — 115 A – 0 A transient response:

CIN = 100 µF, no external COUT

Figure 12 — 0 A – 115 A transient response:

CIN = 100 µF, no external COUT

Figure 11 — Start up from application of VC;

VIN pre-applied COUT = 64400 µF

Load Current (A)

IM Voltage vs. Load at VIN = 48 V

IM (V)

T :

CASE -40 °C 25 °C 100 °C

0.1

0.2

0.3

0.4

0.5

0.6

12 23 35 46 58 69 81 92 104 115

Figure 14 — IM voltage vs. load

TCASE (°C)

IM Voltage at 115 A Load vs. TCASE

IM (V)

V :

IN 26 V 48 V 55 V

0.2

0.3

0.4

0.5

0.6

-40 -20 0 20 40 60 80 100

Figure 16 — Full load IM voltage vs. TCASE

Load Current (A)

IM Voltage vs. Load at 25 °C Case

IM (V)

V :

IN 26 V 48 V 55 V

0.0

0.1

0.2

0.3

0.4

0.5

0.6

12 23 35 46 58 69 81 92 104 115

Figure 15 — IM voltage vs. load

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VTM48EF015T115A00

ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT

MECHANICAL

Length L 32.25 / [1.270] 32.5 / [1.280] 32.75 / [1.289] mm/[in]

Width W 21.75 / [0.856] 22.0 / [0.866] 22.25 / [0.876] mm/[in]

Height H 6.48 / [0.255] 6.73 / [0.265] 6.98 / [0.275] mm/[in]

Volume Vol No heat sink 4.81 / [0.294] cm3/[in3]

Weight W 14.5 / [0.512] g/[oz]

Nickel 0.51 2.03

Lead finish Palladium 0.02 0.15 µm

Gold 0.003 0.051

THERMAL

VTM48EF015T115A00 (T-Grade) -40 125 °C

Operating temperature TJVTM48EF015M115A00 (M-Grade) N/A N/A °C

Thermal resistance fJC Isothermal heatsink and 1 °C/W

isothermal internal PCB

Thermal capacity 9 Ws/°C

ASSEMBLY

Peak compressive force Supported by J-lead only 6lbs

applied to case (Z-axis) 5.41 lbs / in2

VTM48EF015T115A00 (T-Grade) -40 125 °C

Storage temperature TST VTM48EF015M115A00 (M-Grade) N/A N/A °C

ESDHBM TBD

ESD withstand

ESDCDM TBD

VDC

SOLDERING

Peak temperature during reflow MSL 4 (Datecode 1528 and later) 245 °C

Peak time above 245°C 60 90 s

Peak heating rate during reflow 1.5 3 °C/s

Peak cooling rate post reflow 1.5 6 °C/s

SAFETY

Working voltage (IN – OUT) VIN_OUT 60 VDC

Isolation voltage (hipot) VHIPOT 1500 VDC

Isolation capacitance CIN_OUT Unpowered unit 1800 2000 2200 pF

Isolation resistance RIN_OUT 10 MΩ

MTBF

MIL-HDBK-217 Plus Parts Count;

TBD MHrs25ºC Ground Benign, Stationary,

Indoors / Computer Profile

Telcordia Issue 2 - Method I Case III; TBD MHrs

Ground Benign, Controlled

cTUVus

Agency approvals / standards cURus

CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable

Human Body Model,

"JEDEC JESD 22-A114C.01"

Charge Device Model,

"JEDEC JESD 22-C101-C"

6.0 GENERAL CHARACTERISTICS

Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature

range of -40 ºC < TJ< 125 ºC (T-Grade); All Other specifications are at TJ= 25°C unless otherwise noted.

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VTM48EF015T115A00

7.0 USING THE CONTROL SIGNALS VC, PC, TM, IM

The VTM Control (VC) pin is an input pin which powers the

internal VCC circuitry when within the specified voltage range

of 11.5 V to 16.5 V. This voltage is required for VTM™ current

multiplier start up and must be applied as long as the input is

below 26 V. In order to ensure a proper start, the slew rate of

the applied voltage must be within the specified range.

Some additional notes on the using the VC pin:

• In most applications, the VTM module will be powered

by an upstream PRM™ regulator which provides a 10 ms

VC pulse during start up. In these applications the VC pins

of the PRM module and VTM module should be tied together.

• The VC voltage can be applied indefinitely allowing for

continuous operation down to 0 VIN.

• The fault response of the VTM module is latching.

A positive edge on VC is required in order to restart the unit.

If VC is continuously applied the PC pin may be toggled to

restart the VTM module.

Primary Control (PC) pin can be used to accomplish the

following functions:

• Delayed start: Upon the application of VC, the PC pin will

source a constant 100 µA current to the internal RC

network. Adding an external capacitor will allow further

delay in reaching the 2.5 V threshold for module start.

• Auxiliary voltage source: Once enabled in regular

operational conditions (no fault), each VTM PC provides a

regulated 5 V, 2 mA voltage source.

• Output disable: PC pin can be actively pulled down in order

to disable the module. Pull down impedance shall be lower

than 400 Ω.

• Fault detection flag: The PC 5 V voltage source is internally

turned off as soon as a fault is detected. It is important to

notice that PC doesn’t have current sink capability. Therefore,

in an array, PC line will not be capable of disabling

neighboring modules if a fault is detected.

• Fault reset: PC may be toggled to restart the unit if VC

is continuously applied.

Temperature Monitor (TM) pin provides a voltage

proportional to the absolute temperature of the converter

control IC.

It can be used to accomplish the following functions:

• Monitor the control IC temperature: The temperature in

Kelvin is equal to the voltage on the TM pin scaled

by 100. (i.e. 3.0 V = 300 K = 27 ºC). If a heat sink is applied,

TM can be used to thermally protect the system.

• Fault detection flag: The TM voltage source is internally

turned off as soon as a fault is detected. For system

monitoring purposes (microcontroller interface) faults are

detected on falling edges of TM signal.

Current Monitor (IM) pin provides a voltage proportional to

the output current of the VTM module. The nominal voltage

will vary between 0.07 V and 0.61 V over the output current

range of the VTM module (See Figures 14–16). The accuracy of

the IM pin will be within 25% under all line and temperature

conditions between 50% and 100% load.

8.0 START UP BEHAVIOR

Depending on the sequencing of the VC with respect to the

input voltage, the behavior during start up will vary as follows:

• Normal operation (VC applied prior to VIN): In this case the

controller is active prior to ramping the input. When the

input voltage is applied, the VTM module output voltage

will track the input (See Figure 10). The inrush current is

determined by the input voltage rate of rise and output

capacitance. If the VC voltage is removed prior to the input

reaching 26 V, the VTM may shut down.

• Stand-alone operation (VC applied after VIN): In this case the

VTM module output will begin to rise upon the application

of the VC voltage (See Figure 11). The Adaptive Soft Start

Circuit (See Section 11) may vary the ouput rate of rise in

order to limit the inrush current to its maximum level. When

starting into high capacitance, or a short, the output current

will be limited for a maximum of 120 µ/sec. After this period,

the Adaptive Soft Start Circuit will time out and the VTM

module may shut down. No restart will be attempted until

VC is re-applied or PC is toggled. The maximum output

capacitance is limited to 64400 µF in this mode of operation

to ensure a sucessful start.

9.0 THERMAL CONSIDERATIONS

VI Chip®products are multi-chip modules whose temperature

distribution varies greatly for each part number as well as with

the input / output conditions, thermal management and

environmental conditions. Maintaining the top of the

VTM48EF015T115A00 case to less than 100 ºC will keep all

junctions within the VI Chip®module below 125 ºC for most

applications.

The percent of total heat dissipated through the top surface

versus through the J-lead is entirely dependent on the

particular mechanical and thermal environment. The heat

dissipated through the top surface is typically 60%. The heat

dissipated through the J-lead onto the PCB board surface is

typically 40%. Use 100% top surface dissipation when

designing for a conservative cooling solution.

It is not recommended to use a VI Chip®module for an extended

period of time at full load without proper heat sinking.

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VTM48EF015T115A00

+VIN

Temperature

Dependent

Voltage Source

2.5 V

100 A

5 V

40 K

1000 pF

10.5 V

3.1 V

Single Ended

Primary

Current Sensing

VREF

(127°C)

Enable

Synchronous

Rectification

Primary Stage &

Resonant Tank

PC Pull-Up

& Source

Over

Temperature

Protection

CIN

18 V

Power

Transformer

Primary

Gate

Drive

Secondary

Gate Drive

3 VMAX

240 AMAX

Gate Drive

Supply

Regulator

Supply

Enable

Adaptive

Soft Start

Enable

Cr Lr

VREF

0.01 F

1 K

2 mA

Modulator

Enable

150 K

VDD

DVC_INT

RVC_INT

-VIN

VIN

OVLO

UVLO Fault Logic

COUT

Left

J-lead

Right

J-lead

COUT

+VOUT

-VOUT

+VOUT

-VOUT

102

10.0 VTM MODULE BLOCK DIAGRAM

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11.0 SINE AMPLITUDE CONVERTERTM POINT OF LOAD CONVERSION

The Sine Amplitude Converter (SAC™) uses a high frequency

resonant tank to move energy from input to output. (The

resonant tank is formed by Cr and leakage inductance Lr in the

power transformer windings as shown in the VTM™ Module

Block Diagram. See Section 10). The resonant LC tank,

operated at high frequency, is amplitude modulated as a

function of input voltage and output current. A small amount

of capacitance embedded in the input and output stages of

the module is sufficient for full functionality and is key to

achieving power density.

The VTM48EF015T115A00 SAC can be simplified into the

following model:

At no load:

VOUT = VIN •K (1)

K represents the “turns ratio” of the SAC.

Rearranging Eq (1):

K= VOUT (2)

VIN

In the presence of load, VOUT is represented by:

VOUT = VIN •K – IOUT •ROUT (3)

and IOUT is represented by:

IOUT =IIN –I

Q(4)

ROUT represents the impedance of the SAC, and is a function of

the RDSON of the input and output MOSFETs and the winding

resistance of the power transformer. IQrepresents the

quiescent current of the SAC control and gate drive circuitry.

The use of DC voltage transformation provides additional

interesting attributes. Assuming that ROUT = 0 Ωand IQ= 0 A,

Eq. (3) now becomes Eq. (1) and is essentially load

independent, resistor R is now placed in series with VIN as

shown in Figure 18.

The relationship between VIN and VOUT becomes:

VOUT = (VIN –I

IN •R) •K (5)

Substituting the simplified version of Eq. (4)

(IQis assumed = 0 A) into Eq. (5) yields:

VOUT = VIN •K – IOUT •R •K2(6)

–

VOUT

COUT

VIN

V•I

–

CIN

IOUT

RCOUT

ROUT

RCIN

46 mA

1/32 • IOUT 1/32 • VIN

0.84 mΩ

RCIN

6.3 mΩ

90 pH

0.98 ΩRCOUT

50 µΩ

420 µF

LOUT = 150 pH

900 nF

LIN = 3.7 nH IOUT ROUT

VIN VOUT

SAC

K = 1/32

Vin

Vout

–

VIN VOUT

SAC™

K = 1/32

Figure 18 – K = 1/32 Sine Amplitude Converter with series

input resistor

Figure 17 — VI Chip®product AC model

COUT

CIN

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This is similar in form to Eq. (3), where ROUT is used to

represent the characteristic impedance of the SAC™. However,

in this case a real R on the input side of the SAC is effectively

scaled by K2with respect to the output.

Assuming that R = 1 Ω, the effective R as seen from the secondary

sideis1mΩ, with K = 1/32 as shown in Figure 18.

A similar exercise should be performed with the addition of a

capacitor or shunt impedance at the input to the SAC.

A switch in series with VIN is added to the circuit. This is

depicted in Figure 19.

A change in VIN with the switch closed would result in a

change in capacitor current according to the following

equation:

IC(t) = C dVIN (7)

Assume that with the capacitor charged to VIN, the switch is

opened and the capacitor is discharged through the idealized

SAC. In this case,

IC=I

OUT •K (8)

Substituting Eq. (1) and (8) into Eq. (7) reveals:

IOUT =C•dVOUT (9)

K2dt

The equation in terms of the output has yielded a K2scaling

factor for C, specified in the denominator of the equation.

A K factor less than unity, results in an effectively larger

capacitance on the output when expressed in terms of the

input. With a K=1/32 as shown in Figure 19, C=1 µF would

appear as C=1024 µF when viewed

from the output.

Low impedance is a key requirement for powering a high-

current, low voltage load efficiently. A switching regulation

stage should have minimal impedance while simultaneously

providing appropriate filtering for any switched current. The

use of a SAC between the regulation stage and the point of

load provides a dual benefit of scaling down series impedance

leading back to the source and scaling up shunt capacitance or

energy storage as a function of its K factor squared. However,

the benefits are not useful if the series impedance of the SAC

is too high. The impedance of the SAC must be low, i.e. well

beyond the crossover frequency of the system.

A solution for keeping the impedance of the SAC low involves

switching at a high frequency. This enables small magnetic

components because magnetizing currents remain low. Small

magnetics mean small path lengths for turns. Use of low loss

core material at high frequencies also reduces core losses.

The two main terms of power loss in the VTMTM module are:

-No load power dissipation (PNL): defined as the power

used to power up the module with an enabled powertrain

at no load.

-Resistive loss (ROUT): refers to the power loss across

the VTMTM current multiplier modeled as pure resistive

impedance.

PDISSIPATED = PNL + PROUT (10)

Therefore,

POUT = PIN –P

DISSIPATED = PIN –P

NL –P

ROUT (11)

The above relations can be combined to calculate the overall

module efficiency:

h=POUT =PIN –P

NL –P

ROUT (12)

PIN PIN

=VIN •IIN –P

NL –(I

OUT)2•ROUT

VIN •IIN

=1 –

(

PNL + (IOUT)2•ROUT

)

VIN •IIN

SAC

K = 1/32

Vin

Vout

–

VIN VOUT

SACTM

K = 1/32

Figure 19 — Sine Amplitude Converter™ with input capacitor

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12.0 INPUT AND OUTPUT FILTER DESIGN

A major advantage of a SAC™ system versus a conventional

PWM converter is that the former does not require large

functional filters. The resonant LC tank, operated at extreme

high frequency, is amplitude modulated as a function of input

voltage and output current and efficiently transfers charge

through the isolation transformer. A small amount of

capacitance embedded in the input and output stages of the

module is sufficient for full functionality and is key to achieving

high power density.

This paradigm shift requires system design to carefully evaluate

external filters in order to:

1.Guarantee low source impedance.

To take full advantage of the VTM™ current multiplier

dynamic response, the impedance presented to its input

terminals must be low from DC to approximately 5 MHz.

Input capacitance may be added to improve transient

performance or compensate for high source impedance.

2.Further reduce input and/or output voltage ripple without

sacrificing dynamic response.

Given the wide bandwidth of the VTM module, the source

response is generally the limiting factor in the overall

system response. Anomalies in the response of the source

will appear at the output of the VTM module multiplied by

its K factor.

3.Protect the module from overvoltage transients imposed

by the system that would exceed maximum ratings and

cause failures.

The VI Chip®module input/output voltage ranges must

not be exceeded. An internal overvoltage lockout function

prevents operation outside of the normal operating input

range. Even during this condition, the powertrain is

exposed to the applied voltage and power MOSFETs must

withstand it.

13.0 CAPACITIVE FILTERING CONSIDERATIONS

FOR A SINE AMPLITUDE CONVERTERTM

It is important to consider the impact of adding input and

output capacitance to a Sine Amplitude Converter on the

system as a whole. Both the capacitance value and the

effective impedance of the capacitor must be considered.

A Sine Amplitude Converter has a DC ROUT value which has

already been discussed in section 11. The AC ROUT of the

SAC contains several terms:

• Resonant tank impedance

• Input lead inductance and internal capacitance

• Output lead inductance and internal capacitance

The values of these terms are shown in the behavioral model in

section 11. It is important to note on which side of the

transformer these impedances appear and how they reflect

across the transformer given the K factor.

The overall AC impedance varies from model to model. For

most models it is dominated by DC ROUT value from DC to

beyond 500 KHz. The behavioral model in section 11 should be

used to approximate the AC impedance of the specific model.

Any capacitors placed at the output of the VTM reflect back to

the input of the VTM module by the square of the K factor (Eq.

9) with the impedance of the VTM module appearing in series.

It is very important to keep this in mind when using a PRM™

regulator to power the VTM module. Most PRM modules have

a limit on the maximum amount of capacitance that can be

applied to the output. This capacitance includes both the PRM

output capacitance and the VTM module output capacitance

reflected back to the input. In PRM remote sense applications,

it is important to consider the reflected value of VTM module

output capacitance when designing and compensating the

PRM control loop.

Capacitance placed at the input of the VTM module appear to

the load reflected by the K factor with the impedance of the

VTM module in series. In step-down ratios, the effective

capacitance is increased by the K factor. The effective ESR of

the capacitor is decreased by the square of the K factor, but

the impedance of the module appears in series. Still, in most

step-down VTM modules an electrolytic capacitor placed at the

input of the module will have a lower effective impedance

compared to an electrolytic capacitor placed at the output. This

is important to consider when placing capacitors at the output

of the module. Even though the capacitor may be placed at

the output, the majority of the AC current will be sourced from

the lower impedance, which in most cases will be the module.

This should be studied carefully in any system design using a

module. In most cases, it should be clear that electrolytic

output capacitors are not necessary to design a stable,

well-bypassed system.

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VIN VOUT

–DC

ZIN_EQ1

ZIN_EQ2

ZOUT_EQ1

ZOUT_EQ2

Load

VTM™1

RO_1

VTM™2

RO_2

VTM™n

RO_n

ZOUT_EQn

ZIN_EQn

Figure 20 — VTM current multiplier array

14.0 CURRENT SHARING

The SAC™ topology bases its performance on efficient transfer

of energy through a transformer without the need of closed

loop control. For this reason, the transfer characteristic can be

approximated by an ideal current multiplier with some resistive

drop and positive temperature coefficient.

This type of characteristic is close to the impedance

characteristic of a DC power distribution system, both in

behavior (AC dynamic) and absolute value (DC dynamic).

When connected in an array with the same K factor, the VTM

module will inherently share the load current (typically 5%)

with parallel units according to the equivalent impedance

divider that the system implements from the power source to

the point of load.

Some general recommendations to achieve matched array

impedances:

• Dedicate common copper planes within the PCB

to deliver and return the current to the modules.

• Provide the PCB layout as symmetric as possible.

• Apply same input / output filters (if present) to each unit.

For further details see AN:016 Using BCM® Bus Converters

in High Power Arrays.

15.0 FUSE SELECTION

In order to provide flexibility in configuring power systems

VI Chip®products are not internally fused. Input line fusing

of VI Chip®products is recommended at system level to provide

thermal protection in case of catastrophic failure.

The fuse shall be selected by closely matching system

requirements with the following characteristics:

• Current rating (usually greater than maximum current

of VTM module)

• Maximum voltage rating (usually greater than the maximum

possible input voltage)

• Ambient temperature

• Nominal melting I2t

16.0 REVERSE INRUSH CURRENT PROTECTION

The VTM48EF015T115A00 provides reverse inrush protection

which prevents reverse current flow until the input voltage is

high enough to first establish current flow in the forward

direction. In the event that there is a DC voltage present on the

output before the VTM module is powered up, this feature

protects sensitive loads from excessive dV/dT during power up

as shown in Figure 21.

If a voltage is present at the output of the VTM module which

satisfies the condition VOUT > VIN • K after a successful power

up the energy will be transferred from secondary to primary.

The input to output ratio of the VTM module will be

maintained. The VTM module will continue to operate in

reverse as long as the input and output voltages are within the

specified range. The VTM48EF015T115A00 has not been

qualified for continuous reverse operation.

VIN

Supply

VOUT

VIN

VOUT

Supply

ABCD EFG H

A: VOUT supply > 0 V

B: VC to -IN > 11.5 V controller wakes-up, PC & TM pulled

high, reverse inrush protection blocks VOUT supplying VIN

C: VIN supply ramps up

D: VIN > VOUT /K, powertrain starts in normal mode

E: VIN supply ramps down

F: VIN > VOUT /K, powertrain transfers reverse energy

G: VOUT ramps down, VIN follows

H: VC turns off

VIN

Supply

-Out

+Out

-In

+In

VTM®

Current Multiplier

Figure 21 — Reverse inrush protection

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17.0 LAYOUT CONSIDERATIONS

The VTM48EF015T115A00 requires equal current density along

the output J-leads to achieve rated efficiency and output power

level. The negative output J-leads are not connected internally

and must be connected on the board as close to the VTMT™

current multiplier as possible. The layout must also prevent the

high output current of the VTM48EF015T115A00 from

interfering with the input-referenced signals.

To achieve these requirements, the following layout guidelines

are recommended:

• The total current path length from any point on the V+OUT

J-leads to the corresponding point on the V-OUT J-leads should

be equal (see Figure 22) .

• Use vias along the negative output J-leads to connect the

negative output to a common power plane.

• Use sufficient copper weight and number of layers to carry

the output current to the load or to the output connectors.

• Be sure to include enough vias along both the positive and

negative J leads to distribute the current among the layers

of the PCB.

• Do not run input-referenced signal traces (VC, PC, TM

and IM) between the layers of the secondary outputs.

• Run the input-referenced signal traces (VC, PC, TM and IM)

such that V-IN shields the signals. See AN:005 FPA Printed

Circuit Board Layout Guidelines for more details.

Equalizing the current paths is most easily accomplished by

centering the VTM module output J-leads between the output

connections of the PCB and by designing the board such that

the layout is symmetric from both sides of the output and from

the front and back ends of the output as shown in Figures 23

and 24.

Figure 22 — Equal current path

Figure 23 — Symmetric layout

Figure 24 — Symmetric layout

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inch

NOTES:

1. DIMENSIONS ARE .

2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:

.X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]

3. PRODUCT MARKING ON TOP SURFACE

DXF and PDF files are available on vicorpower.com

17.1 MECHANICAL DRAWING

inch

NOTES:

1. DIMENSIONS ARE .

2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:

.X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]

3. PRODUCT MARKING ON TOP SURFACE

DXF and PDF files are available on vicorpower.com

17.2 RECOMMENDED LAND PATTERN

Bottom View

4 3 2 1

Signal

Name Designation

+In M2, M1

–In M4, M3

IM N3

TM N4

VC N2

PC N1

+Out A3-L3, A2-L2

–Out A4-L4, A1-L1

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