22uF
1.8V / 0.5A
10uF
2.2µH
TPS62171
VIN
EN
AGND
PGND
SW
VOS
PG
FB
100k
(3 .. 17)V
TPS62170, TPS62171
TPS62172, TPS62173
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SLVSAT8C NOVEMBER 2011REVISED SEPTEMBER 2013
3-17V 0.5A Step-Down Converter with DCS-Control
TM
Check for Samples: TPS62170,TPS62171,TPS62172,TPS62173
1FEATURES DESCRIPTION
The TPS6217X family is an easy to use synchronous
DCS-ControlTM Topology step down DC-DC converter optimized for
Input Voltage Range: 3 to 17 V applications with high power density. A high switching
Up to 500 mA Output Current frequency of typically 2.25MHz allows the use of
small inductors and provides fast transient response
Adjustable Output Voltage from 0.9 to 6 V as well as high output voltage accuracy by utilization
Fixed Output Voltage Versions of the DCS-Control™ topology.
Seamless Power Save Mode Transition With its wide operating input voltage range of 3V to
Typically 17µA Quiescent Current 17V, the devices are ideally suited for systems
Power Good Output powered from either a Li-Ion or other battery as well
as from 12V intermediate power rails. It supports up
100% Duty Cycle Mode to 0.5A continuous output current at output voltages
Short Circuit Protection between 0.9V and 6V (with 100% duty cycle mode).
Over Temperature Protection Power sequencing is also possible by configuring the
Available in a 2 × 2 mm, WSON-8 Package Enable and open-drain Power Good pins.
In Power Save Mode, the devices show quiescent
APPLICATIONS current of about 17μA from VIN. Power Save Mode,
Standard 12V Rail Supplies entered automatically and seamlessly if load is small,
POL Supply from Single or Multiple Li-Ion maintains high efficiency over the entire load range.
In Shutdown Mode, the device is turned off and
Battery shutdown current consumption is less than 2μA.
LDO Replacement The device, available in adjustable and fixed output
Embedded Systems voltage versions, is packaged in an 8-pin WSON
Digital Still Camera, Video package measuring 2 × 2 mm (DSG).
Mobile PC's, Tablet, Modems
spacing
spacing
Figure 1. Typical Application and Efficiency
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS62170, TPS62171
TPS62172, TPS62173
SLVSAT8C NOVEMBER 2011REVISED SEPTEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TAOUTPUT VOLTAGE PART NUMBER(2) PACKAGE ORDERING PACKAGE MARKING
adjustable TPS62170 TPS62170DSG QUE
1.8 V TPS62171 TPS62171DSG QUF
-40°C to 85°C 8-Pin WSON
3.3 V TPS62172 TPS62172DSG QUG
5.0 V TPS62173 TPS62173DSG QUH
(1) For detailed ordering information please check the PACKAGE OPTION ADDENDUM section at the end of this datasheet.
(2) Contact the factory to check availability of other fixed output voltage versions.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE UNIT
VIN –0.3 to 20 V
EN –0.3 to VIN+0.3
Pin Voltage
Range(2) SW -0.3 to VIN+0.3 V
FB, PG, VOS –0.3 to 7 V
Power Good sink PG 10 mA
current Operating junction temperature range, TJ–40 to 125
Temperature range °C
Storage temperature range, Tstg –65 to 150
HBM Human body model 2 kV
ESD rating(3) CDM Charge device model 0.5 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) ESD testing is performed according to the respective JESD22 JEDEC standard.
THERMAL INFORMATION TPS6217X
THERMAL METRIC(1) UNITS
DSG (8) PINS
θJA Junction-to-ambient thermal resistance 61.8
θJC(TOP) Junction-to-case(top) thermal resistance 61.3
θJB Junction-to-board thermal resistance 15.5 °C/W
ψJT Junction-to-top characterization parameter 0.4
ψJB Junction-to-board characterization parameter 15.4
θJC(BOTTOM) Junction-to-case(bottom) thermal resistance 8.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT
Supply Voltage, VIN 3 17 V
Operating free air temperature, TA–40 85 °C
Operating junction temperature, TJ–40 125 °C
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SLVSAT8C NOVEMBER 2011REVISED SEPTEMBER 2013
ELECTRICAL CHARACTERISTICS
over free-air temperature range (TA=-40°C to +85°C), typical values at VIN=12V and TA=25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input Voltage Range(1) 3 17 V
IQOperating Quiescent Current EN=High, IOUT=0mA, device not switching 17 25 µA
ISD Shutdown Current(2) EN=Low 1.5 4 µA
Falling Input Voltage 2.6 2.7 2.82 V
VUVLO Undervoltage Lockout Threshold Hysteresis 180 mV
TSD Thermal Shutdown Temperature 160 °C
Thermal Shutdown Hysteresis 20
CONTROL (EN, PG)
VEN_H High Level Input Threshold Voltage (EN) 0.9 V
VEN_L Low Level Input Threshold Voltage (EN) 0.3 V
ILKG_EN Input Leakage Current (EN) EN=VIN or GND 0.01 1 µA
Rising (%VOUT) 92 95 98
VTH_PG Power Good Threshold Voltage %
Falling (%VOUT) 87 90 93
VOL_PG Power Good Output Low IPG=-2mA 0.07 0.3 V
ILKG_PG Input Leakage Current (PG) VPG=1.8V 1 400 nA
POWER SWITCH
VIN6V 300 600
High-Side MOSFET ON-Resistance mΩ
VIN=3V 430
RDS(ON) VIN6V 120 200
Low-Side MOSFET ON-Resistance mΩ
VIN=3V 165
ILIMF High-Side MOSFET Forward Current Limit(3) VIN=12V, TA=25°C 0.85 1.05 1.35 A
OUTPUT
VREF Internal Reference Voltage(4) 0.8 V
ILKG_FB Pin Leakage Current (FB) TPS62170, VFB=1.2V 5 400 nA
Output Voltage Range (TPS62170) VIN VOUT 0.9 6.0 V
PWM mode operation, VINVOUT+1V –3 3
Initial Output Voltage Accuracy(5) %
Power Save Mode operation, COUT=22µF -3.5 4
VOUT DC Output Voltage Load Regulation(6) VIN=12V, VOUT=3.3V, PWM mode operation 0.05 % / A
DC Output Voltage Line Regulation (6) 3V VIN 17V, VOUT=3.3V, IOUT= 0.5A, PWM 0.02 % / V
mode operation
(1) The device is still functional down to Under Voltage Lockout (see parameter VUVLO).
(2) Current into VIN pin.
(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit And Short
Circuit Protection).
(4) This is the voltage regulated at the FB pin.
(5) This is the accuracy provided by the device itself (line and load regulation effects are not included). For fixed voltage versions, the
(internal) resistive feedback divider is included.
(6) Line and load regulation are depending on external component selection and layout (see Figure 13 and Figure 14).
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8PG
SW
VOS
FB
Exposed
Thermal
Pad
PGND
VIN
EN
AGND
7
6
5
2
3
1
4
TPS62170, TPS62171
TPS62172, TPS62173
SLVSAT8C NOVEMBER 2011REVISED SEPTEMBER 2013
www.ti.com
DEVICE INFORMATION
DSG PACKAGE
(TOP VIEW)
Terminal Functions
PIN(1) I/O DESCRIPTION
NAME NO.
PGND 1 Power ground
VIN 2 I Supply voltage
EN 3 I Enable input (High = enabled, Low = disabled)
AGND 4 Analog Ground
FB 5 I Voltage feedback of adjustable version. Connect resistive voltage divider to this pin. It is recommended to
connect FB to AGND on fixed output voltage versions for improved thermal performance.
VOS 6 I Output voltage sense pin and connection for the control loop circuitry.
Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and
SW 7 O output capacitor.
PG 8 O Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires
pull-up resistor; goes high impedance, when device is switched off)
Exposed Must be connected to AGND. Must be soldered to achieve appropriate power dissipation and mechanical
Thermal Pad reliability.
(1) For more information about connecting pins, see DETAILED DESCRIPTION and APPLICATION INFORMATION sections.
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control logic
Soft
start
Thermal
Shtdwn UVLO PG control
power
control
error
amplifier
gate
drive
HS lim
LS lim
VINPG
PGND
AGND
comp
comp
+
_
timer tON
DCS - ControlTM
direct control
&
compensation
comparator
ramp
SW
EN*
VOS
FB
*This pin is connected to a pull down resistor internally
(see Detailed Description section).
TPS62170, TPS62171
TPS62172, TPS62173
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SLVSAT8C NOVEMBER 2011REVISED SEPTEMBER 2013
FUNCTIONAL BLOCK DIAGRAM
Figure 2. TPS62170 (adjustable output voltage)
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control logic
Soft
start
Thermal
Shtdwn UVLO PG control
power
control
error
amplifier
gate
drive
HS lim
LS lim
VINPG
PGND
AGND
comp
comp
+
_
timer tON
DCS - ControlTM
direct control
&
compensation
comparator
ramp
SW
EN*
VOS
FB*
*This pin is connected to a pull down resistor internally
(see Detailed Description section).
TPS62170, TPS62171
TPS62172, TPS62173
SLVSAT8C NOVEMBER 2011REVISED SEPTEMBER 2013
www.ti.com
Figure 3. TPS62171/2/3 (fixed output voltage)
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CIN
VIN
TPS62170
VIN
EN
GND
PGND
SW
VOS
PG
FB
COUT
2.2µH
R1
R2
R3
VOUT
TPS62170, TPS62171
TPS62172, TPS62173
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SLVSAT8C NOVEMBER 2011REVISED SEPTEMBER 2013
PARAMETER MEASUREMENT INFORMATION
List of Components
REFERENCE DESCRIPTION MANUFACTURER
IC 17V, 1A Step-Down Converter, WSON TPS62170DSG, Texas Instruments
L1 2.2uH, 1.4A, 3 x 2.8 x 1.2 mm VLF3012ST-2R2M1R4, TDK
Cin 10µF, 25V, Ceramic Standard
Cout 22µF, 6.3V, Ceramic Standard
R1 depending on Vout
R2 depending on Vout
R3 100kΩ, Chip, 0603, 1/16W, 1% Standard
spacing
spacing
Figure 4. Measurement Setup
spacing
TYPICAL CHARACTERISTICS
Table of Graphs
DESCRIPTION FIGURE
Efficiency vs Output Current, vs Input Voltage 5 - 12
vs Output current (Load regulation) 13
Output voltage vs Input Voltage (Line regulation) 14
vs Input Voltage 15
Switching Frequency vs Output Current 16
Quiescent Current vs Input Voltage 17
Shutdown Current vs Input Voltage 18
Power FET RDS(on) vs Input Voltage (High-Side, Low-Side) 19, 20
Output Voltage Ripple vs output Current 21
Maximum Output Current vs Input Voltage 22
PWM-PSM-PWM Mode Transition 23, 24
Load Transient Response 25 - 28
Waveforms Startup 29, 30
Typical Power Save Mode Operation 31
Typical PWM Mode Operation 32
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0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0001 0.001 0.01 0.1 1
VIN=5V
VIN=12V
VIN=17V
Output Current (A)
Efficiency (%)
VOUT=1.8V
L=2.2uH (VLF3012ST)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
IOUT=1mA IOUT=10mA IOUT=100mA
IOUT=500mA
Input Voltage (V)
Efficiency (%)
VOUT=1.8V
L=2.2uH (VLF3012ST)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0001 0.001 0.01 0.1 1
VIN=5V
VIN=12V
VIN=17V
Output Current (A)
Efficiency (%)
VOUT=3.3V
L=2.2uH (VLF3012ST)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
4 5 6 7 8 9 10 11 12 13 14 15 16 17
IOUT=1mA IOUT=10mA IOUT=100mA
IOUT=500mA
Input Voltage (V)
Efficiency (%)
VOUT=3.3V
L=2.2uH (VLF3012ST)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0001 0.001 0.01 0.1 1
VIN=6V
VIN=12V
VIN=17V
Output Current (A)
Efficiency (%)
VOUT=6.0V
L=2.2uH (VLF3012ST)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
7 8 9 10 11 12 13 14 15 16 17
IOUT=1mA
IOUT=10mA
IOUT=100mA
IOUT=500mA
Input Voltage (V)
Efficiency (%)
VOUT=6.0V
L=2.2uH (VLF3012ST)
Cout=22uF
G001
TPS62170, TPS62171
TPS62172, TPS62173
SLVSAT8C NOVEMBER 2011REVISED SEPTEMBER 2013
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EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
Figure 5. Vout=6V Figure 6. Vout=6V
EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
Figure 7. Vout=3.3V Figure 8. Vout=3.3V
EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
Figure 9. Vout=1.8V Figure 10. Vout=1.8V
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0
0.5
1
1.5
2
2.5
3
3.5
4
0 0.1 0.2 0.3 0.4 0.5
Output Current (A)
Switching Frequency (MHz)
VIN=12V, VOUT=3.3V
L=2.2uH (VLF3012ST)
G000
0
0.5
1
1.5
2
2.5
3
3.5
4
4 6 8 10 12 14 16 18
IOUT=0.5A
Input Voltage (V)
Switching Frequency (MHz)
VOUT=3.3V
L=2.2uH (VLF3012ST)
Cout=22uF
G000
3.20
3.25
3.30
3.35
0.0001 0.001 0.01 0.1 1
VIN=5V VIN=12V VIN=17V
Output Current (A)
Output Voltage (V)
VOUT=3.3V
L=2.2uH (VLF3012ST)
Cout=22uF
G001
3.20
3.25
3.30
3.35
4 7 10 13 16
IOUT=1mA IOUT=10mA
IOUT=100mA IOUT=500mA
Input Voltage (V)
Output Voltage (V)
VOUT=3.3V
L=2.2uH (VLF3012ST)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0001 0.001 0.01 0.1 1
VIN=5V
VIN=12V
VIN=17V
Output Current (A)
Efficiency (%)
VOUT=0.9V
L=2.2uH (VLF3012ST)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
IOUT=1mA
IOUT=10mA IOUT=100mA IOUT=500mA
Input Voltage (V)
Efficiency (%)
VOUT=0.9V
L=2.2uH (VLF3012ST)
Cout=22uF
G001
TPS62170, TPS62171
TPS62172, TPS62173
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SLVSAT8C NOVEMBER 2011REVISED SEPTEMBER 2013
EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
Figure 11. Vout=0.9V Figure 12. Vout=0.9V
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
OUTPUT CURRENT INPUT VOLTAGE
Figure 13. Output Voltage Accuracy (Load Regulation) Figure 14. Output Voltage Accuracy (Line Regulation)
SWITCHING FREQUENCY SWITCHING FREQUENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
Figure 15. Switching Frequency Figure 16. Switching Frequency
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0
0.01
0.02
0.03
0.04
0.05
0 0.1 0.2 0.3 0.4 0.5
VIN=5V
VIN=12V
VIN=17V
Output Current (A)
Output Voltage Ripple (V)
VOUT=3.3V,
L=2.2uH (VLF3012ST)
Cout=22uF
G000
0
0.2
0.5
0.8
1
1.2
1.5
4 5 6 7 8 9 10 11 12 13 14 15 16 17
−40°C 25°C
85°C
Input Voltage (V)
Output Current (A)
VOUT=3.3V
L=2.2uH (VLF3012ST)
Cout=22uF
G000
0.0
50.0
100.0
150.0
200.0
250.0
300.0
350.0
400.0
450.0
500.0
550.0
600.0
3.0 6.0 9.0 12.0 15.0 18.0
−40°C
−20°C
25°C
85°C 125°C
Input Voltage (V)
RDSon High−Side (m)
G001
0.0
25.0
50.0
75.0
100.0
125.0
150.0
175.0
200.0
225.0
250.0
3.0 6.0 9.0 12.0 15.0 18.0 20.0
−40°C
−20°C
25°C
85°C 125°C
Input Voltage (V)
RDSon Low−Side (m)
G001
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
0.0 3.0 6.0 9.0 12.0 15.0 18.0 20.0
−40°C
25°C 85°C
Input Voltage (V)
Input Current (µA)
G001
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0 3.0 6.0 9.0 12.0 15.0 18.0 20.0
−40°C 25°C
85°C
Input Voltage (V)
Input Current (µA)
G001
TPS62170, TPS62171
TPS62172, TPS62173
SLVSAT8C NOVEMBER 2011REVISED SEPTEMBER 2013
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INPUT CURRENT INPUT CURRENT
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 17. Quiescent Current Figure 18. Shutdown Current
STATIC DRAIN-SOURCE-RESISTANCE (RDSon) STATIC DRAIN-SOURCE-RESISTANCE (RDSon)
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 19. High-Side Switch Figure 20. Low-Side Switch
OUTPUT VOLTAGE RIPPLE OUTPUT CURRENT
vs vs
OUTPUT CURRENT INPUT VOLTAGE
Figure 21. Output Voltage Ripple Figure 22. Maximum Output Current
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TPS62172, TPS62173
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SLVSAT8C NOVEMBER 2011REVISED SEPTEMBER 2013
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
TIME TIME
Figure 23. PWM to PSM Mode Transition Figure 24. PSM to PWM Mode Transition
TRANSIENT RESPONSE TRANSIENT RESPONSE
vs vs
TIME TIME
Figure 25. Load Transient Response in PWM Mode (200mA Figure 26. Load Transient Response from Power Save Mode
to 500mA) (100mA to 500mA)
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TRANSIENT RESPONSE TRANSIENT RESPONSE
vs vs
TIME TIME
Figure 27. Load Transient Response in PWM Mode (200mA Figure 28. Load Transient Response in PWM Mode (200mA
to 500mA), rising edge to 500mA), falling edge
STARTUP TO VOUT=3.3V STARTUP TO VOUT=3.3V
vs vs
TIME TIME
Figure 29. Startup with Iout=100mA Figure 30. Startup with Iout=500mA
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PSM MODE OPERATION PWM MODE OPERATION
vs vs
TIME TIME
Figure 31. Typical Operation in Power Save Mode Figure 32. Typical Operation in PWM mode (Iout=500mA)
(Iout=66mA)
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ON
OUTIN
peakLPSM t
L
VV
I×
-
=
)(
)(
ns
V
V
t
IN
OUT
ON 420×=
TPS62170, TPS62171
TPS62172, TPS62173
SLVSAT8C NOVEMBER 2011REVISED SEPTEMBER 2013
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DETAILED DESCRIPTION
Device Operation
The TPS6217X synchronous switched mode power converters are based on DCS-Control™ (Direct Control with
Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the advantages of
hysteretic, voltage mode and current mode control including an AC loop directly associated to the output voltage.
This control loop takes information about output voltage changes and feeds it directly to a fast comparator stage.
It sets the switching frequency, which is constant for steady state operating conditions, and provides immediate
response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The
internally compensated regulation network achieves fast and stable operation with small external components
and low ESR capacitors.
The DCS-ControlTM topology supports PWM (Pulse Width Modulation) mode for medium and heavy load
conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in
continuous conduction mode. This frequency is typically about 2.25MHz with a controlled frequency variation
depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain
high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly with the
load current. Since DCS-ControlTM supports both operation modes within one single building block, the transition
from PWM to Power Save Mode is seamless without effects on the output voltage.
Fixed output voltage versions provide smallest solution size and lowest current consumption, requiring only 3
external components. An internal current limit supports nominal output currents of up to 500mA.
The TPS6217X family offers both excellent DC voltage and superior load transient regulation, combined with
very low output voltage ripple, minimizing interference with RF circuits.
Pulse Width Modulation (PWM) Operation
The TPS6217X operates with pulse width modulation in continuous conduction mode (CCM) with a nominal
switching frequency of about 2.25MHz. The frequency variation in PWM is controlled and depends on VIN, VOUT
and the inductance. The device operates in PWM mode as long the output current is higher than half the
inductor's ripple current. To maintain high efficiency at light loads, the device enters Power Save Mode at the
boundary to discontinuous conduction mode (DCM). This happens if the output current becomes smaller than
half the inductor's ripple current.
Power Save Mode Operation
The TPS6217X's built in Power Save Mode will be entered seamlessly, if the load current decreases. This
secures a high efficiency in light load operation. The device remains in Power Save Mode as long as the inductor
current is discontinuous.
In Power Save Mode the switching frequency decreases linearly with the load current maintaining high efficiency.
The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in
both directions.
TPS6217X includes a fixed on-time circuitry. This on-time, in steady-state operation, can be estimated as:
(1)
For very small output voltages, the on-time increases beyond the result of Equation 1, to stay above an absolute
minimum on-time, tON(min), which is around 80ns to limit switching losses. The peak inductor current in PSM can
be approximated by:
(2)
When VIN decreases to typically 15% above VOUT, the TPS6217X won't enter Power Save Mode, regardless of
the load current. The device maintains output regulation in PWM mode.
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Product Folder Links: TPS62170 TPS62171 TPS62172 TPS62173
PD
L
LIMFtyppeak t
L
V
II ×+=
)(
TPS62170, TPS62171
TPS62172, TPS62173
www.ti.com
SLVSAT8C NOVEMBER 2011REVISED SEPTEMBER 2013
100% Duty-Cycle Operation
The duty cycle of the buck converter is given by D=Vout/Vin and increases as the input voltage comes close to
the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch
100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal
setpoint. This allows the conversion of small input to output voltage differences, e.g. for longest operation time of
battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
(3)
where
IOUT is the output current,
RDS(on) is the RDS(on) of the high-side FET and
RLis the DC resistance of the inductor used.
Enable / Shutdown (EN)
When Enable (EN) is set High, the device starts operation.
Shutdown is forced if EN is pulled Low with a shutdown current of typically 1.5µA. During shutdown, the internal
power MOSFETs as well as the entire control circuitry are turned off. The internal resistive divider pulls down the
output voltage smoothly. If the EN pin is Low, an internal pull-down resistor of about 400kΩis connected and
keeps it Low, to avoid bouncing. To avoid ON/OFF oscillations, a minimum slew rate of about 50mV/s is
recommended for the EN signal.
Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple
power rails.
Softstart
The internal soft start circuitry controls the output voltage slope during startup. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high-
impedance power sources or batteries. When EN is set to start device operation, the device starts switching after
a delay of about 50µs and VOUT rises with a slope of about 25mV/µs. See Figure 29 and Figure 30 for typical
startup operation.
The TPS6217X can start into a pre-biased output. During monotonic pre-biased startup, the low-side MOSFET is
not allowed to turn on until the device's internal ramp sets an output voltage above the pre-bias voltage.
Current Limit And Short Circuit Protection
The TPS6217X devices are protected against heavy load and short circuit events. At heavy loads, the current
limit determines the maximum output current. If the current limit is reached, the high-side FET will be turned off.
Avoiding shoot through current, the low-side FET will be switched on to sink the inductor current. The high-side
FET will turn on again, only if the current in the low-side FET has decreased below the low side current limit
threshold.
The output current of the device is limited by the current limit (see ELECTRICAL CHARACTERISTICS). Due to
internal propagation delay, the actual current can exceed the static current limit during that time. The dynamic
current limit can be calculated as follows:
(4)
where
ILIMF is the static current limit, specified in the electrical characteristic table,
L is the inductor value,
VLis the voltage across the inductor and
tPD is the internal propagation delay.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
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( ) ns
L
VV
II OUTIN
HSLIMFtyppeak 30×
-
+= _)(
TPS62170, TPS62171
TPS62172, TPS62173
SLVSAT8C NOVEMBER 2011REVISED SEPTEMBER 2013
www.ti.com
The dynamic high side switch peak current can be calculated as follows:
(5)
Care on the current limit has to be taken if the input voltage is high and very small inductances are used.
Power Good (PG)
The TPS6217X has a built in power good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an
open-drain output that requires a pull-up resistor (to any voltage below 7V). It can sink 2mA of current and
maintain its specified logic low level. It is high impedance when the device is turned off due to EN, UVLO or
thermal shutdown.
Under Voltage Lockout (UVLO)
If the input voltage drops, the under voltage lockout prevents misoperation of the device by switching off both the
power FETs. The under voltage lockout threshold is set typically to 2.7V. The device is fully operational for
voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts
operation again once the input voltage exceeds the threshold by a hysteresis of typically 180mV.
Thermal Shutdown
The junction temperature (Tj) of the device is monitored by an internal temperature sensor. If Tj exceeds 160°C
(typ), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off and PG
goes high impedance. When Tj decreases below the hysteresis amount, the converter resumes normal
operation, beginning with Soft Start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented
on the thermal shut down temperature.
16 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS62170 TPS62171 TPS62172 TPS62173
÷
÷
÷
÷
÷
ø
ö
ç
ç
ç
ç
ç
è
æ
×
-
×=D
SW
IN
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OUTL fL
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V
VI
(min)
(max)
(max)
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(max)(max)
L
OUTL
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II
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+=
÷
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ø
ö
ç
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æ-= 1
21
REF
OUT
V
V
RR
TPS62170, TPS62171
TPS62172, TPS62173
www.ti.com
SLVSAT8C NOVEMBER 2011REVISED SEPTEMBER 2013
APPLICATION INFORMATION
The following information is intended to be a guideline through the individual power supply design process.
Programming The Output Voltage
While the output voltage of the TPS62170 is adjustable, the TPS62171/2/3 are programmed to fixed output
voltages. For fixed output versions, the FB pin is pulled down internally and may be left floating. it is
recommended to connect it to AGND to improve thermal resistance. The adjustable version can be programmed
for output voltages from 0.9V to 6V by using a resistive divider from VOUT to AGND. The voltage at the FB pin is
regulated to 800mV. The value of the output voltage is set by the selection of the resistive divider from
Equation 6. It is recommended to choose resistor values which allow a cross current of at least 2uA, meaning the
value of R2 shouldn't exceed 400kΩ. Lower resistor values are recommended for highest accuracy and most
robust design. For applications requiring lowest current consumption, the use of fixed output voltage versions is
recommended.
(6)
In case the FB pin gets opened, the device clamps the output voltage at the VOS pin to about 7.4V.
External Component Selection
The external components have to fulfill the needs of the application, but also the stability criteria of the devices
control loop. The TPS6217X is optimized to work within a range of external components. The LC output filters
inductance and capacitance have to be considered together, creating a double pole, responsible for the corner
frequency of the converter (see Output Filter And Loop Stability section). Table 1 can be used to simplify the
output filter component