Addendum DS1, 2003-07-02 QuadFALC(R) Quad E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications PEF 22554 HT/E, Version 2.1 Abstract This document is an Addendum to the PEF 22554 HT/E, QuadFALC(R), Version 2.1 Data Sheet DS1, release date 2002-09. It describes data that has to be changed or added. 1 Referenced Standards Page 5, Related Documentation In addition to the standards listed in the Data Sheet, the device complies also with: * * * ITU-T G.705 ITU-T G.733 ITU-JT G.733 Revision History: Previous Version: -/- Major Changes: -/- Addendum 1 DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E Logic Symbol for BGA Package 2 Logic Symbol for BGA Package Page 23, Chapter 1.2, Logic Symbol VSSP VDDP(2:1) RCLK(4:1) MCLK SYNC SEC/FSC Due to the slight difference (number of power supply and ground connections) between the TQFP package and the BGA package, a separate drawing is provided for the BGA. Receive System Interface SCLKX(4:1) XDI(4:1) XPA(4:1) XPB(4:1) XPC(4:1) XPD(4:1) Transmit System Interface QuadFALC(R) PEF 22554 V2.1 P-TQFP-144 CS WR/RW RD/DS BHE/BLE ALE DBW IM RES INT VDDX(4:1) VSSX(4:1) XL1/XDOP/XIOD(4:1) XL2/XDON/XFM(4:1) VSEL VDDC(2:1) VDD(5:1) VSS(6:1) Transmit Line Interface TDI TMS TCK TRS TDO A(9:0) Boundary Scan Interface D(15:0) Receive Line Interface VDDR(4:1) VSSR(4:1) RL1/RDIP/ROID(4:1) RL2/RDIN/RCLK(4:1) SCLKR(4:1) RDO(4:1) RPA(4:1) RPB(4:1) RPC(4:1) RPD(4:1) Microprocessor Interface F0263_TQFP_22554 Figure 1 Addendum Logic Symbol (TQFP Package) 2 DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E VSSP VDDP(2:1) RCLK(4:1) MCLK SYNC SEC/FSC Logic Symbol for BGA Package Receive System Interface SCLKX(4:1) XDI(4:1) XPA(4:1) XPB(4:1) XPC(4:1) XPD(4:1) Transmit System Interface QuadFALC(R) PEF 22554 V2.1 P-BGA-160 CS WR/RW RD/DS BHE/BLE ALE DBW IM RES INT VDDX(8:1) VSSX(8:1) XL1/XDOP/XIOD(4:1) XL2/XDON/XFM(4:1) VSEL VDDC(2:1) VDD(9:1) VSS(10:1) Transmit Line Interface TDI TMS TCK TRS TDO A(9:0) Boundary Scan Interface D(15:0) Receive Line Interface VDDR(4:1) VSSR(4:1) RL1/RDIP/ROID(4:1) RL2/RDIN/RCLK(4:1) SCLKR(4:1) RDO(4:1) RPA(4:1) RPB(4:1) RPC(4:1) RPD(4:1) Microprocessor Interface F0263_BGA_22554 Figure 1A Addendum Logic Symbol (BGA Package) 3 DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E JTAG Ball Names 3 JTAG Ball Names Page 52, Chapter 2.2, Pin Definitions and Functions The BGA ball numbers are missing for the JTAG pins. They are as shown below. Table 5 Pin No. Pin Definitions - Miscellaneous Ball No. Symbol Input Output Supply Function Boundary Scan/Joint Test Access Group (JTAG) 131 B6 TRS I + PU Test Reset for Boundary Scan (active low). If not connected, an internal pullup transistor ensures high input level. If the JTAG boundary scan is not used, this pin must be connected to RES or VSS. 112 D11 TDI I + PU Test Data Input for Boundary Scan If not connected an internal pullup transistor ensures high input level. 141 D5 TMS I + PU Test Mode Select for Boundary Scan If not connected an internal pullup transistor ensures high input level. 140 C4 TCK I + PU Test Clock for Boundary Scan If not connected an internal pullup transistor ensures high input level. 113 C11 TDO O Test Data Output for Boundary Scan Addendum 4 DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E Boundary Scan 4 Boundary Scan 4.1 JTAG Instructions Page 63, Chapter 3.4.2, Boundary Scan Interface The TAP controller instruction codes 01010101B and 01010100B have been added. Both are reserved for device tests and shall not be used. 4.2 JTAG ID Page 427, Chapter 11.4.2, JTAG Boundary Scan Interface The correct Boundary Scan IDCODE field is: 0001 0000 0000 1000 1110 0000 1000 0011 (Version = 1H, Part Number = 008EH) 5 RCLK Clock Multiplexing Page 65/124, Chapter 4.1/5.1, Receive Path in E1 or T1/J1 Mode Some details have been added to the figure showing the clock multiplexing options for RCLK. recovered clock channel 1 recovered clock channel 2 recovered clock channel 3 recovered clock channel 4 A A A: controlled by CMR1.DRSS(1:0) B: controlled by GPC1.R1S(1:0) A A DCO-R channel 1 C DCO-R channel 2 C RCLK2 DCO-R channel 3 C RCLK3 DCO-R channel 4 C RCLK4 C: controlled by CMR1.RS(1:0) Figure 17/46 Addendum B RCLK1 F0131_2 Receive Clock Selection (E1/T1/J1) 5 DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E Bipolar Violation Detection 6 Bipolar Violation Detection Page 68, Chapter 4.1.6, Receive Line Coding in E1 Mode The HDB3 line code or the AMI coding is provided for the data received from the ternary or the dual rail interface. All code violations that do not correspond to zero substitution rules are detected, resulting in an increment of the 16-bit code violation counter. If a bit error causes a code violation that leads to a valid substitution pattern, this code violation is neither detected nor counted and the substitution pattern is replaced by the corresponding zero pattern. In case of the optical interface a selection between the NRZ code and the CMI Code (1T2B) with HDB3 or AMI postprocessing is provided. If CMI code is selected the receive route clock is recovered from the data stream. The CMI decoder does not correct any errors. In case of NRZ coding data is latched with the falling edge of signal RCLKI. The HDB3 code is used along with double violation detection or extended code violation detection (selectable by FMR0.EXZE). In AMI code all code violations are detected. The detected errors increment the code violation counter (16 bits length). Page 127, Chapter 5.1.6, Receive Line Coding in T1/J1 Mode The B8ZS line code or the AMI (ZCS, zero code suppression) coding is provided for the data received from the ternary or the dual rail interface. All code violations that do not correspond to zero substitution rules are detected, resulting in an increment of the 16-bit code violation counter. If a bit error causes a code violation that leads to a valid substitution pattern, this code violation is neither detected nor counted and the substitution pattern is replaced by the corresponding zero pattern. The detected errors increment the code violation counter (16 bits length). Addendum 6 DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E Signaling Marker Diagrams 7 Signaling Marker Diagrams Page 180/181, Chapter 5.5.2, Transmit System Interface The following diagrams have been modified for clarity. 125 s SYPX SCLKX T TS24 TS1 TS2 TS24 XDI 45 67F01 23456 70123 4567 XSIG A B CD A B CD A B CD A B CD ESF XSIG ABAB ABAB AB AB ABAB F12 T F ABCD ABAB Figure 71 Addendum 01 23456 7F = Time slot offset (RC0, RC1) = FS/DL-bit (XDI only) = ESF signaling bits for time slots 1...24 read only during last frame of a multiframe, = F12 signaling bits for time slots 1...24 read only during last frame of a multiframe (bit positions 4/5) F0137 1.544 MHz Transmit Signaling Highway (T1/J1) 7 DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E Signaling Marker Diagrams Multiframe n (F12 for example) Frame 1 Frame 6 Frame 12 Frame 1 RDO XDI RMFB XMFB A: Channel Translation Mode 0 RDO XDI 24 FS/ DL 1 2 3 4 5 6 7 8 9 19 20 21 22 23 24 FS/ DL 1 FS/ DL 1 RSIGM1) XSIGM B: Channel Translation Mode 1 RDO XDI FS/ DL 1 2 3 4 5 6 19 20 21 22 23 24 RSIGM1) XSIGM Notes: 1) RSIGM and XSIGM are programmed to mark only channel 24 in this example (via RTR(4:1) and TTR(4:1)). F0267_1 Figure 72 Addendum Signaling Marker for CAS/CAS-CC Applications (T1/J1) 8 DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E Clock Mode Selection 8 Clock Mode Selection Page 194/200, Chapter 6.3 and Chapter 7.3, Device Initialization E1 and T1/J1 The following text has been added: The clock mode must be programmed according to the selected MCLK frequency before any XL1/2 output is enabled (while the outputs are not yet activated by selection of the line coding). Otherwise the output pulse width might not match the pulse mask requirements. Page 277, Chapter 9.2 and Page 384, Chapter 10.2, Clock Mode Register programming for E1 and T1/J1 The following text has been added/corrected (for E1 and T1/J1 operation): Attention: Write operations to GCM5 and/or GCM6 register initiate a PLL reset (see below) and must be performed before any port configuration is done. If this is not possible set LIM01.DRS (if not set) of every channel separately before writing to these registers and reset LIM01.DRS (if it was not set before) after these write operations. 9 Device Initialization Page 192, Table 46, Initial Values after Reset (E1) The second row shall read: 2.048 8.192 MHz system clocking rate... Page 194, Table 47, Initialization Parameters (E1) The row "Framing additions" shall read: RC0RC1.ASY4, RC0RC1.SWD 10 HDLC Handling Page 221/321, Chapter 9.2/10.2, Register bit CMDR.RMC Confirmation from CPU to QuadFALC that the current frame or data block has been fetched following an RPF or RME interrupt, thus the occupied space in the RFIFO can be released. While the FIFO is empty, RMC must not be set. If RMC is given while RFIFO is already cleared, the next incoming data block is cleared instantly, although interrupts are generated. This might lead to incorrect software behaviour. Addendum 9 DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E Port RMFB Configuration 11 Port RMFB Configuration Page 269/375, Chapter 9.2/10.2, Register Description, PC(4:1) The following text has been added: RMFB is only valid, if the receive buffer is not bypassed. 12 Port RSIG Configuration Page 270/376, Chapter 9.2/10.2, Register Description, PC(4:1) The following text has been added: RSIG is only valid, if the receive buffer is not bypassed. 13 Port XMFS Configuration Page 270/376, Chapter 9.2/10.2, Register Description, PC(4:1) The following text has been added: The activity level of port XMFS can be selected to be active high or active low by programming PC5.CXMFS. This bit must not be set, if XMFS is not enabled as an input. XMFS input selection is done by programming one of the Transmit Multifunction Ports, using registers PC4(4:1).XPC(3:0). Note: XMFS must not be used together with SYPX on different Multifunction Ports. 14 Port RFSP Configuration Page 376, Chapter 10.2, Register Description, PC(4:1) in T1/J1 mode The description of register bit PC(4:1).RPC(2:0) = 111 in T1/J1 mode shall read as: "This marker is active low for 488 648 ns with a frequency of 8 kHz." Addendum 10 DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E Absolute Maximum Ratings 15 Absolute Maximum Ratings Page 420, Chapter 11.1, Absolute Maximum Ratings The allowed voltage range has been increased. The following values and the text below the table have changed: Parameter Symbol Limit Values IC supply voltage (pads, digital) VDD VDDC VDDP VDDR VDDX VPAD VRL1/RL2 - 0.3 0.5 to 3.6 4.5 V IC supply voltage (core, digital) IC supply voltage PLL (analog) IC supply voltage receive (analog) IC supply voltage transmit (analog) Voltage on any pin with respect to ground1) Voltage on RL1/RL2 with respect to ground 1) - 0.3 to 2.4 Unit V - 0.3 0.5 to 3.6 4.5 V - 0.3 0.5 to 3.6 4.5 V - 0.3 0.5 to 3.6 4.5 V - 0.3 0.5 to 3.6 4.5 V - 0.8 to 4.5 V except VDDC and VRL1/RL2 Attention: Absolute Maximum Ratings are stress ratings only, and functional operation and reliability under conditions beyond those defined in the normal operating conditions is not guaranteed. Stresses above the maximum ratings are likely to cause permanent damage to the device while extended exposure to conditions outside the operating range may have an impact on component life time. Addendum 11 DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E DC Characteristics 16 DC Characteristics Page 422/423, Chapter 11.3, DC Characteristics The transmitter output maximum leakage value and receiver maximum input voltage have been changed. Parameter Symbol Limit Values Min. Transmitter leakage current ITL Receiver peak voltage of a VR12 mark (at RL1 or RL2) Receiver differential peak voltage of a mark (between RL1 and RL2) -0.45 -0.751) VR Unit Notes 15.0 30.0 A XL1/2 = VDDX; XPM2.XLT = 1 15.0 30.0 A XL1/2 = VSSX; XPM2.XLT = 1 3.8 4.11) V RL1, RL2; RZ signals only2) VDDR +0.3 4.00 4.631) V RL1, RL2; RZ signals only2) Max. 1) Limit values must only be applied during T1 pulse over-/undershoot according to ANSI T1.403-1999. 2) RZ = return to zero Addendum 12 DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E System Interface Marker Timing (Receive) 17 System Interface Marker Timing (Receive) Page 437, Chapter 11.4.6, AC Characteristics, System Interface The timing figure has been modified for clarity. The timing values have been corrected. positive edge timing 1) positive edge timing 1) negative edge timing 1) negative edge timing 1) SCLKR 1(A) RDO RSIG RSIGM DLR RFM RMFB FREEZE 2(A) data valid 1(A) 2(A) data valid 1) active edge can be programmed to be positive or negative F0011 possible negative delay values are not explicitely drawn Figure 99 System Interface Marker Timing (Receive) Table 79 System Interface Marker Timing Parameter Values No. Parameter Limit Values Min. Typ. Unit Max. SCLKR Input Mode 1 RDO delay 0 35 ns 2 RSIGM, RMFB, DLR, RFM1), FREEZE, RSIG marker delay 0 45 ns SCLKR Output Mode 1A RDO delay -55 0 9 -20 20 ns 2A RSIGM, RMFB, DLR, RFM1), FREEZE, RSIG marker delay -55 0 9 -20 20 ns SCLKR can be input or output. 1) Timing for RMF is valid only for active high polarity selection. Addendum 13 DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E SYPR/SYPX Timing 18 SYPR/SYPX Timing Page 438/439, Chapter 11.4.6, AC Characteristics, System Interface The output timing has been corrected as shown in the table below. 1(A) active edge SCLKR SCLKX 2(A) 3(A) SYPR SYPX inactive 4(A) active low 5(A) 6(A) XMFS inactive 7(A) active low F0012 Figure 100 SYPR/SYPX Marker Timing Table 80 SYPR/SYPX Timing Parameter Values No. Parameter Limit Values Min. Typ. Unit Max. SCLKR Input Mode 1 SCLKR period (t1) 61 2 SYPR/SYPX inactive setup time 1 x t1 ns 3 SYPR/SYPX setup time 5 ns 4 SYPR/SYPX hold time 15 ns 5 XMFS inactive setup time 1 x t1 ns 6 XMFS setup time 5 ns 7 XMFS hold time 15 ns 648 ns SCLKR Output Mode 1A SCLKR period (t1) 61 2A SYPR/SYPX inactive setup time 1 x t1 Addendum 14 648 ns ns DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E SYPR/SYPX Timing Table 80 No. SYPR/SYPX Timing Parameter Values (cont'd) Parameter Limit Values Min. Typ. Unit Max. SCLKR Output Mode 3A SYPR/SYPX setup time 10 0 ns 4A SYPR/SYPX hold time 0 10 ns 5A XMFS inactive setup time 1 x t1 ns 6A XMFS setup time 10 0 ns 7A XMFS hold time 0 10 ns Addendum 15 DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E Marker Output Timing Parameters 19 Marker Output Timing Parameters Page 440, Chapter 11.4.6, AC Characteristics, System Interface The output timing has been corrected as shown in the table below. active edge1) SCLKR SCLKX 1(A) XMFB DLX XSIGM 1) active edge can be programmed to be positive or negative Figure 101 System Interface Marker Timing Table 81 System Interface Marker Timing Parameter Values No. Parameter F0013 Limit Values Min. Typ. Unit Max. SCLKR Input Mode 1 XMFB, DLX, XSIGM delay 100 ns -20 20 ns SCLKR Output Mode 1A XMFB, DLX, XSIGM delay Addendum 0 16 9 DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E XDI/XSIG Timing Parameters 20 XDI/XSIG Timing Parameters Page 441, Chapter 11.4.6, AC Characteristics, System Interface The timing has been corrected as shown in the table below. active edge1) SCLKR SCLKX 1(A) 2(A) 3(A) 4(A) XDI XSIG 1) active edge can be programmed to be positive or negative F0014 Figure 101 XDI/XSIG Marker Timing Table 81 XDI/XSIG Timing Parameter Values No. Parameter Limit Values Min. Typ. Unit Max. SCLKR Input Mode 1 XDI setup time 5 ns 2 XDI hold time 15 ns 3 XSIG setup time 5 ns 4 XSIG hold time 15 ns SCLKR Output Mode 1A XDI setup time 10 0 ns 2A XDI hold time 20 10 ns Addendum 17 DS1, 2003-07-02 QuadFALC(R) V2.1 PEF 22554 HT/E SYNC Input Timing Parameters Table 81 No. XDI/XSIG Timing Parameter Values (cont'd) Parameter Limit Values Min. Typ. Unit Max. 3A XSIG setup time 10 0 ns 4A XSIG hold time 20 10 ns 21 SYNC Input Timing Parameters Page 446, Chapter 11.4.6, AC Characteristics, System Interface The input timing has been relaxed as shown in the table below. 1 2 SYNC F0125 Figure 107 SYNC Timing Table 87 SYNC Timing Parameter Values No. Parameter Limit Values Min. Typ. Unit Max. 1 SYNC high time 30 122 % ns 2 SYNC low time 30 122 % ns 22 Typographical Errata Page 57, Table 7: "BHE" should read "BHE" Page 57, Table 8: "BLE" should read "BLE" Page 256/361, FLLB = 1: The line loopback code is transmitted in unframed mode. LLB code does not overwrite the FS/DL-bits. Addendum 18 DS1, 2003-07-02