MIPI/DSI Receiver
with HDMI Transmitter
Data Sheet
ADV7533
Rev. A
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
FEATURES
General
Low power MIPI/DSI receiver
Low power HDMI/DVI transmitter ideal for portable
applications
CEC controller and expanded message buffer (3 messages)
reduces system overhead
Incorporates HDMI v.1.3 (x.v.Color™) technology
Compatible with DVI v.1.0
Optional embedded HDCP keys to support HDCP 1.3
1.8 V, 1.2 V (optional), and 3.3 V supplies for ultralow
operating power
Audio inputs accept logic levels from 1.8 V to 3.3 V
MIPI/DSI receiver
2-, 3-, or 4-lane DSI receiver
Supports up to 800 Mbps per lane
Compatible with DPHY V.0.90 and DSI V.1.02
Supports inputs of
16-bit RGB 4:4:4
24-bit RGB 4:4:4
30-bit RGB 4:4:4
HDMI (TMDS) video out
80 MHz operation supports all video and graphics
resolutions from 480i to 1080p at 30 Hz
Programmable 2-way color space converter
Output supports
36-, 30-, or 24-bit RGB 4:4:4
36-, 30-, or 24-bit YCbCr 4:4:4
Automatic input video format timing detection (CEA-861E)
Digital audio
Supports standard S/PDIF for stereo LPCM or compressed
audio up to 192 kHz
2-channel uncompressed LPCM I2S audio up to 192 kHz
Special features for easy system design
On-chip MPU with I2C master to perform EDID reading and
HDCP operations; reports HDMI events through interrupts
and registers
5 V tolerant I2C and HPD I/Os, no extra device needed
No audio master clock needed for supporting S/PDIF
and I2S
APPLICATIONS
Mobile systems
Cellular handsets
Digital video cameras
Digital still cameras
Personal media players
Gaming
GENERAL DESCRIPTION
The ADV7533 is a multifunction video interface chip. The
ADV7533 provides a mobile industry processor interface/
display serial interface (MIPI®/DSI) input port, a high definition
multimedia interface (HDMI®) data output in a 49-ball wafer
level chip scale package (WLCSP). The display serial interface
(DSI) input provides up to four lanes of MIPI/DSI data, each
running up to 800 Mbps. The DSI Rx implements DSI video
mode operation only. The HDMI Tx supports video resolutions
using pixel clocks of up to 80 MHz.
With the optional inclusion of embedded HDCP keys, the
ADV7533 allows the secure transmission of protected content,
as specified by the HDCP 1.3 protocol.
The ADV7533 supports x.v.Color™ (gamut metadata) for a
wider color gamut.
The ADV7533 supports both S/PDIF and 2-channel I2S audio.
Its high fidelity 2-channel I2S can transmit stereo up to a 192 kHz
sampling rate. The S/PDIF can carry stereo LPCM audio or
compressed audio, including Dolby® Digital and DTS®.
The ADV7533 helps to reduce system design complexity and
cost by incorporating such features as an I2C master for EDID
reading and 5 V tolerance on the I2C and Hot Plug™ detect pins.
Fabricated in an advanced CMOS process, the ADV7533 is
available in a space saving, 49-ball, WLCSP surface mount
package. This package is RoHS compliant and specified to
operate from −10°C to +85°C.
ADV7533 Data Sheet
Rev. A | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications ..................................................................................... 4
MIPI/DSI Specifications .............................................................. 6
Absolute Maximum Ratings ............................................................ 8
ESD Caution...................................................................................8
Explanation of Test Levels ............................................................8
Pin Configuration and Function Descriptions ..............................9
Applications Information .............................................................. 11
Design Resources ....................................................................... 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
8/12—Rev. 0 to Rev. A
Changed Storage Temperature from −65°C to +150°C to −40°C
to +85°C ............................................................................................. 8
7/11—Revision 0: Initial Version
Data Sheet ADV7533
Rev. A | Page 3 of 12
FUNCTIONAL BLOCK DIAGRAM
AUDIO
DATA
CAPTURE
CEC
CONTROLLER
BUFFER
HDCP
ENCRYPTION
HDCP KEYS
N/V MEMORY
CEC_CLK
CEC
SPDIF/I2S
LRCLK
SCLK/MCLK
HDCP AND
EDID
MICRO-
CONTROLLER
DDC_SCL
DDC_SDA
SDA
SCL
HPD
INT
CTRL
ADV7533
SYNC
ADJUST
AND
GENERATION
DRx0
DRx1
DRxC
DRx2
2
2
2
2
HDMI_Tx0
HDMI_Tx1
HDMI_Tx2
HDMI_TxC
HDMI
TMDS
Tx
DSI
DECODE
POWER
AVDD
DVDD
A2VDD
V1P2
GND
V3P3
PD
COLOR
SPACE
CONVERTER
R_EXT
PVDD
DRx3
2
2
2
2
2
UP/
DOWN
DITHER
PATTERN
GENERATOR
BAND
GAP
I
2
C
SLAVE
I
2
C
MASTER
4 CH
DPHY
09821-001
Figure 1.
ADV7533 Data Sheet
Rev. A | Page 4 of 12
SPECIFICATIONS
Table 1. Electrical Specifications
Parameter Conditions Temp
Test
Level1
ADV7533BCBZ
Min Typ Max Unit
DIGITAL INPUTS
Data Inputs—Audio, CEC_CLK
Input Voltage, High (V
IH
) Full VI 1.4 3.5 V
Input Voltage, Low (V
IL
) Full VI −0.3 +0.7 V
Input Capacitance 25°C VIII 1.0 1.5 pF
I2C Lines (SDA, SCL)
Input Voltage, High (VIH) Full VI 1.3 5.5 V
Input Voltage, Low (V
IL
) Full VI −0.3 +0.6 V
I
2
C Lines (DDCSDA, DDCSCL)
Input Voltage, High (V
IH
) Default values Full VI 1.3 5.5 V
Input Voltage, Low (V
IL
) Full VI −0.3 +0.6 V
Input Voltage, High (V
IH
) Programmable optional values Full IV 3.5 5.5 V
Input Voltage, Low (V
IL
) Full IV −0.5 +1.2 V
CEC
Input Voltage, High (V
IH
) Full VI 2.0 V
Input Voltage, Low (V
IL
) Full VI 0.6 V
Output Voltage, High (V
OH
) Full VI 2.5 3.63 V
Output Voltage, Low (V
OL
) Full VI −0.3 +0.6 V
HPD
Input Voltage, High (V
IH
) Full VI 1.3 5.5 V
Input Voltage, Low (V
IL
) Full VI −0.3 +0.6 V
DIGITAL OUTPUTS—INT
Output Voltage, Low (V
OL
) Load = 5 pF Full VI 0.4 V
THERMAL CHARACTERISTICS
Thermal Resistance
θ
JC
Junction-to-Case Full V 20 °C/W
θ
JA
Junction-to-Ambient Full V 43 °C/W
Ambient Temperature Full V −10 +25 +85 °C
DC SPECIFICATIONS
Input Leakage Current, I
IL
25°C VI −1 +1 μA
POWER SUPPLY
1.8 V Supply Voltage (DVDD, AVDD, A2VDD,
PV
DD
)
Full IV 1.71 1.8 1.9 V
V1P2 = (1.2 V) Full IV 1.14 1.2 1.26 V
V1P2 = (1.8 V) Full IV 1.71 1.8 1.9 V
Supply Voltage Noise Limit
DVDD —Digital I/O Pad Logic Full IV 64 mV rms
AVDD—HDMI Analog Core Full IV 64 mV rms
V1P2—HDMI/DSI Digital Core
1.2 V
Full
IV
43
mV rms
1.8 V Full Iv 64 mV rms
A2VDD—MIPI DPHY Full IV 64 mV rms
PVDD—HDMI PLL Refer to Figure 2 Full IV mV rms
3.3 V Supply Voltage (V3P3) Full IV 3.15 3.30 3.45 V
3.3 V Supply Voltage Noise Limit Full IV 64 mV rms
Power-Down Current 25°C VI 15 μA
Operating Current
DVDD I/O pads (30 bits at 720p) Full IV 6 mA
Data Sheet ADV7533
Rev. A | Page 5 of 12
Parameter Conditions Temp
Test
Level1
ADV7533BCBZ
Min Typ Max Unit
AVDD HDMI analog core (24 bits at
720p)
Full IV 11 mA
V1P2 (1.2 V) HDMI/DSI digital core (DSI 30
bits/HDMI 24 bits at 720p)
Full IV 39 mA
A2VDD MIPI DPHY (30 bits/three
lanes/720p)
Full IV 12 mA
PVDD HDMI PLL (24 bits at 720p) Full IV 11 mA
V3P3—HDMI/HDCP Memory HDMI HDCP memory Full IV 0.3 mA
Transmitter Total Power 720p, 30-bit DSI in; 720p, 36-bit
HDMI out; typical random
pattern with CSC enabled,
HDCP enabled, audio enabled
V1P2 = 1.2 V Full IV 120 154 mW
V1P2 = 1.8 V Full VI 204 mW
AC SPECIFICATIONS
TMDS Output Clock Frequency 25°C IV 20 112 MHz
TMDS Output Clock Duty Cycle
25°C
IV
48
52
%
TMDS Differential Swing 25°C VII 800 1000 1200 mV
Differential Output Timing
Low-to-High Transition Time 25°C VII 75 175 ps
High-to-Low Transition Time 25°C VII 75 175 ps
AUDIO AC TIMING2
SCLK Duty Cycle
When N = Even Number Full IV 40 50 60 %
When N = Odd Number Full IV 49 50 51 %
I2S, S/PDIF Setup, tASU Full IV 2 ns
I
2
S, S/PDIF Hold Time, tAHLD Full IV 2 ns
LRCLK Setup Time, tASU Full IV 2 ns
LRCLK Hold Time, tAHLD Full IV 2 ns
CEC
CEC_CLK Frequency3 Full VIII 3 12 100 MHz
CEC_CLK Accuracy Full VIII −2 +2 %
CEC_CLK Duty Cycle Full VIII 40 60 %
I2C INTERFACE
SCL Clock Frequency Full VIII 400
4
kHz
SDA Setup Time, tDSU Full VIII 100 ns
SDA Hold Time, t
DHO
Full VIII 100 ns
Setup for Start, tSTASU Full VIII 0.6 μs
Hold Time for Start, tSTAH Full VIII 0.6 μs
Setup for Stop, tSTOSU Full VIII 0.6 μs
Bus Free Between Stop and Start, tBUF Full VIII 1.3 μs
SCL High, tHIGH Full VIII 0.6 μs
SCL Low, tLOW Full VIII 1.3 μs
1 See the Explanation of Test Levels section.
2 12 MHz crystal for default register settings.
3 Only applies to S/PDIF if external MCLK is used.
4 I2C data rates of 100 KHz and 400 KHz are supported.
ADV7533 Data Sheet
Rev. A | Page 6 of 12
The power supply noise sensitivity of the ADV7533 is frequency dependent. Therefore, the maximum noise limit for the PVDD is
specified in mV rms vs. frequency (see Figure 2).
70
60
50
40
30
20
10
0
1 10 100 1k 10k
09821-102
NOISE LIMIT (mV rms)
FREQUENCY (Hz)
Figure 2. PVDD Maximum Noise Limit
MIPI/DSI SPECIFICATIONS
Unless noted, timing and levels comply with MIPI DPHY standards.
Table 2. DSI High Speed (HS) Specifications
Parameters Symbol
ADV7533
Temp Test Level Min Typ Max Unit
DC SPECIFICATIONS
DSI Input Common Mode Voltage V
CMRX
25°C VII 70 330 mV
DSI Input High Threshold V
IDTH
25°C VII 70 mV
DSI Input Low Threshold V
IDTL
25°C VII −70 mV
DSI Single-Ended Input High Voltage V
IHHS
25°C VII 460 mV
DSI Single-Ended Input Low Voltage V
ILHS
25°C VII −40 mV
DSI Single-Ended Threshold for Termination Enable
VTERM-EN
25°C
VII
450
mV
Differential Input Impedance Z
ID
25°C VII 80 100 125 Ω
AC SPECIFICATIONS
Single Channel Data Rate 25°C IV 200 800 Mbps
Data to Clock Setup Time t
SETUP
25°C VII 0.15 UI
INST
Data to Clock Hold Time t
HOLD
25°C VII 0.15 UI
INST
DSI Clock Duty Cycle 25°C VII 45 50 55 %
Common-Mode Interference Beyond 450 MHz ∆V
CMRX(HF)
25°C VII 100 mV
Common-Mode Interference 50 MHz to 450 MHz ∆V
CMRX(LF)
25°C VII −50 +50 mV
Common-Mode Termination C
CM
25°C VII 60 pF
Data Sheet ADV7533
Rev. A | Page 7 of 12
REFERENCE TIME
CLKp
CLKn
0.5UI
INST
+
1UI
INST
t
SETUP
t
SKEW
t
CLKp
t
HOLD
09821-002
Figure 3. DSI Data to Clock Timing Definitions
Table 3. DSI Low Power Specifications
Parameter Symbol Temp Test Level Min Typ Max Unit
DC SPECIFICATIONS
Logic 1 Input Voltage VIH 25°C VII 880 mV
Logic 0 Input Voltage, Not in ULP State VIL 25°C VII 550 mV
Input Hysteresis VHYST 25°C VII 25 mV
AC SPECIFICATIONS
Input Pulse Rejection ESPIKE 25°C VII 300 V × ps
Minimum Pulse Width Response TMIN-RX 25°C VII 20 ns
Peak Interference Amplitude VINT 25°C VII 200 mV
Interference Frequency fINT 25°C VII 450 MHz
Table 4. DSI Pin Specifications
Parameter Conditions
ADV7533
Temp Test Level Min Typ Max Unit
DC SPECIFICATIONS
Pin Signal Voltage Range VPIN 25°C VII −50 +1350 mV
Pin Leakage Current ILEAK 25°C VII −10 +10 μA
Ground Shift VGNDSH 25°C VII −50 +50 mV
Transient Pin Voltage Level VPIN(absmax) 25°C VII −0.15 +1.45 V
Maximum Transient Time Above VPIN
(Max) or Below VPIN (Min)
TVPIN(absmax) 25°C VII 20 ns
ADV7533 Data Sheet
Rev. A | Page 8 of 12
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Digital Inputs—I2C (DDCSDA, DDCSCL,
SDA, SCL) and HPD
5.5 V to −0.3 V
Digital Inputs—MIPI/DSI 1.8 V
Digital Inputs—Video/Audio Inputs,
CEC_IO, CEC_CLK
3.63 V to −0.3 V
Digital Output Current 20 mA
Operating Temperature Range −10°C to +85°C
Storage Temperature Range −40°C to +85°C
Maximum Junction Temperature 150°C
Maximum Case Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
EXPLANATION OF TEST LEVELS
I 100% production tested.
II 100% production tested at 25°C and sample tested at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design and characterization testing.
VII Limits defined by HDMI specification; guaranteed by design and characterization testing.
VIII Parameter is guaranteed by design.
Data Sheet ADV7533
Rev. A | Page 9 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADV7533
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
09821-003
1
A
B
C
D
E
F
G
2 3 4
BALL A1
CORNER
5 6 7
DRxC– DRx0– DRx1– DRx2– DRx3–
DRxC+ DRx0+ DRx1+ DRx2+ DRx3+
V1P2
GNDV3P3 GND GND
GND
GND
GND
GND
DVDD
DVDD
SCL
DDCSCL DDCSDA
SCLK/MCLK
SDA
V1P2LRCLK
GND
GND
CECCLK
A2VDD
CEC
SPDIF/I
2
S
AVDD
DVDD
PVDDPD HPD REXT
INT
Tx2+
TxC–
TxC+Tx0–Tx0+Tx1–Tx1+Tx2–
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
F6, G6 DRx3−/DRx3+ I MIPI/DSI Differential Pair for Lane 3. Unused channel should be connected to ground.
F5, G5 DRx2−/DRx2+ I MIPI/DSI Differential Pair for Lane 2. Unused channel should be connected to ground.
F4, G4 DRx1−/DRx1+ I MIPI/DSI Differential Pair for Lane 1.
F3, G3 DRx0−/DRx0+ I MIPI/DSI Differential Pair for Lane 0.
F2, G2 DRxC−/DRxC+ I MIPI/DSI Differential Clock.
C3 PD I Power-Down. Programmable polarity is determined at power-up. The I2C address and
the PD polarity are set by the PD pin state when the supplies are applied to the
ADV7533. Internally pulled up for 1; if 0 desired, pull down to ground with a 2 kΩ
resistor. Supports typical CMOS logic levels from 1.8 V up to 3.3 V.
C5 R_EXT I Sets internal reference currents. Place a 1 KΩ resistor (1% tolerance) between this pin
and ground.
C4 HPD I Hot Plug Detect Signal. Indicates to the interface whether the receiver is connected. 1.8
V to 5.0 V CMOS logic level.
C1 SPDIF/I2S I S/PDIF or I2S Audio Data Input. Represents the S/PDIF block or the two channels of
audio available through I2S. Supports typical CMOS logic levels from1.8 V to 3.3 V.
C2 SCLK/MCLK I Audio Clock. Supports typical CMOS logic levels from1.8 V to 3.3 V. Unused input should
be connected to ground.
D3 LRCLK I Audio Left/Right Clock Input. Supports typical CMOS logic levels from1.8 V to 3.3 V.
Unused input should be connected to ground.
B7, A7 TxC−/TxC+ O Differential Clock Output. Differential clock output at pixel clock rate; TMDS logic level.
A2, A1 Tx2−/Tx2+ O Differential Output Channel 2. Differential output of the red data at 10× the pixel clock
rate; TMDS logic level.
A4, A3 Tx1−/Tx1+ O Differential Output Channel 1. Differential output of the green data at 10× the pixel
clock rate; TMDS logic level.
A6, A5 Tx0−/Tx0+ O Differential Output Channel 0. Differential output of the blue data at 10× the pixel clock
rate; TMDS logic level.
D5 INT O Interrupt. CMOS logic level. A 2 kΩ pull-up resistor to interrupt the microcontroller I/O
supply is recommended. This is a low active signal.
B4 AVDD P 1.8 V Power Supply for TMDS Outputs. Should be filtered and as quiet as possible.
D4, E3 V1P2 P Digital Logic Supply (1.2 V or 1.8 V). Set to 1.2 V for lowest power consumption. Should
be filtered and as quiet as possible.
ADV7533 Data Sheet
Rev. A | Page 10 of 12
Pin No. Mnemonic Type1 Description
G7 A2VDD P 1.8 V Power Supply for MIPI/DPHY Input. Should be filtered and as quiet as possible.
E2, E4, G1 DVDD P 1.8 V Power Supply for Digital and I/O Power Supply. Supply power to the digital logic
and I/Os. Should be filtered and as quiet as possible.
C6 PVDD P 1.8 V Power Supply for the PLL. Should be filtered and as quiet as possible. This supply is
the most noise sensitive.
B1 V3P3 P 3.3 V programming pin for HDCP nonvolatile memory.
B2, B3, B5, B6, C7,
E1, E7, F1, F7
GND P Ground for all domains.
E5 SDA C Serial Port Data I/O. Serves as the serial port data I/O slave for register access. Supports
CMOS logic levels from 1.8 V to 3.3 V.
E6 SCL C Serial Port Data Clock. Serves as the serial port data clock slave for register access.
Supports CMOS logic levels from 1.8 V to 3.3 V.
D2 DDCSDA C Serial Port Data I/O to Receiver. Serves as the master to the DDC bus. 5 V CMOS logic
level.
D1 DDCSCL C Serial Port Data Clock to Receiver. Serves as the master clock for the DDC bus. 5 V CMOS
logic level.
D6 CEC I/O CEC I/O. If unused, pin should be connected to ground.
D7 CEC_CLK I CEC External Clock. Can be from 3 MHz to 100 MHz. Settings default to 12 MHz. If
unused, pin should be connected to ground.
1 I = input, O = output, P = power supply, C = control.
Data Sheet ADV7533
Rev. A | Page 11 of 12
APPLICATIONS INFORMATION
DESIGN RESOURCES
Analog Devices, Inc., offers the following design resources:
xEvaluation kits
xReference design schematics
xHardware and software guides
xSoftware driver reference code
xHDMI compliance pretest services
Other support documentation is available under the
nondisclosure agreement (NDA) from
ATV_VideoTx_Apps@analog.com.
Other references include the following:
EIA/CEA-861E, which describes audio and video infoframes as
well as the E-EDID structure for HDMI. It is available from the
Consumer Electronics Association (CEA).
The HDMI v.1.3, the defining document for HDMI Version 1.3,
and the HDMI Compliance Test Specification Version 1.3 are
available from HDMI Licensing, LLC.
ADV7533 Data Sheet
Rev. A | Page 12 of 12
OUTLINE DIMENSIONS
A
B
C
D
E
F
G
3.500
3.460 SQ
3.420
1
234567
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
3.000
REF SQ
0.50
REF
0
8-17-2010-B
BALL A1
IDENTIFIER
0.660
0.600
0.540
END VIEW
0.270
0.240
0.210
0.390
0.360
0.330
0.360
0.320
0.280
COPLANARITY
0.05
SEATING
PLANE
Figure 5. 49-Ball Wafer Level Chip Scale Package [WLCSP]
7 mm × 7 mm Body (CB-49-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADV7533BCBZ-RL −10°C to +85°C 49-Ball Wafer Level Chip Scale Package [WLCSP] CB-49-1
EVAL-ADV7533-SAZ Evaluation Board
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other
countries.
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09821-0-8/12(A)
