Preliminary Technical Data AD9780/AD9781/AD9783
Rev. PrG | Page 23 of 32
SPI PORT, RESET, AND PIN MODE
In general, when the AD9780/AD9781/AD9783 are powered
up, an active high pulse applied to the RESET pin should follow.
This insures the default state of all control register bits. In
addition, once the RESET pin goes low, the SPI port can be
activated, so, CSB should be held high.
For applications without a controller, the AD9780/AD9781/
AD9783 also supports pin mode operation, which allows some
functional options to be pin, selected without the use of the SPI
port. Pin mode is enabled anytime the RESET pin is held high.
In pin mode, the four SPI port pins take on secondary functions
as shown in Table 13.
Table 13. SPI Pin Functions (Pin Mode)
Pin
Name Pin Mode Function
SDIO DATA (Register 0x02, Bit 7), bit value (1/0) equals pin
state (high/low)
CSB Enable Mix Mode, if CSB is high, Register 0x0A is set to
0x05 putting both DAC1 and DAC2 into mix mode
SDO Enable full power-down, if SDO is high, Register 0x03
is set to 0xFF
PARALLEL DATA PORT INTERFACE
The parallel port data interface consists of 18 differential LVDS
signals, DCO, DCI, and the sixteen DATA lines (DATA[15:0]),
as shown in Figure 56. DCO is the output clock generated by
theAD9780/AD9781/AD9783 that is used to clock out the data
from the digital data engine. The DATA lines transmit the
multiplexed I and Q data words for the I and Q DACs
respectively. The DCI provides timing information about the
parallel data as well as signals the I/Q status of the data.
As shown in Figure 56, the incoming LVDS data is latched by an
internally generated clock referred to as the data sampling
signal (DSS). DSS is a delayed version of the main DAC clock
signal CLKP/CLKN. Optimal positioning of the rising and
falling edges of DSS with respect to the incoming DATA signals
results in the most robust transmission of the DAC data.
Positioning the edges of DSS with respect to the DATA signals
is achieved by selecting the value of a programmable delay
element, SMP. A procedure for determining optimal value of
SMP is given in the Optimizing the Parallel Port Timing
section.
In addition to properly positioning the DSS edges, maximizing
the opening of the eye in the DCLK_IN and DATA signals
improves the reliability of the data port interface. The two
sources of degradation that reduce the eye in the DCLK_IN and
DATA signals are the jitter on these signals and the skew
between them. Therefore, it is recommended that the
DCLK_IN be generated in the same manner as the DATA
signals with the same output driver and data line routing. In
other words, it should be implemented as a seventeenth DATA
line with an alternating (010101…) bit sequence.
FF
FF
DCLK_IN
DATA[15:0]
FF
SET_DLY
HLD_DLY
SMP_DLY
SEEK
DCLK_OUT
CLK
DSS
DDSS
DDCI
RETIMING
AND
DEMUX
I DAC
Q DAC
06936-071
CLOCK
DISTRIBUTION
Figure 56. AD9873 Digital Data Port
OPTIMIZING THE PARALLEL PORT TIMING
Before outlining the procedure for determining the delay for
SMP (that is, the positioning of DSS with respect to the DATA
signals), it is worthwhile describing the simplified block
diagram of the digital data port. As can be seen in Figure 56, the
DATA signals are latched-in on the rising and falling edges of
DSS. From there, the data is demultiplexed and retimed before
being sent to the DACs.
The DCLK_IN signal provides timing information about the
parallel data as well as indicating the destination (that is, I DAC
or Q DAC) of the data. A delayed version of DCI is generated
by a delay element, SET and is referred to as DDCI. DDCI is
sampled by a delayed version of the DSS signal, labeled as DDSS
in Figure 56. DDSS is simply DSS delayed by a period of time,
HLD. The pair of delays, SET and HLD allow accurate timing
information to be extracted from DCLK_IN. Increasing the
delay of the HLD block, results in DCLK_IN being sampled
later in it’s cycle. Increasing the delay of the SET block, results in
DCLK_IN being sampled earlier in it’s cycle. The result of this
sampling is stored and can be queried by reading the SEEK bit.
Since DSS and DCLK_IN are the same frequency, the SEEK bit
should be a constant value. By varying the SET and HLD delay
blocks and seeing the effect on the SEEK bit, the setup and hold
timing of DSS with respect to DCLK_IN (and hence, DATA)
can be measured.
t
1
t
2
t
3
I0 Q0 I1 Q1 I2 Q2
SAMPLE 6SAMPLE 5SAMPLE 4SAMPLE 3SAMPLE 2SAMPLE 1
t
HLD0
0ps 2500ps 5000ps 7500ps 10000ps
DATA
DCLK_IN
DSS
06936-072
t
HLD0
Figure 57. Digital Data Timing
The incremental units of SET, HLD, and SMP are in units of
real time, not fractions of a clock cycle. The nominal step size