intel" 8251A PROGRAMMABLE COMMUNICATION INTERFACE m Synchronous and Asynchronous mg Asynchronous Baud RateDC to 19.2K Operation Baud w Synchronous 5-8 Bit Characters; a Fuli-Duplex, Double-Buffered. Internal or External Character Transmitter and Receiver Synchronization; Automatic Syne @ Error DetectionParity, Overrun and Insertion Framing m Asynchronous 5-8 Bit Characters; . ; Clock Rate1, 16 or 64 Times Baud mel Microprocessors nee Rate; Break Character Generation; 1, , 114, or 2 Stop Bits; False Start Bit m 28-Pin DIP Package Detection; Automatic Break Detect and @ All Inputs and Outputs are TTL Handling Compatible m Synchronous Baud RateDC to 64K w Available in EXPRESS and Military Baud Versions The Intel 8251A is the industry standard Universal Synchronous/Asynchronous Receiver/Transmitter (USART), designed for data communications with Intel's microprocessor families such as MCS-48, 80, 85, and iAPX-86, 88. The 8251A is used as a peripheral device and is programmed by the CPU to operate using virtually any serial data transmission technique presently in use (including IBM bi-sync). The USART accepts data characters from the CPU in parallel format and then converts them into'a continuous serial data stream for transmission. Simultaneously, it can receive serial data streams and convert them into parallel data charac- ters for the CPU. The USART will signal the CPU whenever it can accept a new character for transmission or whenever it has received a character for the CPU. The CPU can read the complete status of the USART at any time, These include data transmission errors and control signals such as SYNDET, TxEMPTY. The chip is fabricated using Intels high performance HMOS technology. DATA TRANSMIT Doo BUS BUFFER f= TxD re BUFFER (P +S) 4 1 | 2 |_.TxRDY CLK +1] RE ADAWRITE cB CONTROL TRANSMIT } TxE 1 2 = FO__ag Locic CONTROL _ one : s Be +d 4 a o, C6 23 (J ats cs J o,(]7 8261A 22 osA o,C) 8 21 (7) RESET OSR Tre 9 20D cik OTR -a MODEM RECEIVE wr Ch 10 19 [7] txo ET8__- CONTROL oureee FP eau 18 A TxEMPTY ATS aq KC co M12 17) crs , | a 13 16 [-) synvet/80 a RxRDY 14 1S TxRDY RxRDY necelve ae 206222-2 bate sus CONTROL | gyuoer Figure 2. Pin Configuration A 205222-1 Figure 1. Block Diagram November 1986 2-1 Order Number: 205222-002intel 8251A FEATURES AND ENHANCEMENTS The 8251A is an advanced design of the industry standard USART, the Intel 8251. The 8251A oper- ates with an extended range of Intel microproces- sors and maintains compatibility with the 8251. Fa- miliarization time is minimal because of compatibility and involves only knowing the additional features and enhancements, and reviewing the AC and DC specifications of the 8251A. The 8251A incorporates all the key features of the 8251 and has the following additional features and enhancements: e 8251A has double-buffered data paths with sepa- rate |/O registers for control, status, Data In, and Data Out, which considerably simplifies control programming and minimizes CPU overhead. * In asynchronous operations, the Receiver de- tects and handles break automatically, reliev- ing the CPU of this task. A refined Rx initialization prevents the Receiver from starting when in break state, preventing unwanted interrupts from a _ disconnected USART. At the conclusion of a transmission, TxD line will always return to the marking state unless SBRK iS programmed. * Tx Enable logic enhancement prevents a Tx Dis- able command from halting transmission until all data previously written has been transmitted. The logic also prevents the transmitter from turning off in the middle of a word. e When External Syn Detect is programmed, In- ternal Sync_Detect is disabled, dnd an External Sync Detect status is provided via a flip-flop which clears itself upon a status read. Possibility of false sync detect is minimized by ensuring that if double character sync is pro- grammed, the characters be contiguously detect- ed and also by clearing the Rx register to all ones whenever Enter Hunt command is issued in Sync mode. * As long as the 8251A is not selected, the RD and WR do not affect the internal operation of the device. The 8251A Status can be read at any time but the status update will be inhibited during status read. The 8251A is free from extraneous glitches and has enhanced AC and DC characteristics, provid- ing higher speed and better operating margins. Synchronous Baud rate from DC to 64K. 2-2 FUNCTIONAL DESCRIPTION General The 8251A is a Universal Synchronous/Asynchro- nous Receiver/Transmitter designed for a wide range of Inte! microcomputers such as 8048, 8080, 8085, 8086 and 8088. Like other I/O devices in a microcomputer system, its functional confiquration is programmed by the systems software for maximum flexibility. The 8251A can support most serial data techniques in use, including IBM bi-sync. In a communication environment an interface device must convert parallel format system data into serial format for transmission and convert incoming serial format data into parallel system data for reception. The interface device must also delete or insert bits or characters that are functionally unique to the communication technique. In essence, the interface should appear transparent to the CPU, a simple input or output of byte-oriented system data. Data Bus Buffer This 3-state bidirectional, 8-bit buffer is used to inter- face the 8251A to the system Data Bus. Data is transmitted or received by the buffer upon execution of INput or OUTput instructions of the CPU. Control words, Command words and Status information are also transferred through the Data Bus Buffer. The Command Status, Data-In and Data-Out registers are separate, 8-bit registers communicating with the system bus through the Data Bus Buffer. This functional block accepts inputs from the system Control bus and generates control signals for overall device operation. It contains the Control Word Reg- ister and Command Word Register that store the various control formats for the device functional defi- nition. RESET (Reset) A high on this input forces the 8251A into an Idle mode. The device will remain at Idle until a new set of control words is written into the 8251A to Program its functional definition. Minimum RESET pulse width is 6 tcy (clock must be running). A command reset operation also puts the device into the Idle state.intel 8251A TRANSMIT BUFFER P+ !x0 iP -S) Pe TxROY TRANSMIT contRon [~~ TxEMPTY Tat DSA OTR. MODEM cys CONTROL RTS a INTERNAL DATA BUS U RECEIVE BUFFER fe-RxD y (S$ -P) L | pRxADY RECEIVE J AxC CONTROL jae SYNDET/ BRKDET 205222-9 Figure 3. 8251A Block Diagram Showing Data Bus Buffer and Read/Write Logic Functions CLK (Clock) The CLK input is used to generate internal device timing and is normally connected to the Phase 2 (TTL) output of the Clock Generator. No external in- puts or outputs are referenced to CLK but the fre- quency of CLK must be greater than 30 times the Receiver or Transmitter data bit rates. WR (Write) A low on this input informs the 8251A that the CPU is writing data or control words to the 8251A. RD (Read) A low on this input informs the 8251A that the CPU is reading data or status information from the 8251A. 2-3 c/D RO WR CS 0 0 1 0 | 8251A DATA DATA BUS 0 1 0 0 |DATABUS 8251A DATA 1 0 1 0 | STATUS DATA BUS 1 1 0 0 | DATA BUS CONTROL x 1 1 0 |DATABUS 3-STATE x x xX 1 |DATABUS > 3-STATE C/D (Control/Data) This input, in conjunction with the WR and AD in- puts, informs the 8251A that the word on the Data Bus is either a data character, control word or status information. 1 = CONTROL/STATUS; 0 = DATA.intel 8251A CS (Chip Select) A low on this input selects the 8251A. No reading or writing will occur unless the device is selected. When CS is high, the Data Bus is in the float state and RD and WR have no effect on the chip. Modem Control The 8251A has a set of control inputs and outputs that can be used to simplify the interface to almost any modem. The modem control signals are general purpose in nature and can be used for functions oth- er than modem control, if necessary. DSR (Data Set Ready) The DSR input signal is a general-purpose, 1-bit in- verting input port. Its condition can be tested by the CPU using a Status Read operation. The DSR input is normally used to test modem conditions such as Data Set Ready. DTR (Data Terminal Ready) The DTR output signal is a general-purpose, 1-bit inverting output port. It can be set low by program- ming the appropriate bit in the Command Instruction word. The DTR output signal is normally used for modem control such as Data Terminal Ready. RTS (Request to Send) The RTS output signal is a general-purpose, 1-bit inverting output port. It can be set low by program- ming the appropriate bit in the Command Instruction word. The RTS output signal is normally used for modem control such as Request to Send. CTS (Clear to Send) A low on this input enables the 8251A to transmit serial data if the Tx Enable bit in the Command byte is set to a one. If either a Tx Enable off or CTS off condition occurs while the Tx is in operation, the Tx will transmit all the data in the USART, written prior to Tx Disable command before shutting down. Transmitter Buffer The Transmitter Buffer accepts paralle! data from the Data Bus Buffer, converts it to a serial bit stream, inserts the appropriate characters or bits (based on the communication technique) and outputs a com- posite serial stream of data on the TxD output pin on the falling edge of TxC. The transmitter will begin transmission upon being enabled if CTS = 0. The TxD tine will be held in the marking state immediate- ly upon a master Reset or when Tx Enable or CTS is off or the transmitter is empty. Transmitter Control The Transmitter Control manages ail activities asso- ciated with the transmission of seria) data. It accepts and issues signals both externally and internally to accomplish this function. TxRDY (Transmitter Ready) This output signals the CPU that the transmitter is ready to accept a data character. The TxRDY output pin can be used as an interrupt to the system, since it is masked by TxEnable; or, for Potled operation, the CPU can check TxRDY using a Status Read op- eration. TxRDY is automatically reset by the leading edge of WR when a data character is loaded from the CPU. Note that when using the Polled operation, the TxRDY status bit is not masked by TxEnable, but will only indicate the Empty/Full Status of the Tx Data Input Register. TxE (Transmitter Empty) When the 8251A has no characters to send, the TxEMPTY output will go high. It resets upon re- ceiving a character from CPU if the transmitter is enabled. TxEMPTY remains high when the transmit- ter is disabled. TxEMPTY can be used to indicate the end of a transmission mode, so that the CPU knows when to turn the line around in the half- duplex operational mode. In the Synchronous mode, a high on this output indicates that a character has not been loaded and the SYNC character or characters are about to be or are being transmitted automatically as fillers. Tx EMPTY does not go low when the SYNC characters are being shifted out.8251A DATA BUS BUFFER RESET CLK ~ READ/WRITE Cc/D CONTROL LoGic wR INTERNAL DATA BUS TxRDY TxEMPTY Tal RECEIVE BUFFER (S -P) RECEIVE CONTROL Rae SYNDET/ BRKDET 205222-4 Figure 4. 8251A Block Diagram Showing Modem and Transmitter Buffer and Control Functions TxC (Transmitter Clock) The Transmitter Clock controls the rate at which the character is to be transmitted. In the Synchronous transmission mode, the Baud Rate (1x) is equal to the TxC frequency. In Asynchronous transmission mode, the baud rate is a fraction of the actual TxC frequency. A portion of the mode instruction selects this factor; it can be 1, %4 or Yeq the TxC. For Example: \f Baud Rate equals 110 Baud, TxC equals 110 Hz in the 1x mode. TxC equals 1.72 kHz in the 16x mode. TxC equals 7.04 kHz in the 64x mode. The falling edge of TxC shifts the serial data out of the 8251A. Receiver Buffer The Receiver accepts serial data, converts this seri- al input to parallel format, checks for bits or charac- ters that are unique to the communication technique and sends an assembled character to the CPU. Serial data is input to RxD pin, and is clocked in on the rising edge of AxC. 2-5 Receiver Control This functional block manages all receiver-related activities which consists of the following features. The RxD initialization circuit prevents the 8251A from mistaking an unused input line for an active iow data line in the break condition. Before starting to receive serial characters on the RxD line, a valid 1 must first be detected after a chip master Reset. Once this has been determined, a search for a valid low (Start bit) is enabled. This feature is only active in the asynchronous mode, and is only done once for each master Reset. The False Start bit detection circuit prevents false starts due to a transient noise spike by first detecting the falling edge and then strobing the normal center of the Start bit (RxD = low). Parity error detection sets the corresponding status bit. The Framing Error status bit is set if the Stop bit is absent at the end of the data byte (asynchronous mode).tte 8251A RxRDY (Receiver Ready) This output indicates that the 8251A contains a character that is ready to be input to the CPU. RxRDY can be connected to the interrupt structure of the CPU or, for polled operation, the CPU can check the condition of RxRDY using a Status Read operation. RxEnable, when off, holds RxRDY in the Reset Con- dition. For Asynchronous mode, to set RxRDY, the Receiver must be enabled to sense a Start Bit and a complete character must be assembled and trans- ferred to the Data Output Register. For Synchronous mode, to set RxRDY, the Receiver must be enabled and a character must finish assembly and be trans- ferred to the Data Output Register. Failure to read the received character from the Rx Data Output Register prior to the assembly of the next Rx Data character will set overrun condition er- ror and the previous character will be written over and lost. lf the Rx Data is being read by the CPU when the internal transfer is occurring, overrun error will be set and the old character will be lost. RxC (Receiver Clock) The Receiver Clock controls the rate at which the character is to be received. In Synchronous Mode, the Baud Rate (1x) is equal to the actual frequency of RxC. In Asynchronous Mode, the Baud Rate is a fraction of the actual RxC frequency. A portion of the mode instruction selects this factor: 1, Ye or Yea the RxC. For Example: Baud Rate equals 300 Baud, if RxC equals 300 Hz in the 1x mode; RxC equals 4800 Hz in the 16x mode; RxC equals 19.2 kHz in the 64x mode. Baud Rate equals 2400 Baud, if RxC equals 2400 Hz in the 1x mode; RxC equals 38.4 kHz in the 16 mode; RxC equals 153.6 kHz in the 64 mode. PL. -_ TRANSMIT BUFFER (P -$) = TxD p TxRDY TRANSMIT conTROL [> TXEMPTY BUS B, D9 BUFFER RESET, CLK __o} ne aD/WRITE Kk) c/O____[ CONTROL RD. q toaic ; wa. oO cd bsAR oTR. J MODEM CTS CONTROL RTS a INTERNAL DATA BUS a TC av, BRKDET 205222-5 Figure 5. 8251A Block Diagram Showing Receiver Buffer and Control Functions 2-6intel 8251A Data is sampled into the 8251A on the rising edge of RxC. NOTE: in most communication systems, the 8251A will be handling both the transmission and reception oper- ations of a single link. Consequently, the Receive and Transmit Baud Rates will be the same. Both TxG and AxC will require identical frequencies for this operation and can be tied together and con- nected to a single frequency source (Baud Rate Generator) to simplify the interface. SYNDET (SYNC Detect/ BRKDET Break Detect) This pin is used in Synchronous Mode for SYNDET and may be used as either input or output, program- mable through the Control Word. It is reset to output mode low upon RESET. When used as an output (internal Sync mode), the SYNDET pin will go high to indicate that the 8251A has located the SYNC character in the Receive mode. If the 8251A is pro- grammed to use double Sync characters (bi-sync), then SYNDET will go high in the middle of the last bit of the second Sync character. SYNDET is auto- matically reset upon a Status Read operation. When used as an input (external SYNC detect mode), a positive going signal will cause the B251A to start assembling data characters on the rising edge of the next RxC. Once in SYNC, the high input signal can be removed. When External SYNC Detect is programmed, Internal SYNC Detect is dis- abled. BREAK (Async Mode Only) This output will go high whenever the receiver re- mains low through two consecutive stop bit se- quences (including the start bits, data bits, and parity bits). Break Detect may also be read as a Status bit. It is reset only upon a master chip Reset or Rx Data returning to a one state. 5 ADDRESS BUS ' | | , CONTROL BUS | 70 R| WO W| RESET 23 (TTL) 7 DATA BUS Ss cap 6 OSS. D,-D) RD WR RESET CLK 8251A 205222-6 Figure 6. 8251A Interface to 8080 Standard System Busintel 8251A DETAILED OPERATION DESCRIPTION General The complete functional definition of the 8251A is programmed by the systems software. A set of con- trol words must be sent out by the CPU to initialize the 8251A to support the desired communications format. These control words will program the: BAUD RATE, CHARACTER LENGTH, NUMBER OF STOP BITS, SYNCHRONOUS or ASYNCHRONOUS OP- ERATION, EVEN/ODD/OFF PARITY, etc. In the Synchronous Mode, options are also provided to se- lect either internal or external character synchroni- zation. Once programmed, the 8251A is ready to perform its communication functions. The TxRDY output is raised high to signal the CPU that the 8251A is ready to receive a data character from the CPU. This output (TxRDY) is reset automatically when the CPU writes a character into the 8251A. On the other hand, the 8251A receives serial data from the MO- DEM or I/O device. Upon receiving an entire charac- ter, the RxRDY output is raised high to signal the CPU that the 8251A has a complete character ready for the CPU to fetch. RxRDY is reset automatically upon the CPU data read operation. The 8251A cannot begin transmission until the Tx Enable (Transmitter Enable) bit is set in the Com- mand Instruction and it has received a Clear To Send (CTS) input. The TxD output will be held in the marking state upon Reset. C/O =1 MODE INSTRUCTION c/o =1 SYNC CHARACTER 1 SYNC MODE ONLY * c/O=1 SYNC CHARACTER 2 ciD = 14 COMMAND INSTRUCTION c/D=0 + DATA c/D=1 COMMAND INSTRUCTION OATA COMMAND INSTRUCTION 205222-7 *The second sync character is skipped if mode instruction has programmed the 8251A to single character sync mode. Both sync characters are skipped if mode instruction has programmed the 8251A to async mode. Figure 7. Typical Data Block 2-8 Programming the 8251A Prior to starting data transmission or reception, the 8251A must be loaded with a set of control words generated by the CPU. These control signals define the complete functional definition of the 8251A and must immediately follow a Reset operation (internal or external). The control words are split into two formats: 1. Mode Instruction 2. Command Instruction Mode Instruction This instruction defines the general operational characteristics of the 8251A. It must follow a Reset operation (internal or external). Once the Mode In- struction has been written into the 8251A by the CPU, SYNC characters or Command Instructions may be written. Command Instruction This instruction defines a word that is used to control the actual operation of the 8251A. Both the Mode and Command Instructions must conform to a specified sequence for proper device Operation (see Figure 7). The Mode Instruction must be written immediately following a Reset operation, prior to using the 8251A for data communication. All contro! words written into the 8251A after the Mode Instruction will load the Command Instruction. Command instructions can be written into the 8251A at any time in the data block during the operation of the 8251A. To return to the Mode Instruction format, the master Reset bit in the Command Instruction word can be set to initiate an internal Reset opera- tion which automatically places the 8251A back into the Mode Instruction format. Command Instructions must follow the Mode Instruction or Sync characters. Mode Instruction Definition The 8251A can be used for either Asynchronous or Synchronous data communication. To understand how the Mode Instruction defines the functional op- eration of the 8251A, the designer can best view the device as two separate components, one Asynchro- nous and the other Synchronous, sharing the same package. The format definition can be changed only after a master chip Reset. For explanation purposes the two formats will be isolated.intel 8251A NOTE: When parity is enabled it is not considered as one of the data bits for the purpose of programming word length. The actual parity bit received on the Rx Data line cannot be read on the Data Bus. In the case of a programmed character length of less than 8 bits, the least significant Data Bus bits will hold the data; unused bits are dont care when writing data to the 8251A, and will be zeros when reading the data from the 8251A. Asynchronous Mode (Transmission) Whenever a data character is sent by the CPU the 8251A automatically adds a Start bit (low level) fol- lowed by the data bits (least significant bit first), and the programmed number of Stop bits to each char- acter. Also, an even or odd Parity bit is inserted prior to the Stop bit(s), as defined by the Mode Instruc- tion. The character is then transmitted as a serial data stream on the TxD output. The serial data is shifted out on the falling edge of TxC at a rate equal to 1, Ye, or Yeq that of the TxC, as defined by the Mode Instruction. BREAK characters can be contin- uously sent to the TxD if commanded to do so. When no data characters have been loaded into the 8251A the TxD output remains high (marking) un- less a Break (continuously low) has been pro- grammed. Asynchronous Mode (Receive) The RxD line is normally high. A falling edge on this line triggers the beginning of a START bit. The validi- ty of this START bit is checked by again strobing this bit at its nominal center (16X or 64X mode only). Ifa low is detected again, it is a valid START bit, and the bit counter will start counting. The bit counter thus locates the center of the data bits, the parity bit (if it exists) and the stop bits. {f parity error occurs, the parity error flag is set. Data and parity bits are sam- pled on the RxD pin with the rising edge of the RxC. If a low level is detected as the STOP bit the Fram- ing Error flag will be set. The STOP bit signals the end of a character. Note that the receiver requires only one stop bit, regardless of the number of stop bits programmed. This character is then loaded into the parallel i/O buffer of the 8251A. The RxRDY pin is raised to signal the CPU that a character is ready to be fetched. If a previous character has not been fetched by the CPU, the present character replaces it in the 1/O buffer, and the OVERRUN Error flag 0, De O, DBD, 0, DB, Dy BAUD RATE FACTOR 0 1 0 1 0 9 1 1 SYNC MODE (VX) | (16) | (64x) CHARACTER LENGTH 0 1 Qo 1 er a 0 1 1 5 6 7 8 BITS | BITS | Bits | BITS PARITY ENABLE 1> ENABLE 0 = DISABLE EVEN PARITY GENERATION/CHECK 1= EVEN 0-000 NUMBER OF STOP BITS 9 1 0 1 0 a 1 1 7 TA 2 INVALID] git | sits | BITS (ONLY AFFECTS Tx; Rx NEVER REQUIRES MORE THAN ONE STOP BIT) 205222-8 Figure 8. Mode Instruction Format, Asynchronous Modeintel 8251A is raised (thus the previous character is lost). All of the error flags can be reset by an Error Reset In- struction. The occurrence of any of these errors will not affect the operation of the 8251A. Synchronous Mode (Transmission) The TxD output is continuously high until the CPU sends its first character to the 8251A which usually is a SYNC character. When the CTS line goes iow, the first character is serially transmitted out. All char- acters are shifted out on the falling edge of TxC. Data is shifted out at the same rate as the TxC. Once transmission has started, the data stream at the TxD output must continue at the TxC rate. If the CPU does not provide the 8251A with a data charac- ter before the 8251A Transmitter Buffers become empty, the SYNC characters (or character if in single SYNC character mode) will be automatically inserted in the TxD data stream. In this case, the TxXEMPTY pin is raised high to signal that the 8251A is empty and SYNC characters are being sent out. TxEMPTY does not go low when the SYNC is being shifted out (see figure below). The TxEMPTY pin is internally reset by a data character being written into the 8251A. TRANSMISSION FORMAT GENERATED TRANSMITTER OUTPUT DoQ1---~ Dx = BY 82514 i 4,4 ! s START PARITY sToP TxD MARKING BIT DATA BITS BIT sive 4 DOES NOT APPEAR RECEIVER INPUT Oo D1---Dx ON THE DATA BUS thet of START PARITY stop RxD BIT DATA BITS nT ee | 4+ PROGRAMMED CHARACTER LENGTH CPU BYTE (5-8 BITS/CHAR) 44 7y DATA CHARACTER Lt ASSEMBLED SERIAL DATA OUTPUT (TxD) + F 1 START BIT DATA CHARACTER PARITY BIT STOP BITS 4 RECEIVE FORMAT SERIAL DATA INPUT (RxD) 35 START BIT 4 1 F DATA CHARACTER PARITY BIT $ STOP BITS *NOTE: CPU BYTE (5-8 BITS/CHAR)* _; DATA CHARACTER | ff if character length is defined as 5, 6, or 7 bits the unused bits are set to zero. 205222-9 Figure 9. Asynchronous Modeintel 8251A AUTOMATICALLY INSERTED BY USART TxD pata | DATA | SYNC 1 | SYNC 2 DATA | ~-- ~ | FALLS UPON CPU WRITING A TxEMPTY / CHARACTER TO THE USART x NOMINAL CENTER OF LAST BIT 205222-10 i the USART ends the HUNT mode and is in charac- ron eive Synch onous Mode (Rec ) ter synchronization. The SYNDET pin is then set In this mode, character synchronization can be inter- high, and is reset automatically by a STATUS READ. nally or externally achieved. If the SYNC mode has If parity is programmed, SYNDET will not be set until been programmed, ENTER HUNT command should the middle of the parity bit instead of the middle of be included in the first command instruction word the last data bit. written. Data on the RxD pin is then sampled on the rising edge of RxC. The content of the Rx buffer is In the external SYNC mode, synchronization is compared at every bit boundary with the first SYNC achieved by applying a high level on the SYNDET character until a match occurs. If the 8251A has _ pin, thus forcing the 8251A out of the HUNT mode. been programmed for two SYNC characters, the The high level can be removed after one RxC cycle. subsequent received character is also compared; An ENTER HUNT command has no effect in the when both SYNC characters have been detected, asynchronous mode of operation. D, Dg OD, Dy Dz OD, D, Dy scs esol EP pew | ty] bl, 9 Oo CHARACTER LENGTH L____,.. 0 1 0 4 bo 6 0 1 1 6 7 BITS | BITS BITS BITS $$ PARITY ENABLE (1 = ENABLE) {0 = DISABLE) nn ree EVEN PARITY GENERATION/CHECK 1>= EVEN 0= 000 te EXTERNAL SYNC DETECT 1 = SYNDET IS AN INPUT 0 = SYNDET IS AN OUTPUT SINGLE CHARACTER SYNC 1= SINGLE SYNC CHARACTER 0 = DOUBLE SYNC CHARACTER NOTE: 205222~11 In external sync mode, programming double character sync will affect only the Tx. Figure 10. Mode Instruction Format, Synchronous Modeintel 8251A Parity error and overrun error are both checked in the same way as in the Asynchronous Rx mode. Parity is checked when not in Hunt, regardless of whether the Receiver is enabled or not. The CPU can command the receiver to enter the HUNT mode if synchronization is lost. This will also set all the used character bits in the buffer to a one, thus preventing a possible false SYNDET caused by data that happens to be in the Rx Buffer at ENTER HUNT time. Note that the SYNDET F/F is reset at each Status Read, regardless of whether internal or external SYNC has been programmed. This does not cause the 8251A to return to the HUNT mode. When in SYNC mode, but not in HUNT, Sync Detection is still functional, but only oc- curs at the known word boundaries. Thus, if one Status Read indicates SYNDET and a second Status Read also indicates SYNDET, then the pro- grammed SYNDET characters have been received since the previous Status Read. (If double character sync has been programmed, then both sync charac- ters have been contiguously received to gate a SYN- DET indication). When external SYNDET mode is selected, internal Sync Detect is disabled, and the SYNDET F/F may be set at any bit boundary. COMMAND INSTRUCTION DEFINITION Once the functional definition of the 8251A has been programmed by the Mode Instruction and the Sync characters are loaded (if in Sync Mode) then the device is ready to be used for data communica- tion. The Command Instruction controls the actual operation of the selected format. Functions such as: Enable Transmit/Receive, Error Reset and Modem Controls are provided by the Command instruction. Once the Mode Instruction has been written into the 8251A and Sync characters inserted, of necessary, then all further control writes (C/D = 1) willloada Command Instruction. A Reset Operation (internal or external) will return the 8251A to the Mode Instruc- tion format. NOTE: Internal Reset on Power-up: When power is first applied, the 8251A may come up in the Mode, Sync character or Command format. To guarantee that the device is in the Command In- struction format before the Reset command is is- sued, it is safest to execute the worst-case initializa- tion sequence (sync mode with two sync charac- ters). Loading three 00Hs consecutively into the de- vice with C/D = 1 configures sync operation and writes two dummy OOH sync characters. An Internal Reset command (40H) may then be issued to return the device to the idle state. CPU BYTES (5-8 BITS/CHAR}) DATA CHARACTERS ASSEMBLED SERIAL DATA OUTPUT (TxD) SYNC CHAR 1 SYNC CHAR 2 + Ff DATA CHARACTERS RECEIVE FORMAT SERIAL DATA INPUT (RxD) af SYNC CHAR 1 SYNC CHAR 2 mf DATA CHARACTERS CPU BYTES (5-8 BITS/CHAR} DATA CHARACTERS 4 ? F 205222-12 Figure 11. Data Format, Synchronous Mode 2-128251A D, Dg 0, Dy 03 22 2, Do EH | IR | RTS | ER |SBAK] Axe | DIR | TKEN TRANSMIT ENABLE + = enable 0 = disable DATA TERMINAL READY high will force OTR output to zero RECEIVE ENABLE 1 = enable 0 = disable SEND BREAK CHARACTER 1 = forces TxD low Q = normal operation ERROR RESET 1 = reset error flags PE. OE, FE REQUEST TO SEND high will force RTS Output to zero INTERNAL RESET high returns 82514 to Mode Instruction Format ENTER HUNT MODE NOTE: Error Reset must be performed whenever RxEnable and Enter Hunt are programmed. 1 - enable search for Syne Characters "(HAS NO EFFECT IN ASYNC MODE) 205222-13 Figure 12. Command Instruction Format STATUS READ DEFINITION In data communication systems it is often necessary to examine the status of the active device to as- certain if errors have occurred or other conditions that require the processors attention. The 8251A has facilities that allow the programmer to read the status of the device at any time during the func- tional operation. (Status update is inhibited during status read.) 2-13 A normal read command is issued by the CPU with C/D = 1 to accomplish this function. Some of the bits in the Status Read Format have identical meanings to external output pins so that the 8251A can be used in a completely polled or interrupt-driven environment. TXRDY is an excep- tion.intel 8251A Note that status update can have a maximum delay of 28 clock periods from the actual event affecting the status. D, De Dy dD, Dy Dz D, Do SYNDET/ - DSR BRKDET FE OE PE TxEMPTY] RxRDY | TxRDY tC. Note SAME DEFINITIONS AS 1/0 PINS PARITY ERROR The PE flag ts set when a parity error is detected. It is reset by the ER bit of the Command Instruction. PE does not inhibit operation of the 82514 OVERRUN ERROR The OE flag Is set when the CPU does not read a character before the next one becomes available Its reset by the ER bet of the Command Instruction O does not inhibit operation of the 82514 however, the previously overrun character 15 lost. FRAMING ERROR (Async only) The FE flag is set when a valid Stop bit +s not detected at the rrr end of every character. It 1s reset by the ER bit of the Command Instruction. FE does not inhibit the operation of the 82514 DATA SET READY Indicates that the DSR 1s at a zero level 205222-14 NOTE: 1. TxRDY status bit has different meanings from the TxRDY output pin. The former is not conditioned by CTS and TxEN; the latter is conditioned by both CTS and TxEN.. i.e. TxRDY status bit = DB Buffer Empty TxRDY pin out = DB Buffer Empty (CTS = 0) (TxXEN = 1) Figure 13, Status Read Format 2-14intel 8251A APPLICATIONS OF THE 8251A ( ADDRESS BUS e Lh u | CONTROL BUS : i DATA BUS t T T | i} Jeb Us ! ree3rr- | pJ+_-+4 ElaroTt 4 CONVERT TD }_-_+! (OPT) }+___- L..-4d } Rx re | BAUD RATE CRT GENERATOR TERMINAL 8251A 205222-15 Figure 14. Asynchronous Serial Interface to CAT Terminal, DC--9600 Baud , ADDRESS BUS if |_| ) ree Bus 4 iL BUS \ Ted TxO SYNCHRONOUS TERMINAL 8251A Axc Pp] OR PERIPHERAL ra DEVICE SYNDET 205222-16 Figure 15. Synchronous Interface to Terminal or Peripheral Device 2-15intel 8251A APPLICATIONS OF THE 8251A (Continued) t ADORESS BUS 5 am 4 CONTROL BUS 4 5 DATA BUS if RxD J~_ TD _ PHONE osk b= ASYNG LINE OTR b+ MODEM INTER _ FACE 82518 CTS ats Ast fe BAUD 5 RATE Tae GENERATOR TELEPHONE LINE 205222-18 Figure 16. Asynchronous Interface to Telephone Lines ADDHESS BUS CONTROL BUS DATA 8US Axt Txt SYNDET cts ATs TELEPHONE LINE 205222-17 Figure 17. Synchronous Interface to Telephone Lines NOTES: 1. AC timings measured Voy = 2.0 Vo, = 0.8, and with load circuit of Figure 18. 2. Chip Select (CS) and Command/Data (C/D) are considered as Addresses. 3. Assumes that Address is valid before Rp |. 4. This recovery time is for Mode Initialization only. Write Data is allowed only when TxRDY = 1. Recovery Time between Writes for Asynchronous Mode is 8 tcy and for Synchronous Mode is 16 tcy. 5. The TxC and RxC frequencies have the following limitations with respect to CLK: For 1x Baud Rate, fry or fay < 1/(30 tcy): For 16x and 64x Baud Rate, fr, of fax < 1/(4.5 toy). This applies to Baud Rates less than or equal to 64K Baud. 6. Reset Pulse Width = 6 toy minimum; System clock must be running during Reset. 7. Status update can have a maximum delay of 28 clock periods from the event affecting the status. 8. In external sync mode the tes spec. requires the ratio of the system clock (clock) to receive or transmit bit ratios to be greater than 34. 9. A float is defined as the point where the data bus falls betow a logic 1 (2.0V @ Igy limit) or rises above a Logic 0 (0.8V @ lo. limit). . 2-16intel 8251A ABSOLUTE MAXIMUM RATINGS* Ambient Temperature Under Bias ...... 0C to 70C Storage Temperature .......... ~ 65C to + 150C Voltage on Any Pin with Respect to Ground.......... 0.5V to +7V Power Dissipation ............... 2.0... e eee 1W NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WAANING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. D.C. CHARACTERISTICS T, = 0C to 70C, Voc = 5.0V 10%, GND = OV* Symbol Parameter Min Max Unit Test Conditions VIL Input Low Voltage 0.5 0.8 Vv Vin Input High Voitage 2.0 Voc Vv VoL Output Low Voltage 0.45 Vv lot = 2.2 mA Vou Output High Voltage 2.4 v lon = 400 nA loFL Output Float Leakage +10 pA Vout = Voc to 0.45V hie Input Leakage +10 pA Vin = Voc to 0.45V loc Power Supply Current 100 ma All Outputs = High CAPACITANCE Ta = 25C, Voc = GND = OV Symbol! Parameter Min Max Unit Test Conditions Cin Input Capacitance 10 pF fe = 1 MHz Clio |/O Capacitance 20 pF Unmeasured pins returned to GND A.C. CHARACTERISTICS Ty, = 0C to 70C, Vcc = 5.0V + 10%, GND = OV* Bus Parameters (Note 1) READ CYCLE Symbol Parameter Min Max Unit Test Conditions tar Address Stable Before READ (CS, C/D) 0 ns (Note 2) tra Address Hold Time for READ (CS, C/D) 0 ns (Note 2) trrR READ Pulse Width 250 ns tap Data Delay from READ 200 ns 3, CL = 150 pF tor READ to Data Floating 10 100 ns (Note 1, 9) WRITE CYCLE Symbol Parameter Min Max Unit Test Conditions taw Address Stable Before WRITE 0 ns twa Address Hold Time for WRITE 0 ns tww WRITE Pulse Width 250 ns tpw Data Set-Up Time for WAITE 150 ns two Data Hold Time for WRITE. 20 ns tay Recovery Time Between WRITES 6 toy (Note 4) 2-17intel 8251A A.C. CHARACTERISTICS (Continued) OTHER TIMINGS Symbol Parameter Min Max Unit | Test Conditions toy Clock Period 320 1350 ns_ | (Note 5, 6) to Clock High Pulse Width 120 tcy 90 ns to Clock Low Pulse Width 90 ns tp, te Clock Rise and Fall Time 20 ns totx TxD Delay from Falling Edge of TxC 1 ps tx Transmitter tnput Clock Frequency 1x Baud Rate DC 64 kHz 16x Baud Rate DC 310 kHz 64x Baud Rate DC 615 kHz trpw Transmitter Input Clock Pulse Width 1x Baud Rate 12 toy 16x and 64x Baud Rate 1 tcy ttpp Transmitter Input Clock Pulse Delay 1x Baud Rate 15 tcy 16x and 64x Baud Rate 3 toy fax Receiver Input Clock Frequency 1x Baud Rate DC 64 kHz 16x Baud Rate DC 310 kHz 64x Baud Rate DC 615 kHz tapw Receiver Input Clock Pulse Width 1x Baud Rate 12 toy 16x and 64x Baud Rate 1 toy tapp Receiver Input Clock Pulse Delay 1x Baud Rate 15 tcy 16x and 64x Baud Rate 3 tcy tTxADY TxRDY Pin Delay from Center of Last Bit 14 tcy | (Note 7) trxADY CLEAR | TXRDY | from Leading Edge of WR 400 ns_ | (Note 7) trxADY RxRDY Pin Delay from Center of Last Bit 26 tcy | (Note 7) tRxADY CLEAR | RxRDY | from Leading Edge of RD 400 ns_ | (Note 7) tis Internal SYNDET Delay from Rising Edge of RxC 26 toy | (Note 7) tes External SYNDET Set-Up Time After Rising Edge of AxC 16 tcy | tapp-tcy | ms | (Note 7) tTxEMPTY TxEMPTY Delay from Center of Last Bit 20 tcy | (Note 7) two Control Delay from Rising Edge of 8 tc (Note 7) WRITE (TxEn, DTR, RTS) Y tcr Control to READ Set-Up Time (DSR, CTS) 20 tcy | (Note 7) *NOTE: For Extended Temperature EXPRESS, use MIL 8251A electrical parameters.intel 8251A A.C. CHARACTERISTICS (Continued) TYPICAL A OUTPUT DELAY VS. A CAPACITANCE (pF) +20 10 a . ~ > < a a bk 9 N a SPEC. =) 3 4 -10 V4 100 -50 0 +50 +100 > CAPACITANCE (pF) 205222-19 A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 24 20 2.0 > TEST POINTS < 0.8 os 82514 OUT 0.45 205222-20 CL AC Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V L for a Logic 0. Timing measurements are made at 2.0V for a ~ Logic 1 and 0.8V for a Logic 0. Cy = 150 pF 206222-21 Figure 18 WAVEFORMS SYSTEM CLOCK INPUT j*# te ba t, te ar 7 ete _ CLOCK o | | \_ f/f 205222-22 2-198251A WAVEFORMS (Continued) p2-Z222eS0e asind ONIMIdAYS LNI (JOOW *94) _ SOO 3d D*y 8 (3QOW XL). O*Y Qeu, ligviva XxX e-cees0e x Lia vivd / 11 LYVLS h vivo d (243H SLYVIS WILNNOD ANVS *y) VLVG GNV 19019 Y3AIRZ934 xK x viva XL + x40, X10) + (3Q0W=9L) OXL (3GOW *L) Ox. I Oddi t Md Li 1 VLVG GNV 49019 YSLLINSNVYL 2-20intel 8251A WAVEFORMS (Continued) WRITE DATA CYCLE (CPU USART) TROY / \ | le seirspow cues tww || + | Tow Th two OONT CARE DONT CARE DATA IN (0.B.) DATA STABLE fe 5 ct SYS tWA ts TAW | TWA 205222-25 READ DATA CYCLE (CPU < USART) RxRDY fT tRxRDY CLEAR . Teer fe-tro | |--tor DATA OUT (DB DATA FLOAT Ceara ourncrive DATA FLOAT on taR tra | a TT tAR TRA 205222-26 2-21intel 8251A WAVEFORMS (Continued) WRITE CONTROL OR OUTPUT PORT CYCLE (CPU USART) OTR, RTS (NOTE =1) x [- tww >| a we | Wr BN |-' tow + = two DATA IN (0.6.).; ___{ }___ |- =| AW >| (WA cD A . i I ~~ TAW | IWA cs Nf 205222-27 READ CONTROL OR INPUT PORT (CPU < USART) DSR, CTS (NOTE 2) | ter | ial tRR | Rd | | \j tRD I tOF DATA OUT <4 ) a (D.B.) Xd | tar ~ +l tra j- c/D A K +| tAR -*+ ) tRA (= cs \ / 205222~28 NOTES: 1. Two includes the response timing of a control byte. 2. Tor includes the effect of CTS on the TxENBL circuitry. 2-228251A WAVEFORMS (Continued) 0-cees07e sug dog z 9 Aue uM Je1eeUO Hg 2 = yeUUOS aidwexg oe 24 4 35 nz gs ee = prea 23 Be 2S 2s vena vay 2 = ES waue to , mreunio nen t HUH VIVO ZuVHO viva (HVHO vLv0 wiv ty | rr te aew ; Pf * We | wed ta \ CC J If or i wivo PH YW AQH ty. iso7 AOM = 2 18S! s viva yous aNNHMAAD HB SALTS HIVE ONY A hh ~~ 497190 Xv de (SGOW DNASV) DNIALL SV14 ONY TOULNOD H3AIS034 62-2e7eS07d wn oY a Be 2 aa sug dois Ze Aved WIA Je0BIeYO Wg Z = yeuuo4 ajdwex3 a a5 sree YVHO viva Z HwHO Viva tL uvHD viva e vivax Y HSS UM Va UM \ f I y\ mi PTT | a rvivalm fvivom ZVIVOOM LVivOUM intel | : 4 f aavay [ (aia savas) AQVIH *L \ ALdWw2 *L _.| je ALdWa* LS \ \ su2 (3GOW ONASV) DNIWIL DV14 GNV TOHLNOD H3LLINSNVYL 2-238251A WAVEFORMS (Continued) sueyoRseyd OUAS 2 AWE YM J8}OReYD 11g G = yeWOY a}duexg l-2eeS0e va ave ays awe uss ys wre eye 7O86G600 So6o6 ot HVHD 5 avHo 31vis ZHVHD INAS b YYHO 247iS ONINE UW DNAS viva ONDA Vi vivo *HaS HVHO ZaWHI | L HWHD viva ia ONVWWO2 4M viva Mm viva'm vivg'm wuss ONY AWOD OM Lf Vivo Xi iNtdl AQV3Y *L tht SAA WLS) AQVIY ML ALAN TL $12 (AGOW DNAS) ONIWIL DV14 GNV JOHLNOS HALLINSNVEL 2-248251A WAVEFORMS (Continued) Aud UNM SIG g OUAS jBUIEIXA *Z Aureg YUM SUG g ssejBIeYD oUAg Z OUAS jeULE}UI *| SALON c&-zzes0e (418 SNAWAS) LIQNAS 135 bla vel 3g NAS 138 130 DNAS 435 30GW INAH 103 y JU 19079 SNIDaS | SNID3G ASV HHO # ASSY HHO eheqehifo efcIetido Viva yy 2 VHD INAS viva Py ayy taVHD vivo py viva Pi owas v vd Py Snivis a2 su Ua OM WLS Pu INid) AQd 29 19S} uwOuna NNBRIAO 19S) 1 3QNAS t 21ON iNta 130NAS (4GOW ONAS) ONIWIL DV 1d ONY TOH.LNOO H3AI303Y 2-25