L6229 DMOS DRIVER FOR THREE-PHASE BRUSHLESS DC MOTOR 1 2 FEATURES Figure 1. Package OPERATING SUPPLY VOLTAGE FROM 8 TO 52V 2.8A OUTPUT PEAK CURRENT (1.4A DC) RDS(ON) 0.73 TYP. VALUE @ Tj = 25 C OPERATING FREQUENCY UP TO 100KHz NON DISSIPATIVE OVERCURRENT DETECTION AND PROTECTION DIAGNOSTIC OUTPUT CONSTANT tOFF PWM CURRENT CONTROLLER SLOW DECAY SYNCHR. RECTIFICATION 60 & 120 HALL EFFECT DECODING LOGIC BRAKE FUNCTION TACHO OUTPUT FOR SPEED LOOP CROSS CONDUCTION PROTECTION THERMAL SHUTDOWN UNDERVOLTAGE LOCKOUT INTEGRATED FAST FREEWEELING DIODES PowerDIP24 (20+2+2) PowerSO36 SO24 (20+2+2) DESCRIPTION The L6229 is a DMOS Fully Integrated Three-Phase Motor Driver with Overcurrent Protection. Realized in MultiPower-BCD technology, the device combines isolated DMOS Power Transistors with CMOS and bipolar circuits on the same chip. The device includes all the circuitry needed to drive a three-phase BLDC motor including: a three-phase DMOS Bridge, a constant off time PWM Current Controller and the decoding logic for single ended hall sensors that generates the required sequence for the power stage. Available in PowerDIP24 (20+2+2), PowerSO36 and SO24 (20+2+2) packages, the L6229 features a non- October 2004 Table 1. Order Codes Part Number Package L6229N PowerDIP24 L6229PD PowerSO36 L6229PDTR PowerSO36 in Tape & Reel L6229D SO24 L6229DTR SO24 in Tape & Reel dissipative overcurrent protection on the high side Power MOSFETs and thermal shutdown. Rev. 3 1/25 L6229 Figure 2. Block Diagram VBOOT VBOOT VBOOT CHARGE PUMP VCP VSA THERMAL PROTECTION OCD1 DIAG OCD OUT1 10V OCD1 OCD2 OCD OCD3 VBOOT EN BRAKE FWD/REV OCD2 H3 HALL-EFFECT SENSORS DECODING LOGIC H2 GATE LOGIC SENSEA VBOOT H1 RCPULSE OUT2 10V TACHO MONOSTABLE VSB OCD3 OUT3 10V TACHO 10V 5V SENSEB PWM VOLTAGE REGULATOR ONE SHOT MONOSTABLE MASKING TIME + SENSE COMPARATOR VREF RCOFF D99IN1095B Table 2. Absolute Maximum Ratings Symbol VS VOD VBOOT Parameter Test conditions Value Unit Supply Voltage VSA = VSB = VS 60 V Differential Voltage between: VSA, OUT1, OUT2, SENSEA and VSB, OUT3, SENSEB VSA = VSB = VS = 60V; VSENSEA = VSENSEB = GND 60 V Bootstrap Peak Voltage VSA = VSB = VS VS + 10 V VIN, VEN Logic Inputs Voltage Range -0.3 to 7 V VREF Voltage Range at pin VREF -0.3 to 7 V Voltage Range at pin RCOFF -0.3 to 7 V VRCPULSE Voltage Range at pin RCPULSE -0.3 to 7 V VSENSE Voltage Range at pins SENSEA and SENSEB -1 to 4 V IS(peak) Pulsed Supply Current (for each VSA and VSB pin) VSA = VSB = VS; TPULSE < 1ms 3.55 A DC Supply Current (for each VSA and VSB pin) VSA = VSB = VS 1.4 A -40 to 150 C VRCOFF IS Tstg, TOP 2/25 Storage and Operating Temperature Range L6229 Table 3. Recommended Operating Condition Symbol VS Parameter Test Conditions Supply Voltage VSA = VSB = VS VOD Differential Voltage between: VSA, OUT1, OUT2, SENSEA and VSB, OUT3, SENSEB VSA = VSB = VS; VSENSEA = VSENSEB VREF Voltage Range at pin VREF VSENSE IOUT Voltage Range at pins SENSEA and SENSEB (pulsed tW < trr) (DC) DC Output Current VSA = VSB = VS TJ Operating Junction Temperature fSW Switching Frequency MIN MAX Unit 12 52 V 52 V -0.1 5 V -6 -1 6 1 V V 1.4 A 125 C 100 KHz -25 Table 4. Thermal Data Symbol Description PDIP24 SO24 19 15 Rth(j-pins) Maximum Thermal Resistance Junction-Pins Rth(j-case) Maximum Thermal Resistance Junction-Case Rth(j-amb)1 MaximumThermal Resistance Junction-Ambient (1) 44 Rth(j-amb)1 Maximum Thermal Resistance Junction-Ambient (2) Rth(j-amb)1 Rth(j-amb)2 PowerSO36 Unit C/W 2 C/W 55 - C/W - - 36 C/W MaximumThermal Resistance Junction-Ambient (3) - - 16 C/W Maximum Thermal Resistance Junction-Ambient (4) 59 78 63 C/W (1) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm2 (with a thickness of 35 m). (2) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 m). (3) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 m), 16 via holes and a ground layer. (4) Mounted on a multi-layer FR4 PCB without any heat-sinking surface on the board. 3/25 L6229 Figure 3. Pin Connections (Top view) GND 1 36 GND N.C. 2 35 N.C. N.C. H1 1 24 H3 N.C. 3 34 DIAG 2 23 H2 VSA 4 33 VSB OUT2 5 32 OUT3 SENSEA 3 22 VCP RCOFF 4 21 OUT2 OUT1 5 20 VSA GND 6 19 GND GND 7 18 GND TACHO 8 17 VSB RCPULSE 9 16 OUT3 SENSEB 10 15 VBOOT FWD/REV 11 14 BRAKE EN 12 13 VREF D01IN1194A N.C. 6 31 N.C. VCP 7 30 VBOOT H2 8 29 BRAKE H3 9 28 VREF H1 10 27 EN DIAG 11 26 FWD/REV SENSEA 12 25 SENSEB RCOFF 13 24 RCPULSE N.C. 14 23 N.C. OUT1 15 22 TACHO N.C. 16 21 N.C. N.C. 17 20 N.C. GND 18 19 GND D01IN1195A PowerSO36 (5) PowerDIP24/SO24 (5) The slug is internally connected to pins 1, 18, 19 and 36 (GND pins). Table 5. Pin Description PACKAGE SO24/ PowerDIP24 PowerSO36 PIN # PIN # 1 2 4/25 Name Type Function 10 H1 Sensor Input Single Ended Hall Effect Sensor Input 1. 11 DIAG Open Drain Output Overcurrent Detection and Thermal Protection pin. An internal open drain transistor pulls to GND when an overcurrent on one of the High Side MOSFETs is detected or during Thermal Protection. 3 12 SENSEA 4 13 RCOFF RC Pin 5 15 OUT1 Power Output 6, 7, 18, 19 1, 18, 19, 36 GND GND Ground terminals. On PowerDIP24 and SO24 packages, these pins are also used for heat dissipation toward the PCB. On PowerSO36 package the slug is connected on these pins. 8 22 TACHO Open Drain Output Frequency-to-Voltage open drain output. Every pulse from pin H1 is shaped as a fixed and adjustable length pulse. 9 24 RCPULSE RC Pin RC Network Pin. A parallel RC network connected between this pin and ground sets the duration of the Monostable Pulse used for the Frequency-to-Voltage converter. Power Supply Half Bridge 1 and Half Bridge 2 Source Pin. This pin must be connected together with pin SENSEB to Power Ground through a sensing power resistor. RC Network Pin. A parallel RC network connected between this pin and ground sets the Current Controller OFF-Time. Output 1 L6229 Table 5. Pin Description (continued) PACKAGE SO24/ PowerDIP24 PowerSO36 PIN # PIN # 10 25 SENSEB 11 26 FWD/REV Logic Input Selects the direction of the rotation. HIGH logic level sets Forward Operation, whereas LOW logic level sets Reverse Operation. If not used, it has to be connected to GND or +5V.. 12 27 EN Logic Input Chip Enable. LOW logic level switches OFF all Power MOSFETs. If not used, it has to be connected to +5V. 13 28 VREF Logic Input Current Controller Reference Voltage. Do not leave this pin open or connect to GND. 14 29 BRAKE Logic Input Brake Input pin. LOW logic level switches ON all High Side Power MOSFETs, implementing the Brake Function. If not used, it has to be connected to +5V. 15 30 VBOOT 16 32 OUT3 17 33 VSB Power Supply Half Bridge 3 Power Supply Voltage. It must be connected to the supply voltage together with pin VSA. 20 4 VSA Power Supply Half Bridge 1 and Half Bridge 2 Power Supply Voltage. It must be connected to the supply voltage together with pin VSB. 21 5 OUT2 22 7 VCP Output 23 8 H2 Sensor Input Single Ended Hall Effect Sensor Input 2. 24 9 H3 Sensor Input Single Ended Hall Effect Sensor Input 3. Name Type Function Power Supply Half Bridge 3 Source Pin. This pin must be connected together with pin SENSEA to Power Ground through a sensing power resistor. At this pin also the Inverting Input of the Sense Comparator is connected. Supply Voltage Bootstrap Voltage needed for driving the upper Power MOSFETs. Power Output Power Output Output 3. Output 2. Charge Pump Oscillator Output. Table 6. Electrical Characteristics (VS = 48V , Tamb = 25 C , unless otherwise specified) Symbol Min Typ Max Unit VSth(ON) Turn ON threshold 5.8 6.3 6.8 V VSth(OFF) Turn OFF threshold 5 5.5 6 V 5 10 mA IS TJ(OFF) Parameter Quiescent Supply Current Test Conditions All Bridges OFF; Tj = -25 to 125C (6) Thermal Shutdown Temperature C 165 Output DMOS Transistors RDS(ON) High-Side + Low-Side Switch ON Resistance IDSS Leakage Current Tj = 25 C Tj =125 C (7) EN = Low; OUT = VCC EN = Low; OUT = GND -0.3 1.47 1.69 2.35 2.70 2 mA mA 5/25 L6229 Table 6. Electrical Characteristics (continued) (VS = 48V , Tamb = 25 C , unless otherwise specified) Symbol Parameter Test Conditions Min Typ Max Unit 1.3 V Source Drain Diodes VSD Forward ON Voltage ISD = 1.4A, EN = LOW 1.15 trr Reverse Recovery Time If = 1.4A 300 ns tfr Forward Recovery Time 200 ns Logic Input (H1, H2, H3, EN, FWD/REV, BRAKE) VIL Low level logic input voltage -0.3 0.8 V VIH High level logic input voltage 2 7 V IIL Low level logic input current GND Logic Input Voltage IIH High level logic input current 7V Logic Input Voltage Vth(ON) Turn-ON Input Threshold 1.8 Vth(OFF) Turn-OFF Input Threshold VthHYS A -10 Input Thresholds Hysteresys 10 A 2.0 V 0.8 1.3 V 0.25 0.5 V 650 Switching Characteristics tD(on)EN Enable to out turn-ON delay time (7) ILOAD = 1.4 A, Resistive Load 500 tD(off)EN Enable to out turn-OFF delay time (7) ILOAD = 1.4 A, Resistive Load 500 tD(on)IN Other Logic Inputs to Output TurnON delay Time ILOAD = 1.4 A, Resistive Load 1.6 s tD(off)IN Other Logic Inputs to out Turn-OFF ILOAD = 1.4 A, Resistive Load delay Time 800 ns 800 ns 1000 ns tRISE Output Rise Time (7) ILOAD = 1.4 A, Resistive Load 40 250 ns tFALL Output Fall Time (7) ILOAD = 1.4 A, Resistive Load 40 250 ns tDT Dead Time fCP Charge Pump Frequency 0.5 Tj = -25 to 125C 1 0.6 (6) s 1 MHz PWM Comparator and Monostable IRCOFF Source current at pin RCOFF VOFFSET Offset Voltage on Sense Comparator tprop Turn OFF Propagation delay (8) tblank Internal Blanking Time on Sense Comparator tON(min) tOFF IBIAS VRCOFF = 2.5 V 3.5 5.5 mA Vref = 0.5 V 5 mV Vref = 0.5 V 500 ns 1 s Minimum on Time PWM RecirculationTime 2.5 3 s ROFF= 20k ; COFF =1nF 13 s ROFF= 100k ; COFF =1nF 61 s Input Bias Current at pin VREF 10 A Tacho Monostable IRCPULSE Source Current at pin RCPULSE 6/25 VRCPULSE = 2.5V 3.5 5.5 mA L6229 Table 6. Electrical Characteristics (continued) (VS = 48V , Tamb = 25 C , unless otherwise specified) Symbol tPULSE Parameter Test Conditions Monostable of Time Min Typ Max Unit RPUL = 20k ; CPUL =1nF 12 s RPUL = 100k ; CPUL =1nF 60 s RTACHO Open Drain ON Resistance 40 60 2.8 3.55 A 60 Over Current Detection & Protection ISOVER Supply Overcurrent Protection Threshold TJ = -25 to 125C (6) ROPDR Open Drain ON Resistance IDIAG = 4mA 40 OCD high level leakage current VDIAG = 5V 1 A IDIAG = 4mA; CDIAG < 100pF 200 ns IDIAG = 4mA; CDIAG < 100pF 100 ns IOH tOCD(ON) OCD Turn-ON Delay Time (9) tOCD(OFF) OCD Turn-OFF Delay Time (9) 2 (6) Tested at 25C in a restricted range and guaranteed by characterization. (7) See Fig. 4. (8) Measured applying a voltage of 1V to pin SENSE and a voltage drop from 2V to 0V to pin VREF. (9) See Fig. 5. Figure 4. Switching Characteristic Definition EN Vth(ON) Vth(OFF) t IOUT 90% 10% t D01IN1316 tRISE tFALL tD(OFF)EN tD(ON)EN Figure 5. Overcurrent Detection Timing Definition IOUT ISOVER ON BRIDGE OFF VDIAG 90% 10% tOCD(ON) tOCD(OFF) D02IN1387 7/25 L6229 3 CIRCUIT DESCRIPTION 3.1 POWER STAGES and CHARGE PUMP The L6229 integrates a Three-Phase Bridge, which consists of 6 Power MOSFETs connected as shown on the Block Diagram. Each Power MOS has an RDS(ON) = 0.73 (typical value @25C) with intrinsic fast freewheeling diode. Switching patterns are generated by the PWM Current Controller and the Hall Effect Sensor Decoding Logic (see relative paragraphs). Cross conduction protection is implemented by using a dead time (tDT = 1s typical value) set by internal timing circuit between the turn off and turn on of two Power MOSFETs in one leg of a bridge. Pins VSA and VSB MUST be connected together to the supply voltage (VS). Using N-Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The Bootstrapped Supply (VBOOT) is obtained through an internal oscillator and few external components to realize a charge pump circuit as shown in Figure 6. The oscillator output (pin VCP) is a square wave at 600KHz (typically) with 10V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Table 7. Table 7. Charge Pump External Component Values. CBOOT 220nF CP 10nF RP 100 D1 1N4148 D2 1N4148 Figure 6. Charge Pump Circuit VS D1 CBOOT D2 RP CP VCP VBOOT VSA VSB D01IN1328 3.2 LOGIC INPUTS Pins FWD/REV, BRAKE, EN, H1, H2 and H3 are TTL/CMOS and C compatible logic inputs. The internal structure is shown in Figure 4. Typical value for turn-ON and turn-OFF thresholds are respectively Vth(ON) = 1.8V and Vth(OFF) = 1.3V. Pin EN (enable) may be used to implement Overcurrent and Thermal protection by connecting it to the open collector DIAG output If the protection and an external disable function are both desired, the appropriate connection must be implemented. When the external signal is from an open collector output, the circuit in Figure 8 can be used . For external circuits that are push pull outputs the circuit in Figure 9 could be used. The resistor REN should be chosen in the range from 2.2K to 180K. Recommended values for REN and CEN are respectively 100K and 5.6nF. More information for selecting the values can be found in the Overcurrent Protection section. 8/25 L6229 Figure 7. Logic Input Internal Structure 5V ESD PROTECTION D01IN1329 Figure 8. Pin EN Open Collector Driving DIAG 5V 5V REN OPEN COLLECTOR OUTPUT CEN EN ESD PROTECTION D02IN1378 Figure 9. Pin EN Push-Pull Driving DIAG 5V PUSH-PULL OUTPUT REN EN CEN ESD PROTECTION D02IN1379 3.3 PWM CURRENT CONTROL The L6229 includes a constant off time PWM Current Controller. The current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the three lower power MOS transistors and ground, as shown in Figure 10. As the current in the motor increases the voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor becomes greater than the voltage at the reference input pin VREF the sense comparator triggers the monostable switching the bridge off. The power MOS remain off for the time set by the monostable and the motor current recirculates around the upper half of the bridge in Slow Decay Mode as described in the next section. When the monostable times out, the bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays the turn on of the power MOS, the effective Off Time tOFF is the sum of the monostable time plus the dead time. Figure 11 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the pin RC voltage and the status of the bridge. More details regarding the Synchronous Rectification and the output stage configuration are included in the next section. Immediately after the Power MOS turn on, a high peak current flows through the sense resistor due to the re- 9/25 L6229 verse recovery of the freewheeling diodes. The L6229 provides a 1s Blanking Time tBLANK that inhibits the comparator output so that the current spike cannot prematurely retrigger the monostable. Figure 10. PWM Current Controller Simplified Schematic VSA VSB BLANKING TIME MONOSTABLE TO GATE LOGIC 1s 5mA FROM THE LOW-SIDE GATE DRIVERS MONOSTABLE SET BLANKER S (0) OUT2 Q (1) OUT3 R DRIVERS + DEAD TIME - OUT1 DRIVERS + DEAD TIME DRIVERS + DEAD TIME + 5V 2.5V + SENSE COMPARATOR COFF - RCOFF VREF ROFF RSENSE SENSEB SENSEA D02IN1380 Figure 11. Output Current Regulation Waveforms IOUT VREF RSENSE tON tOFF tOFF 1s tBLANK VSENSE 1s tBLANK VREF Slow Decay 0 Slow Decay tRCRISE VRC tRCRISE 5V 2.5V tRCFALL tRCFALL 1s tDT 1s tDT ON OFF SYNCHRONOUS RECTIFICATION D02IN1351 10/25 VS B C D A B C D L6229 Figure 12 shows the magnitude of the Off Time tOFF versus COFF and ROFF values. It can be approximately calculated from the equations: tRCFALL = 0.6 * ROFF * COFF tOFF = tRCFALL + tDT = 0.6 * ROFF * COFF + tDT where ROFF and COFF are the external component values and tDT is the internally generated Dead Time with: 20K ROFF 100K 0.47nF COFF 100nF tDT = 1s (typical value) Therefore: tOFF(MIN) = 6.6s tOFF(MAX) = 6ms These values allow a sufficient range of tOFF to implement the drive circuit for most motors. The capacitor value chosen for COFF also affects the Rise Time tRCRISE of the voltage at the pin RCOFF. The Rise Time tRCRISE will only be an issue if the capacitor is not completely charged before the next time the monostable is triggered. Therefore, the On Time tON, which depends by motors and supply parameters, has to be bigger than tRCRISE for allowing a good current regulation by the PWM stage. Furthermore, the On Time tON can not be smaller than the minimum on time tON(MIN). t O N > tON ( MI N ) = 2.5s (typ. value) tON > tRC R ISE - tDT tRCRISE = 600 * COFF Figure 13 shows the lower limit for the On Time tON for having a good PWM current regulation capacity. It has to be said that tON is always bigger than tON(MIN) because the device imposes this condition, but it can be smaller than tRCRISE - tDT. In this last case the device continues to work but the Off Time tOFF is not more constant. So, small COFF value gives more flexibility for the applications (allows smaller On Time and, therefore, higher switching frequency), but, the smaller is the value for COFF, the more influential will be the noises on the circuit performance. Figure 12. tOFF versus COFF and ROFF. 4 1 .10 R off = 100k 3 1 .10 R off = 47k toff [s] R off = 20k 100 10 1 0.1 1 10 100 Coff [nF] 11/25 L6229 Figure 13. Area where tON can vary maintaining the PWM regulation. ton(min) [s] 100 10 1.5s (typ. value) 1 0.1 1 10 100 Coff [nF] 3.4 SLOW DECAY MODE Figure 14 shows the operation of the bridge in the Slow Decay mode during the Off Time. At any time only two legs of the three-phase bridge are active, therefore only the two active legs of the bridge are shown in the figure and the third leg will be off. At the start of the Off Time, the lower power MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across the coil is low, the current decays slowly. After the Dead Time the upper power MOS is operated in the synchronous rectification mode reducing the impendence of the freewheeling diode and the related conducting losses. When the monostable times out, upper MOS that was operating the synchronous mode turns off and the lower power MOS is turned on again after some delay set by the Dead Time to prevent cross conduction. Figure 14. Slow Decay Mode Output Stage Configurations A) ON TIME B) 1s DEAD TIME D01IN1336 12/25 C) SYNCHRONOUS RECTIFICATION D) 1s DEAD TIME L6229 3.5 DECODING LOGIC The Decoding Logic section is a combinatory logic that provides the appropriate driving of the three-phase bridge outputs according to the signals coming from the three Hall Sensors that detect rotor position in a 3phase BLDC motor. This novel combinatory logic discriminates between the actual sensor positions for sensors spaced at 60, 120, 240 and 300 electrical degrees. This decoding method allows the implementation of a universal IC without dedicating pins to select the sensor configuration. There are eight possible input combinations for three sensor inputs. Six combinations are valid for rotor positions with 120 electrical degrees sensor phasing (see Figure 15, positions 1, 2, 3a, 4, 5 and 6a) and six combinations are valid for rotor positions with 60 electrical degrees phasing (see Figure 17, positions 1, 2, 3b, 4, 5 and 6b). Four of them are in common (1, 2, 4 and 5) whereas there are two combinations used only in 120 electrical degrees sensor phasing (3a and 6a) and two combinations used only in 60 electrical degrees sensor phasing (3b and 6b). The decoder can drive motors with different sensor configuration simply by following the Table 8. For any input configuration (H1, H2 and H3) there is one output configuration (OUT1, OUT2 and OUT3). The output configuration 3a is the same than 3b and analogously output configuration 6a is the same than 6b. The sequence of the Hall codes for 300 electrical degrees phasing is the reverse of 60 and the sequence of the Hall codes for 240 phasing is the reverse of 120. So, by decoding the 60 and the 120 codes it is possible to drive the motor with all the four conventions by changing the direction set. Table 8. 60 and 120 Electrical Degree Decoding Logic in Forward Direction. Hall 120 1 2 3a - 4 5 6a - Hall 60 1 2 - 3b 4 5 - 6b H1 H H L H L L H L H2 L H H H H L L L H3 L L L H H H H L OUT1 Vs High Z GND GND GND High Z Vs Vs OUT2 High Z Vs Vs Vs High Z GND GND GND OUT3 GND GND High Z High Z Vs Vs High Z High Z Phasing 1->3 2->3 2->1 2->1 3->1 3->2 1->2 1->2 Figure 15. 120 Hall Sensor Sequence. H1 H3 H1 H2 1 =H H3 H1 H2 2 H3 H1 H2 3a H3 H1 H2 4 H3 H1 H2 5 H3 H2 6a =L 13/25 L6229 Figure 16. 60 Hall Sensor Sequence. H1 H1 H1 H1 H1 H1 H2 H2 H2 H2 H2 H2 H3 H3 1 =H H3 2 H3 3b 4 H3 H3 5 6b =L 3.6 TACHO A tachometer function consists of a monostable, with constant off time (tPULSE), whose input is one Hall Effect signal (H1). It allows developing an easy speed control loop by using an external op amp, as shown in Figure 18. For component values refer to Application Information section. The monostable output drives an open drain output pin (TACHO). At each rising edge of the Hall Effect Sensors H1, the monostable is triggered and the MOSFET connected to pin TACHO is turned off for a constant time tPULSE (see Figure 17). The off time tPULSE can be set using the external RC network (RPUL, CPUL) connected to the pin RCPULSE. Figure 19 gives the relation between tPULSE and CPUL, RPUL. We have approximately: tPULSE = 0.6 * RPUL * CPUL where CPUL should be chosen in the range 1nF ... 100nF and RPUL in the range 20K ... 100K. By connecting the tachometer pin to an external pull-up resistor, the output signal average value VM is proportional to the frequency of the Hall Effect signal and, therefore, to the motor speed. This realizes a simple Frequency-to-Voltage Converter. An op amp, configured as an integrator, filters the signal and compares it with a reference voltage VREF, which sets the speed of the motor. t P UL SE V M = ------------------ V DD T Figure 17. Tacho Operation Waveforms. H1 H2 H3 VTACHO VDD VM t PULSE T 14/25 L6229 Figure 18. Tachometer Speed Control Loop. H1 RCPULSE TACHO MONOSTABLE VDD CPUL RPUL R3 RDD TACHO C1 R4 VREF R1 VREF CREF2 CREF1 R2 Figure 19. tPULSE versus CPUL and RPUL. 4 1 .10 R PUL = 100k R PUL = 47k 3 1 .10 tpulse [s] R PUL = 20k 100 10 1 10 Cpul [nF] 100 15/25 L6229 3.7 NON-DISSIPATIVE OVERCURRENT DETECTION and PROTECTION The L6229 integrates an Overcurrent Detection Circuit (OCD) for full protection. This circuit provides Output-toOutput and Output-to-Ground short circuit protection as well. With this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 20 shows a simplified schematic for the overcurrent detection circuit. To implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each High Side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current IREF. When the output current reaches the detection threshold (typically ISOVER = 2.8A) the OCD comparator signals a fault condition. When a fault condition is detected, an internal open drain MOS with a pull down capability of 4mA connected to pin DIAG is turned on. The pin DIAG can be used to signal the fault condition to a C or to shut down the Three-Phase Bridge simply by connecting it to pin EN and adding an external R-C (see REN, CEN). Figure 20. Overcurrent Protection Simplified Schematic OUT1 VSA HIGH SIDE DMOS C or LOGIC VDD REN VSB HIGH SIDE DMOS I2 POWER DMOS n cells POWER DMOS n cells I3 POWER SENSE 1 cell POWER DMOS n cells POWER SENSE 1 cell + OCD COMPARATOR EN OUT3 HIGH SIDE DMOS I1 POWER SENSE 1 cell TO GATE LOGIC OUT2 I1 / n I2/ n I1+I2 / n CEN INTERNAL OPEN-DRAIN DIAG RDS(ON) 40 TYP. IREF OVER TEMPERATURE I3/ n IREF D02IN1381 Figure 21 shows the Overcurrent Detetection operation. The Disable Time tDISABLE before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by CEN and REN values and its magnitude is reported in Figure 22. The Delay Time tDELAY before turning off the bridge when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in Figure 23 CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN should be chosen as big as possible according to the maximum tolerable Delay Time and the REN value should be chosen according to the desired Disable Time. The resistor REN should be chosen in the range from 2.2K to 180K. Recommended values for REN and CEN are respectively 100K and 5.6nF that allow obtaining 200s Disable Time. 16/25 L6229 Figure 21. Overcurrent Protection Waveforms IOUT ISOVER VEN=VDIAG VDD Vth(ON) Vth(OFF) VEN(LOW) ON OCD OFF ON tDELAY BRIDGE tDISABLE OFF tOCD(ON) tEN(FALL) tOCD(OFF) tEN(RISE) tD(ON)EN tD(OFF)EN D02IN1383 Figure 22. tDISABLE versus CEN and REN. R EN = 220 k 3 1 .1 0 R EN = 100 k R EN = 47 k R EN = 33 k R EN = 10 k tDISABLE [s] 1 00 10 1 1 10 1 00 C E N [n F ] Figure 23. tDELAY versus CEN. tdelay [s] 10 1 0.1 1 10 Cen [nF] 100 17/25 L6229 4 APPLICATION INFORMATION A typical application using L6229 is shown in Figure 24. Typical component values for the application are shown in Table 9. A high quality ceramic capacitor (C2) in the range of 100nF to 200nF should be placed between the power pins VSA and VSB and ground near the L6229 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitor (CEN) connected from the EN input to ground sets the shut down time when an over current is detected (see Overcurrent Protection). The two current sensing inputs (SENSEA and SENSEB) should be connected to the sensing resistor RSENSE with a trace length as short as possible in the layout. The sense resistor should be non-inductive resistor to minimize the di/ dt transients across the resistor. To increase noise immunity, unused logic pins are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin description). It is recommended to keep Power Ground and Signal Ground separated on PCB. Table 9. Component Values for Typical Application. C1 100F R1 5K6 C2 100nF R2 1K8 C3 220nF R3 4K7 CBOOT 220nF R4 1M COFF 1nF RDD 1K CPUL 10nF REN 100K CREF1 33nF RP 100 CREF2 100nF RSENSE 0.6 CEN 5.6nF ROFF 33K CP 10nF RPUL 47K D1 1N4148 RH1, RH2, RH3 10K D2 1N4148 Figure 24. Typical Application VSA + VS 8-52VDC C1 C2 POWER GROUND - VSB D1 RP CP VCP 20 22 SIGNAL GROUND 2 VBOOT RSENSE THREE-PHASE MOTOR SENSEA SENSEB OUT1 HALL SENSOR +5V RH1 RH2 RH3 M OUT2 OUT3 H1 H2 H3 GND 15 5 21 16 VREF CREF2 R2 C3 R4 EN REN ENABLE CEN 11 14 8 FWD/REV FWD/REV BRAKE BRAKE TACHO R3 COFF RDD 1 23 4 RCOFF 5V ROFF CPUL 24 18 19 6 7 D02IN1357 18/25 12 + DIAG 3 10 R1 VREF CREF1 17 D2 CBOOT 13 9 RCPULSE RPUL L6229 4.1 OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION In Figure 25 is shown the approximate relation between the output current and the IC power dissipation using PWM current control. For a given output current the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125C maximum). Figure 25. IC Power Dissipation versus Output Power. I1 IOUT 10 I2 8 PD [W] 6 IOUT I3 IOUT 4 Test Condition s: Supply Voltage = 24 V 2 0 0 0.25 0.5 0.75 1 1.25 1.5 IOUT [A] No PWM fSW = 30 kHz (slow decay) 4.2 THERMAL MANAGEMENT In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Selecting the appropriate package and heatsinking configuration for the application is required to maintain the IC within the allowed operating temperature range for the application. Figures 26, 27 and 28 show the Junction-to-Ambient Thermal Resistance values for the PowerSO36, PowerDIP24 and SO24 packages. For instance, using a PowerSO package with copper slug soldered on a 1.5mm copper thickness FR4 board with 6cm2 dissipating footprint (copper thickness of 35m), the Rth(j-amb) is about 35C/W. Figure 29 shows mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to 15C/W. Figure 26. PowerSO36 Junction-Ambient thermal resistance versus on-board copper area. C / W 43 38 33 W ith o ut G ro u nd La yer 28 W ith Gro un d La yer W ith Gro un d La yer+ 16 via H o le s 23 On-Board Copper Area 18 13 1 2 3 4 5 6 7 8 9 10 11 12 13 s q. cm 19/25 L6229 Figure 27. PowerDIP24 Junction-Ambient thermal resistance versus on-board copper area. C / W On-Board Copper Area 49 48 C o p pe r Are a is o n Bo tto m S id e 47 C o p pe r Are a is o n To p S i de 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 11 12 s q . cm Figure 28. SO24 Junction-Ambient thermal resistance versus on-board copper area. On-Board Copper Area C / W 68 66 64 62 60 C o pp er A re a is o n T op S id e 58 56 54 52 50 48 1 2 3 4 5 6 7 8 9 10 11 12 s q. cm Figure 29. Mounting the PowerSO Package. Slug soldered to PCB with dissipating area 20/25 Slug soldered to PCB with dissipating area plus ground layer Slug soldered to PCB with dissipating area plus ground layer contacted through via holes L6229 Figure 30. PowerSO36 Mechanical Data & Package Dimensions DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s MIN. 3.25 mm TYP. 0.8 MAX. 3.5 3.3 1 MIN. 0.128 0.075 0.38 0.32 16 9.8 0 0.008 0.009 0.622 0.37 14.5 11.1 2.9 6.2 3.2 0.547 0.429 0.031 0.2 1 0.003 0.015 0.012 0.630 0.38 0.039 13.9 10.9 5.8 2.9 0.57 0.437 0.114 0.244 1.259 0.228 0.114 0.65 11.05 0.026 0.435 0.075 0 15.9 0.61 1.1 1.1 0.031 10 (max) 8 (max) 0.8 OUTLINE AND MECHANICAL DATA MAX. 0.138 0.13 0.039 0.008 0 0.22 0.23 15.8 9.4 0 15.5 inch TYP. 0.003 0.625 0.043 0.043 PowerSO36 Note: "D and E1" do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006") - Critical dimensions are "a3", "E" and "G". N N a2 e A DETAIL A A c a1 DETAIL B E e3 H DETAIL A lead D slug a3 36 BOTTOM VIEW 19 E3 B E1 E2 D1 DETAIL B 0.35 Gage Plane 1 1 -C- 8 S L SEATING PLANE G h x 45 b 0.12 M AB PSO36MEC C (COPLANARITY) 0096119 B 21/25 L6229 Figure 31. PDIP-24 Mechanical Data & Package Dimensions mm DIM. MIN. TYP. A A1 inch MAX. MIN. TYP. 4.320 0.380 A2 0.170 0.015 3.300 0.130 B 0.410 0.460 0.510 0.016 0.018 0.020 B1 1.400 1.520 1.650 0.055 0.060 0.065 c 0.200 0.250 0.300 0.008 0.010 0.012 D 31.62 31.75 31.88 1.245 1.250 1.255 E 7.620 8.260 0.300 e 2.54 E1 6.350 e1 L 6.600 M 0.325 0.100 6.860 0.250 0.260 0.270 0.300 7.620 3.180 OUTLINE AND MECHANICAL DATA MAX. 3.430 0.125 PDIP 24 (0.300") 0.135 0 min, 15 max. E1 A2 A A1 L B B1 e e1 D 24 13 c 1 12 M SDIP24L 0034965 D 22/25 L6229 Figure 32. SO24 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.200 C 0.23 0.32 0.009 0.013 D (1) 15.20 15.60 0.598 0.614 E 7.40 7.60 0.291 0.299 e 1.27 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 ddd Weight: 0.60gr 0.050 H k OUTLINE AND MECHANICAL DATA 0 (min.), 8 (max.) 0.10 0.004 (1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO24 0070769 C 23/25 L6229 Table 10. Revision History Date Revision September 2003 1 First Issue January 2004 2 Migration from ST-Press dms to EDOCS. October 2004 3 Updated the style graphic form. 24/25 Description of Changes L6229 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. 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