1/25
L6229
October 2004
1FEATURES
■OPERATING SUPPLY VOLTAGE FROM 8 TO
52V
■2.8A OUTPUT PEAK CURRENT (1.4A DC)
■RDS(ON) 0.73Ω TYP. VALUE @ Tj = 25 °C
■OPERATING FREQUENCY UP TO 100KHz
■NON DISSIPATIVE OVERCURRENT
DETECTION AND PROTECTION
■DIAGNOSTIC OUTPUT
■CONSTANT tOFF PWM CURRENT
CONTROLLER
■SLOW DECAY SYNCHR. RECTIFICATION
■60° & 120° HALL EFFECT DECODING LOGIC
■BRAKE FUNCTION
■TACHO OUTPUT FOR SPEED LOOP
■CROSS CONDUCTION PROTECTION
■THERMAL SHUTDOWN
■UNDERVOLTAGE LOCKOUT
■INTEGRATED FAST FREEWEELING DIODES
2 DESCRIPTION
The L6229 is a DMOS Fully Integrated Three-Phase
Motor Driver with Overcurrent Protection.
Realized in MultiPower-BCD technology, the device
combines isolated DMOS Power Transistors with
CMOS and bipolar circuits on the same chip.
The device includes all the circuitry needed to drive a
three-phase BLDC motor including: a three-phase
DMOS Bridge, a constant off time PWM Current Con-
troller and the decoding logic for single ended hall
sensors that generates the required sequence for the
power stage.
Available in PowerDIP24 (20+2+2), PowerSO36 and
SO24 (20+2+2) packages, the L6229 features a non-
dissipative overcurrent protection on the high side
Power MOSFETs and thermal shutdown.
DMOS DRIVER FOR
THREE-PHASE BRUSHLESS DC MOTOR
Fi
gure 1.
P
ac
k
age
Table 1. Order Codes
Part Number Package
L6229N PowerDIP24
L6229PD PowerSO36
L6229PDTR PowerSO36 in Tape & Reel
L6229D SO24
L6229DTR SO24 in Tape & Reel
PowerDIP24
(20+2+2)
PowerSO36
SO24
(20+2+2)
Rev. 3
L6229
2/25
Figure 2. Block Diagram
Table 2. Absolute Maximum Ratings
Symbol Parameter Test conditions Value Unit
VSSupply Voltage VSA = VSB = VS60 V
VOD Differential Voltage between:
VSA, OUT1, OUT2, SENSEA
and VSB, OUT3, SENSEB
VSA = VSB = VS = 60V;
VSENSEA = VSENSEB = GND
60 V
VBOOT Bootstrap Peak Voltage VSA = VSB = VSVS + 10 V
VIN, VEN Logic Inputs Voltage Range -0.3 to 7 V
VREF Voltage Range at pin VREF -0.3 to 7 V
VRCOFF Voltage Range at pin RCOFF -0.3 to 7 V
VRCPULSE Voltage Range at pin RCPULSE -0.3 to 7 V
VSENSE Voltage Range at pins SENSEA
and SENSEB
-1 to 4 V
IS(peak) Pulsed Supply Current (for each
VSA and VSB pin)
VSA = VSB = VS; TPULSE < 1ms 3.55 A
ISDC Supply Current (for each
VSA and VSB pin)
VSA = VSB = VS1.4 A
Tstg, TOP Storage and Operating
Temperature Range
-40 to 150 °C
CHARGE
PUMP
VOLTAGE
REGULATOR
HALL-EFFECT
SENSORS
DECODING
LOGIC
THERMAL
PROTECTION
TACHO
MONOSTABLE
OCD1
OCD
OCD
OCD2
10V 5V
VCP
VSA
GATE
LOGIC
VBOOT VBOOT
OUT1
OUT2
SENSEA
VSB
OUT3
SENSEB
DIAG
EN
FWD/REV
BRAKE
H3
H1
RCPULSE
D99IN1095B
TACHO
RCOFF
H2
OCD3
ONE SHOT
MONOSTABLE
MASKING
TIME
VBOOT
OCD1
10V
VBOOT
OCD2
10V
VBOOT
OCD3
10V
SENSE
COMPARATOR
+
-
PWM
VREF
3/25
L6229
Table 3. Recommended Operating Condition
Table 4. Thermal Data
Symbol Parameter Test Conditions MIN MAX Unit
VSSupply Voltage VSA = VSB = VS12 52 V
VOD Differential Voltage between:
VSA, OUT1, OUT2, SENSEA and
VSB, OUT3, SENSEB
VSA = VSB = VS;
VSENSEA = VSENSEB
52 V
VREF Voltage Range at pin VREF -0.1 5 V
VSENSE Voltage Range at pins SENSEA
and SENSEB
(pulsed tW < trr)
(DC)
-6
-1
6
1
V
V
IOUT DC Output Current VSA = VSB = VS1.4 A
TJOperating Junction Temperature -25 125 °C
fSW Switching Frequency 100 KHz
Symbol Description PDIP24 SO24
PowerSO36
Unit
Rth(j-pins) Maximum Thermal Resistance Junction-Pins 19 15 °C/W
Rth(j-case) Maximum Thermal Resistance Junction-Case 2 °C/W
Rth(j-amb)1 MaximumThermal Resistance Junction-Ambient (1)
(1) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm2 (with a thickness of 35 µm).
44 55 - °C/W
Rth(j-amb)1 Maximum Thermal Resistance Junction-Ambient (2)
(2) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm).
--36°C/W
Rth(j-amb)1 MaximumThermal Resistance Junction-Ambient (3)
(3) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm),
16 via holes and a ground layer.
--16°C/W
Rth(j-amb)2 Maximum Thermal Resistance Junction-Ambient (4)
(4) Mounted on a multi-layer FR4 PCB without any heat-sinking surface on the board.
59 78 63 °C/W
L6229
4/25
Figure 3. Pin Connections (Top view)
(5) The slug is internally connected to pins 1, 18, 19 and 36 (GND pins).
Table 5. Pin Description
PACKAGE
Name Type Function
SO24/
PowerDIP24 PowerSO36
PIN # PIN #
110H
1Sensor Input Single Ended Hall Effect Sensor Input 1.
2 11 DIAG Open Drain
Output
Overcurrent Detection and Thermal Protection pin. An
internal open drain transistor pulls to GND when an
overcurrent on one of the High Side MOSFETs is
detected or during Thermal Protection.
3 12 SENSEAPower Supply Half Bridge 1 and Half Bridge 2 Source Pin. This pin
must be connected together with pin SENSEB to
Power Ground through a sensing power resistor.
4 13 RCOFF RC Pin RC Network Pin. A parallel RC network connected
between this pin and ground sets the Current
Controller OFF-Time.
515OUT
1Power Output Output 1
6, 7,
18, 19
1, 18,
19, 36
GND GND Ground terminals. On PowerDIP24 and SO24
packages, these pins are also used for heat
dissipation toward the PCB. On PowerSO36 package
the slug is connected on these pins.
8 22 TACHO Open Drain
Output
Frequency-to-Voltage open drain output. Every pulse
from pin H1 is shaped as a fixed and adjustable length
pulse.
9 24 RCPULSE RC Pin RC Network Pin. A parallel RC network connected
between this pin and ground sets the duration of the
Monostable Pulse used for the Frequency-to-Voltage
converter.
GND
GND
TACHO
RCPULSE
SENSE
B
EN
FWD/REV
1
3
2
4
5
6
7
8
9
VREF
VBOOT
BRAKE
OUT3
VS
B
GND
GND19
18
17
16
15
13
14
D01IN1194A
10
11
12
24
23
22
21
20
H1
DIAG
SENSE
A
RCOFF
OUT1VS
A
OUT2
VCP
H2
H3
GND
N.C.
N.C.
VS
A
RCOFF
OUT1
N.C.
N.C.
N.C. N.C.
N.C.
TACHO
RCPULSE
N.C.
VS
B
N.C.
N.C.
GND
1
3
2
4
13
14
15
16
17
34
33
24
23
22
20
21
19
35
18
36
GND GND
D01IN1195A
H1
SENSE
A
DIAG
SENSE
B
EN
FWD/REV
10
11
12
27
26
25
H3VREF928
OUT2
H2
VCP
BRAKE
OUT3
VBOOT
5
7
8
32
30
29
N.C. N.C.631
PowerSO36 (5)
PowerDIP24/SO24
5/25
L6229
PACKAGE
Name Type Function
SO24/
PowerDIP24 PowerSO36
PIN # PIN #
10 25 SENSEBPower Supply Half Bridge 3 Source Pin. This pin must be connected
together with pin SENSEA to Power Ground through a
sensing power resistor. At this pin also the Inverting
Input of the Sense Comparator is connected.
11 26 FWD/REV Logic Input Selects the direction of the rotation. HIGH logic level
sets Forward Operation, whereas LOW logic level sets
Reverse Operation.
If not used, it has to be connected to GND or +5V..
12 27 EN Logic Input Chip Enable. LOW logic level switches OFF all Power
MOSFETs.
If not used, it has to be connected to +5V.
13 28 VREF Logic Input Current Controller Reference Voltage.
Do not leave this pin open or connect to GND.
14 29 BRAKE Logic Input Brake Input pin. LOW logic level switches ON all High
Side Power MOSFETs, implementing the Brake
Function.
If not used, it has to be connected to +5V.
15 30 VBOOT Supply Voltage Bootstrap Voltage needed for driving the upper Power
MOSFETs.
16 32 OUT3Power Output Output 3.
17 33 VSBPower Supply Half Bridge 3 Power Supply Voltage. It must be
connected to the supply voltage together with pin VSA.
20 4 VSAPower Supply Half Bridge 1 and Half Bridge 2 Power Supply Voltage.
It must be connected to the supply voltage together
with pin VSB.
21 5 OUT2Power Output Output 2.
22 7 VCP Output Charge Pump Oscillator Output.
23 8 H2Sensor Input Single Ended Hall Effect Sensor Input 2.
24 9 H3Sensor Input Single Ended Hall Effect Sensor Input 3.
Table 6. Electrical Characteristics
(VS = 48V , Tamb = 25 °C , unless otherwise specified)
Symbol Parameter Test Conditions Min Typ Max Unit
VSth(ON) Turn ON threshold 5.8 6.3 6.8 V
VSth(OFF) Turn OFF threshold 5 5.5 6 V
ISQuiescent Supply Current All Bridges OFF;
Tj = -25 to 125°C (6)
510mA
TJ(OFF) Thermal Shutdown Temperature 165 °C
Output DMOS Transistors
RDS(ON) High-Side + Low-Side Switch ON
Resistance
Tj = 25 °C 1.47 1.69 Ω
Tj =125 °C (7) 2.35 2.70 Ω
IDSS Leakage Current EN = Low; OUT = VCC 2mA
EN = Low; OUT = GND -0.3 mA
Table 5. Pin Description (continued)
L6229
6/25
Symbol Parameter Test Conditions Min Typ Max Unit
Source Drain Diodes
VSD Forward ON Voltage ISD = 1.4A, EN = LOW 1.15 1.3 V
trr Reverse Recovery Time If = 1.4A 300 ns
tfr Forward Recovery Time 200 ns
Logic Input (H1, H2, H3, EN, FWD/REV, BRAKE)
VIL Low level logic input voltage -0.3 0.8 V
VIH High level logic input voltage 2 7 V
IIL Low level logic input current GND Logic Input Voltage -10 µA
IIH High level logic input current 7V Logic Input Voltage 10 µA
Vth(ON) Turn-ON Input Threshold 1.8 2.0 V
Vth(OFF) Turn-OFF Input Threshold 0.8 1.3 V
VthHYS Input Thresholds Hysteresys 0.25 0.5 V
Switching Characteristics
tD(on)EN Enable to out turn-ON delay time (7) ILOAD = 1.4 A, Resistive Load 500 650 800 ns
tD(off)EN
Enable to out turn-OFF delay time
(7
)ILOAD = 1.4 A, Resistive Load 500 1000 ns
tD(on)IN Other Logic Inputs to Output Turn-
ON delay Time
ILOAD = 1.4 A, Resistive Load 1.6 µs
tD(off)IN Other Logic Inputs to out Turn-OFF
delay Time
ILOAD = 1.4 A, Resistive Load 800 ns
tRISE Output Rise Time (7) ILOAD = 1.4 A, Resistive Load 40 250 ns
tFALL Output Fall Time (7) ILOAD = 1.4 A, Resistive Load 40 250 ns
tDT Dead Time 0.5 1 µs
fCP Charge Pump Frequency Tj = -25 to 125°C (6) 0.6 1 MHz
PWM Comparator and Monostable
I
RCOFF
Source current at pin RCOFF V
RCOFF = 2.5 V 3.5 5.5 mA
VOFFSET Offset Voltage on Sense
Comparator
Vref = 0.5 V ±5 mV
tprop Turn OFF Propagation delay (8) Vref = 0.5 V 500 ns
tblank
Internal Blanking Time on Sense
Comparator
1µs
tON(min)
Minimum on Time
2.5 3 µs
tOFF PWM RecirculationTime ROFF= 20kΩ ; COFF =1nF
13
µs
ROFF= 100kΩ ; COFF =1nF
61
µs
IBIAS Input Bias Current at pin VREF 10 µA
Tacho Monostable
IRCPULSE Source Current at pin RCPULSE VRCPULSE = 2.5V 3.5 5.5 mA
Table 6. Electrical Characteristics (continued)
(VS = 48V , Tamb = 25 °C , unless otherwise specified)
7/25
L6229
(6) Tested at 25°C in a restricted range and guaranteed by characterization.
(7) See Fig. 4.
(8) Measured applying a voltage of 1V to pin SENSE and a voltage drop from 2V to 0V to pin VREF.
(9) See Fig. 5.
Figure 4. Switching Characteristic Definition
Figure 5. Overcurrent Detection Timing Definition
Symbol Parameter Test Conditions Min Typ Max Unit
tPULSE Monostable of Time RPUL = 20kΩ ; CPUL =1nF
12
µs
RPUL = 100kΩ ; CPUL =1nF
60
µs
RTACHO Open Drain ON Resistance 40 60 Ω
Over Current Detection & Protection
ISOVER Supply Overcurrent Protection
Threshold TJ = -25 to 125°C (6) 2 2.8 3.55 A
ROPDR Open Drain ON Resistance IDIAG = 4mA 40 60 Ω
IOH OCD high level leakage current VDIAG = 5V 1 µA
tOCD(ON) OCD Turn-ON Delay Time (9) IDIAG = 4mA; CDIAG < 100pF 200 ns
t
OCD(OFF)
OCD Turn-OFF Delay Time (9) IDIAG = 4mA; CDIAG < 100pF 100 ns
Table 6. Electrical Characteristics (continued)
(VS = 48V , Tamb = 25 °C , unless otherwise specified)
Vth(ON)
Vth(OFF)
90%
10%
EN
IOUT
t
t
tFALL
tD(OFF)EN
tRISE
tD(ON)EN
D01IN1316
ISOVER
90%
10%
IOUT
VDIAG
tOCD(OFF)
tOCD(ON)
D02IN1387
ON
OFF
BRIDGE
L6229
8/25
3 CIRCUIT DESCRIPTION
3.1 POWER STAGES and CHARGE PUMP
The L6229 integrates a Three-Phase Bridge, which consists of 6 Power MOSFETs connected as shown on the
Block Diagram. Each Power MOS has an R
DS(ON)
= 0.73
Ω
(typical value @25°C) with intrinsic fast freewheeling
diode. Switching patterns are generated by the PWM Current Controller and the Hall Effect Sensor Decoding
Logic (see relative paragraphs). Cross conduction protection is implemented by using a dead time (t
DT
= 1µs
typical value) set by internal timing circuit between the turn off and turn on of two Power MOSFETs in one leg
of a bridge.
Pins VS
A
and VS
B
MUST be connected together to the supply voltage (V
S
).
Using N-Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above the
power supply voltage. The Bootstrapped Supply (V
BOOT
) is obtained through an internal oscillator and few ex-
ternal components to realize a charge pump circuit as shown in Figure 6. The oscillator output (pin VCP) is a
square wave at 600KHz (typically) with 10V amplitude. Recommended values/part numbers for the charge
pump circuit are shown in Table 7.
Table 7. Charge Pump External Component Values.
Figure 6. Charge Pump Circuit
3.2 LOGIC INPUTS
Pins FWD/REV, BRAKE, EN, H
1
, H
2
and H
3
are TTL/CMOS and µC compatible logic inputs. The internal struc-
ture is shown in Figure 4. Typical value for turn-ON and turn-OFF thresholds are respectively V
th(ON)
= 1.8V and
V
th(OFF)
= 1.3V.
Pin EN (enable) may be used to implement Overcurrent and Thermal protection by connecting it to the open collector
DIAG output If the protection and an external disable function are both desired, the appropriate connection must be
implemented. When the external signal is from an open collector output, the circuit in Figure 8 can be used . For ex-
ternal circuits that are push pull outputs the circuit in Figure 9 could be used. The resistor R
EN
should be chosen in
the range from 2.2K
Ω
to 180K
Ω
. Recommended values for R
EN
and C
EN
are respectively 100K
Ω
and 5.6nF. More
information for selecting the values can be found in the Overcurrent Protection section.
CBOOT 220nF
CP10nF
RP100Ω
D11N4148
D21N4148
D2
C
BOOT
D1
R
P
C
P
V
S
VS
A
VCP VBOOT VS
B
D01IN1328
9/25
L6229
Figure 7. Logic Input Internal Structure
Figure 8. Pin EN Open Collector Driving
Figure 9. Pin EN Push-Pull Driving
3.3 PWM CURRENT CONTROL
The L6229 includes a constant off time PWM Current Controller. The current control circuit senses the bridge
current by sensing the voltage drop across an external sense resistor connected between the source of the
three lower power MOS transistors and ground, as shown in Figure 10. As the current in the motor increases
the voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor
becomes greater than the voltage at the reference input pin VREF the sense comparator triggers the
monostable switching the bridge off. The power MOS remain off for the time set by the monostable and the mo-
tor current recirculates around the upper half of the bridge in Slow Decay Mode as described in the next section.
When the monostable times out, the bridge will again turn on. Since the internal dead time, used to prevent
cross conduction in the bridge, delays the turn on of the power MOS, the effective Off Time t
OFF
is the sum of
the monostable time plus the dead time.
Figure 11 shows the typical operating waveforms of the output current, the voltage drop across the sensing re-
sistor, the pin RC voltage and the status of the bridge. More details regarding the Synchronous Rectification and
the output stage configuration are included in the next section.
Immediately after the Power MOS turn on, a high peak current flows through the sense resistor due to the re-
5V
D01IN1329
ESD
PROTECTION
5V
5V
OPEN
COLLECTOR
OUTPUT
R
EN
C
EN
EN
DIAG
D02IN137
8
ESD
PROTECTION
5V
PUSH-PULL
OUTPUT
REN
CEN
EN
D02IN1379
DIAG
ESD
PROTECTION
L6229
10/25
verse recovery of the freewheeling diodes. The L6229 provides a 1µs Blanking Time t
BLANK
that inhibits the
comparator output so that the current spike cannot prematurely retrigger the monostable.
Figure 10. PWM Current Controller Simplified Schematic
Figure 11. Output Current Regulation Waveforms
DRIVERS
+
DEAD TIME
S
Q
R
DRIVERS
+
DEAD TIME DRIVERS
+
DEAD TIME
OUT3
OUT2
SENSEBSENSEA
RSENSE
D02IN1380
RCOFF
R
OFF
C
OFF
VREF
OUT1
+
+
-
-
1µs
5mA
BLANKER
SENSE
COMPARATOR
MONOSTABLE
SET
2.5V
5V
FROM THE
LOW-SIDE
GATE DRIVERS
BLANKING TIME
MONOSTABLE
VS
B
VS
VS
A
TO GATE
LOGIC
(0) (1)
OFF
BCDDA
tON tOFF
BC
ON
2.5V
0Slow Decay Slow Decay
1µs tBLANK
tRCRISE tRCRISE
SYNCHRONOUS RECTIFICATION
1µs tBLANK
5V
VRC
VSENSE
VREF
IOUT
VREF
RSENSE
D02IN1351
tOFF
1µs tDT 1µs tDT
tRCFALL tRCFALL
11/25
L6229
Figure 12 shows the magnitude of the Off Time t
OFF
versus C
OFF
and R
OFF
values. It can be approximately
calculated from the equations:
t
RCFALL
= 0.6 · R
OFF
· C
OFF
t
OFF
= t
RCFALL
+ t
DT
= 0.6 · R
OFF
· C
OFF
+ t
DT
where R
OFF
and C
OFF
are the external component values and t
DT
is the internally generated Dead Time with:
20K
Ω
≤
R
OFF
≤
100K
Ω
0.47nF
≤
C
OFF
≤
100nF
t
DT
= 1µs (typical value)
Therefore:
t
OFF(MIN)
= 6.6µs
t
OFF(MAX)
= 6ms
These values allow a sufficient range of t
OFF
to implement the drive circuit for most motors.
The capacitor value chosen for C
OFF
also affects the Rise Time t
RCRISE
of the voltage at the pin RCOFF. The
Rise Time t
RCRISE
will only be an issue if the capacitor is not completely charged before the next time the
monostable is triggered. Therefore, the On Time t
ON
, which depends by motors and supply parameters, has to
be bigger than t
RCRISE
for allowing a good current regulation by the PWM stage. Furthermore, the On Time t
ON
can not be smaller than the minimum on time t
ON(MIN)
.
t
RCRISE
= 600 · C
OFF
Figure 13 shows the lower limit for the On Time t
ON
for having a good PWM current regulation capacity. It has
to be said that t
ON
is always bigger than t
ON(MIN)
because the device imposes this condition, but it can be smaller
than t
RCRISE
- t
DT
. In this last case the device continues to work but the Off Time t
OFF
is not more constant.
So, small C
OFF
value gives more flexibility for the applications (allows smaller On Time and, therefore, higher
switching frequency), but, the smaller is the value for C
OFF
, the more influential will be the noises on the circuit
performance.
Figure 12. tOFF versus COFF and ROFF.
tON tON MIN()
>2.5µs (typ. value)=
tON tRCRISE tDT
–>
⎩
⎨
⎧
0.1 1 10 100
1
10
100
1.103
1.104
Coff [nF]
toff [µs]
Roff = 100kΩ
Roff = 47kΩ
Roff = 20kΩ
L6229
12/25
Figure 13. Area where tON can vary maintaining the PWM regulation.
3.4 SLOW DECAY MODE
Figure 14 shows the operation of the bridge in the Slow Decay mode during the Off Time. At any time only two
legs of the three-phase bridge are active, therefore only the two active legs of the bridge are shown in the figure
and the third leg will be off. At the start of the Off Time, the lower power MOS is switched off and the current
recirculates around the upper half of the bridge. Since the voltage across the coil is low, the current decays slow-
ly. After the Dead Time the upper power MOS is operated in the synchronous rectification mode reducing the
impendence of the freewheeling diode and the related conducting losses. When the monostable times out, up-
per MOS that was operating the synchronous mode turns off and the lower power MOS is turned on again after
some delay set by the Dead Time to prevent cross conduction.
Figure 14. Slow Decay Mode Output Stage Configurations
0.1 1 10 100
1
10
100
Coff [nF]
ton(min) [µs]
1.5µs (typ. value)
A) ON TIME B) 1µs DEAD TIME C) SYNCHRONOUS
RECTIFICATION
D) 1µs DEAD TIME
D01IN1336
13/25
L6229
3.5 DECODING LOGIC
The Decoding Logic section is a combinatory logic that provides the appropriate driving of the three-phase
bridge outputs according to the signals coming from the three Hall Sensors that detect rotor position in a 3-
phase BLDC motor. This novel combinatory logic discriminates between the actual sensor positions for sensors
spaced at 60, 120, 240 and 300 electrical degrees. This decoding method allows the implementation of a uni-
versal IC without dedicating pins to select the sensor configuration.
There are eight possible input combinations for three sensor inputs. Six combinations are valid for rotor posi-
tions with 120 electrical degrees sensor phasing (see Figure 15, positions 1, 2, 3a, 4, 5 and 6a) and six combi-
nations are valid for rotor positions with 60 electrical degrees phasing (see Figure 17, positions 1, 2, 3b, 4, 5
and 6b). Four of them are in common (1, 2, 4 and 5) whereas there are two combinations used only in 120 elec-
trical degrees sensor phasing (3a and 6a) and two combinations used only in 60 electrical degrees sensor phas-
ing (3b and 6b).
The decoder can drive motors with different sensor configuration simply by following the Table 8. For any input
configuration (H
1
, H
2
and H
3
) there is one output configuration (OUT
1
, OUT
2
and OUT
3
). The output configura-
tion 3a is the same than 3b and analogously output configuration 6a is the same than 6b.
The sequence of the Hall codes for 300 electrical degrees phasing is the reverse of 60 and the sequence of the
Hall codes for 240 phasing is the reverse of 120. So, by decoding the 60 and the 120 codes it is possible to drive
the motor with all the four conventions by changing the direction set.
Table 8. 60 and 120 Electrical Degree Decoding Logic in Forward Direction.
Figure 15. 120° Hall Sensor Sequence.
Hall 120° 1 2 3a - 4 5 6a -
Hall 60° 1 2 - 3b 4 5 - 6b
H1HH L H L LHL
H2LHHHHLLL
H3LL L HHHHL
OUT1Vs High Z GND GND GND High Z Vs Vs
OUT2High Z Vs Vs Vs High Z GND GND GND
OUT3GND GND High Z High Z Vs Vs High Z High Z
Phasing 1->3 2->3 2->1 2->1 3->1 3->2 1->2 1->2
H1
H2 H2 H2 H2 H2 H3 H3 H3 H3 H3
H1 H1 H1 H1
H3 H2
H1
1 2 3a 4 5 6a
= H = L
L6229
14/25
Figure 16. 60° Hall Sensor Sequence.
3.6 TACHO
A tachometer function consists of a monostable, with constant off time (t
PULSE
), whose input is one Hall Effect
signal (H
1
). It allows developing an easy speed control loop by using an external op amp, as shown in Figure
18. For component values refer to Application Information section.
The monostable output drives an open drain output pin (TACHO). At each rising edge of the Hall Effect Sensors
H
1
, the monostable is triggered and the MOSFET connected to pin TACHO is turned off for a constant time
t
PULSE
(see Figure 17). The off time t
PULSE
can be set using the external RC network (R
PUL
, C
PUL
) connected
to the pin RCPULSE. Figure 19 gives the relation between t
PULSE
and C
PUL
, R
PUL
. We have approximately:
t
PULSE
= 0.6 · R
PUL
· C
PUL
where C
PUL
should be chosen in the range 1nF … 100nF and R
PUL
in the range 20K
Ω
… 100K
Ω
.
By connecting the tachometer pin to an external pull-up resistor, the output signal average value V
M
is propor-
tional to the frequency of the Hall Effect signal and, therefore, to the motor speed. This realizes a simple Fre-
quency-to-Voltage Converter. An op amp, configured as an integrator, filters the signal and compares it with a
reference voltage V
REF
, which sets the speed of the motor.
Figure 17. Tacho Operation Waveforms.
H1 H1
H2 H2 H2 H2 H2
H3 H3 H3 H3 H3
H1 H1 H1 H1
H3
H2
1 2 3b 4 5 6b
= H = L
VM
tPULSE
T
--------- ---------VDD
⋅=
T
tPULSE
H1
VTACHO
H2
H3
VM
VDD
15/25
L6229
Figure 18. Tachometer Speed Control Loop.
Figure 19. tPULSE versus CPUL and RPUL.
CREF2
RPUL C
PUL
RDD
R3
R2
R1
C1
CREF1
VREF
TACHO
H1
TACHO
MONOSTABLE
RCPULSE
VDD
VREF
R4
110100
10
100
1.10
3
1.10
4
Cpul [nF]
tpulse [µs]
RPUL = 100kΩ
RPUL = 47kΩ
RPUL = 20kΩ
L6229
16/25
3.7 NON-DISSIPATIVE OVERCURRENT DETECTION and PROTECTION
The L6229 integrates an Overcurrent Detection Circuit (OCD) for full protection. This circuit provides Output-to-
Output and Output-to-Ground short circuit protection as well. With this internal over current detection, the exter-
nal current sense resistor normally used and its associated power dissipation are eliminated. Figure 20 shows
a simplified schematic for the overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise fraction of the out-
put current is implemented with each High Side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference cur-
rent I
REF
. When the output current reaches the detection threshold (typically I
SOVER
= 2.8A) the OCD compar-
ator signals a fault condition. When a fault condition is detected, an internal open drain MOS with a pull down
capability of 4mA connected to pin DIAG is turned on.
The pin DIAG can be used to signal the fault condition to a
µ
C or to shut down the Three-Phase Bridge simply
by connecting it to pin EN and adding an external R-C (see R
EN
, C
EN
).
Figure 20. Overcurrent Protection Simplified Schematic
Figure 21 shows the Overcurrent Detetection operation. The Disable Time t
DISABLE
before recovering normal
operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected
whether by C
EN
and R
EN
values and its magnitude is reported in Figure 22. The Delay Time t
DELAY
before turn-
ing off the bridge when an overcurrent has been detected depends only by C
EN
value. Its magnitude is reported
in Figure 23
C
EN
is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C
EN
should be chosen as big as possible according to the maximum tolerable Delay Time and the R
EN
value should
be chosen according to the desired Disable Time.
The resistor R
EN
should be chosen in the range from 2.2K
Ω
to 180K
Ω
. Recommended values for R
EN
and C
EN
are respectively 100K
Ω
and 5.6nF that allow obtaining 200
µ
s Disable Time.
+
OVER TEMPERATURE
IREF
IREF
I1+I2 / n
I1 / n
HIGH SIDE DMOS
POWER SENSE
1 cell POWER SENSE
1 cell
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
POWER DMOS
n cells
HIGH SIDE DMOS HIGH SIDE DMOS
OUT1OUT2
VSA OUT3VSB
I1I2I3
I2/ n
I3/ n
OCD
COMPARATOR
TO GATE
LOGIC
INTERNAL
OPEN-DRAIN
RDS(ON)
40Ω TYP.
CEN
REN
DIAG
EN
VDD
µC or LOGIC
D02IN1381
17/25
L6229
Figure 21. Overcurrent Protection Waveforms
Figure 22. tDISABLE versus CEN and REN.
Figure 23. tDELAY versus CEN.
ISOVER
IOUT
Vth(ON)
Vth(OFF)
VEN(LOW)
VDD
tOCD(ON) tD(ON)EN
tEN(FALL) tEN(RISE)
tDISABLE
tDELAY
tOCD(OFF)
tD(OFF)EN
VEN=VDIAG
BRIDGE
ON
OFF
OCD
ON
OFF
D02IN1383
110100
1
10
100
1.103
CEN [n F ]
tDISABLE [µs]
REN = 220 kΩREN = 100 kΩREN = 47 kΩ
REN = 33 kΩ
REN = 10 kΩ
110100
1
10
100
1.103
CEN [n F ]
tDISABLE [µs]
REN = 220 kΩREN = 100 kΩREN = 47 kΩ
REN = 33 kΩ
REN = 10 kΩ
110100
0.1
1
10
Cen [nF]
tdelay [µs]
L6229
18/25
4 APPLICATION INFORMATION
A typical application using L6229 is shown in Figure 24. Typical component values for the application are shown
in Table 9. A high quality ceramic capacitor (C
2
) in the range of 100nF to 200nF should be placed between the
power pins VS
A
and VS
B
and ground near the L6229 to improve the high frequency filtering on the power supply
and reduce high frequency transients generated by the switching. The capacitor (C
EN
) connected from the EN
input to ground sets the shut down time when an over current is detected (see Overcurrent Protection). The two
current sensing inputs (SENSE
A
and SENSE
B
) should be connected to the sensing resistor R
SENSE
with a trace
length as short as possible in the layout. The sense resistor should be non-inductive resistor to minimize the di/
dt transients across the resistor. To increase noise immunity, unused logic pins are best connected to 5V (High
Logic Level) or GND (Low Logic Level) (see pin description). It is recommended to keep Power Ground and
Signal Ground separated on PCB.
Table 9. Component Values for Typical Application.
Figure 24. Typical Application
C1100µF R15K6Ω
C2100nF R21K8Ω
C3220nF R34K7Ω
CBOOT 220nF R41MΩ
COFF 1nF RDD 1KΩ
CPUL 10nF REN 100KΩ
CREF1 33nF RP100Ω
CREF2 100nF RSENSE 0.6Ω
CEN 5.6nF ROFF 33KΩ
CP10nF RPUL 47KΩ
D11N4148 RH1, RH2, RH3 10KΩ
D21N4148
VREF +
-
BRAKE
14
5
18
19
21
16
OUT
1
H
1
H
2
H
3
GND
RCOFF
OUT
3
OUT
2
VS
A
POWER
GROUND
SIGNAL
GROUND
+5V
+
-
V
S
8-52V
DC
13
VS
B
VCP
VBOOT
C
P
C
BOOT
R
P
D
2
D
1
C
1
C
2
SENSE
A
R
SENSE
20
BRAKE
6
7
DIAG
EN
C
EN
R
EN
ENABLE
2
FWD/REV FWD/REV
11
TACHO
8
12
1
23
24
4
17
3
15
22
SENSE
B
THREE-PHASE MOTOR
C
OFF
R
OFF
R
H1
R
H2
R
H3
10
C
REF1
R
2
R
3
R
1
R
DD
R
4
C
3
C
REF2
RCPULSE
9
C
PUL
R
PUL
D02IN1357
M
V
REF
5V
HALL
SENSOR
19/25
L6229
4.1 OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION
In Figure 25 is shown the approximate relation between the output current and the IC power dissipation using
PWM current control.
For a given output current the power dissipated by the IC can be easily evaluated, in order to establish which
package should be used and how large must be the on-board copper dissipating area to guarantee a safe op-
erating junction temperature (125°C maximum).
Figure 25. IC Power Dissipation versus Output Power.
4.2 THERMAL MANAGEMENT
In most applications the power dissipation in the IC is the main factor that sets the maximum current that can
be delivered by the device in a safe operating condition. Selecting the appropriate package and heatsinking con-
figuration for the application is required to maintain the IC within the allowed operating temperature range for
the application. Figures 26, 27 and 28 show the Junction-to-Ambient Thermal Resistance values for the
PowerSO36, PowerDIP24 and SO24 packages.
For instance, using a PowerSO package with copper slug soldered on a 1.5mm copper thickness FR4 board
with 6cm
2
dissipating footprint (copper thickness of 35
µ
m), the R
th(j-amb)
is about 35°C/W. Figure 29 shows
mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance
can be reduced down to 15°C/W.
Figure 26. PowerSO36 Junction-Ambient thermal resistance versus on-board copper area.
No PWM
f
SW
= 30 kHz (slow decay)
Test Conditions:
Supply Voltage = 24 V
0 0.25 0.5 0.75 1 1.25 1.5
0
2
4
6
8
10
P
IOUT [A]
D
[W]
I
OUT
I
1
I
3
I
2
I
OUT
I
OUT
13
18
23
28
33
38
43
12345678910111213
Without Ground La
y
er
With Ground La
y
er
With Ground La
y
er+16 via
Holes
sq. cm
ºC / W
On-Board Copper Area
L6229
20/25
Figure 27. PowerDIP24 Junction-Ambient thermal resistance versus on-board copper area.
Figure 28. SO24 Junction-Ambient thermal resistance versus on-board copper area.
Figure 29. Mounting the PowerSO Package.
39
40
41
42
43
44
45
46
47
48
49
1 2 3 4 5 6 7 8 9 101112
Co
pp
er Area is on Bottom
Side
Co
pp
er Area is on To
p
Side
sq. cm
ºC / W On-Board Copper Area
48
50
52
54
56
58
60
62
64
66
68
123456789101112
Copper Area is on Top Side
sq. cm
ºC / W On-Board Copper Area
Slug soldered
to PCB with
dissipating area
Slug soldered
to PCB with
dissipating area
plus ground layer
Slug soldered to PCB with
dissipating area plus ground layer
contacted through via holes
21/25
L6229
Figure 30. PowerSO36 Mechanical Data & Package Dimensions
OUTLINE AND
MECHANICAL DATA
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 3.25 3.5 0.128 0.138
A2 3.3 0.13
A4 0.8 1 0.031 0.039
A5 0.2 0.008
a100.07500.003
b 0.22 0.38 0.008 0.015
c 0.23 0.32 0.009 0.012
D 15.8 16 0.622 0.630
D1 9.4 9.8 0.37 0.38
D2 1 0.039
E 13.9 14.5 0.547 0.57
E1 10.9 11.1 0.429 0.437
E2 2.9 0.114
E3 5.8 6.2 0.228 0.244
E4 2.9 3.2 0.114 1.259
e 0.65 0.026
e3 11.05 0.435
G 0 0.075 0 0.003
H 15.5 15.9 0.61 0.625
h1.10.043
L 0.8 1.1 0.031 0.043
N 10˚ (max)
s 8˚ (max)
Note: “D and E1” do not include mold flash or protusions.
- Mold flash or protusions shall not exceed 0.15mm (0.006”)
- Critical dimensions are "a3", "E" and "G".
PowerSO36
e
a2 A
E
a1
PSO36MEC
DETAIL A
D
118
1936
E1
E2
h x 45
DETAIL A
lead
slug
a3
S
Gage Plane
0.35
L
DETAIL B
DETAIL B
(COPLANARITY)
GC
- C -
SEATING PLANE
e3
c
NN
M
0.12 AB
b
B
A
H
E3
D1
BOTTOM VIEW
0096119 B
L6229
22/25
Figure 31. PDIP-24 Mechanical Data & Package Dimensions
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.320 0.170
A1 0.380 0.015
A2 3.300 0.130
B 0.410 0.460 0.510 0.016 0.018 0.020
B1 1.400 1.520 1.650 0.055 0.060 0.065
c 0.200 0.250 0.300 0.008 0.010 0.012
D 31.62 31.75 31.88 1.245 1.250 1.255
E 7.620 8.260 0.300 0.325
e 2.54 0.100
E1 6.350 6.600 6.860 0.250 0.260 0.270
e1 7.620 0.300
L 3.180 3.430 0.125 0.135
M 0˚ min, 15˚ max.
PDIP 24 (0.300")
A1
B eB1
D
13
12
24
1
L
A
e1
A2
c
E1
SDIP24L
M
0034965 D
OUTLINE AND
MECHANICAL DATA
23/25
L6229
Figure 32. SO24 Mechanical Data & Package Dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B 0.33 0.51 0.013 0.200
C 0.23 0.32 0.009 0.013
D (1) 15.20 15.60 0.598 0.614
E 7.40 7.60 0.291 0.299
e 1.27 0.050
H 10.0 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.40 1.27 0.016 0.050
k 0˚ (min.), 8˚ (max.)
ddd 0.10 0.004
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO24
0070769 C
Weight: 0.60gr
L6229
24/25
Table 10. Revision History
Date Revision Description of Changes
September 2003 1 First Issue
January 2004 2 Migration from ST-Press dms to EDOCS.
October 2004 3 Updated the style graphic form.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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25/25
L6229
