ADS822
ADS825
®
10-Bit, 40MHz Sampling
ANALOG-TO-DIGITAL CONVERTERS
FEATURES
●HIGH SNR: 60dB
●HIGH SFDR: 72dBFS
●LOW POWER: 190mW
●INTERNAL/EXTERNAL REFERENCE OPTION
●SINGLE-ENDED OR
FULLY DIFFERENTIAL ANALOG INPUT
●PROGRAMMABLE INPUT RANGE
●LOW DNL: 0.5LSB
●SINGLE +5V SUPPLY OPERATION
●
+3V OR +5V LOGIC I/O COMPATIBLE (ADS825)
●POWER DOWN: 20mW
●28-LEAD SSOP PACKAGE
APPLICATIONS
●MEDICAL IMAGING
● TEST EQUIPMENT
●COMPUTER SCANNERS
●COMMUNICATIONS
●VIDEO DIGITIZING
DESCRIPTION
The ADS822 and ADS825 are pipeline, CMOS analog-to-digital
converters that operate from a single +5V power supply. These
converters provide excellent performance with a single-ended
input and can be operated with a differential input for added
spurious performance. These high-performance converters in-
clude a 10-bit quantizer, high-bandwidth track-and-hold, and a
high-accuracy internal reference. They also allow for the user to
disable the internal reference and utilize external references. This
external reference option provides excellent gain and offset
matching when used in multi-channel applications or in applica-
tions where full-scale range adjustment is required.
The ADS822 and ADS825 employ digital error correction tech-
niques to provide excellent differential linearity for demanding
imaging applications. Its low distortion and high SNR give the
extra margin needed for medical imaging, communications,
video, and test instrumentation. The ADS822 and ADS825 offer
power dissipation of 190mW and also provide a power-down
mode, thus reducing power dissipation to only 20mW. The
ADS825 is +3V or +5V Logic I/O compatible.
The ADS822 and ADS825 are specified at a maximum sampling
frequency of 40MHz and a single-ended input range of 1.5V to
3.5V. The ADS822 and ADS825 are available in a 28-lead SSOP
package and are pin-for-pin compatible with the 10-bit, 60MHz
ADS823 and ADS826, and the 10-bit, 70MHz ADS824, provid-
ing an upgrade path to higher sampling frequencies.
TM
©1997 Burr-Brown Corporation PDS-1385E Printed in U.S.A. October, 1999
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
For most current data sheet and other product
information, visit www.burr-brown.com
10-Bit
Pipelined
A/D Core
Internal
Reference
Optional External
Reference
Timing
Circuitry
Error
Correction
Logic
3-State
Outputs
T/H
CLK VDRV
ADS822
ADS825
+VS
OEPDInt/Ext
D0
D9
•
•
•
INVIN
IN
CM
ADS822
ADS825
2
®
ADS822, ADS825
SPECIFICATIONS
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.
CMOS-Compatible
Rising Edge of Convert Clock
CMOS-Compatible
Straight Offset Binary
CMOS-Compatible
Straight Offset Binary
ADS822E ADS825E(1)
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 10 Guaranteed 10 Guaranteed Bits
SPECIFIED TEMPERATURE RANGE Ambient Air –40 to +85 –40 to +85 °C
ANALOG INPUT
Standard Single-Ended Input Range 2Vp-p 1.5 3.5 ✻✻V
Optional Single-Ended Input Range 1Vp-p 2 3 ✻✻V
Common-Mode Range 2.5 ✻V
Optional Differential Input Range 2Vp-p 2 3 ✻✻V
Analog Input Bias Current 1✻µA
Input Impedance 1.25 || 5 ✻MΩ || pF
Track-Mode Input Bandwidth –3dBFS Input 300 ✻MHz
CONVERSION CHARACTERISTICS
Sample Rate 10k 40M ✻✻Samples/s
Data Latency 5✻Clk Cyc
DYNAMIC CHARACTERISTICS
Differential Linearity Error
(largest code error)
f = 1MHz ±0.25 ±1.0 ✻✻ LSB
f = 10MHz ±0.5 ✻LSB
No Missing Codes Guaranteed Guaranteed
Integral Nonlinearity Error, f = 1MHz ±0.5 ±2.0 ✻✻ LSBs
Spurious Free Dynamic Range(2) Referred to Full Scale
f = 1MHz 72 71 dBFS(3)
f = 10MHz 63 66 60 65 dBFS
Two-Tone Intermodulation Distortion(4)
f = 9.5MHz and 9.9MHz (–7dB each tone) –67 ✻dBc
Signal-to-Noise Ratio (SNR) Referred to Full Scale
f = 1MHz 60 ✻dB
f = 10MHz 57 60 ✻✻ dB
Signal-to-(Noise + Distortion) (SINAD) Referred to Full Scale
f = 1MHz 59 ✻dB
f = 10MHz 56 58 ✻✻ dB
Effective Number of Bits(5), f = 1MHz 9.5 ✻Bits
Output Noise Input Tied to Common-Mode 0.2 ✻LSBs rms
Aperture Delay Time 3✻ns
Aperture Jitter 1.2 ✻ps rms
Overvoltage Recovery Time 2✻ns
Full-Scale Step Acquisition Time 5✻ns
DIGITAL INPUTS
Logic Family
Convert Command Start Conversion
High Level Input Current(6) (VIN = 5VDD)100 ✻µA
Low Level Input Current (VIN = 0V) 10 ✻µA
High Level Input Voltage +3.5 +2.0 V
Low Level Input Voltage +1.0 +0.8 V
Input Capacitance 5✻pF
DIGITAL OUTPUTS
Logic Family
Logic Coding
Low Output Voltage (IOL = 50µA to 1.6mA) VDRV = 5V +0.1 ✻V
High Output Voltage, (IOH = 50µA to 0.5mA) +4.9 ✻V
Low Output Voltage, (IOL = 50µA to 1.6mA) VDRV = 3V +0.1 ✻V
High Output Voltage, (IOH = 50µA to 0.5mA) +2.8 ✻V
3-State Enable Time OE = H to L 2 40 ✻✻ ns
3-State Disable Time OE = L to H 2 10 ✻✻ ns
Output Capacitance 5✻pF
ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted)
Zero Error (referred to –FS) at 25°C±1.0 ±3.0 ✻✻ % FS
Zero Error Drift (referred to –FS) 5✻ppm/°C
Midscale Offset Error at 25°C±0.29 % FS
Gain Error(7) at 25°C±1.5 ±2.5 ✻✻ % FS
Gain Error Drift(7) 38 ✻ppm/°C
Gain Error(8) at 25°C±0.75 ±1.5 ✻✻ % FS
Gain Error Drift(8) 25 ✻ppm/°C
Power Supply Rejection of Gain ∆ VS = ±5% 70 ✻dB
REFT Tolerance Deviation From Ideal 3.5V ±10 ±25 ✻✻ mV
REFB Tolerance Deviation From Ideal 1.5V ±10 ±25 ✻✻ mV
External REFT Voltage Range REFB + 0.8 3.5 VS – 1.25 ✻✻✻ V
External REFB Voltage Range 1.25 1.5 REFT – 0.8 ✻✻✻ V
Reference Input Resistance REFT to REFB 1.6 ✻kΩ
TTL, +3V/+5V CMOS-Compatible
Rising Edge of Convert Clock
3
®
ADS822, ADS825
SPECIFICATIONS (Cont.)
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.
PIN DESIGNATOR DESCRIPTION
1 GND Ground
2 Bit 1 Data Bit 1 (D9) (MSB)
3 Bit 2 Data Bit 2 (D8)
4 Bit 3 Data Bit 3 (D7)
5 Bit 4 Data Bit 4 (D6)
6 Bit 5 Data Bit 5 (D5)
7 Bit 6 Data Bit 6 (D4)
8 Bit 7 Data Bit 7 (D3)
9 Bit 8 Data Bit 8 (D2)
10 Bit 9 Data Bit 9 (D1)
11 Bit 10 Data Bit 10 (D0) (LSB)
12 OE Output Enable. HI = high impedance state
LO = normal operation (internal pull-down
resistor)
13 PD Power Down. HI = enable; LO = disable
14 CLK Convert Clock Input
15 +VS+5V Supply
16 GND Ground
17 RSEL Input Range Select. HI = 2V; LO = 1V
18 INT/EXT
Reference Select. HI = external, LO = internal
19 REFB Bottom Reference
20 ByB Bottom Ladder Bypass
21 ByT Top Ladder Bypass
22 REFT Top Reference
23 CM Common-Mode Voltage Output
24 IN Complementary Input (–)
25 IN Analog Input (+)
26 GND Analog Ground
27 +VS+5V Supply
28 VDRV Output Logic Driver Supply Voltage
PIN DESCRIPTIONS
Top View SSOP
PIN CONFIGURATION
POWER SUPPLY REQUIREMENTS
Supply Voltage: +VSOperating +4.75 +5.0 +5.25 ✻✻✻ V
Supply Current: +ISOperating (External Reference) 40 ✻mA
Power Dissipation: VDRV = 5V External Reference 200 230 ✻✻ mW
VDRV = 3V External Reference 190 ✻mW
VDRV = 5V Internal Reference 250 ✻mW
VDRV = 3V Internal Reference 240 ✻mW
Power Down Operating 20 ✻mW
Thermal Resistance,
θ
JA
28-Lead SSOP 89 ✻°C/W
✻ Indicates the same specifications as the ADS822E.
NOTES: (1) ADS825E accepts a +3V clock input. (2) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (3) dBFS means dB relative to Full Scale. (4) Two-tone intermodulation
distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (5) Effective number of bits (ENOB) is defined
by (SINAD – 1.76)/6.02. (6) A 50kΩ pull-down resistor is inserted internally on OE pin. (7) Includes internal reference. (8) Excludes internal reference.
ADS822E ADS825E(1)
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
GND
Bit 1 (MSB)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10 (LSB)
OE
PD
CLK
VDRV
+V
S
GND
IN
IN
CM
REFT
ByT
ByB
REFB
INT/EXT
RSEL
GND
+V
S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS822
ADS825
4
®
ADS822, ADS825
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility
for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights
or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life
support devices and/or systems.
TIMING DIAGRAM
5 Clock Cycles
Data Invalid
t
D
t
L
t
H
t
CONV
N–5 N–4 N–3 N–2 N–1 N N+1 N+2Data Out
Clock
Analog In N
t
2
N+1 N+2 N+3 N+4 N+5 N+6 N+7
t
1
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tCONV Convert Clock Period 25 100µsns
tLClock Pulse Low 11.5 12.5 ns
tHClock Pulse High 11.5 12.5 ns
tDAperture Delay 3 ns
t1Data Hold Time, CL = 0pF 3.9 ns
t2New Data Delay Time, CL = 15pF max 12 ns
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
+VS....................................................................................................... +6V
Analog Input............................................................. –0.3V to (+VS + 0.3V)
Logic Input ............................................................... –0.3V to (+VS + 0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature..................................................................... +150°C
ABSOLUTE MAXIMUM RATINGS
PACKAGE SPECIFIED
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER(1) MEDIA
ADS822E SSOP-28 324 –40°C to +85°C ADS822E ADS822E Rails
" " " " " ADS822E/1K Tape and Reel
ADS825E SSOP-28 324 –40°C to +85°C ADS825E ADS825E Rails
" " " " " ADS825E/1K Tape and Reel
NOTE: (1) Models with a slash ( /) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of ADS822E/1K” will get a single 1000-piece Tape and Reel.
PACKAGE/ORDERING INFORMATION
PRODUCT DEMO BOARD
ADS822E DEM-ADS822E
DEMO BOARD ORDERING INFORMATION
5
®
ADS822, ADS825
SPECTRAL PERFORMANCE
Frequency (MHz)
Magnitude (dB)
0
–20
–40
–60
–80
–100 0 5 10 15 20
f
IN
= 10MHz
SPECTRAL PERFORMANCE
(Single-Ended, 1Vp-p)
Frequency (MHz)
Magnitude (dB)
0
–20
–40
–60
–80
–100 0 5 10 15 20
fIN = 20MHz
SNR = 57dBFS
SFDR = 70dBFS
SPECTRAL PERFORMANCE
(Single-Ended, 1Vp-p)
Frequency (MHz)
Magnitude (dB)
0
–20
–40
–60
–80
–100 0 5 10 15 20
fIN = 10MHz
SNR = 57dBFS
SFDR = 71dBFS
SPECTRAL PERFORMANCE
(Differential Input, 1Vp-p)
Frequency (MHz)
Magnitude (dB)
0
–20
–40
–60
–80
–100 0 5 10 15 20
fIN = 10MHz
SNR = 58dBFS
SFDR = 74dBFS
SPECTRAL PERFORMANCE
Frequency (MHz)
Magnitude (dB)
0
–20
–40
–60
–80
–100 0 5 10 15 20
f
IN
= 1MHz
UNDERSAMPLING
(Differential Input, 2Vp-p)
Frequency (MHz)
Magnitude (dB)
0
–20
–40
–60
–80
–100 0 5 10 15 20
fS = 40MHz
fIN = 45MHz
SNR = 60dBFS
SFDR = 74dBFS
TYPICAL PERFORMANCE CURVES
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.
6
®
ADS822, ADS825
UNDERSAMPLING
(Differential Input, 2Vp-p)
Frequency (MHz)
Magnitude (dB)
0
–20
–40
–60
–80
–100 0 5 10 15 20
fS = 40MHz
fIN = 75MHz
SNR = 59dBFS
SFDR = 66dBFS
TWO-TONE INTERMODULATION DISTORTION
Frequency (MHz)
Magnitude (dB)
0
–20
–40
–60
–80
–100 0 5 10 15 20
f
1
= 9.5MHz at –7dBFS
f
2
= 9.9MHz at –7dBFS
IMD (3) = –67dB
INTEGRAL LINEARITY ERROR
Output Code
ILE (LSB)
2.0
1.0
0
–1.0
–2.0 0 256 512 768 1024
DIFFERENTIAL LINEARITY ERROR
Output Code
DLE (LSB)
1.0
0.5
0
–0.5
–1.0 0 20 40 60 80 1024
f
IN
= 10MHz
DIFFERENTIAL LINEARITY ERROR
Output Code
DLE (LSB)
1.0
0.5
0
–0.5
–1.0 0 20 40 60 80 1024
f
IN
= 1MHz
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.
SWEPT POWER SFDR
Input Amplitude (dBFS)
100
80
60
40
20
0–60 –50 –40 –30 –10–20 0
SFDR (dBFS, dBc)
dBc
dBFS
7
®
ADS822, ADS825
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.
75
70
65
60
55
DYNAMIC PERFORMANCE vs TEMPERATURE
SFDR, SNR (dBFS)
–50 –25 0 25 50 75 100
Temperature (°C)
SFDR (f
IN
= 10MHz)
SNR (f
IN
= 10MHz)
SNR (f
IN
= 20MHz)
SFDR (f
IN
= 20MHz)
60
59
58
57
SIGNAL-TO-(NOISE + DISTORTION)
vs TEMPERATURE
Sinad (dBFS)
–50 –25 0 25 50 75 100
Temperature (°C)
f
IN
= 1MHz
f
IN
= 20MHz
f
IN
= 10MHz
.60
.50
.40
.30
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
DLE (LSB)
–50 –25 0 25 50 75 100
Temperature (°C)
fIN = 10MHz
fIN = 20MHz
800k
600k
400k
200k
0
OUTPUT NOISE (DC Input)
Counts
N-2 N-1 N N+1 N+2
Code
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
Frequency (MHz)
75
70
65
60
55
500.1 1 10 100
SFDR, SNR (dBFS)
SNR
SFDR
POWER DISSIPATION vs TEMPERATURE
Temperature (°C)
205
200
195
190–50 0 25–25 50 75 100
Power (mW)
8
®
ADS822, ADS825
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS822 and ADS825 are high-speed CMOS analog-to-
digital converters which employ a pipelined converter archi-
tecture consisting of 9 internal stages. Each stage feeds its
data into the digital error correction logic ensuring excellent
differential linearity and no missing codes at the 10-bit level.
The output data becomes valid on the rising clock edge (see
Timing Diagram). The pipeline architecture results in a data
latency of 5 clock cycles.
The analog inputs of the ADS822 and ADS825 are differen-
tial track-and-hold (see Figure 1). The differential topology,
along with tightly matched capacitors, produce a high level
of AC performance while sampling at very high rates.
The ADS822 and ADS825 allow their analog inputs to be
driven either single-ended or differentially. The typical con-
figuration for the ADS822 and ADS825 is the single-ended
mode in which the input track-and-hold performs a single-
ended-to-differential conversion of the analog input signal.
Both inputs (IN, IN) require external biasing using a com-
mon-mode voltage that is typically at the mid-supply level
(+VS/2).
The following application discussion focuses on the single-
ended configuration. Typically, its implementation is easier
to achieve and the rated specifications for the ADS822 and
ADS825 are characterized using the single-ended mode of
operation.
DRIVING THE ANALOG INPUT
The ADS822 and ADS825 achieve excellent AC performance
either in the single-ended or differential mode of operation.
FIGURE 1. Simplified Circuit of Input Track-and-Hold with
Timing Diagram.
The selection for the optimum interface configuration will
depend on the individual application requirements and sys-
tem structure. For example, communications applications
often process a band of frequencies that do not include DC,
whereas in imaging applications, the previously restored DC
level must be maintained correctly up to the A/D converter.
Features on the ADS822 and ADS825, such as the input
range select (RSEL pin) or the option for an external
reference, provide the needed flexibility to accommodate a
wide range of applications. In any case, the ADS822 and
ADS825 should be configured such that the application
objectives are met while observing the headroom require-
ments of the driving amplifier in order to yield the best
overall performance.
INPUT CONFIGURATIONS
AC-Coupled, Single-Supply Interface
Figure 2 shows the typical circuit for an AC-coupled analog
input configuration of the ADS822 and ADS825 while all
components are powered from a single +5V supply.
With the RSEL pin connected high, the full-scale input
range is set to 2Vp-p. In this configuration, the top and
bottom references (REFT, REFB) provide an output voltage
of +3.5V and +1.5V, respectively. Two resistors ( 2x 1.62kΩ)
are used to create a common-mode voltage (VCM) of ap-
proximately +2.5V to bias the inputs of the driving amplifier
A1. Using the OPA680 on a single +5V supply, its ideal
common-mode point is at +2.5V which coincides with the
recommended common-mode input level for the ADS822
and ADS825. This obviates the need of a coupling capacitor
between the amplifier and the converter. Even though the
OPA680 has an AC gain of +2, the DC gain is only +1 due
to the blocking capacitor at resistor RG.
The addition of a small series resistor (RS) between the
output of the op amp and the input of the ADS822 and
ADS825 will be beneficial in almost all interface configura-
tions. This will decouple the op amp’s output from the
capacitive load and avoid gain peaking, which can result in
increased noise. For best spurious and distortion perfor-
mance, the resistor value should be kept below 100Ω.
Furthermore, the series resistor in combination with the
10pF capacitor establishes a passive low-pass filter limiting
the bandwidth for the wideband noise, thus helping improve
the SNR performance.
AC-Coupled, Dual Supply Interface
The circuit provided in Figure 3 shows typical connections
for the analog input in case the selected amplifier operates
on dual supplies. This might be necessary to take full
advantage of very low distortion operational amplifiers, like
the OPA642. The advantage is that the driving amplifier can
be operated with a ground referenced bipolar signal swing.
This will keep the distortion performance at its lowest since
the signal range stays within the linear region of the op amp
and sufficient headroom to the supply rails can be main-
tained. By capacitively coupling the single-ended signal to
the input of the ADS822 and ADS825, its common-mode
requirements can easily be satisfied with two resistors con-
nected between the top and bottom reference.
φ1
φ1φ2φ1
φ1φ1
φ1
φ1
φ2
φ1φ2φ1
φ2
IN
IN
OUT
OUT
Op Amp
Bias VCM
Op Amp
Bias VCM
CH
CI
CI
CH
Input Clock (50%)
Internal Non-overlapping Clock
9
®
ADS822, ADS825
FIGURE 2. AC-Coupled Input Configuration for a 2Vp-p Full-Scale Range and a Common-Mode Voltage, VCM, at +2.5V Derived
From the Internal Top (REFT) and Bottom Reference (REFB).
FIGURE 3. AC-Coupling the Dual Supply Amplifier OPA642 to the ADS822 for a 2Vp-p Full-Scale Input Range.
For applications requiring the driving amplifier to provide a
signal amplification, with a gain ≥ 5, consider using decom-
pensated voltage-feedback op amps, like the OPA643, or
current-feedback op amps like the OPA681 and OPA658.
DC-coupled with Level Shift
Several applications may require that the bandwidth of the
signal path include DC, in which case, the signal has to be
DC-coupled to the A/D converter. In order to accomplish
this, the interface circuit has to provide a DC level shift to
the analog input signal. The circuit shown in Figure 4
employs a dual op amp, A1, to drive the input of the
ADS822 and ADS825, and level shifts the signal to be
compatible with the selected input range. With the RSEL pin
tied to the supply and the INT/EXT pin to ground, the
ADS822 and ADS825 are configured for a 2Vp-p input
range and use the internal references. The complementary
input (IN) may be appropriately biased using the +2.5V
common-mode voltage available at the CM pin. One half of
amplifier A1 buffers the REFB pin and drives the voltage
divider R1, R2. Due to the op amp’s noise gain of
+2V/V, assuming RF = RIN , the common-mode voltage
(VCM) has to be re-scaled to +1.25V. This results in the
correct DC level of +2.5V for the signal input (IN). Any DC
voltage differences between the IN and IN inputs of the
ADS822 and ADS825 effectively produces an offset, which
can be corrected for by adjusting the resistor values of the
divider, R1and R2. The selection criteria for a suitable op
amp should include the supply voltage, input bias current,
output voltage swing, distortion, and noise specification.
Note that in this example, the overall signal phase is in-
verted. To re-establish the original signal polarity, it is
always possible to interchange the IN and IN connections.
+V
IN
0V
–V
IN
OPA680
V
IN
R
F
402Ω
1.62kΩ
R
G
402Ω
ADS822
ADS825
R
S
50Ω
10pF
0.1µF
IN
IN
CM
INT/EXT GND
REFT
+3.5V
1.62kΩ
50Ω
V
CM
+2.5V
REFB
+1.5V
0.1µF
0.1µF
RSEL +V
S
+5V
+5V
OPA642
V
IN
R
F
402Ω
1.62kΩ
R
G
402Ω
ADS822
ADS825
R
S
24.9Ω
1.62kΩ
100pF
0.1µF
0.1µFIN
IN
CM
REFB
+1.5V INT/EXT GND
REFT
+3.5V RSEL +V
S
+5V
+5V
–5V
10
®
ADS822, ADS825
FIGURE 4. DC-Coupled Interface Circuit with Dual Current-Feedback Amplifier OPA2681.
FIGURE 5. Transformer Coupled Input. FIGURE 6. Equivalent Reference Circuit with Recommended
Reference Bypassing.
SINGLE-ENDED-TO-DIFFERENTIAL CONFIGURATION
(Transformer Coupled)
If the application requires a signal conversion from a single-
ended source to feed the ADS822 and ADS825 differen-
tially, a RF transformer might be a good solution. The
selected transformer must have a center tap in order to apply
the common-mode DC voltage necessary to bias the con-
verter inputs. AC-grounding the center tap will generate the
differential signal swing across the secondary winding. Con-
sider a step-up transformer to take advantage of a signal
amplification without the introduction of another noise source.
Furthermore, the reduced signal swing from the source may
lead to an improved distortion performance.
The differential input configuration may provide a notice-
able advantage of achieving good SFDR performance over
a wide range of input frequencies. In this mode, both inputs
of the ADS822 and ADS825 see matched impedances, and
the differential signal swing can be reduced to half of the
swing required for single-ended drive. Figure 5 shows the
schematic for the suggested transformer-coupled interface
circuit. The component values of the R-C low-pass may be
optimized depending on the desired roll-off frequency. The
resistor across the secondary side (RT) should be calculated
using the equation RT = n2 • RG to match the source impedance
(RG) for good power transfer and Voltage Standing Wave Ratio
(VSWR).
REFERENCE OPERATION
Figure 6 depicts the simplified model of the internal refer-
ence circuit. The internal blocks are the bandgap voltage
reference, the drivers for the top and bottom reference, and
2Vp-p
NOTE: R
F
= R
IN
, G = –1
V
IN
R
2
200Ω
R
1
1kΩ
ADS822
ADS825
R
S
50Ω
10pF
0.1µF
IN
IN
CM (+2.5)
INT/EXT
R
F
499Ω
R
IN
499Ω
V
CM
= +1.25V
REFB
(+1.5V) REFT
(+3.5V)
1/2
OPA2681
1/2
OPA2681
R
F
1kΩ
50Ω0.1µF
0.1µF
RSEL +V
S
+5V
+5V
V
IN
IN
IN CM
22Ω
22Ω
47pF
R
T
47pF
+10µF0.1µF
INT/EXTRSEL
+5V
ADS822
ADS825
1:n
0.1µF
R
G
ADS822
REFT ByT CM ByB REFB
Bypass Capacitors: 0.1µF || 2.2µF each
Bandgap Reference and Logic
VREF
400Ω400Ω400Ω400Ω
+1+1
+VS
50kΩ50kΩ
INT/EXTRSEL
11
®
ADS822, ADS825
the resistive reference ladder. The bandgap reference circuit
includes logic functions that allows setting the analog input
swing of the ADS822 and ADS825 to either a 1Vp-p or
2Vp-p full-scale range simply by tying the RSEL pin to a
Low or High potential, respectively. While operating the
ADS822 in the external reference mode, the buffer amplifi-
ers for the REFT and REFB are disconnected from the
reference ladder.
As shown, the ADS822 and ADS825 have internal 50kΩ
pull-up resistors at the range select pin (RSEL) and refer-
ence select pin (INT/EXT). Leaving these pins open config-
ures the ADS822 and ADS825 for a 2Vp-p input range and
external reference operation. Setting the ADS822 and
ADS825 up for internal reference mode requires bringing
the INT/EXT pin Low.
The reference buffers can be utilized to supply up to 1mA
(sink and source) to external circuitry. The resistor ladders
of the ADS822 and ADS825 are divided into several seg-
ments and have two additional nodes, ByT and ByB, which
are brought out for external bypassing only (see Figure 6).
To ensure proper operation with any reference configura-
tions, it is necessary to provide solid bypassing at all refer-
ence pins in order to keep the clock feedthrough to a
minimum. All bypassing capacitors should be located as
close to their respective pins as possible.
The common-mode voltage available at the CM pin may be
used as a bias voltage to provide the appropriate offset for
the driving circuitry. However, care must be taken not to
appreciably load this node, which is not buffered and has a
high impedance. An alternative way of generating a com-
mon-mode voltage is given in Figure 7. Here, two external
precision resistors (tolerance 1% or better) are located
between the top and bottom reference pins. The common-
mode voltage, CMV, will appear at the midpoint.
EXTERNAL REFERENCE OPERATION
For even more design flexibility, the internal reference can
be disabled and an external reference voltage be used. The
utilization of an external reference may be considered for
applications requiring higher accuracy, improved tempera-
ture performance, or a wide adjustment range of the
converter’s full-scale range. Especially in multichannel
applications, the use of a common external reference has the
benefit of obtaining better matching of the full-scale range
between converters.
The external references can vary as long as the value of the
external top reference REFTEXT stays within the range of
(VS – 1.25V) and (REFB + 0.8V), and the external bottom
reference REFBEXT stays within 1.25V and (REFT – 0.8V)
(See Figure 8).
DIGITAL INPUTS AND OUTPUTS
Clock Input Requirements
Clock jitter is critical to the SNR performance of high-speed,
high-resolution A/D converters. Clock jitter leads to aperture
jitter (tA), which adds noise to the signal being converted. The
ADS822 and ADS825 samples the input signal on the rising
edge of the CLK input. Therefore, this edge should have the
lowest possible jitter. The jitter noise contribution to total
FIGURE 8. Configuration Example for External Reference Operation.
FIGURE 7. Alternative Circuit to Generate CM Voltage.
REFT
+3.5V
ADS822
ADS825
CMV
+2.5V
REFB
+1.5V
R
1
1.6kΩR
2
1.6kΩ
0.1µF0.1µF
ADS822
ADS825
IN
IN
INT/EXT
REFT ByT GND ByB REFB
4 x 0.1µF || 2.2µF
External Top Reference
REFT = REFB +0.8V to +3.75V
+VS
BA
RSEL GND
+5V
External Bottom Reference
REFB = REFT –0.8V to +1.25V
V
IN
A - Short for 1Vp-p Input Range
B - Short for 2Vp-p Input Range (Default)
CMV
+2.5V
DC
12
®
ADS822, ADS825
SNR is given by the following equation. If this value is near
your system requirements, input clock jitter must be reduced.
where: ƒIN is input signal frequency
tA is rms clock jitter
Particularly in undersampling applications, special consider-
ation should be given to clock jitter. The clock input should
be treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should
have 50% duty cycle (tH = tL), along with fast rise and fall
times of 2ns or less. The clock input of the ADS825 can be
driven with either 3V or 5V logic levels. Using low-voltage
logic (3V) may lead to improved AC performance of the
converter.
Digital Outputs
The output data format of the ADS822 and ADS825 are in
positive Straight Offset Binary code (see Tables I and II).
This format can easily be converted into the Binary Two’s
Complement code by inverting the MSB.
It is recommended to keep the capacitive loading on the data
lines as low as possible (≤ 15pF). Higher capacitive loading
will cause larger dynamic currents as the digital outputs are
changing. Those high current surges can feed back to the
analog portion of the ADS822 and ADS825 and affect the
performance. If necessary, external buffers or latches close
to the converter’s output pins may be used to minimize the
capacitive loading. They also provide the added benefit of
isolating the ADS822 and ADS825 from any digital noise
activities on the bus coupling back high frequency noise.
Digital Output Driver (VDRV)
The ADS822 features a dedicated supply pin for the output
logic drivers, VDRV, which is not internally connected to
the other supply pins. Setting the voltage at VDRV to +5V
or +3V, the ADS822 and ADS825 produce corresponding
logic levels and can directly interface to the selected logic
family. The output stages are designed to supply sufficient
current to drive a variety of logic families. However, it is
recommended to use the ADS822 and ADS825 with +3V
logic supply. This will lower the power dissipation in the
output stages due to the lower output swing and reduce
current glitches on the supply line which may affect the AC-
performance of the converter. In some applications, it might
be advantageous to decouple the VDRV pin with additional
capacitors or a pi-filter.
GROUNDING AND DECOUPLING
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multilayer PC boards are recommended
for best performance since they offer distinct advantages
like minimizing ground impedance, separation of signal
layers by ground layers, etc. The ADS822 and ADS825
should be treated as analog components. Whenever possible,
the supply pins should be powered by the analog supply.
This will ensure the most consistent results since digital
supply lines often carry high levels of noise which otherwise
would be coupled into the converter and degrade the achiev-
able performance. All ground connections on the ADS822
and ADS825 are internally joined together obviating the
design of split ground planes. The ground pins (1, 16, 26)
should directly connect to an analog ground plane which
covers the PC board area around the converter. While
designing the layout, it is important to keep the analog signal
traces separated from any digital lines to prevent noise
coupling onto the analog signal path. Due to their high
sampling rates, the ADS822 and ADS825 generate high
frequency current transients, and noise (clock feedthrough)
that are fed back into the supply and reference lines. This
requires that all supply and reference pins are sufficiently
bypassed. Figure 9 shows the recommended decoupling
scheme for the ADS822 and ADS825. In most cases, 0.1µF
ceramic chip capacitors at each pin are adequate to keep the
impedance low over a wide frequency range. Their effec-
tiveness largely depends on the proximity to the individual
supply pin. Therefore, they should be located as close to the
supply pins as possible. In addition, a larger bipolar capaci-
tor (1µF to 22µF) should be placed on the PC board in
proximity of the converter circuit.
+FS –1LSB (IN = +3V, IN = +2V) 11 1111 1111
+1/2 Full Scale 11 0000 0000
Bipolar Zero (IN = IN = CMV) 10 0000 0000
–1/2 Full Scale 01 0000 0000
–FS (IN = +2V, IN = +3V) 00 0000 0000
STRAIGHT OFFSET BINARY
DIFFERENTIAL INPUT (SOB)
TABLE II. Coding Table for Differential Input Configuration
and 2Vp-p Full-Scale Range.
+FS –1LSB (IN = REFT) 11 1111 1111
+1/2 Full Scale 11 0000 0000
Bipolar Zero (IN = CMV) 10 0000 0000
–1/2 Full Scale 01 0000 0000
–FS (IN = REFB) 00 0000 0000
SINGLE-ENDED INPUT STRAIGHT OFFSET BINARY
(IN = CMV) (SOB)
TABLE I. Coding Table for Single-Ended Input Configura-
tion with IN Tied to the Common-Mode Voltage
(CMV).
JitterSNR trmssignaltormsnoise
IN A
=ƒ
20 1
2
log π
