This is information on a product in full production.
February 2015 DocID023206 Rev 4 1/20
VNLD5090-E
OMNIFET III fully protected low-side driver
Datasheet
-
production data
Features
•Automotive qualified
•Drain current: 13 A
•ESD protection
•Overvoltage clamp
•Thermal shutdown
•Current and power limitation
•Very low standby current
•Very low electromagnetic susceptibility
•In compliance with the 2002/95/EC European
directive
•Open drain status output
Description
The VNLD5090-E is a monolithic device made
using STMicroelectronics
®
VIPowe r
®
technology,
intended for driving resistive or inductive loads
with one side connected to the battery. Built-in
thermal shutdown protects the chip from
overtemperature and short-circuit. Output current
limitation protects the device in an overload
condition. In case of long duration overload, the
device limits the dissipated power to a safe level
up to thermal shutdown intervention.Thermal
shutdown, with automatic restart, allows the
device to recover normal operation as soon as a
fault condition disappears. Fast demagnetization
of inductive loads is achieved at turn-off.
Type V
clamp
R
DS(on)
I
D
VNLD5090-E 41 V 90 mΩ25 A
SO-8
Table 1. Devices summary
Package Order codes
Tube Tape and reel
SO-8 VNLD5090-E VNLD5090TR-E
www.st.com
Contents VNLD5090-E
2/20 DocID023206 Rev 4
Contents
1 Block diagrams and pins configurations . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Elect rical char acteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 ECOPACK
®
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3 SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DocID023206 Rev 4 3/20
VNLD5090-E List of tables
3
List of tables
Table 1. Devices summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Suggested connections for unused and n.c. pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. PowerMOS section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Source drain diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 8. Input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 9. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 10. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 11. Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 13. SO-8 thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 14. SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 15. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
List of figures VNLD5090-E
4/20 DocID023206 Rev 4
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Configuration diagrams (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Maximum demagnetization energy (V
CC
= 16 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. SO-8 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . 13
Figure 9. SO-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Thermal fitting model of a LSD in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. SO-8 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DocID023206 Rev 4 5/20
VNLD5090-E Block diagrams and pins configurations
19
1 Block diagrams and pins configurations
Figure 1. Block diagram
Table 2. Pin function
Name Function
IN
1,2
/VSUPPLY
1,2
Voltage controll ed input pin with hysteresi s , CMOS compatible. They contr ols
output switch state
DRAIN
1,2
PowerMOS drain
SOURCE
1,2
PowerMOS source and ground reference for the control section
STATUS
1,2
Open drain digital diagnostic pin
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Block diagrams and pins configurations VNLD5090-E
6/20 DocID023206 Rev 4
Fig ure 2. Cu rrent and voltage conventions
Figure 3. Configuration diagrams (top view)
Table 3. Suggested connections for unused and n.c. pins
Connection / pin STATUS
1,2
N.C. INPUT
1,2
Floating X
(1)
1. X: do not care.
XX
To ground Not allowed X Through 10 kΩ resistor
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DocID023206 Rev 4 7/20
VNLD5090-E Electical specifications
19
2 Electical specifications
2.1 Absolute maximum ratings
S tressing the device above the rating listed in the Table 4 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
2.2 Thermal data
Ta ble 4. Absolute maximum ratings
Symbol Parameter Value Unit
SO-8
V
DS
Drain-source voltage (V
IN
= 0 V) Internally clamped V
I
D
DC drain current Internally limited A
-I
D
Reverse DC drain current 12.5 A
I
S
DC supply current -1 to 10 mA
I
IN
DC input current -1 to 10 mA
I
STAT
DC status current -1 to 10 mA
V
ESD1
Electrostati c discharge
(R
= 1.5 kΩ; C
= 100 pF)
– DRAIN
– SUPPLY, INPUT, STATUS 5000
4000
V
V
ESD2
Electrostatic discha rge on outp ut pin only
(R
= 330 Ω, C
= 150 pF) 2000 V
T
j
Junction operating temperature -40 to 150 °C
T
stg
Storage temperature -55 to 150 °C
E
AS
Single pulse avalanche energy
(L = 1.1 mH; T
j
= 150 °C; R
L
= 0; I
OUT
= I
limL
)50 mJ
Table 5. Thermal data
Symbol Parameter Maximu m valu e Unit
SO-8
R
thj-amb
Thermal resistance junction-ambient 108 °C/W
Electical specifications VNLD5090-E
8/20 DocID023206 Rev 4
2.3 Electrical characteristics
Values specified in this section are for V
INx/SUPPLYx
= 4.5 V to 5.5 V, -40°C < T
j
< 150°C,
unless otherwise stated.
Table 6. Power MO S sec tion
Symbol Parameter Test conditions Min. Typ. Max. Unit
R
ON
ON-state resistance
I
D
= 1.6 A; T
j
= 25°C,
V
INx/SUPPLYx
= 5 V 90
mΩ
I
D
= 1.6 A; T
j
= 150°C,
V
INx/SUPPLYx
= 5 V 180
I
D
= 1.6 A; T
j
= 150°C,
V
INx/SUPPLYx
= 4.5 V 190
V
CLAMP
Drain-source clamp voltage V
IN
= 5 V; I
D
= 1.6 A 414652 V
V
CLTH
Drain-source clamp
threshold volt ag e V
IN
= 0 V; I
D
= 2 mA 36 V
I
DSS
OFF-state outp ut current
V
IN
= 0 V; V
DS
= 13 V;
T
j
= 25°C 03
µA
V
IN
= 0 V; V
DS
= 13 V;
T
j
= 125°C 05
Table 7. Source drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
SD
Forward on voltage I
D
= 1.6 A; V
IN
= 0 V — 0.8 — V
Table 8. Input section
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
ISS
Supply c urre nt fro m in pu t pin
ON -sta te: V
INx/SUPPLYx
= 5 V;
V
DS
= 0 V 30 65 µA
OFF-state; T
j
= 25°C;
V
IN
= V
DRAIN
= 0 V; 10 25
V
ICL
Input clamp voltage I
S
= 1 m A 5.5 7 V
I
S
= -1 mA -0.7
V
INTH
Input threshold voltage V
DS
= V
IN
; I
D
= 1 mA 1 3.5 V
Table 9. Status pin
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
STAT
Status low output voltage I
STAT
= 1 mA 0.5 V
I
LSTAT
Status leaka ge current Normal operation;
V
STAT
= 5 V 10 µA
C
STAT
Status pin input capacitance Normal operation;
V
STAT
= 5 V 100 pF
DocID023206 Rev 4 9/20
VNLD5090-E Electical specifications
19
V
STCL
Status cl am p voltage I
STAT
= 1 mA 5.5 7 V
I
STAT
= -1 mA -0.7
Table 10. Switching characteristics
(1)
1. See Figure 5: Application schematic.
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(ON)
Turn-on delay time R
L
= 8.2 Ω; V
CC
= 13 V
(2)
2. See Figure 4: Switching characteristics.
—8—µs
t
d(OFF)
Turn-o f f del ay time R
L
= 8.2 Ω; V
CC
= 13 V
(2)
—3.4—µs
t
r
Rise time R
L
= 8.2 Ω; V
CC
= 13 V
(2)
—10—µs
t
f
Fall time R
L
= 8.2 Ω; V
CC
= 13 V
(2)
—2.7—µs
W
ON
Switching energy
losses at turn- on R
L
= 8.2 Ω; V
CC
= 13 V
(2)
—57—µJ
W
OFF
Switching energy
losses at turn- off R
L
= 8.2 Ω; V
CC
= 13 V
(2)
—14—µJ
Qg Total gate change V
INx/SUPPLYx
= 5 V 2 nC
Table 11. Protection and diagnostics
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
limH
DC short-circuit current V
DS
= 13 V;
V
INx/SUPPLYx
= 5 V 13 18 25 A
I
limL
Short-circuit current
during thermal cycling V
DS
= 13 V; T
R
< T
j
< T
TSD;
V
INx/SUPPLYx
= 5 V 8A
t
dlimL
Step response current
limit V
DS
= 13 V; V
input
= 5 V 44 µ s
T
TSD
Shutdown temperature 150 175 200 °C
T
R
Reset temperature T
RS
+ 1 T
RS
+ 5 °C
T
RS
Thermal reset of
STATUS 135 °C
T
HYST
Thermal hysteresis
(T
TSD
- T
R
)7°C
Table 9. Status pin (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Electical specifications VNLD5090-E
10/20 DocID023206 Rev 4
Figure 4. Switching characteristics
Table 12. Truth table
Conditions INPUT DRAIN STATUS
Normal op erat ion L
HH
LH
H
Current limitation L
HH
XH
H
Overtemperature L
HH
HH
L
Undervoltage L
HH
HX
X
DocID023206 Rev 4 11/20
VNLD5090-E Application information
19
3 Application information
Figure 5. Application schematic
3.1 MCU I/O protection
ST suggests to insert a resistor (R
prot
) in line to prevent the microcontroller I/O pins from
latching up
(a)
. The value of these resistors is a compromise between the leakage current of
microcontroller and the current required by the LSD I/Os (input levels compatibility) with the
latch-up limit of microcontroller I/Os:
Equation 1
Let:
•I
latchup
> 20 mA
•V
OHµC
> 4.5 V
•35 Ω ≤ R
prot
≤ 100 KΩ
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a. In case of negative transient on the drain pin.
0.7
I
latchup
-------------------- R
prot
V
OHμC
V
IH
–()
I
IH max
----------------------------------------≤≤
Application information VNLD5090-E
12/20 DocID023206 Rev 4
Then, the recommended value is R
prot
= 1 KΩ
Figure 6 shows the turn-off current drawn during the demagnetization.
Figure 6. Maximum demagnetization energy (V
CC
= 16 V)
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DocID023206 Rev 4 13/20
VNLD5090-E Package and PC board thermal data
19
4 Package and PC board thermal data
4.1 SO-8 thermal data
Figure 7. SO-8 PC board
Note: Layout condition of R
th
and Z
th
measurements (Board finish thickness 1.6 mm +/- 10%;
Board double layer; Board dimension 78 mm x 86 mm; Board Material FR4; Cu thickness
0.070 mm (front and back side); Thermal vias separation 1.2 mm; Thermal via diameter
0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm).
Figure 8.
SO-8 R
thj-amb
vs PCB copper area in open box free air condition
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Package and PC board thermal data VNLD5090-E
14/20 DocID023206 Rev 4
Figure 9. SO-8 thermal impedance junction ambient single pulse
Equation 2: pulse calculation formula
where δ
=
t
P
/T
Figure 10. Thermal fitting mode l of a LSD in SO-8
Note: The fitting model is a semplified thermal tool and is valid for transient evolutions where the
embedded protections (power limitation or thermal cycling during thermal shutdown) are not
triggered.
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DocID023206 Rev 4 15/20
VNLD5090-E Package and PC board thermal data
19
Table 13. SO-8 thermal parameters
Area/island (cm
2
) Footprint 2
R1 = R7 (°C/W) 0.8 0.8
R2 = R8 (°C/W) 2.7 2.7
R3 = R9 (°C/W) 1.5 1.5
R4 = R10 (°C/W) 32 25
R5 (°C/W) 36 20
R6 (°C/W) 35 27
C1 = C7 (W.s/°C) 0.00005 0.00005
C2 = C8 (W.s/°C) 0.001 0.001
C3 = C9 (W.s/°C) 0.01 0.01
C4 = C10 (W.s/°C) 0.02 0.02
C5 (W.s/°C) 0.1 0.15
C6 (W.s/°C) 2.5 3.5
Package and packing information VNLD5090-E
16/20 DocID023206 Rev 4
5 Package and packing information
5.1 ECOPACK
®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
5.2 SO-8 mechanical data
Figure 11. SO-8 package dimensions
GAPGCFT00145
DocID023206 Rev 4 17/20
VNLD5090-E Package and packing information
19
Table 14. SO-8 mechanical data
Symbol Millimeters
Min. Typ. Max.
A1.75
A1 0.10 0.25
A2 1.25
b0.28 0.48
c0.17 0.23
D
(1)
1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs
shall not exceed 0.15 mm in total (both side).
4.80 4.90 5.00
E 5.80 6.00 6.20
E1
(2)
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25 mm per side.
3.80 3.90 4.00
e1.27
h0.25 0.50
L0.40 1.27
L1 1.04
k0° 8°
ccc 0.10
Package and packing information VNLD5090-E
18/20 DocID023206 Rev 4
5.3 SO-8 packing information
Figure 12. SO-8 tube shipment (no suffix)
Figure 13. SO-8 tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base q.ty 100
Bulk q.ty 2000
Tube length (± 0 .5 ) 532
A3.2
B6
C (± 0.1) 0.6
C
B
A
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 12
Tape hole sp acing P0 (± 0.1) 4
Component spacing P 8
Hole diameter D ( + 0.1/-0) 1.5
Hole diameter D1 (min) 1.5
Hole position F (± 0.05) 5.5
Comp artment depth K (max) 4.5
Hole spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
Reel dimensions
All dimensio ns are in mm.
Base q.ty 2500
Bulk q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
DocID023206 Rev 4 19/20
VNLD5090-E Revision history
19
6 Revision history
Table 15. Document revision history
Date Revision Changes
16-May-2012 1 Initial release.
21-Jun-2012 2 Updated Figure 3: Configuration diagrams (top view)
13-Nov-2013 3
Updated Features list
Table 4: Absolute maximum ratings:
–-I
D
, E
AS
: updated valu es
Updated Table 5: Thermal data
Table 6: PowerMOS section:
–V
CLAMP
: updated parameter
Table 8: Input section:
–I
ISS
: updated maximum v alue
Table 10: Switching characteristics:
–W
ON
, W
OFF
: updated unit values
Updated Figure 5: Application schematic
Updated Section 3.1: MCU I/O protection
Added Chapter 4: Package and PC board thermal data
26-Feb-2015 4 Table 12: Truth table: removed “Output voltage < V
OL
” condition
VNLD5090-E
20/20 DocID023206 Rev 4
Please Read Carefully:
Informa tion in this do cument is prov ided solely in connec tion with ST products. STMic roelect ronics NV and its subsidiari es (“ST”) reser ve the
right to mak e chang es, c or recti ons , modif ic ations or improv ement s, t o th is documen t, and the prod ucts an d servic es des crib ed he rein a t any
time, without notice.
All ST produ cts are sold purs uant to ST’s terms and conditions of sale.
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