107578627 - Agere Systems, Inc.

Data Sheet

February 1999

T7531A/T7536 16-Channel Programmable

Codec Chip Set

Features

■Single 5 V power supply operation

■Per-channel programmable transmit gain

— 19.4 dB range, better than 0.01 dB steps

■Per-channel programmable receive gain

— 25.4 dB range, better than 0.01 dB steps

■Per-channel programmable internal balance

networks

■Programmable termination impedances

■Per-channel programmable µ-law, A-law, or linear

PCM output

■Automatic gain calibration

■Advanced board- and self-test capability

■Programmable time-slot assignment

■Data rate of 2.048 MHz or 4.096 MHz

■Differential transmit amplifiers

■Single-ended or differential receive amplifiers

■Analog and digital loopbacks

■Sigma-delta converters with dither noise reduction

■Serial microcontroller control interface

■JTAG test port

General Description

The T7531A is a custom, 16-channel line card signal

processor which, together with a pair of custom

T7536 octal A/D and D/A converters, comprises a

low-cost, highly programmable voice codec that is

compatible with all worldwide POTS lines.

Transmit and receive gains and h ybrid balance coeffi-

cients are programmable per channel. Termination

impedance is programmable per chip set. These

functions, as well as time-slot assignment, calibra-

tion, and board test, are controlled via a microcontrol-

ler int er face.

The DSP engine in the T7531A can be used to test

the line card. When voice processing is not required,

the spare processing time can be allocated on a per-

line basis to a suite of user-controlled board-test rou-

tines. Providing inte llig ent boar d -te st functi ona lity at

the line-card level frees the s witch from having to per-

form test and erro r dia gno si s tasks.

5-3793.c (F)

Figure 1. System Block Diagram

T7536

OCTAL

A/D

D/A

T7536

OCTAL

A/D

D/A

T7531A

DIGITAL

SIGNAL

PROCESSOR

VTX (8)

VRP (8)

VRN (8)

VTX (8)

VRP (8)

VRN (8)

CK16

VRTX (8)

PCM

INTERFACE

MICROPROCESSOR

INTERFACE

2Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Table of Contents

Contents Page

Features ..................................................................... 1

General Description.................................................... 1

T7536 Description.................................................... 4

T7531A Descripti on ......... ...... ....... ...... ....... ...... ........ 5

Pin Information ........................................................... 7

Chip Set Functional Description............................... 12

Transmit Path......................................................... 12

Receive Path.......................................................... 13

Other Chip Set Functions....................................... 13

T7531A Functional Blocks..................................... 14

DSP Engine Timing................................................ 16

T7531A Program Structure.................................... 16

Control of the DSP Engine via the Microprocessor

Interface .............................................................. 17

The DSP Engine Time-Slot Information Tables..... 17

The DSP Engine ac Path Coefficient Table........... 17

The Time-Slot Control Word.................................. 18

Operations Performed by the DSP Engine at

T7531A Start -Up ........... ...... .................... ............ 18

Microprocessor Start-Up of the DSP Engine ......... 19

Powering Up a Time Slot in the T7531A................ 19

Disabling a Time Slot in the T7531A...................... 19

T7536 Powerup/Powerdown.................................. 19

Changing DSP RAM Space of an Active Time

Slot...................................................................... 20

DSP Engine Memory Requ irem ents................ ...... 20

T7531A Reset and Start-Up................................... 20

Hardware Reset..................................................... 20

Internal Reset......................................................... 21

Reset of the T7536 Devices................................... 21

Start-Up After Internal Reset.................................. 21

Autocalibration........................................................22

User Test Features................................................ 22

Self-Test and Board-Test Routines.........................22

Handling Precautions ......... ...... ....... ...... ................... 23

Absolute Maximum Ratings...................................... 23

Electrical Characteristics.......................................... 24

dc Characteristics .................................................. 24

Transmission Characteristics ................................... 25

Timing Characteristics.............................................. 29

Software Interfa ce ........ ................... ................... ...... 32

Applications...............................................................42

Outline Diagram........................................................ 43

68-Pin PLCC.................... ................... ................... 43

Ordering Information................................................. 44

Figures Page

Figure 1. System Block Diagram................................ 1

Figure 2. Block Diagram of T7536 Octal Converter.... 4

Figure 3. Block Diagram of One T7536 Analog

Channel .......................................................4

Figure 4. T7531A Block Diagram ................................5

Figure 5. T7531A Digital ac Path ................................6

Figure 6. Control, PCM, and Octal Interfaces .............6

Figure 7. T7536 68-Pin PLCC ....................................7

Figure 8. T7531A 68-Pin PLCC ..................................8

Figure 9. Timing Characteristics of PCM Interface

Assuming 2.048 MHz SCK Rate ...............30

Figure 10. Timing Diagram for Microprocessor

Write/Read to/from the DSP on the

Control Interface ......................................31

Figure 11. 16-Channel Line Card Solution ...............42

Lucent Technologies Inc. 3

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Table of Contents

Tables Page

Table 1. T7536 Pin Descriptions ............................................................................................................................. 9

Table 2. T7531A Pin Descriptions ........................................................................................................................ 10

Table 3. Active Time-Slot Spacing in a PCM Bus Frame ...................................................................................... 15

Table 4. DSP Engine RAM Map for Channel_0 ac P a th Coefficients ................................................................... 17

Table 5A. Bit Maps for DSP Engine Time-Slot Control Word .............................................................................. 18

Table 5B. Bit Map for Default Per-Board Coefficient Tables ................................................................................... 18

Table 6. DSP Engine RAM Map for Time-Slot Information Table 0 ....................................................................... 18

Table 7. Summary of Microprocessor Commands for Control of T7531A Data Processing ................................. 20

Table 8. Digital Interface ....................................................................................................................................... 24

Table 9. Analog Interface ...................................................................................................................................... 24

Table 10. T7536 Power Dissipation ...................................................................................................................... 25

Table 11. T7531A Power Dissipation .................................................................................................................... 25

Table 12. Gain and Dynamic Range ..................................................................................................................... 25

Table 13. Noise (per Channel) .............................................................................................................................. 27

Table 14. Distortion and Group Delay .................................................................................................................. 28

Table 15. Crosstalk ............................................................................................................................................... 28

Table 16. PCM Interface Timing ............................................................................................................................ 29

Table 17. Serial Control Port Timing ...................................................................................................................... 31

Table 18. DSP Engine RAM Memory Map ........................................................................................................... 32

Table 19. T7531A Time-Slot Assignment Memory Map ........................................................................................ 34

Table 20A. Bit Map for T7531A Time-Slot Assignment Registers at 0x1400—0x140F ........................................ 34

Table 20B. Bit Map for CTZ Disable and Null Channel ......................................................................................... 34

Table 21. T7531A Channel Register Memory Map for T7536 Device 0 ................................................................35

Table 22. T7531A Channel Register Memory Map for T7536 Device 1 ................................................................35

Table 23. Bit Map for T7536 Powerup/Powerdown Registers at 0x1500—0x1507 and 0x1540—0x1547 ............ 35

Table 24. Bit Map for T7536 Channel Control Register 1 at 0x1508—0x150F and 0x1548—0x154F .................. 36

Table 25. T7536 Control Register 1: Transmit Gain .............................................................................................. 36

Table 26. T7536 Control Register 1: Analog Termination Impedance ................................................................... 36

Table 27. T7536 Control Register 1: Digital Loopback .......................................................................................... 37

Table 28. Bit Map for T7536 All Channel Test Register at 0x1510 and 0x1550 .................................................... 37

Table 29. Bits 3:0 of T7536 All Channel Test Register at 0x1510 and 0x1550 ...................................................... 37

Table 30. Bit Map for T7536 Channel Control Register 2 at 0x1518—0x151F and 0x1558—0x155F .................. 38

Table 31. T7536 Control Register 2: Receive Gain ............................................................................................... 38

Table 32. T7531A Control Register Map ............................................................................................................... 38

Table 33. Bits 15:8 of T7531A Board Control Word 1 at 0x1FFE ......................................................................... 39

Table 34. Bits 7:0 of T7531A Board Control Word 1 at 0x1FFE ........................................................................... 39

Table 35. Bits 15:9 of T7531A Board Control Word 2 at 0x1FFC ......................................................................... 40

Table 36. Bits 8:0 of T7531A Board Control Word 2 at 0x1FFC ........................................................................... 40

Table 37. Bits 15:0 of T7531A Board Control Word 3 at 0x1FFA ......................................................................... 40

Table 38. Bits 15:0 of T7531A Board Control Word 4 at 0x1FF8 ......................................................................... 40

Table 39. Bits 15:0 of T7531A Board Control Word 5 at 0x1FF6 ......................................................................... 40

Table 40. Bits 15:0 of T7531A Reset of Microprocessor Commands at 0x7FFF ................................................. 40

Table 41. DSP Engine ROM Memory Map ........................................................................................................... 41

4Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

General Description (continued)

T7536 Description

The T7536 bloc k diagram is shown in Figure 2. Each of its eight channels consists of an antialias filter, sigma-delta

A/D and D/A converters, reconstruction and smoothing filters, termination impedance synthesis, and selectable

gain. The digital oversampled data is multiplexed onto a serial data port designed to interface with the T7531A.

Another serial interf ace accepts control data from the T7531A f or activating the various gain settings, self-test, and

powerdown modes. This chip also contains a precision voltage reference. It is packaged in a 68-pin PLCC.

5-3794.b (F)

Figure 2. Block Diagram of T7536 Octal Converter

5-3796.d (F)

* Antialiasing filter.

Figure 3. Block Diagram of One T7536 Analog Channel

8-CHANNEL

A/D D/A

ANALOG HYBRI D

TERMINATION

VOLTAGE

REFERENCE

OVERSAMPLED

DATA

INTERFACE

CONTROL

INTERFACE

VTX[7:0]

VRTX[7:0]

VRP[7:0]

VRN[7:0]

VDDA

VSSA

VDD

VSS

OSDX[1:0]

OSDR[1:0]

OSCK

OSFS

CDO

CDI

CCS

RSTB

GAIN AAF* ∑-∆

A/D

GAIN

SUM GAIN

V REFERENCES

RECEIVE

FILTER D/A

D/A

VTX

VRP

VRN

1.024 MHz

VRTX

DIGITAL LOOPBACK

Lucent Technologies Inc. 5

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

General Description (continued)

T7531A Description

As shown in Figure 4, the T7531A contains a digital signal processor (DSP) engine surrounded by a customized

input/output frame. The I/O frame performs the µ-law or A-law conversion as well as the decimation and interpola-

tion functions needed to interface the sigma-delta bit streams to the digital signal processor engine. The sigma-

delta converters operate at a 1.024 MHz sample rate, while the signal processor operates at 16 ksamples/s. A ke y

function of the I/O frame is to control the timing of the digital data going to the signal processor so that group dela y

is minimiz ed.

The I/O frame also contains an integrated phase-locked loop which synthesizes all the required internal clocks for

the chip set.

The microcontroller interface is used to download the gain and balance network settings, powerup/powerdown

commands, time-slot assignments, digital loopback settings, and commands f or the T7536 octal chips. This chip is

packaged in a 68-pin PLCC.

5-3795.c (F)r03

Figure 4. T7531A Block Diagram

PLL

CLOCK

SYNTHESIZER

JTAG

SYST EM PCM INTERFACE

DATA TRANSFER

µ/A-LAW CONVERTER

MICRO-

PROCESSOR

CONTROL

INTERFACE

DSP

ROM

DSP

RAM

DIGITAL

SIGNAL

PROCESSING

ENGINE

DECIMATOR INTERPOLATOR

TSA

T7536 CONTROL INTERFACET7536 OVERSAMP LED INTER FACE

UPCK

UPDI

UPDO

TSTCLK

VDD

VSS

HDS

UPCS

HIGHZB

RSTB

T_SYNC

TEST

OSDX/R[3:0]

OSCK

OSFS

CDO

CCS0

CCS1

CDI

TDI

TCK

TMS

FVSS

TDO

FILT2

FILT1

FVDD

CK16

STSXB

SDX

SDR

SCK

SFS

6Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

General Description (continued)

T7531A Description (continued)

5-3797.b (F)

Figure 5. T7531A Digital ac Path

5-4229.b (F)

Figure 6. Control, PCM, and Octal Interfaces

µ/A-LAW

LINEAR

RECV

FILTER REL

RDG INTER-

POLATOR DIGITAL

∑-∆

BALANCE

FILTER

LINEAR

µ/A-LAW XMT FILTER REL

TGD ∑DECIMATOR

÷ 64

1.024 MHz

8 kHz

PCMRX

8 kHz

PCMTX 1.024 MHz

ABS

RDG

ABS

TGD

CTZ

FILTER

∑

OSFS

OSCK

OSDR0

OSDR1

OSDX0

OSDX1

CDO

CDI

CODEC 0

T7536

DSP

T7531A

8 kHz SYNC

4 MHz CLOCK

4 CH RX DATA

4 CH TX DATA

CHIP SELECT

CONTROL REGISTER

UPCK

UPCS

UPDI

UPDO

CLOCK

CHIP SELECT

CONTROL REGISTER IN

CONTROL REGISTER OUT

SCK

SFS

SDR

SDX

STSXB DATA TRANSMIT

CLOCK

FRAME SYNC

DATA RECEIVE

BACKPLANE

CODEC 1

T7536

CHIP SELECT

OSDX2

OSDR2

OSDR3

OSDX3

PCM

INTERFACE

CONTROL

INTERFACE

OCTAL

INTERFACE

OSDX2

OSDR2

OSDR3

OSDX3

CDO

CDI

OSCK

OSFS

4 CH RX DATA

4 CH TX DATA

OSFS

OSCK

OSDR0

OSDR1

OSDX0

OSDX1

CDI

CDO

CCS0

CCS1

CCS0

CCS1

DRIVER ENABLE

MICRO-

PROCESSOR

PCM

BUS

Lucent Technologies Inc. 7

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Pin Information

5-4230.b (F)

Figure 7. T7536 68-Pin PLCC

VRTX3

VRP3

VRN3

VSSA

VRN2

VRTX2

VTX2

VDDA

VRP2

VTX1

VRTX1

VRP1

VSSA

VRN1

VRN0

VRP0

VRTX0

T7536

VRTX4

VRP4

VRN4

VSSA

VRN5

VRTX5

VTX5

VDDA

VRP5

VTX6

VRTX6

VRP6

VSSA

VRN6

VRN7

VRP7

VRTX7

VDDA

VTX0

TEST

OSFS

OSCK

OSDR0

OSDX0

OSDR1

OSDX1

VSSD

VDDA

VTX7

VDDA

CDO

CCS

RSTB

CDI

VDDA

VTX4

VSSA

VDDD

VTX3

8Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Pin Information (continued)

5-4231.b (F)

Figure 8. T7531A 68-Pin PLCC

VSS

VDD

CDI

CCS0

CDO

T_SYNC

VDD

CCS1

VSS

RSTB

HIGHZB

CK16

TEST

VDD

VSS

T7531A

VSS

VDD

UPDO

UPDI

UPCS

UPCK

VSS

VDD

STSXB

SDX

SDR

SCK

SFS

VDD

VSS

SCKSEL

VSS

VDD

OSDX3

OSDX0

OSDR0

VDD

VSS

OSDX2

OSDR2

OSDR3

VSS

OSFS

OSCK

OSDR1

OSDX1

TCK

VSS

VDD

FVDD

FILT1

FVSS

FILT2

FILT3

VSS

VDD

VSS

VDD

TDI

TDO

TSTCLK

TMS

Lucent Technologies Inc. 9

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Pin Information (continued)

Table 1. T7536 Pin Descriptions

Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; Id indicates a pull-do wn

device is included on this lead, Iu indicates a pull-up device is included on this lead.

Number Name Type Name/Function

9, 17, 19, 27,

43, 51, 53, 61 VTX[7:0] AI Analog Input. Transmit signal voltage to be encoded.

10, 16, 20, 26,

44, 50, 54, 60 VRTX[7:0] AI Transmit Reference Voltage. +2.4 V reference. Each pin must have a

separate supply associated with the corresponding VTX pin.

11, 15, 21, 25,

45, 49, 55, 59 VRP[7:0] AO Noninverting Receive Output. This pin can drive high-impedance loads

either differentially or single ended. It is the complement of the VRN output.

12, 14, 22, 24,

46, 48, 56, 58 VRN[7:0] AO In verting Receive Output. This pin can drive high-impedance loads either

diff erentially or single ended. It is the complement of the VRP output.

8, 18, 28, 38,

42, 52, 62 VDDA —+5 V Analog Power Supply. Power supply decoupling capacitor (0.1 µF)

should be connected from each VDDA pin to analog ground. Capacitors

should be located as close as possible to the device pins.

13, 23, 31,

47, 57 VSSA —Analog Ground.

63 VDDD —+5 V Digital Power Su pply. Decouple with a 0.1 µF capacitor to digital

ground.

SSD —Digital Ground.

5, 4 OSDX[1:0] CO Oversampled Transmit Data. Four channels of 1.024 MHz Σ-∆ transmit

data is transmitted to the T7531A through each of these pins. The data rate

is 4.096 MHz.

6, 3 OSDR[1:0] CI Oversampled Receive Data. F our channels of 1.024 MHz Σ-∆ re ce ive

data is received from the T7531A on each of these pins. The data rate is

4.096 MHz.

2OSCKCI

Interface Clock. The 4.096 MHz clock that enters this pin from the T7531A

serves as the bit clock for all the oversampled data transmission between

this chip and the T7531A. This is the master clock input for the T7536.

1OSFSCI

Interface Frame Sync. This signal serves as the frame sync for the over-

sampled data interface between the T7536 and the T7531A.

66 CDI CI Contr ol Data Interface Input. The T7531A sends control register address

and data to the T7536 through this pin. One address byte and one data

byte are accepted each time CCS is toggled.

64 CDO CO Control Data Interface Output. Control register contents are clocked out

through this pin.

65 CCS CI Control Interface Chip Select (Active-Low). This active-low input

enables the control interface.

68 RSTB TIuReset (Active-Low). This input must be pulled high for normal operation.

When pulled momentarily low (at least 1 µs) while OSCK is active, all pro-

grammable registers in the device are reset to the states specified under

powerup initialization. This pin has an internal pull-up resistor.

67 TEST TIdTest. This pin is for factory test purposes only. Connect to VDDD for normal

operation. This pin has an internal pull-down resistor.

29, 30, 32—37,

39—41 NC — No Connect. No conne ct ion to chip. These p in s can be us ed as lo gi c l eve l

tie points.

10 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Pin Information (continued)

Table 2. T7531A Pin Descriptions

Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; Iu indicates a pull-up

device is included on this lead.

Number Name Type Name/Function

22 UPDI TI Control Data Interface Input. The microcontroller sends control register

address and data to the T7531A through this pin.

23 UPDO TO Control Data Interface Output. The microcontroller receives control regis-

ter contents from this pin. Inactive state is high impedance.

20 UPCK TI Control Data Interface Clock. Bit clock for the control interface. Speed is

limited to 4.096 MHz.

21 UPCS TI Control Interface Chip Select (Active-Low). This active-low input enables

the control interface.

38, 40,

31, 33 OSDX[3:0] CI Oversampled Transmit Data. Four channels of 1 Msamples/s Σ-∆ transmit

data are received from the T7536 chips through each of these pins. The data

rate is 4.096 MHz.

37, 39,

30, 32 OSDR[3:0] CO Oversampled Receive Data. Four channels of 1 Msamples/s Σ-∆ receive

data is transmitted to the T7536 chips on each of these pins. The data rate is

4.096 MHz.

34 OSCK CO 4.096 MHz Clock. Clock for data transfer to/from T7536 chips.

35 OSFS CO Oversampling Sync. 8 kHz synchronization pulse for data transfer

to/from T7536 chip s.

4FILT1—

Filter. External filter pin for the clock synthesizer block. Connect a 6.8 kΩ,

10% resistor in series with a 0.1 µF, 20% capacitor to ground. Placement of

these components is not as critical as power supply decoupling capacitor

placement.

5FILT2—

Filter. External filter pin for the clock synthesizer block. Connect a 6.8 kΩ,

10% resistor in series with a 0.1 µF, 20% capacitor to ground. Placement of

these components is not as critical as power supply decoupling capacitor

placement.

7FILT3—

Filter. External filter pin for the clock synthesizer’ s v oltage regulator . Connect

a 0.1 µF, 20% capacitor to ground.

3FV

DD —Synthesizer VDD. Power supp ly for clock synthesizer block.

6FV

SS —Synthesizer Ground. Ground connection for the clock synthesizer block.

17 STSXB TO Backplane Drive Enable (Active-Low). Active when SDX is transmitting

valid data; high impedance otherwise. This pin provides an enable signal for

a backplane line driver.

13 SCK TI Master Clock Input. This is the bit clock used to shift data into and out of the

SDR and SDX pins. It is the input to the clock synthesizer and is used to gen-

erate all internal clocks. Rate is 4.096 MHz.

10 SCKSEL TIuMaster Clock Select Input. A logic low selects the 2.048 MHz SCK. A logic

high selects the 4.096 MHz SCK. An internal pull-up device is included, pro-

viding 4.096 MHz SCK operation with no external connections.

15 SDR TI Receive PCM Input. The data on this pin is shifted into the T7531A on the

falling edges of SCK. Data is only entered for valid time slots as defined in

the TSA registers.

Lucent Technologies Inc. 11

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Pin Information (continued)

Table 2. T7531A Pin Descriptions (continued)

Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; Iu indicates t hat a pull-up

device is included on this lead.

Number Name Type Name/Function

16 SDX TO Transmit PCM Output. This pin remains in the high-impedance state

except during the transmit time slots as defined in the TSA registers.

Data is shifted out on the rising edge of SCK.

14 SFS TI Frame Sync. Active-high pulse or square wave with an 8 kHz pulse

repetition rate. The rising edge defines the start of the transmit and

receive frames.

50 CDO CO T7536 Control Data Output. Control register information for the T7536

chips. Data is valid only when either CCS0 or CCS1 is low.

47 CDI TIuT7536 Control Data Input. Control register information from the T7536

chips. Data is valid only when either CCS0 or CCS1 is low. An internal

pull-up device is provided.

49, 48 CCS[1:0] CO Control Interface Chip Select. These active-low outputs select one of

the associated T7536 chips.

67 TCK TI JTAG Common Test Clock. Rate ≤20 MHz.

64 TDI TIuJTAG Serial Data Input. A pull-up device is provided.

65 TDO TO JTAG Ser ial Dat a Outp ut.

66 TMS TIuJTAG Mode Select. A pull-up device is provided.

55 HIGHZB TIu3-State Control Pin (Active-Low). When pulled low, the device output

pins go into a high-impedance state. A pull-up device is provided.

56 TEST CIuTest Mode Input (Active-Low). This input allows bypass of cloc k synthe-

sizer and uses TSTCLK to drive the chip. A pull-up device is provided.

57 CK16 CO 16 MHz Clock Output. 16 MHz clock output (50% duty cycle).

68 TSTCLK CI Test Clock. Test mode 98.304 MHz clock input for bypass of clock syn-

thesizer.

26, 27, 43, 44,

60, 61 NC — No Connect. Do not make any connections to thes e pins.

51 T_SYNC CIuTest Sync (Active-Low). Used for f actory testing. Do not make any con-

nection to this pin. A pull-up device is provided.

54 RSTB TIuReset (Active-Low). A logic low initiates reset. A pull-up device is pro-

vided.

2, 9, 12, 18, 24,

29, 41, 46, 52,

58, 63

VDD —+5 V Digital P o wer Supply. P ower supply decoupling capacitors (0.1 µF)

should be connected from each VDD pin to ground. Capacitors should be

located as close as possible to the device pins.

1, 8, 11, 19, 25,

28, 36, 42, 45,

53, 59, 62

VSS —Digital Ground.

1212 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Chip Set Functional Description

Transmit Path

Antialias Filter and Σ-∆ Converter

The line interf ace circuit must provide a transmit signal,

VTX, and a ref e rence voltage, VRTX, which is the dc

voltage of the VTX signal for that channel.

The input signal goes into a programmable-gain ampli-

fier . The signal is then passed through an antialias filter

followed by a Σ-∆ A/D converter. The Σ-∆ converter

operates at 1.024 MHz. The processed output signals

are multiplexed into two groups of four channels each

onto output pins OSDX[1:0], each of which operates at

4.096 MHz.

A precision, on-chip voltage reference helps ensure

acc urate and highly stable tr ansmission levels .

It is important to understand the difference between

how the gain levels should be set in the T7536 and

how these levels would be set in a standard codec.

The T7536 is best thought of as a data acquisition sys-

tem, not a codec. Hybrid balance, fine gain adjust,

µ- or A-law coding, filtering, and equalization are done

after the A/D in the T7536 by the DSP processor in the

T7531A. The analog gain adjust taps should not be

used to set the absolute level at the PCM output. This

can be done using the DSP gain adjust taps. The ana-

log taps should be set so the signal at the input to the

A/D converter is as close as possible to the full-scale

input level of the A/D for the largest signal le vel that will

be present at the VTX input. This optimizes the

dynamic range of the A/D. The 0 dB gain tap should

thus be used if the maximum signal lev el is in the range

between 2.25 Vp-p and 3.2 Vp-p. The 3 dB tap should

be used for signals with a maximum signal level in the

range between 1.6 Vp-p and 2.25 Vp-p. The 6 dB tap

should be used for signals with a maximum signal lev el

in the range between 1.1 Vp-p and 1.6 Vp-p. Higher

gain levels should be used for signals with smaller

absolute levels.

The signal le v el to produce a 0 dBm0 lev el at the digital

transmit output of the T7531A is not a fix ed quantity as

explained above. For a line with a complex impedance

or an RX echo signal, extra headroom must be allowed

and the TX signal level must be set to account for the

headroom. In this specification, the largest possible

0 dBm0 level for the TX signal is assumed. This guar-

antees that the distortion specification will not be

exceeded for all practical 0 dBm signal levels. The larg-

est possible 0 dBm signal is one that has no headroom

for TX gain equalization. For the case of 0 dB transmit

gain, this level is found as:

(3.2 V/log –1 (3.15/20)) = 2.23 Vp-p.

This level is the worst-case 0 dBm0 level.

Decimator

The decimato r fil ter s out the high-f reque nc y co mpo-

nents and down-samples to 16 kHz. It also reorders the

16 channels of transmit signals into a sequence that is

determined by the time-slot assignment.

Digital Transmit Gain Adjustment

The transmit absolute and relative gains are specified

as 15-bit binary numbers representing their linear

magnitude. These gains default to 4000 Hex. This

equates to a 0 dB gain for the relative gain but equates

to a 1.65 dB gain for the absolute gain. For a 0 dB gain,

program the absolute gain for 34ED Hex. Gain can be

varied from minus infinity dB (off) (0000 Hex) to 6 dB

relative gain or 7.65 dB absolute gain (7FFF Hex).

The relative gain control allows TLP adjustment without

hybrid balance or termination coefficient modification.

Band Filtering

The bandpass filter in the transmit path remov es pow er

line and ringing frequencies, and eliminates most of the

signal energy at 4 kHz and above. This allows the

encoder to transmit the filtered signal at

8 ksamples/s, the worldwide standard.

The transmit filtering is implemented with a low-pass

filter, followed by a high-pass filter. The data samples

enter the filter at 16 ksamples/s. They are first low-pass

filtered to 3.4 kHz. After low-pass filtering, the sampling

rate is reduced to 8 ksamples/s. The samples are then

high-pass filtered to 300 Hz.

The low-pass fi lt e r al so serves as an equ al izer f o r co m -

plex termination impedance cases. A given set of

equalizer coefficients that modify this filter are required

for each complex termination impedance. These are

supplied in the user manual.

µ-Law, A-Law, and Linear PCM Modes

In the transmit path, the 8 ksamples/s PCM signal out-

put from the filter is processed prior to transmission

ov er the system interface. The 16-bit linear PCM signal

may be compressed according to either µ-law or A-law,

or transmitted as two consecutive 8-bit words. The

selection is programmable via the microprocessor

interface. Please note, when using A-law, a linear value

of 0 is always encoded as 7F.

Lucent Technologies Inc. 13

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Chip Set Functional Description

(continued)

Recei ve Path

In the receive direction, the signal received from the sys-

tem interface is converted to a 16-bit linear PCM signal.

Receive Path Filtering

The 16-bit linear PCM signal is filtered and interpolated

to 16 ksamples/s to meet the receive signal loss charac-

teristics. This filter smooths the data following interpola-

tion from 8 ksamples/s to 16 ksamples/s.

Digital Receive Gain

The receive absolute and relative gains are specified as

15-bit binary numbers representing their linear magni-

tude. These gains default to 4000 Hex. This equates to

a 0 dB gain for the relative gain but equates to a

–0.211 dB gain for the absolute gain. For a 0 dB gain,

program the absolute gain for 4193 Hex. Gain can be

v aried from minus infinity dB (0) (0000 Hex) to 6 dB rela-

tive gain or 5.8 dB absolute gain (7FFF Hex).

The relative gain control allows TLP adjustment without

hybrid balance or termination coefficient modification.

Interpolator and Digital Sigma-Delta Modulator

The sampling frequency of the receive signal from the

digital gain adjustment is increased from 16 kHz to

64 kHz by the interpolator, which removes most of the

high-frequency signal images above 8 kHz. The interpo-

lator also maps each of 16 time slots to the appropriate

line channel through the digital sigma-delta modulator.

The digital sigma-delta modulator converts the interpo-

lated signal to a 1.024 MHz bit stream which is then sent

to the T7536 device.

Decoder, Filters, and Receive Amplifier

Receive data enters the T7536 on pins OSDR[1:0] at

4.096 MHz; four channels are time-division multiplexed

onto each pin. The data is demultiplexed into eight indi-

vidual channels. The processed signal f or each channel

passes through s witched-capacitor D/A and reconstruct

filters, followed by a smoothing filter. A programmable

gain amplifier is included, follo wed by an output amplifier

capable of driving a 50 kΩ load to ±1.58 V single-ended

(relative to VOS) or ±3.16 V differential at peak over-

load. For single-ended operation, the load must be ac

coupled to VRP (or VRN).

Other Chip Set Functions

Voltage Reference

The T7536 has a precision on-chip voltage reference

which ensures accurate and highly stable transmission

levels.

Hybrid Balance

The hybrid balance function is provided as a d igital

block in the T7531A.

The T7531A implements a 9-tap FIR and a single-pole

IIR digital balance filter in which a replica of the echo is

digitally subtracted from the transmit plus near-end

echo signal. The coefficients are user programmable

on a per-line basis via the microprocessor interface.

Analog Termination Impedance Synthesis

Termination impedance matching is implemented to

maximize the power transfer capability at the loop inter-

face and to minimize signal reflections between the

transmit and receive paths.

The resistive component, implemented in the T7536

device, comprises a variable attenuated path between

VTX and VRP. The capacitive component is imple-

mented in the digital domain.

Analog termination impedance (ATI) is provided with 16

gain settings to match a voltage drive/current sense

line interface circuit with the following characteristics:

ZT = 2RP + GTX * GRX * AT

where ZT is the termination impedance in ohms,

RP= 82.5 Ω is the resistance of each protection resis-

tor, GTX is the SLIC transmit gain (300 V/A for the

L7585), GRX is the SLIC receive gain (2 for the L7585),

and AT is the T7536 f eedback gain. The polarity of the

AT gain is positive (positive v oltage s wing on VTX giv es

a positive voltage swing on VRP). The gain values and

the corresponding effective termination impedance are

shown in Table 26; gain tolerances are ±2%. Differential

receive output is assumed.

1414 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Chip Set Functional Description

(continued)

Other Chip Set Functions (continued)

Digital Termination Impedance Synthesis

The CTZ filter in the T7531A synthesizes complex ter-

mination impedances. The CTZ filter utilizes alpha and

beta coefficients (board control words 4 and 5, respec-

tively) to perform the synthesis. One set of alpha and

beta coefficients is required for each termination

impedance and balance network. These are provided

in the user manual. Alpha bits [9:0] represent the RC

time constant of the impedance that the filter is going to

synthesize. The bits are formatted as two’s comple-

ment. Alpha bits must be a nonzero value. Beta bits

[7:0] represent the dc gain of the filter . Beta coefficients

are also formatted as two’s complement. Setting beta

equal to zero turns off the CTZ function.

There is a constraint on the value of the protection

resistor with regard to termination impedance synthe-

sis and hybrid balance. For synthesis to operate prop-

erly, the total series Tip/Ring resistance must be 165 Ω

or greater . Coefficients for use with the L7585 SLIC are

set up for a protection value resistance of 82.5 Ω in Tip

and 82.5 Ω in Ring.

Loopback Modes

There are four loopback modes in the T7536.

The first two loopback modes are controlled by the all

channel test (ACT) register. ACT bits 0 and 1 place all

eight channels into loopback mode. Analog and digital

loopback are described and shown in block diagram

form in Table 29. Analog loopback allows one to check

functionality from Tip/Ring up to and including the

T7536. Digital loopback allows the T7531A to check

T7536 functionality.

The third loopba ck mode is used in the autocali bration

sequence (control register 2). This mode provides a

loopback between a selected channel and channel four

of a given T7536. The channel to be calibrated is

selected via control register 1 (see Table 27). Channel

f our is the only channel in the T7536 that is trimmed f or

gain accuracy. Every other channel uses channel four

as a reference and is calibrated to it during the autocal-

ibration sequence.

The fourth loopback mode is a digital loopback mode

located in control register 1. This operates like the digi-

tal loopback mode described in the notes for the ACT

loopback mode is selectable per channel. This loop-

back mode can be used to check T7536 functionality

from the T7531A device. It is also used during the cali-

bration seque nce.

There is one loopback mode in the T7531A. Loopback

at the oversampled data interface is controlled by board

control word 1. This mode allows the T7531A to test

itself. When bit 0 of 0x1FFE is selected, all 16 channels

of octal interface receive data (OSDRn) are looped

back to the T7531A transmit inputs (OSDXn).

Interchip Control Interface

The control interface is a 4-pin interface used to send

control information to the T7536 from the T7531A, and

to read back the control register contents. The pins

consist of a chip select input (CCS0/CCS1), a data

input (CDI), and a data output (CDO). The transfer of

control data is synchronous with the 4.096 MHz OSCK,

which is also used for oversampled data transf er.

T7531A Functional Blocks

Clock Synthesizer

The clock synthesizer block is a phase-lock loop (PLL)

circuit which tak es SCK supplied by the backplane and

uses it to produce the 98.304 MHz DSP engine clock.

The input clock, SCK, can be 2.048 MHz or 4.096 MHz.

An on-chip clock synthesizer has the advantages

shown below:

■Precludes the need f or extra cloc ks to be fed ov er the

backplane.

■Constrains the high-speed DSP engine clock within

the device.

■Synchronizes all clocks used on the line card to the

backplane clock, thus reducing board noise due to

beat frequencies.

A clock generator block takes the PLL output and

divides it down to produce all the lower-frequency

clocks used by the T7531A and T7536.

T7531A System Interface

The system interface is a full-duplex interface used for

the exchange of PCM data with the system. The sys-

tem is the master of this bus. No control information is

transmitted over the system interface; all control

instructions are routed over the microprocessor inter-

face.

Lucent Technologies Inc. 15

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Chip Set Functional Description

(continued)

T7531A Functional Blocks (continued)

The system interf ace is used for all 16 lines serviced by

the T7531A. The PCM data rate is 8 ksamples/s/line,

so the total required channel capacity is 16 x 8 =

128 Kwords/s in each direction. At the 4.096 MHz rate,

each word takes 1.95 µs to transmit interleaved with

5.86 µs of dead time. The frame sync, SFS, is pre-

sented to the system interface at an 8 kHz rate.

A single bit clock and frame sync are used to control

both the transmit and receive directions. The beginning

of the first time slot in a frame is identified from the SFS

input (see Figure 9). In nondela yed mode, SFS is active

coincident with bit 0 of time slot 0 of the RX frame (and

the TX frame if the programmed offset between TX and

RX is 0). In delayed mode, SFS is activ e one cycle ear-

lier.

The amount of sk e w or offset between the transmit and

receive frames and time slots is programmable via

board control word 2, 0x1FFC . The bit offset is up to a

frame, i.e., up to 511 bits in 4 MHz mode. See Table 36

for a listing of invalid bit offset values. The bit offset

skew takes place in the system PCM interface block.

The active transmit and receive time slots are deter-

mined by the card address. The number of time slots

within a frame v aries according to the rate of SCK. Only

16 time slots are ever a ctive in a frame, as shown in

Table 3.

The T7531A obtains its card address in board control

word 1, 0x1FFE.

In µ-law or A-law mode, each PCM word is only 8 bits

long and occupies one time slot. In linear mode, the

PCM word is 16 bits long and occupies two adjacent

time slots. The MSB is the first bit clocked out in the

valid time slot, and the LSB is the last bit of the follow-

ing (invalid) time slot.

T7531A Microprocessor Interface

This interface between the microprocessor (or other

external contro ll er) and the T7531 A device carri es

user-supplied program variables and control and test

instructions to both the T7531A and the T7536 octal

converters. The external device is the master of the

micropr oc esso r int erface. The interface is serial and

asynchronous, and consists of four pins (UPCK,

UPCS, UPDI, UPDO). The data rate is determined by

the customer’s choice of external device, but may not

exceed 4.096 MHz. Microprocessor interface com-

mands consist of two words, address and data.

Address and data are 16 bits wide. The T7531A

expects an address first. The first bit of the address

word is the R/W flag, which tells the T7531A whether

it must receive or send data (receive, R/W = 0; send,

R/W = 1).

Addresses less than 0x1400 refer to the DSP engine

RAM space. If a read from the DSP engine is required,

the microprocessor interf ace issues a read interrupt to

the DSP engine. If it's a write to the DSP engine, the

microprocessor interface shifts in the data word and

saves it into the data register before sending a write

interrupt to the DSP engine. Once in every 7.8 µs time

segment, the DSP engine checks whether an interrupt

is outstanding from the microprocessor interface bloc k.

If so, the DSP engine reads the address register. If it's

a read, the DSP engine fetches the word from RAM,

places it in the data register, and shifts it out to the

micr oproce ssor. If it's a w rite, it puts th e conten ts of th e

data register into RAM.

A pause there fore exis ts between the extern al con tr ol-

ler issuing an address and receiving a data read back.

The data rate of 2.048 MHz allows 256 SCK cycles in a

frame, i.e., eight address/data pairs with no pause

between words. Since the DSP engine can process

only one interrupt every 7.8 µs, the T7531A requires a

separation between address and data on read and

write instructions to the microprocessor interrupt (see

Figure 10). This, in effect, requires UPCK to be

gapped.

Table 3. Active Time-Slot Spacing in a PCM Bus Frame

SCK Rate (MHz) Total # of Time Slots Card Address Valid Time Slots Invalid Time Slots

2.048 32 0

10, 2, 4, . . . 30

1, 3, 5, . . . 31 1, 3, 5, . . . 31

0, 2, 4, . . . 30

4.096 64 0

0, 4, 8, . . . 60

1, 5, 9, . . . 61

2, 6, 10, . . . 62

3, 7, 11, . . . 63

1—3, 5—7, . . . 61—63

0, 2—4, 6—8, . . . 62—63

0—1, 3—5, 7—9, . . . 63

0—2, 4—6, 8—10, . . . 60—62

1616 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Chip Set Functional Description

(continued)

T7531A Functional Blocks (continued)

Addresses ≥0x1400 refer to registers or TSA RAM

external to the DSP engine. If the address word from

the microprocessor is 0x1400 through 0x140F, it acti-

vates the TSA state machine. If the address word from

the microprocessor is 0x1500 through 0x15FF, it acti-

vates the T7536 control state machine.

Microprocessor data and address words can be

flushed out of the T7531A by addressing 0x7FFF with

data word 0xFFFF (see Table 40).

T7536 Octal Control Interface

The two T7536 chips cannot be accessed by the micro-

controller directly; the T7536's registers are all

accessed via the T7531A microprocessor interface.

The microprocessor communicates serially with the

T7536 by simply writing or reading 16-bit address and

16-bit data. The octal control interface block translates

this address and data into 8-bit address and 8-bit data

needed by the T7536. The octal control interface block

waits until the microproce ssor interface block receives

all 16 bits of the address word and determines whether

this is a read or write operation by looking at bit 15. If

this is a write operation for a T7536 chip, it receives

another 16-bit data word.

T7531A Time-Slot Assignment (TSA)

The TSA block contains a 16 x 6 dual-port RAM which

is readable or writable via the microprocessor interface .

Table 18 gives the bit map for TSA RAM words. The

TSA RAM is in time-slot order, i.e., location 0x1400 is

f or time slot 0 and 0x1401 for time slot 1 and so on. The

low 4 bits (B3—B0) indicate which of the 16 possible

channel numbers is assigned to this time slot. The

time-slot assignment is controlled by the microproces-

sor writing to address 0x1400 through 0x140F.

The TSA block also generates the control signals and

flags used to synchronize the TSA, interpolator and

decimator, and T7536 interface blocks. The TSA RAM

is not preinitialized, so the microprocessor is required

to write to all 16 locations of the TSA RAM at start-up

to ensure proper operation. Twice a frame, the TSA

state machine reads the entire TSA RAM from top to

bottom in sequence and sends the contents of each

RAM location to the interpolator as channel numbers

for RX channels. The TSA state machine performs the

same procedure for the decimator to provide it with the

TX channel numbers. By performing TSA at the ov er-

sampled sigma-delta rate, round trip group delay is sig-

nificantly minimized.

DSP Engine Timing

The DSP engine processes all 16 lines every frame. In

order to simplify synchronization of data exchanges,

the processing frame is broken into 16 equal time seg-

ments of 7.8 µs each. The ROM code is identical for

each time segment.

Synchronization between the engine and the rest of the

chip is enforced by the system interface block, which

issues an interrupt every 7.8 µs. This interrupt is the

only unmasked interrupt processed by the engine. The

interrupt service routine f orces the ROM code to

branch to the start of the processing loop.

T7531A Program Structure

The DSP engine firmware performs three types of

operations:

1.Signal processing of the ac path data.

2.RAM accesses initiated by the microprocessor

interface.

3.Data and program flow operations.

The signal processing algorithms performed by the

T7531A are implemented in firmware and are held in

ROM.

Many firmware parameters are user programmable via

the microprocessor interface. Interrupts from the micro-

processor interface are handled once every time seg-

ment (7.8 µs), and the appropriate accesses are made

to the DSP engine RAM registers.

Lucent Technologies Inc. 17

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Chip Set Functional Description

(continued)

Control of the DSP Engine via the Micro-

processor Inte rfac e

There are four types of commands that the external

controlling device may issue to the DSP engine:

1. Downloading data to RAM.

2. Activating and deactivating lines.

3. Changing the RX and TX routine to be run.

4. Periodic read and/or refresh of RAM space.

All of these commands must only involve reading and

writing to the DSP RAM so that the DSP engine does

not have to perform test- and branch-type operations

when a microprocessor interf ace command is received.

The complete memory map for the DSP engine RAM is

given in Table 18. The microprocessor interface is

allowed to read any RAM location in the DSP engine

and to write to specified addresses.

The DSP Engine Time-Slot Information

Tables

In the T7531A, the DSP engine RAM has been set up

to contain 16 tables which hold the pointers to the ac

coefficients and data buffers required to process each

time slot. Each table starts on a 32-word boundary and

is accessed in the firmware using direct addressing

instructions. Each table has an RX part and a TX part

(see Table 18).

The tables are labeled 0 through 15 and are in time-slot

order, i.e., table 0 is used when processing data for

time slot 0. Time-slot number can vary between 0 and

15 and is used in conjunction with the card address to

provide up to 63 time-slot positions on the PCM bus

(see Table 3).

The DSP Engine ac Path Coefficient Ta ble

The microprocessor interface can control the DSP

coefficients, shown in Table 4. The DSP engine RAM

contains space to hold separate sets of coefficients for

each channel, labeled channel_0 through channel_15.

The coefficients are held in channel order, since they

hold information that is channel specific and does not

change with the time slot (see Table 18).

Table 4 shows the ac path coefficient space for

channel_0.

Table 4. DSP Engine RAM Map for Channel_0 ac

Path C o e f fi c i en t s

RAM

Address Purpose Number

of Words Initial

Value

rgain_rel_0 RX path

relativ e gai n 1 1 (4000 H)

Reserved — 1 —

rgain_abs_0 RX path

absolute gain 1 1 (4000 H)

tgain_abs_0 TX path

absolute gain 1 1 (4000 H)

bf_coef_0 Balance filter

coefficients 10 Not

initialized

Reserved — 1 —

tgain_rel_0 TX path

relativ e gai n 1 1 (4000 H)

1818 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Chip Set Functional Description

(continued)

The Time-Slot Control Word

The DSP engine works in time-slot order. The TSA

function is performed by the decimator/interpolator.

The DSP engine is not required to reorder the data in

any way. The advantages of this approach are that the

group delay introduced by the TSA function is very

small, and the DSP code needed for context switching

is small. When the microprocessor assigns a time slot

via the TSA RAM, it also has to issue a new time-slot

control word (TCW) instruction to the DSP engine to

enable the time slot to link to the correct ac coefficients.

The TCW contains the information shown in Tables 5A

and 5B. The TCW is only looked at when a time slot is

inactive. The initial setup of the TCWs assumes chan-

nel-order time-slot assignment.

Operations Performed by the DSP Engine

at T7531A Sta rt-Up

The DSP engine performs its start-up code after it has

been reset. All interrupts are disabled. First, the DSP

engine computes the checksum for its ROM and RAM

to verify their integrity. Next, the DSP engine walks

through each time-slot information table and sets the

data buffer and coefficient pointers. The DSP engine

RAM is set up for channel-order time-slot assignment,

i.e., table 0 points to channel_0 and so on. The start-up

settings for the Time-Slot Information Table (i.e., for

time slot 0) are shown in Tab le 6.

The first 16 locations of RAM bank 1 hold the channel

address table, where pointers to the start of the coeffi-

cient space for each channel are held. These pointers

are set up during the start-up routine. Pointers to the

three sets of default coefficients are also set up. The

DSP engine then walks through all 16 ac coefficient

tables and sets them to their initial values as shown in

the previous section. The RX and TX filter coefficients

(one set for all 16 lines) are taken from ROM and writ-

ten to their RAM locations.

The DSP engine takes about 3 ms to execute the start-

up code. At the end of the code, the interrupt system is

enabled and the DSP engine enters sleep mode.

Table 5A. Bit Maps for DSP Engine Time-Slot Control Word

Table 5B. Bit Map for Default Per-Board Coefficient Tables

Table 6. DSP Engine RAM Map for Time-Slot Information Table 0

0—3 Channel Number channel_(time-slot number)

4 Go to Powerup 0

5 Modify Coefficients 0

6—7 Use Default Per-Board Coefficient Tables 0

Bit 7 Bit 6 Mode

0 0 Do Not Select Default Tables

0 1 Default Table 1 Coefficient Set

1 0 Default Table 2 Coefficient Set

1 1 Default Table 2 Coefficient Set

Variable Function Initialized Address

tcw_0 Time-slot Control Word See above

rx_rtn_0 Address of Receive ac Routine rpath_inactive

tx_rtn_0 Address of Transmit ac Routine tpath_inactive

data storage Reserved NA

Lucent Technologies Inc. 19

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Chip Set Functional Description

(continued)

Microprocessor Start-Up of the DSP

Engine

Once the interrupt system is enabled, the DSP engine

looks f or a read or write interrupt from the microproces-

sor interface once every time segment, i.e., 16 times a

frame.

If the ac coefficients for every channel are to be inde-

pendently controlled, the microprocessor can write

directly to the addresses of the 16 ac coefficient tables.

This requires a total of 16 microprocessor commands

to set up each channel, i.e., 16 frames to set up all

16 channels. Prior to activating any time slots, the

microprocessor has the option of bulk downloading the

coefficients to set up the ac coefficient tables.

When a channel needs to be set up and linked to its

time slot, the microprocessor must send the TCW f o r

that time slot with the modify coefficient (MC) bit (see

Table 5A). The MC bit causes the inactive routine for

that time slot to set pointers from that time-slot space to

the channel space in RAM. The MC bit also causes the

inactive routine to check the default coefficient bits of

the TCW. If set, the appropriate default table coeffi-

cients are copied over to the RAM space for the chan-

nel. This mechanism allows the microprocessor to

download a set of coefficients that can be used by mul-

tiple channels.

A mix-and-match approach can be used, i.e., some

channels are set up with independent sets of coeffi-

cients, while other channels get a default setting.

During start-up, the microprocessor must also down-

load the 16 TSA commands used by the TSA block to

map physical channels to time slots. This is required to

initialize the TSA RAM to known values. When all 16

locations have been set up , the microprocessor must

send BCW2 (0x1FFC). This flags the TSA control to

start normal operation.

Powering Up a Time Slot in the T7531A

Depending on the application, the microprocessor may

choose to set up the ac coefficients for a channel just

prior to enabling it for use. This requires 16 micropro-

cessor commands if the coefficients must be set up

from scratch, or no commands if an appropriate def ault

set has already been set up. In either case, the micro-

processor must ensure that all the TX and RX parts of

a channel are set up prior to enabling the time slot.

If dynamic time-slot assignment is used, the micropro-

cessor must next download a TSA command, which

the TSA block uses to map the time slot to the required

channel number.

The microprocessor must enable the time slot by set-

ting the go to powerup bit of the TCW. This causes the

DSP engine to change the TX and RX ac routine

addresses to active .

A maximum of 17 commands or a minimum of one

command is therefore needed to power up a channel.

Disabling a Time Slot in the T7531A

To disable a time slot, the microprocessor must send a

command that sets the address of either the TX or RX

ac routine to TX_inactive and RX_inactive, respectively.

The inactive routines come into use in the next TX or

RX time segment f or this time slot. Upon returning from

the inactive routine, the DSP engine checks for a

microprocessor interrupt and then enters sleep mode

for the rest of the time segment.

T7536 Powerup/Powerdown

Each channel can be powered up independently. There

are two control register addresses that can be used to

control the power for each channel. In both cases, the

first bit of the address word controls the power. P = 1

for powerup, and P = 0 for powerdown.

One address is provided for each channel which con-

trols the power (0x1508—0x150F and 0x1548—

0x154F), and the address is followed by a data word

which controls the other programmable functions for

the same channel. A second address (0x1500—

0x1507 and 0x1540—0x1547) is provided for each

channel that controls only the power.

2020 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Chip Set Functional Description

(continued)

Changing DSP RAM Space of an Active

Time Slot

The microprocessor is only allowed to change four

RAM locations for an activ e time slot:

■Relative transmit gain

■Relative receive gain

■Address of receive ac routine

■Addres s of transmit ac routine

Absolute gains and time-slot assignment can only be

altered when the time slot is inactive. Note that the

DSP engine does not check the TCW of active time

slots.

F ollo wing the ini tial po werup, the line card is lik ely to be

in service without being reset f or as long as it continues

to operate trouble-free. Therefore, the microprocessor

has the option of continuously monitoring the variables

it has programmed by reading them back from the DSP

engine/microprocessor interface and rewriting them.

DSP Engine Memory Requirements

The size of the DSP engine internal dual-port RAM is

2K x 16-bit words per DSP engine. RAM storage is

used for user-programmable variables and for interme-

diate storage of the data being processed by the

device. The RAM memory map is given in Table 18.

The on-chip ROM is used for both program and data.

The DSP engine firmware is ROM based. The hard-

ware development system code is also ROM based.

The DSP engine ROM memory map is given in

Table 41.

T7531A Reset and Start-Up

The chips support both hardware and software reset.

Hardware Reset

The T7531A reset functions are handled by the reset

control block. Hardware reset occurs if the board is

powered up with RSTB lo w. Si nc e RSTB has a Schmitt

trigger buffer with an internal pull-up, a capacitor

attached external to the RSTB pin causes the pin to

pull high after a specified period of time. For power-on

reset, the T7531A requires that this period of time be

>1 ms to give the on-chip clock synthesizer block time

to start producing clock edges for the T7531A and

T7536 chips (although it may not have reached its final

accuracy yet). Successful hardware reset of the device

requires that:

1. The PCM bus signals SCK and SFS should be valid

at the start of the 1 ms power-on reset period.

2. VDD (and therefore RSTB) should have been low for

at least 200 ms prior to commencing power-on reset

to ensure that the JTAG controller powerup reset cir-

cuit has had time to clear the JTAG controller.

If, during normal operation, VDD falls below the defined

minimum value, VDD min, the power-on reset procedure

described above must be repeated.

Hardwa re re set occ urs if RSTB is pulsed high-low-high

for 1 ms during normal operation (i.e., no loss of

power).

Table 7. Summary of Microprocessor Commands for Control of T7531A Data Processing

Function Required Number of Commands When Issued

Bulk TSA register download & BCW2 17 Start-up

Individual TSA register download 1 Prior to activating a time slot via the TCW

Coefficient download 16 per channel Start-up or when time slot is inactive

Set TCW to use/share coefficients

already downloaded to default tables 1 Start-up or when time slot is inactive

Enable time slot via TCW (fixed TSA) 1 When time slot is inactive

Enable time slot via TCW (dynamic TSA) 2 When time slot is inactive

Disable time slot 1 When time slot is active

Change gain value 1 per gain Any time

Lucent Technologies Inc. 21

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Chip Set Functional Description

(continued)

Internal Reset

Internal reset is defined as the process that starts

when the internal reset line is brought low. This hap-

pens as a conseq uen ce of hardware (RTSB) or soft-

ware (BCW1) reset. The internal reset process

performs the following functions:

1. The frequency synthesizer does not receive any

reset signal, and is thus unaffected by reset. Follow-

ing power-on reset of the T7531A, the frequency

synthesizer takes the mode determined by the

SCKSEL pin .

2. The T7531A custom logic jams all resettable

latches, counters, and registers to their default val-

ues. No data is latched on any of the T7531A inter-

faces during internal reset.

3. The DSP engine is held in reset state.

4. The internal reset line is held low for a minimum of

18 ms to allow the frequency synthesizer to reach its

final accuracy. An internal counter is started when

the internal reset line goes low. It counts 80 frame

sync pulses on SFS before releasing the internal

reset line.

5. When the internal reset line goes high and the EXM

(internal) signal is held low, the DSP engine begins

its start-up routine by fetching the first instruction

from location 0 of the internal ROM.

6. At the rising edge of the internal reset line, all the

T7531A custom logic blocks commence their normal

operation.

Reset of the T7536 Devices

There are two options for reset of the T7536 chips.

The T7536s can make use of the same hardware reset

pulse as the T7531A. The T7531A supplies OSCK to

the T7536s as soon as it is available, i.e., before the

hardware reset has gone awa y. It is recommended that

hardware reset be applied to all chips simultaneously.

Alternatively, the T7536s can be reset through software

reset (Tables 21 and 22), which is generated by the

e xternal controlling device and routed to the T7536s via

the T7531A. This can only occur when OSCK is guar-

anteed to be valid, i.e., not within 10 ms of power-on

hardware reset.

Start-Up After Internal Reset

There is a specific sequence of microprocessor inter-

face instructions that must be followed after internal

reset in order to properly configure the T7531A and

T7536s for normal operation.

1. If nondefault values are required, the T7531A board

control word 1 (address 0x1FFE) must be updated.

2. The 16 TSA RAM locations must be written before

0x1FFC. CTZ must be disabled (see Table 20B).

3. The all channel test register must be set for normal

operation (addresses 0x1510 and 0x1550 set to

0x0004).

4. The T7531A control registers must be set. All 16

channels must be powered up (addresses

0x1500—0x1507 and 0x1540—0x1547 must be set

to 0x8000).

5. The amplitude of the calibration sine wave must be

set by writing address 0x0580 to coefficient

0xAA20, and address 0x0581 to coefficient

0xF49D.

6. All 16 channels must be put into initialization mode

(addresses 0x1518—0x151F and 0x1558—0x155F

must be set to 0x0080).

7. The DSP engine RAM address 0x0002 must be set

to 0x0700 to begin the first part of the T7536 cali-

bration start-up sequence.

8. After 70 ms, all 16 T7536 channels must be put into

loopback mode (addresses 0x1508—0x151F and

0x1548—0x154F must be set to 0x8001).

9. The DSP engine RAM address 0x0002 must be set

to 0x0720 to begin the second part of the T7536

calibration sta rt-up seque nce.

10.After 70 ms, both T7536s should be sent a soft

reset (addresses 0x1517 and 0x1557 set to

0x8000) and the all channel test register should be

set f or normal operation (addresses 0x1510 and

0x1550 set to 0x0004). Normal T7531A operation

commences with the next SFS frame sync. The

chips are now ready f or channels to be enabled and

filter coefficients to be set.

2222 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Chip Set Functional Description

(continued)

Autocalibration

Autocalibration is an analog self-test and trimming pro-

cedure controlled by the DSP core. Sine wave signals

are generated in the receive direction. These signals

are looped back at the analog side of the T7536, and

the return signal amplitudes are measured in the trans-

mit path. This procedure provides on-the-spot fault co v-

erage of the transmit and receive paths. It also

calibrates the octal devices by modifying the gain on

each channel. Channel four of the T7536 is the only

channel trimmed at the factory for absolute gain accu-

racy. When a uto cal ibratio n is r un, all chan nel s are

trimmed with reference to channel four. That is, the

gain on each channel is adjusted so that its absolute

gain is equivalent to that of the trimmed channel. Per-

forming trimming in this manner provides channel-to-

channel gain matching of better than 0.01 dB. This is a

much better perf ormance than could be achiev ed using

conventional trimming. Trimmed values are placed in

data storage, and absolute gain values are then modi-

fied accordingly any time the absolute gain register is

changed.

The calibration sequence measures the looped-back

power result and compares it to the calibrated channel.

The trim window is ±0.2 dB. If any channel exhibits a

power value which is greater than ±0.2 dB , the calibra-

tion procedure sets a failure flag for that channel. Trim-

ming will not be performed on the failed channel, and

the channel’s trimmed gain will be left at 0 dB. The

f ailed channel, theref ore, is left in its previous state and

can still be used. The results of calibration are held in

RAM address 0x07F4 for transmit (pass 1) and 0x07F5

for receive (pass 2). A bit is set high for every failed

channel.

The preceding section discussed the sequence of

instructions that must be followed in order to properly

configure the T7531A for normal operation. The auto-

calibration procedure is mandatory after hardware

reset.

User Test Features

This section outlines the T7531A test features and

architecture. For more information on the board-test

capabilities, see the

T7531A/T7536 User Manual

Off-Line Programmable System Test Capability

The T7531A has a standard 4-pin test access port

known as JTA G that can be used for testing and debug-

ging. The user has the option of downloading custom

firmware to the DSP engine RAM via the JTAG port,

and running it in the DSP engine in place of the normal

ROM-based code. The DSP16 hardware development

tool provides a powerful user interface for real-time

code development and debug. The user can also exe-

cute the self-test ROM routine which exercises signifi-

cant portions of the T7531A and T7536 devices.

On-Line Per-Channel Test Capability

In addition to the active (i.e., normal voice processing

functions) and inactive routines, the user can select the

routines listed in Table 41 by altering the TX and RX

routines address in the time-slot information table (see

Table 6).

Inactive Mode with Loopback

This is a pair of routines that are used for the TX and

RX parts of the channel. Data from SDR is looped bac k

without modification to SDX.

Self-Test and Board-Test Routines

Using the following routines, programs can be written

to test not only the codec function but also all attached

circuitry, like the SLIC, relays, protection devices, and

cabling.

Tone Generation

In tone generation mode, the RX part of the channel is

used to send a sine wave signal out to the line. The

sine wave can be up to 4 kHz in frequency, and up to

1024 points long. The RX filter is not implemented in

tone generation.

Lucent Technologies Inc. 23

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Chip Set Functional Description

(continued)

Self-Test and Board-Test Routines

(continued)

Tone Detection

In tone detection mode, the TX part of the channel can

be used to detect signal energy from the line at a given

frequency up to 4 kHz. This routine performs discrete

Fourier transform (DFT) to capture and analyze the

reflected tone. The routine does not employ the trans-

mit bandpass filters. The number of frames to sample

the reflected tone must be defined. The number of

frames that DFT is run must be a power of 2 and should

be complete cycles of tone value.

dc Generation

This routine generates a dc signal (v alue defined by

user) in the RX path.

Variance Compu tation

The variance routine computes the variance of small

noise signals from the TX path around the computed

mean level. This routine employs the transmit band-

pass filters for out-of-band noise reduction.

Peak Detection

This routine examines the incoming TX signal and

save s the max imum and mi nimum si gna l values.

Handling Precautions

Although protection circuitry has been designed into

this device, proper precautions should be taken to

av oid e xposure to electrostatic discharge (ESD) during

handling and mounting. Lucent Technologies employs

a human-body model (HBM) and a charged-device

model (CDM) for ESD-susceptibility testing and protec-

tion design evaluation. ESD voltage thresholds are

dependent on the circuit parameters used to define the

model. No industry-wide standard has been adopted

for the CDM. A standard HBM (resistance = 1500 Ω,

capacitance = 100 pF) is widely accepted and can be

used for comparison. The HBM ESD threshold pre-

sented here was obtained by using these circuit

parameters:

HBM ESD Threshold

Device Vo ltag e (V)

T7531A >1000

T7536 >1000

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operational section of the data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

Parameter Symbol Min Max Unit

Ambient Operating Temperature TA–40 85 °C

Operating Junction Temperature TJ–40 125 °C

Thermal Resistance, Junction to Case RΘJC —35°C/W

Storage Temperature Range Tstg –55 150 °C

Power Supply Voltage VDD 4.75 5.25 V

Voltage on Any Pin with Respect to Ground VSS –0.25 5.25 V

Package Power Di ssipation PD—1W

24 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Electrical Characteristics

For all specifications: TA = –40 °C to +85 °C, VDD = 5 V ± 5%, unless otherwise noted. Typical values are for

TA = 25 °C and VDD = 5 V. Input signal frequency is 1020 Hz, unless otherwise noted.

dc Charac teristi cs

Table 8. Digital Interface

Table 9. Analog Interface

Parameter Symbol Test Conditions Min Typ Max Unit

Input Voltage Low VIL TTL-compatible inputs — — 0.7 V

High VIH TTL-compatible inputs 2.0 — — V

Output Voltage Low VOL IL = 10 mA — — 0.4 V

High VOH IL = –10 mA 2.4 — — V

VOHC IL = –320 µA3.5——V

Input Current Pins Without a

Pull-up or

Pull-down

Low IIL GND < VIN < VIL –10 — — µA

High IIH VIH < VIN < VDD ——10µA

Pins with a

Pull-up Low IIL GND < VIN < VIL –120 — –2 µA

High IIH VIH < VIN < VDD ——10µA

Pins with a

Pull-down Low IIL GND < VIN < VIL –10 — — µA

High IIH VIH < VIN < VDD 2 — 120 µA

Output Current in High-impedance

State —I

OZ UPDO, SDX –40 °C to 0 °C –30 — 30 µA

UPDO, SDX 0 °C to 85 °C –10 — 10 µA

Parameter Symbol Test Conditions Min Typ Max Unit

Input Resistance RVTX 0.25 V < VTX < 4.75 V 10 — — MΩ

Input Resistance

(dependent on the setting

of the termination impedance)

RVRTX 2.3 V < VRTX < 2.5 V 7 — — kΩ

Common-mode Reference Voltage VVRTX — 2.2 2.4 2.6 V

CMT Input Sink Current IVRTX 2.3 V < VRTX < 2.5 V — — 400 µA

Input Voltage Swing VVTX — — — 3.2 Vp-p

Load Resistance at VRP and VRN

(differential) RL — 4.0 — — kΩ

Load Capacitance CL CL from VRP or VRN to VSSA ——100pF

Output Resistance RO Digital input code corresponding to

0 dBm PCM code at 1.02 kHz —210Ω

Output Offset Voltage Between

VRP and VRN VOS Digital pattern corresponding to idle

PCM code (µ-law) –100 0 100 mV

Output Offset Voltage Between

VRP and VRN, Powerdow n VO S PD C h ann el powe re d down

10 µA max dc load –20 0 20 mV

Output Voltage Swing (differential) VRSW RL = 100 kΩ differential maximum

receive gain 5.28 — — Vp-p

Lucent Technologies Inc. 25

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Electrical Characteristics (continued)

dc Chara cteristics (continued)

Table 10. T7536 Power Dissipation

Table 11. T7531A Power Dissipation

* Powerup current ex hibits a negative temperature coefficient.

Transmission Characte ristics

Table 12. Gain and Dynamic Range

Parameter Symbol Test Conditions Min Typ Max Unit

Powerdown Current IDD0 OSCK and OSFS present, 8 channels powered down — 9 12 mA

Powerup Current IDD1 OSCK and OSFS present, 8 channels powered up,

normal operation —6188mA

Parameter Symbol Test Conditions Min Typ Max Unit

Powerdown Current IDD0 SCK and SFS present, 16 channels powered down

and inactive —105—mA

Powerup Current IDD1 SCK and SFS present, 16 channels powered up and

active — 175* 190 mA

Parameter Symbol Test Conditions Min Typ Max Unit

Absolute

Levels GAL Maximum 0 dBm0 levels (1.02 kHz):

VTX (encoder milliwatt)

(T7536 TX gain = 0 dB; T7531A gain = –1.65 dB)

VRP—VRN (decoder milliwatt)

(T7536 RX gain = 6.02 dB; T7531A gain = 0.21 dB)

Termination impedance off

—

2.23

4.38

—

Vp-p

Minimum 0 dBm0 levels (1.02 kHz):

VTX

(T7536 TX gain =12.04 dB; T7531A gain = –1.65 dB)

VRP—VRN

(T7536 RX gain = –12.04 dB; T7531A gain = 0.21 dB)

Termination impedance off

—

557.0

548.0

—

mVp-p

Tran sm it Ga in

Absolute

Accuracy

GXA Transmit gain programmed f or maximum

0 dBm0 test level, measured deviation of digital code

from ideal 0 dBm0 level at OSDX[1:0] digital outputs,

with transmit gain set to 0 dB:

0 °C to 85 °C

–40 °C to +85 °C–0.25

–0.30 —

—0.25

0.30 dB

Tran sm it Ga in

Variation with

Programmed

Gain

GXAG Measured transmit gain over the range from maxi-

mum to minimum, calculated deviation from the pro-

grammed gain relative to GXA at 0 dB:

VDD = 5 V –0.1 — 0.1 dB

26 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Transmission Characteristics (continued)

Table 12. Gain and Dynamic Range (continued)

Parameter Symbol Test Conditions Min Typ Max Unit

Transmit Gain Variation

with Frequency GXAF Relative to 1016 Hz, minimum gain < GX <

maximum gain, VTX = 0 dBm0 signal,

TZ = 600 Ω,

path gain set to 0 dB:

f = 16.67 Hz

f = 40 Hz

f = 50 Hz

f = 60 Hz

f = 200 Hz

f = 300 Hz to 3000 Hz

f = 3140 Hz

f = 3380 Hz

f = 3860 Hz

f = 4600 Hz and above

—

–1.8

–0.125

–0.57

–0.735

—

–50

–38

–44

–45

–0.5

±0.04

0.01

–0.550

–9.9

—

–30

–26

–30

0.125

0.015

–8.98

–32

Transmit Gain Variation

with Signal Level GXAL Sinusoidal test method reference

level = 0 dBm0:

VTX = –37 dBm0 to +3 dBm0

VTX = –50 dBm0 to –37 dBm0

VTX = –55 dBm0 to –50 dBm0

–0.25

–0.50

–1.4

—

0.25

0.50

1.4

Receive Gain Absolute

Accuracy GRA Receive gai n progr amm ed to 0 dB, apply

0 dB m0 oversampled data to OSDR0 or

OSDR1, measure VRP,

RL = 100 kΩ differ ent ial :

0 to 85 °C

–40 °C to +85 °C–0.25

–0.30 —

—0.25

0.30 dB

Relative Gain:

VRP to VRN — Digital input 0 dBm0 signal

f = 300 Hz to 3400 Hz –0.01 — 0.01 dB

Relative Phase:

VRP to VRN — Digital input 0 dBm0 signal

f = 300 Hz to 3400 Hz –0.25 — 0.25 Deg

Receive Gain V ariation

with Programmed

Gain

GRAG Measure receive gain over the range from

maximum to minimum setting, calculated

deviation from the programmed gain relative

to GRA at 0 dB, VDD = 5 V

–0.1 — 0.1 dB

Receive Gain V ariation

with Frequency GRAF Relative to 1016 Hz, digital input = 0 dBm0

code, minimum gain < GR < maximum gain:

0 dB path gain

f = below 3000 Hz

f = 3140 Hz

f = 3380 Hz

f = 3860 Hz

f = 4600 Hz and above

–0.125

–0.57

–0.735

—

±0.04

–0.550

–10.7

—

0.125

0.015

–8.98

–28

Receive Gain V ariation

with Signal Level GRAL Sinusoidal test method, reference

level = 0 dBm0:

OSDR = –37 dBm0 to +3 dBm0

OSDR = –50 dBm0 to –37 dBm0 –0.25

–0.50 —

—0.25

0.50 dB

Relative Termination

Impedance Gain AT— –0.2 — 0.2 dB

Lucent Technologies Inc. 27

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Transmission Characte ristics (continued)

Table 13. Noise (per Channel)

* Measured with a –50 dBm0 activ ation signal applied to VFXI input of channel under test.

Parameter Symbol Test Conditions Min Typ Max Unit

Tran sm it N ois e,

C-message Weighted NXC 0 dB transmit gain — — 18 dBrnC0

Tran sm it N ois e,

P-message Weighted NXP 0 dB transmit gain — — –68 dBm0p

Recei ve Noise,

C-message Weighted NRC 0 dB receive gain, digital pattern corre-

sponding to idle PCM code, µ-law ——13dBrnC0

Recei ve Noise,

P-message Weighted NRP 0 dB receive gain, digital pattern corre-

sponding to idle PCM code, µ-law — — –75 dBm0p

Noise, Single Frequency NRS f = 0 kHz to 100 kHz, loop around measure-

ment, VTX = 0 Vrms — — –53 dBm0

Power Supply Rejection,

Transmit PSRXVDD = 5.0 Vdc + 100 mVrms

f = 0 kHz to 4 kHz

f = 4 kHz to 50 kHz*

C-message weighted

30 —

——

—dBC

dBC

Power Supply Rejection,

Receive PSRRMeasured on VRP

VDD = 5.0 Vdc + 100 mVrms

f = 0 kHz to 4 kHz

f = 4 kHz to 25 kHz

f = 25 kHz to 50 kHz

Digital patt er n corre spond ing to idle PCM

code, µ-law, C-message weighted

—

dBC

Spurious Out-of-band

Signals at the Channel

Outputs

SOS 0 dBm0, 300 Hz to 3400 Hz input

oversampled data code applied at OSDR0

(or OSDR1):

4600 Hz to 7600 Hz

7600 Hz to 8400 Hz

8400 Hz to 50 kHz

—

–30

–40

–30

28 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Transmission Characteristics (continued)

Table 14. Distortion and Group Delay

* Var ies as a function of bit offset.

Table 15. Crosstalk

Parameter Symbol Test Conditions Min Typ Max Unit

Signal to Total Distortion

Transmit or Receive

C-message Weighted

STDX

STDRSinusoidal test method level:

3.0 dBm0

0 dBm0 33

36 —

——

—dB

Single Frequency Distortion,

Transmit SFDX0 dBm0 single frequency input,

200 Hz ≤ fIN ≤ 3400 Hz; measure at

any other single frequency

— — –46 dB

Single Frequency Distortion,

Receive SFDR0 dBm0 single frequency input,

200 Hz ≤ fIN ≤ 3400 Hz; measure at

any other single frequency

— — –46 dB

Intermodulation Distortion IMD Transmit or receive, two frequencies

in the range (300 Hz to 3400 Hz) — — –41 dB

TX Group Delay, Absolute DXA f = 1600 Hz, SCK = 4.096 MHz,

bit offset = 419 — 250* 300 µs

RX Group Delay, Absolute DRA f = 1600 Hz — 250 300 µs

Parameter Symbol Test Conditions Min Typ Max Unit

Transmit to Transmit Crosstalk,

0 dBm0 Level CTX-X f = 300 Hz to 3400 Hz,

Any channel to any channel — — –75 dB

Transmit to Receiv e Crosstalk,

0 dBm0 Level CTX-R f = 300 Hz to 3400 Hz,

Any channel to any other channel

In-channel —

——

—–75

–50 dB

Receive to Transmit Crosstalk,

0 dBm0 Level CTR-X f = 300 Hz to 3400 Hz,

Any channel to any other channel

In-channel —

——

—–75

–50 dB

Receive to Recei ve Crosstalk,

0 dBm0 Level CTR-R f = 300 Hz to 3400 Hz,

Any channel to any channel — — –75 dB

Lucent Technologies Inc. 29

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Timing Characteristics

A signal is valid if it is above VIH or below VIL and invalid if it is between VIL and VIH. For the purposes of this speci-

fication, the following conditions apply:

■All input signals are defined as VIL = 0.4 V, VIH = 2.7 V, tR < 10 ns, tF < 10 ns.

■tR is measured from VIL to VIH. tF is measured from VIH to VIL.

■Delay times are measured from the input signal valid to the output signal valid.

■Setup times are measured from the data input valid to the clock input invalid.

■Hold times are measured from the clock signal valid to the data input invalid.

■Pulse widths are measured from VIL to VIL or from VIH to VIH.

Table 16. PCM Interface Timing (See Figure 9.)

Symbol Pa rameter Test Conditions Min Typ Max Unit

fSCK F requency of SCK (Selection

frequenc y is pin-stra p

programmable.)

——

—2.048

4.096 —

—MHz

MHz

tSCK Period of SCK Measured from VIL to VIL — 1/fSCK — ns

— Jitter of SCK — — — 100 ns in

100 ms = 1 ppm —

tSCHSCL Period of SCK High Measured from VIH to VIH 80 — — ns

tSCLSCH Period of SCK Low Measured from VIL to VIL 80 — — ns

tSCH1SCH2 Rise Time of SCK Measured from VIL to VIH — — 15 ns

tSCL2SCL1 Fall Time of SCK Measured from VIH to VIL — — 15 ns

tFSHFSL Period of SFS High Measured from VIH to VIL:

2.048 MHz

4.096 MHz 0.488

0.244 —

—62.5

62.5 µs

µs

tSFHSCL Frame Sync High Setup — 30 — — ns

tSCLSF L Frame Sync Hold T ime — 30 — — ns

tSCHDXV Data Enabled on TS Entry 0 < CLOAD < 100 pF 0 9 90 ns

tDRVSCL Receive Data Setup — 30 — — ns

tSCLDRX Receive Data Hold — 30 — — ns

30 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Timing Characteristics (continued)

5-4233.a (F)

* Card address 0, bit offset 0 assumed.

† Card address 0 assumed.

Notes:

A is the position of the frame sync pulse in the delayed mode.

B is the position of the frame sync pulse in the nondelayed mode.

Figure 9. Timing Characteristics of PCM Interface Assuming 2.048 MHz SCK Rate

SFS

BA tFSHFSL

SCK 123456789101112131415161

12345678

SDX*1

SDR†12345678 1

tSCLSFL

tSFHSCL

tSCHDXV

tDRVSCL

tSCLDRX

TIME SLOT 0 TIME SLOT 1

tSCHSCL

tSCLSCH

Lucent Technologies Inc. 31

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Timing Characteristics (continued)

Table 17. Serial Control Port Timing (See Figure 10.)

5-4232a (F)

Notes:

UPDI and UPCS change at the rising edge of UPCK by the microprocessor and are sampled at the falling edge of UPCK by the DSP.

UPDO changes at the rising edge of UPCK by the DSP and is sampled at the falling edge of UPCK by the microprocessor.

Figure 10. Timing Diagram for Microprocessor Write/Read to/from the DSP on the Control Interface

Symbol Par ameter Test Conditions Min Typ Max Unit

tCSHLSET UPCS to UPCK Setup — 25 — — ns

tCSLHHOD UPCS to UPCK Hold — 20 ns — UPCK Period/2 —

tUPDIST UPDI to UPCK Setup — 25 — — ns

tUPDIHD UPDI to UPCK Hold — 20 — — ns

tUPDODEL UPCK to UPDO Delay CL = 50 pF — — 42 ns

tUPDOHZDL UPCS to UPDO High-Z CL = 50 pF — — 34 ns

tCKCSH Duration of UPCK and UPCS High:

Write Cycle

Read Cycle —

—1

9—

——

—µs

µs

tCKCSH1 Duration of UPCK and UPCS High — 9 — — µs

tCSHLSET tCSLHHOD

tUPDOHZDL

013—11415

tUPDIHD

DATA (16 bits)

tUPDODEL

0113—21415

tUPDIST

tUPDIHD

ADDRESS (16 bits)

UPDI

UPDO

UPCS

UPCK

HIGH-Z ST AT E

DATA (16 bits)

tCKCSH

ADDRESS

tCKCSH1

32 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Software Interface

Table 18 lists the RAM data space f or the DSP engine. Space f or up to 16 channels is allocated. The total T7531A

RAM size is 2 Kwords, arranged as 2 x 1 Kbanks. Address bit 15 is used as a read/write flag (1 = read). The micro-

processor interface can read any address in the DSP engine RAM space.

Table 18. DSP Engine RAM Memory Map

1.The receive and transmit ac routine addresses are the only addresses that can address ROM code.

2.For time slots 1—15, the address shown is the first address. Refer to time slot 0 for range inform ation.

Address Range Memory Contents Write by Microprocessor Interface

RAM Bank 0 Time-Slot Information Tables (See page 17.)

0x0000 Time-slot control word (time slot 0) Y

0x00011Receive ac routine address (time slot 0) Y

0x00021Transmit ac routine address (time slot 0) Y

0x0003—0x003F Data storage (time slot 0) Selected locations

0x00402Time slot 1 information table As shown for time slot 0

0x00 80 T ime slot 2 information table As shown for time slot 0

0x00C0 Time slot 3 information table As shown for time slot 0

0x01 00 T ime slot 4 information table As shown for time slot 0

0x01 40 T ime slot 5 information table As shown for time slot 0

0x01 80 T ime slot 6 information table As shown for time slot 0

0x01C0 Time slot 7 information table As shown for time slot 0

0x02 00 T ime slot 8 information table As shown for time slot 0

0x02 40 T ime slot 9 information table As shown for time slot 0

0x0280 Time slot 10 information table As shown for time slot 0

0x02C0 Time slot 11 information table As shown for time slot 0

0x0300 Time slot 12 information table As shown for time slot 0

0x0340 Time slot 13 information table As shown for time slot 0

0x0380 Time slot 14 information table As shown for time slot 0

0x03C0 Time slot 15 information table As shown for time slot 0

RAM Bank 1 ac Coefficient Reference Tables (See page 16.)

0x0400—0x040F Channel coefficient address table N

0x0410—0x0413 Default coefficient address table N

0x0414—0x0434 Reserved N

ac Per- Channel Coefficients (See page 16.)

0x0435 Receive path relative gain (channel 0) Y

0x0436 Dat a storage (ch ann el 0) N

0x0437 Receive path absolute gain (channel 0) Y

0x0438 Transmit path absolute gain (channel 0) Y

0x0439—0x0442 Balance filter coefficients (channel 0) Y

0x0443 Dat a storage (ch ann el 0) N

0x0444 Transmit path relative gain (channel 0) Y

Lucent Technologies Inc. 33

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Software Interface (continued)

Table 18. DSP Engine RAM Memory Map (continued)

1.The receiv e and tr ansmit ac routine addresses are the only addresses that can address ROM code.

2.For time slots 1—15, the address shown is the first address. Ref er to time slot 0 for range information.

3.For channels 1—15, the address shown is the first address. Refer to channel 0 fo r range inform ation.

4.Per-board refers to a function that is common to all 16 channels in a single chip set.

Address Range Memory Contents Write by Microprocessor Interface

0x04453Channel 1 ac filter coefficients As shown for channel 0

0x0455 Channel 2 ac filter coefficients As shown for channel 0

0x0465 Channel 3 ac filter coefficients As shown for channel 0

0x0475 Channel 4 ac filter coefficients As shown for channel 0

0x0485 Channel 5 ac filter coefficients As shown for channel 0

0x0495 Channel 6 ac filter coefficients As shown for channel 0

0x04A5 Channel 7 ac filter coefficients As shown for channel 0

0x04B5 Channel 8 ac filter coefficients As shown for channel 0

0x04C5 Channel 9 ac filter coefficients As shown for channel 0

0x04D5 Channel 10 ac filter coefficients As shown for channel 0

0x04E5 Channel 11 ac filter coefficients As shown for channel 0

0x04F5 Channel 12 ac filter coefficients As shown for channel 0

0x0505 Channel 13 ac filter coefficients As shown for channel 0

0x0515 Channel 14 ac filter coefficients As shown for channel 0

0x0525 Channel 15 ac filter coefficients As shown for channel 0

ac Per-Board4 Coefficients

0x0535—0x053E Receive filter coefficients Y

0x053F—0x0552 Transmit (equalizer) filter coefficients Y

0x0553 Transmit gain coefficients for filter compensation Y

0x0554—0x0560 Unused Y

Default Per-Board4 Coefficient Tables

0x0561 Default Table 1 receive path relative gain Y

0x0562 Default Table 1 receive path absolute gain Y

0x0563 Default Table 1 transmit path absolute gain Y

0x0564–0x056D Default Table 1 balance filter coefficients Y

0x056E Default Table 1 transmit path relative gain Y

0x056F—0x057C Default Table 2 coefficient set Y

Self-Test Flags

0x057D—0x05EE Temporary storage for self-test routines Y

0x05EF—0x07EF Unused Y

0x07F0 Result of ROM checksum test N

0x07F2 Result of RAM checksum test N

0x07F4 Result of TX path self-test N

0x07F5 Result of RX path self-test N

0x07F6 RO M co de vers ion numbe r N

34 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Software Interface (continued)

Table 19. T7531A Time-Slot Assignment Memory Map

All registers can be written by the microprocessor interface.

Table 20A. Bit Map for T7531A Time-Slot Assignment Registers at 0x1400—0x140F

Table 20B. Bit Map for CTZ Disable and Null Channel

Notes:

X = Don’t care.

Bits 4 and 5 default to 1 upon reset.

Address Range Memory Contents

0x1400 Time slot 0 channel assignment

0x1401 Time slot 1 channel assignment

0x1402 Time slot 2 channel assignment

0x1403 Time slot 3 channel assignment

0x1404 Time slot 4 channel assignment

0x1405 Time slot 5 channel assignment

0x1406 Time slot 6 channel assignment

0x1407 Time slot 7 channel assignment

0x1408 Time slot 8 channel assignment

0x1409 Time slot 9 channel assignment

0x140A Time slot 10 channel assignment

0x140B Time slot 11 channel assignment

0x140C Time slot 12 channel assignment

0x140D Time slot 13 channel assignment

0x140E Time slot 14 channel assignment

0x140F Time slot 15 channel assignment

Bit Number and Function

15—6543210

Not used CTZ disable Null channel Binary-coded channel number 0—15

Bit 5 Bit 4 Function

X 0 Disables null pointer

X 1 Nulls channel

0X Enables CTZ

1X Disables CTZ

Data Sheet

February 1999

Lucent Technologies Inc. 35

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Software Interface (continued)

Table 21. T7531A Channel Register Memory Map for

T7536 Device 0

All registers can be written by the microprocessor inter-

face.

Table 22. T7531A Channel Register Memory Map for

T7536 Device 1

All registers can be written by the microprocessor inter-

face.

Table 23. Bit Map for T7536 Powerup/Po werdown

Registers at 0x1500—0x1507 and

0x1540—0x1547

Notes:

PWR = 0: powerdown.

PWR = 1: powerup—normal operation.

Address

Range Memory Contents

0x1500 Channel 0 powerup/powerdown register

0x1501 Channel 1 powerup/powerdown register

0x1502 Channel 2 powerup/powerdown register

0x1503 Channel 3 powerup/powerdown register

0x1504 Channel 4 powerup/powerdown register

0x1505 Channel 5 powerup/powerdown register

0x1506 Channel 6 powerup/powerdown register

0x1507 Channel 7 powerup/powerdown register

0x1508 Channel 0 control register 1

0x1509 Channel 1 control register 1

0x150A Channel 2 control register 1

0x150B Channel 3 control register 1

0x150C Channel 4 control register 1

0x150D Channel 5 control register 1

0x150E Channel 6 control register 1

0x150F Channel 7 control register 1

0x1510 All channel test register

0x1517 Single-byte soft reset (no data word)

0x1518 Channel 0 control register 2

0x1519 Channel 1 control register 2

0x151A Channel 2 control register 2

0x151B Channel 3 control register 2

0x151C Channel 4 control register 2

0x151D Channel 5 control register 2

0x151E Channel 6 control register 2

0x151F Channel 7 control register 2

Address

Range Memory Contents

0x1540 Ch ann el 8 powerup/powerd own regis te r

0x1541 Ch ann el 9 powerup/powerd own regis te r

0x1542 Channel 10 powerup/powerdown register

0x1543 Channel 11 powerup/powerdown register

0x1544 Channel 12 powerup/powerdown register

0x1545 Channel 13 powerup/powerdown register

0x1546 Channel 14 powerup/powerdown register

0x1547 Channel 15 powerup/powerdown register

0x1548 Channel 8 control register 1

0x1549 Channel 9 control register 1

0x154A Channel 10 control register 1

0x154B Channel 11 control register 1

0x154C Channel 12 control register 1

0x154D Channel 13 control register 1

0x154E Channel 14 control register 1

0x154F Channel 15 control register 1

0x1550 All channel test register

0x1557 Single-byte soft reset (no data word)

0x1558 Channel 8 control register 2

0x1559 Channel 9 control register 2

0x155A Channel 10 control register 2

0x155B Channel 11 control register 2

0x155C Channel 12 control register 2

0x155D Channel 13 control register 2

0x155E Channel 14 control register 2

0x155F Channel 15 control register 2

Bit Number and Function

15 14—0

PWR Not used

36 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Software Interface (continued)

Table 24. Bit Map for T7536 Channel Control Register 1 at 0x1508—0x150F and 0x1548—0x154F

Table 25. T7536 Control Register 1: Transmit Gain

Table 26. T7536 Control Register 1: Analog Termination Impedance

* This value is equivalent to the protection resistor value multiplied by 2.

Bit Number and Function

1514—876543210

PWR Not used TX gain Termination impedance LPBK

Bit 7Bit 6Bit 5 Mode

TXGAIN2 TXGAIN1 TXGAIN0

0 0 0 0 dB transmit gain

0 0 1 3.01 dB transmit gain

0 1 0 6.02 dB transmit gain

0 1 1 9.03 dB transmit gain

1 0 0 12.04 dB transmit gain

1 0 1 12.04 dB transmit gain

1 1 0 12.04 dB transmit gain

1 1 1 12.04 dB transmit gain

Bit 4 Bit 3 Bit 2 Bit 1 Gain

(See equation on page 12.) Analog Termination

Impedance (Ω)

TI3TI2TI1TI0

0000 0.0000 165*

0001 0.0583 200

0010 0.1417 250

0011 0.2250 300

0100 0.3083 350

0101 0.3917 400

0110 0.5000 465

0111 0.5583 500

1000 0.6417 550

1001 0.7083 600

1010 0.8083 650

1011 0.8917 700

1100 0.9750 750

1101 1.0583 800

1110 1.2167 895

1111 2.0000 1365

Lucent Technologies Inc. 37

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Software Interface (continued)

Table 27. T7536 Control Register 1: Digital Loopback

Table 28. Bit Map for T7536 All Channel Test Register at 0x1510 and 0x1550

Table 29. Bits 3:0 of T7536 All Channel Test Register at 0x1510 and 0x1550

Notes:

Read out address provides the previous read or write address to CDO whenever a new address is being written into the register.

When analog loopback is high, data that enters the analog transmit path (VTX) is conv erted to a 1.024 MHz digital bit stream and routed back

to the analog receive path (VRP, VRN). The output of the transmit path is available on the oversampled data interface, but receive path over-

sampled data is ignored.

5-5134 (F)

When digital loopback is high, oversampled data receive (OSDR) is routed to oversampled data transmit (OSDX). The receive signal is propa-

gated to VRN/VRP, but any transmit signal from VTX is disconnected. A reference voltage on VRTX is still required in this mode.

5-5135 (F)

Bit 0 Mode

LPBK

0 Norm al oper at ion

1 Digital loopback

Bit Number and Function

15—43210

Not used Read out address Reserved Analog loopback Digital loopback

Bit Number Function

3210

0 — — — Normal operation

1 — — — Read out address

—0—— Reserved

— 1 — — Normal operation

— — 0 — Normal operation

— — 1 — Analog loopback

— — — 0 Normal operation

— — — 1 Digital loopback

OVERSAMPLED

DATA

INTERFACE

A/D, D/A

VTX

VRP

OSDX

OSDR

OVERSAMPLED

DATA

INTERFACE

A/D, D/A

VTX

VRP

OSDX

OSDR

38 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Software Interface (continued)

Table 30. Bit Map for T7536 Channel Control Register 2 at 0x1518—0x151F and 0x1558—0x155F

Notes:

SUSEQ = 0: normal operation.

SUSEQ = 1: start-up calibration sequence.

Table 31. T7536 Control Register 2: Receive Gain

Table 32. T7531A Control Register Map

Note: A board control word controls a function that is common to all 16 channels of a given chip set.

Bit Number and Function

15—8 7 6—3 2 1 0

Not used SUSEQ Not used Receive gain

Bit 2 Bit 1 Bit 0 Mode TLP Levels,

Termination Impedance Is On

RXGAIN2 RXGAIN1 RXGAIN0

0 0 0 6.02 dB receive gain

0 0 1 3.01 dB receive gain

0 1 0 0.0 dB receive gain

0 1 1 –3.01 dB receive gain

1 0 0 –6.02 dB receive gain

1 0 1 –9.03 dB receive gain

1 1 0 –12.04 dB receive gain

1 1 1 –12.04 dB receive gain

Address Range Register Contents Write by Microprocessor Interface

0x1FFE Board control word 1 Y

0x 1FFC Board control word 2 Y

0x1FFA Board control word 3 Y

0x1FF8 Board control word 4 Y

0x1FF6 Board control word 5 Y

Lucent Technologies Inc. 39

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Software Interface (continued)

Table 33. Bits 15:8 of T7531A Board Control Word 1 at 0x1FFE

Table 34. Bits 7:0 of T7531A Board Control Word 1 at 0x1FFE

Notes:

All bits in board control register 1 will be zeros upon hardware reset.

In OSD loopback mode, OSDR0, OSDR1, OSDR2, and OSDR3 are looped back with a delay of two OSCLK clock cycles to OSDX0, OSDX1,

OSDX2, and OSDX3, respectively.

Test modes are for production testing only.

µ-law/A-la w companding mode provides 8 bits of PCM data with the first bit (bit 1) defined as the MSB and the last bit (bit 8) as the LSB. Bit 1 is

the sign bit, bits 2 t hrough 4 are the chord bi ts, and bits 5 through 8 are the interval bits. I n linear mode, the µ-law/A-law conversion in the PCM

interface block is disabled and 16 bits of linear PCM data are provided. In linear mode, bit 1 is the MSB and the sign bit, bits 2 through 14 are

the intervals, and bits 15 and 16 are insignificant. Each interval represents 0.0001362745 Vrms with 8031 intervals being the maximum signal

output of 3 dBm0. Negative values are two’s complement of positive values.

X = don’t care.

Bit Number Function

15 14 13 12 11 10 9 8

0 ——————— Normal operation

1 ——————— Soft reset

———— 0 ——— Normal operation

———— 1 ——— TZ test mode

————— 0 —— Normal operation

————— 1 —— RX dither circuit off

—————— 0 — Normal operation

—————— 1 — Nodecim test mode

——————— 0 Normal operation

——————— 1 Linear mode

Bit Number Function

76543210

0 X—————— Delayed data timing

1 X—————— Nondelayed data timing

—X 0 x ———— µ-law

—X 1 0 ———— A-law, including even bit inversion

—X 1 1 ———— A-law, no even bit inversion

— X — — C1 C0 — — C1C0 = card address in binary

—X———— 0 — Reserved

—X———— 1 — Normal operation

—X————— 0 Normal operation

—X————— 1 Loopback at OSD

40 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Software Interface (continued)

Table 35. Bits 15:9 of T7531A Board Control Word 2 at 0x1FFC

Table 36. Bits 8:0 of T7531A Board Control Word 2 at 0x1FFC

* The f ollowing bit offset values are not valid and should not be used:

When using a 2.048 MHz SCK: bit offset = 0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, and 240.

When using a 4.096 MHz SCK: bit offset = 0, 32, 64, 96, 128, 160, 192, 224, 256, 288, 320, 352, 384, 416, 448, 480.

Note: Bits 15 through 9 are not used; assumed to be zeros. BOF[8:0] provide a fixe d offset, relative to the frame synchronization strobe (S FS),

for the first bit transmitted in each time slot. The offset is the number of data periods by which transmission of the first bit on SDX is

delayed. All subsequent transmi ssions also follow this offset. The default value after hardware reset or powerup is 1A3; howe ver, this reg-

ister must still be written after reset.

Table 37. Bits 15:0 of T7531A Board Control Word 3 at 0x1FFA

Note: For test use only, do not use in normal operation. The default value after hardware reset or powerup is 0.

Table 38. Bits 15:0 of T7531A Board Control Word 4 at 0x1FF8

Note: The default value after hardware reset or powerup is A4.

Table 39. Bits 15:0 of T7531A Board Control Word 5 at 0x1FF6

Note: The default value after hardware reset or powerup is 0.

Table 40. Bits 15:0 of T7531A Reset of Microprocessor Commands at 0x7FFF

Bit Number and Function

15—9

Not used

Bit Number Function

8 7 6 5, 4, 3 2 1 0

BOF8 BOF7 BOF6 BOF5—3 BOF2 BOF1 BOF0 BOF8—0 = Bit offset in binary*

Bit Number and Function

15—5 4—0

Not used TZ test bits

Bit Number and Function

15—10 9—0

Not used CTZ alpha coefficients

Bit Number and Function

15—8 7—0

Not used CTZ beta coefficients

Bit Number Function

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1111111111111111Clear address and data words

in T7531A

Lucent Technologies Inc. 41

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Software Interface (continued)

Table 41 shows the memory map for the DSP engine ROM. The ROM information is not accessible via the micro-

processor. The total ROM size is 4 Kwords.

Table 41. DSP Engine ROM Memory Map

Address Range Memory Contents

0x0003 HDS interrupt service routine

0x0008 Time-slot sync interrupt service routine

0x000B Start-up routine

0x0380 Time segment controller (ts_proc)

0x03B0 Reserved

0x03B8 Reserved

0x0400 Transmit path active routine

0x0500 Receive path active routine

0x0600 Transmit path inactive/loopback routine

0x0610 Transmit path inactive routine

0x0680 Receive path inactive/loopback routine

0x0690 Receive path inactive routine

0x0700 Self-test pass 1 setup (TX)

0x0720 Self-test pass 2 setup (RX)

0x07A0 Tone generation start-up

0x0860 Tone detection start-up

0x0A80 Variance calculation

0x0B00 Peak detection

0x0B60 dc generation

0x0B80 ROM checker

0x0C00 RAM checker

0x0E00 Variance calculation with TX filters

0x0F00 Simultaneous start-up of tone generator and DFT routine

0x0F10 Simultaneous start-up of tone generator and original variance routine

0x0F20 Routine places TX and RX halves of a time slot into inactive loopback

0x0F30 Places TX and RX halves of a time slot into inactive routine

0x0F40 Routine for copying values in channel coefficient table 0 to all 16-channel tables

0x0F60 Approximate location of HDS code

0x0FFE Checksum for ROM 0x0000 : 0x07FF

0x0FFF Checksum for ROM 0x0800 : 0x0FFD

4242 Lucent Technologies Inc.

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Applications

Figure 11 shows a full line card implementation using

the T7531A/T7536 codec and the L7585 SLIC with

integrated relays. One T7531A and two T7536 devices

support 16 SLIC de vices (only one L7585 SLIC is illus-

trated). Figure 11 portrays only the transmission paths

inside the L7585 SLIC. L7585 functionality includes

eight solid-state rela ys, performing ring, test, and break

functions, a ring-trip detector , quiet polarity rev ersal, 13

operating states, and more. For complete functionality

of this SLIC, refer to the L7585 data sheet.

The analog connection between the SLIC and the

codec is direct; no external components are required.

The transfer of control data on the octal interface

between the T7531A and T7536 devices is also direct.

Data is synchronous with OSCK and transmits at a

4.096 MHz rate. The microprocessor control interface

is a standard 4-wire serial port connection, micropro-

cessor clock (UPCK), chip select (UPCS), data input

(UPDI), and output (UPDO). The T7531A generates a

16 MHz clock for microprocessor use. This clock is

always present. The PCM interface consists of a

system clock (SCK) input of either 2.048 MHz or

4.096 MHz, an 8 kHz system frame sync (SFS) input, a

system data transmit port (DX), and a system data

receive (DR) port. Other than power supply decoupling,

the only external components required by the codec

chip set are the two 6.8 kΩ resistors and the three

0.1 µF capacitors. These are required by the internal

clock synthesizer filter circuit of the T7531A. The clock

synthesizer generates a 98.304 MHz master clock for

DSP use.

12-3351.d (F)

* Optional f or quiet reverse battery.

† 4.096 MHz operation; for 2.048 MHz operation, tie SCKSEL to VSS.

Figure 11. 16-Channel Line Card Solution

OSFS

OSCK

OSDR0

OSDR1

OSDX0

OSDX1

CDO

CDI

CODEC 0

T7536

DSP

UPCK

UPCS

UPDI

UPDO

SCK

SFS

SDR

SDX

STSXB

PCM

BUS

CODEC 1

T7536

OSDX2

OSDR2

OSDR3

OSDX3

PCM

INTERFACE

CONTROL

INTERFACE

OCTAL

INTERFACE

OSDX2

OSDR2

OSDR3

OSDX3

CDO

CDI

OSCK

OSFS

OSCK

OSDR0

OSDR1

OSDX0

OSDX1

CDI

CDO

CCS0

CCS1

CCS0

CCS1

DGND

VCCD

RDO

TRNG

RRNG

RSW

RTS

RTI

TTI

CLK

VSP VBAT BGND VCCA AGND

NDET NCSB5 B4 B3 B2 B1 B0

FB1

FB2

CF1

CF2

DCR

DCOUT

IPROG

LCTH

RCVN

RCVP

VTX

VRTX

TXI

VITR

ITR

RELAY

CVD

0.1

CRTF

0.1

RS1

400

Ω

RRTF

1 M

Ω

260 V

SURGE

PROTECTOR

RPR

82.5

Ω

RPT

82.5

Ω

TEST-IN

BUS

1 MHz

CLOCK

RINGING

BUS

CVB

0.1

–48 V CVA

0.1

+5 V

+10 V

FB2*

CF1

0.22

CF2

0.1

RPROG 64.9 k

Ω

RLCTH 2 4.9 k

Ω

+5 V

CB1

0.1

SLIC 0

L7585

PARALLEL DATA BUS TO MICROPROCESSOR

0.1

+5 V

0.1

+5 V

RSTB

SCKSEL

†

RSTB

FILT1

FILT2

0.1

6.8 k

Ω

FILT36.8 k

Ω

0.1

F0.1

CHANNELS

8—15

CHANNELS

1—7

+5 V+5 V

CHANNEL

0VRN0

VRP0

VTX0

VRTX0

TEST

VDDD RSTB

RSTB

CK16

0.1

VSS FVSS

0.1

+5 V

0.1

VDD

2.4 V

RGX1

8.25 k

Ω

TIP

RING

0.047

FB1*

0.047

3231302928271416

VDDA

VSSA

VDDD

VSSD

13 35

10, 36 44

17, 34

15 37

VDDA

VSSA

VDDD

VSSD

FVDD

MICRO-

PROCESSOR

T7531A

Lucent Technologies Inc. 43

Data Sheet

February 1999 Codec Chip Set

T7531A/T7536 16-Channel Programmable

Outline Diagram

68-Pin PLCC

Dimensions are in millimeters. The controlling dimensions are in inches.

Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-

ics to assist your design efforts, please contact your Lucent Technologies Sales Representative.

5-2139.r13 (F)

27 43

PIN #1 IDENTIFIER ZONE

25.146 ± 0.127

24.231 ± 0.102

25.146

± 0.127

24.231

± 0.102

1.27 TYP 0.330/0.533

5.080

MAX

0.51 MIN,

TYP

SEATING PLANE

0.10

Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No

rights under any patent accompany the sale of any such product(s) or information.

February 1999

DS99-093ALC (Replaces DS98-272ALC)

For additional information, contact your Microelectronics Group Account Manager or the following:

INTERNET: http://www.lucent.com/micro

E-MAIL: docmaster@micro.lucent.com

N. AMERICA:Microelectro nics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allen t own, PA 18103

1-800-372-2447, FAX 610-712-4106 ( In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA PACIFIC:Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cinte ch III, Singapore 118256

Tel. (65) 778 8833, FAX (65) 777 7495

CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai

200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652

JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan

Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700

EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148

Technical Inquiries:GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),

FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki),

ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)

Data Sheet

February 1999

Codec Chip Set

T7531A/T7536 16-Channel Programmable

Ordering Information

Device Code Package Temperature Comcode

T-7531A - - - ML 68-Pin PLCC –40 °C to +85 °C 107529729

T-7531A - - - ML-TR 68-Pin PLCC –40 °C to +85 °C 107578627

T-7536 - - - ML 68-Pin PLCC –40 °C to +85 °C 107393993

T-7536 - - - ML-TR 68-Pin PLCC –40 °C to +85 °C 107412041