Data Sheet February 1999 T7531A/T7536 16-Channel Programmable Codec Chip Set Features Single 5 V power supply operation Per-channel programmable transmit gain -- 19.4 dB range, better than 0.01 dB steps Per-channel programmable receive gain -- 25.4 dB range, better than 0.01 dB steps Per-channel programmable internal balance networks Programmable termination impedances Automatic gain calibration Advanced board- and self-test capability Programmable time-slot assignment Data rate of 2.048 MHz or 4.096 MHz Differential transmit amplifiers Single-ended or differential receive amplifiers Analog and digital loopbacks Sigma-delta converters with dither noise reduction VRP (8) JTAG test port The T7531A is a custom, 16-channel line card signal processor which, together with a pair of custom T7536 octal A/D and D/A converters, comprises a low-cost, highly programmable voice codec that is compatible with all worldwide POTS lines. VRTX (8) Serial microcontroller control interface General Description Per-channel programmable -law, A-law, or linear PCM output VTX (8) Transmit and receive gains and hybrid balance coefficients are programmable per channel. Termination impedance is programmable per chip set. These functions, as well as time-slot assignment, calibration, and board test, are controlled via a microcontroller interface. The DSP engine in the T7531A can be used to test the line card. When voice processing is not required, the spare processing time can be allocated on a perline basis to a suite of user-controlled board-test routines. Providing intelligent board-test functionality at the line-card level frees the switch from having to perform test and error diagnosis tasks. 2 T7536 OCTAL A/D D/A 3 PCM INTERFACE VRN (8) 2 VTX (8) VRTX (8) VRP (8) T7536 OCTAL A/D D/A T7531A DIGITAL SIGNAL PROCESSOR CK16 3 MICROPROCESSOR INTERFACE VRN (8) 5-3793.c (F) Figure 1. System Block Diagram T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Table of Contents Contents Page Features ..................................................................... 1 General Description.................................................... 1 T7536 Description.................................................... 4 T7531A Description ................................................. 5 Pin Information ........................................................... 7 Chip Set Functional Description ............................... 12 Transmit Path......................................................... 12 Receive Path.......................................................... 13 Other Chip Set Functions....................................... 13 T7531A Functional Blocks ..................................... 14 DSP Engine Timing................................................ 16 T7531A Program Structure .................................... 16 Control of the DSP Engine via the Microprocessor Interface .............................................................. 17 The DSP Engine Time-Slot Information Tables ..... 17 The DSP Engine ac Path Coefficient Table ........... 17 The Time-Slot Control Word .................................. 18 Operations Performed by the DSP Engine at T7531A Start-Up ................................................. 18 Microprocessor Start-Up of the DSP Engine ......... 19 Powering Up a Time Slot in the T7531A................ 19 Disabling a Time Slot in the T7531A...................... 19 T7536 Powerup/Powerdown.................................. 19 Changing DSP RAM Space of an Active Time Slot ...................................................................... 20 DSP Engine Memory Requirements ...................... 20 T7531A Reset and Start-Up................................... 20 Hardware Reset ..................................................... 20 Internal Reset......................................................... 21 Reset of the T7536 Devices................................... 21 Start-Up After Internal Reset.................................. 21 Autocalibration ........................................................ 22 User Test Features ................................................ 22 Self-Test and Board-Test Routines......................... 22 Handling Precautions ............................................... 23 Absolute Maximum Ratings...................................... 23 Electrical Characteristics .......................................... 24 dc Characteristics .................................................. 24 Transmission Characteristics ................................... 25 Timing Characteristics .............................................. 29 Software Interface .................................................... 32 Applications ............................................................... 42 Outline Diagram........................................................ 43 68-Pin PLCC .......................................................... 43 Ordering Information................................................. 44 2 Figures Page Figure 1. System Block Diagram ................................ 1 Figure 2. Block Diagram of T7536 Octal Converter .... 4 Figure 3. Block Diagram of One T7536 Analog Channel ....................................................... 4 Figure 4. T7531A Block Diagram ................................ 5 Figure 5. T7531A Digital ac Path ................................ 6 Figure 6. Control, PCM, and Octal Interfaces .............6 Figure 7. T7536 68-Pin PLCC .................................... 7 Figure 8. T7531A 68-Pin PLCC .................................. 8 Figure 9. Timing Characteristics of PCM Interface Assuming 2.048 MHz SCK Rate ...............30 Figure 10. Timing Diagram for Microprocessor Write/Read to/from the DSP on the Control Interface ......................................31 Figure 11. 16-Channel Line Card Solution ...............42 Lucent Technologies Inc. Data Sheet February 1999 T7531A/T7536 16-Channel Programmable Codec Chip Set Table of Contents Tables Page Table 1. T7536 Pin Descriptions ............................................................................................................................. 9 Table 2. T7531A Pin Descriptions ........................................................................................................................ 10 Table 3. Active Time-Slot Spacing in a PCM Bus Frame ...................................................................................... 15 Table 4. DSP Engine RAM Map for Channel_0 ac Path Coefficients ................................................................... 17 Table 5A. Bit Maps for DSP Engine Time-Slot Control Word .............................................................................. 18 Table 5B. Bit Map for Default Per-Board Coefficient Tables ................................................................................... 18 Table 6. DSP Engine RAM Map for Time-Slot Information Table 0 ....................................................................... 18 Table 7. Summary of Microprocessor Commands for Control of T7531A Data Processing ................................. 20 Table 8. Digital Interface ....................................................................................................................................... 24 Table 9. Analog Interface ...................................................................................................................................... 24 Table 10. T7536 Power Dissipation ...................................................................................................................... 25 Table 11. T7531A Power Dissipation .................................................................................................................... 25 Table 12. Gain and Dynamic Range ..................................................................................................................... 25 Table 13. Noise (per Channel) .............................................................................................................................. 27 Table 14. Distortion and Group Delay .................................................................................................................. 28 Table 15. Crosstalk ............................................................................................................................................... 28 Table 16. PCM Interface Timing ............................................................................................................................ 29 Table 17. Serial Control Port Timing ...................................................................................................................... 31 Table 18. DSP Engine RAM Memory Map ........................................................................................................... 32 Table 19. T7531A Time-Slot Assignment Memory Map ........................................................................................ 34 Table 20A. Bit Map for T7531A Time-Slot Assignment Registers at 0x1400--0x140F ........................................ 34 Table 20B. Bit Map for CTZ Disable and Null Channel ......................................................................................... 34 Table 21. T7531A Channel Register Memory Map for T7536 Device 0 ................................................................ 35 Table 22. T7531A Channel Register Memory Map for T7536 Device 1 ................................................................ 35 Table 23. Bit Map for T7536 Powerup/Powerdown Registers at 0x1500--0x1507 and 0x1540--0x1547 ............ 35 Table 24. Bit Map for T7536 Channel Control Register 1 at 0x1508--0x150F and 0x1548--0x154F .................. 36 Table 25. T7536 Control Register 1: Transmit Gain .............................................................................................. 36 Table 26. T7536 Control Register 1: Analog Termination Impedance ................................................................... 36 Table 27. T7536 Control Register 1: Digital Loopback .......................................................................................... 37 Table 28. Bit Map for T7536 All Channel Test Register at 0x1510 and 0x1550 .................................................... 37 Table 29. Bits 3:0 of T7536 All Channel Test Register at 0x1510 and 0x1550 ...................................................... 37 Table 30. Bit Map for T7536 Channel Control Register 2 at 0x1518--0x151F and 0x1558--0x155F .................. 38 Table 31. T7536 Control Register 2: Receive Gain ............................................................................................... 38 Table 32. T7531A Control Register Map ............................................................................................................... 38 Table 33. Bits 15:8 of T7531A Board Control Word 1 at 0x1FFE ......................................................................... 39 Table 34. Bits 7:0 of T7531A Board Control Word 1 at 0x1FFE ........................................................................... 39 Table 35. Bits 15:9 of T7531A Board Control Word 2 at 0x1FFC ......................................................................... 40 Table 36. Bits 8:0 of T7531A Board Control Word 2 at 0x1FFC ........................................................................... 40 Table 37. Bits 15:0 of T7531A Board Control Word 3 at 0x1FFA ......................................................................... 40 Table 38. Bits 15:0 of T7531A Board Control Word 4 at 0x1FF8 ......................................................................... 40 Table 39. Bits 15:0 of T7531A Board Control Word 5 at 0x1FF6 ......................................................................... 40 Table 40. Bits 15:0 of T7531A Reset of Microprocessor Commands at 0x7FFF ................................................. 40 Table 41. DSP Engine ROM Memory Map ........................................................................................................... 41 Lucent Technologies Inc. 3 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 General Description (continued) T7536 Description The T7536 block diagram is shown in Figure 2. Each of its eight channels consists of an antialias filter, sigma-delta A/D and D/A converters, reconstruction and smoothing filters, termination impedance synthesis, and selectable gain. The digital oversampled data is multiplexed onto a serial data port designed to interface with the T7531A. Another serial interface accepts control data from the T7531A for activating the various gain settings, self-test, and powerdown modes. This chip also contains a precision voltage reference. It is packaged in a 68-pin PLCC. VTX[7:0] OSDX[1:0] 8-CHANNEL A/D D/A VRTX[7:0] VRP[7:0] ANALOG HYBRID & TERMINATION VRN[7:0] OSDR[1:0] OVERSAMPLED DATA INTERFACE OSCK OSFS VDDA CDO CDI VSSA VOLTAGE REFERENCE VDD CONTROL INTERFACE CCS RSTB VSS 5-3794.b (F) Figure 2. Block Diagram of T7536 Octal Converter DIGITAL LOOPBACK VTX AAF* GAIN VRTX AT GAIN 1.024 MHz - A/D V REFERENCES VRP VRN SUM GAIN RECEIVE FILTER 1.024 MHz D/A 5-3796.d (F) * Antialiasing filter. Figure 3. Block Diagram of One T7536 Analog Channel 4 Lucent Technologies Inc. T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 General Description (continued) T7531A Description As shown in Figure 4, the T7531A contains a digital signal processor (DSP) engine surrounded by a customized input/output frame. The I/O frame performs the -law or A-law conversion as well as the decimation and interpolation functions needed to interface the sigma-delta bit streams to the digital signal processor engine. The sigmadelta converters operate at a 1.024 MHz sample rate, while the signal processor operates at 16 ksamples/s. A key function of the I/O frame is to control the timing of the digital data going to the signal processor so that group delay is minimized. The I/O frame also contains an integrated phase-locked loop which synthesizes all the required internal clocks for the chip set. STSXB SCK SFS SDR SDX FVSS CK16 FVDD FILT1 TDO TDI TCK TMS FILT2 The microcontroller interface is used to download the gain and balance network settings, powerup/powerdown commands, time-slot assignments, digital loopback settings, and commands for the T7536 octal chips. This chip is packaged in a 68-pin PLCC. SYSTEM PCM INTERFACE PLL CLOCK SYNTHESIZER DATA TRANSFER UPCS /A-LAW CONVERTER UPCK MICROPROCESSOR CONTROL INTERFACE JTAG DIGITAL SIGNAL PROCESSING ENGINE HDS DSP ROM UPDI UPDO HIGHZB RSTB DSP RAM T_SYNC TSTCLK TSA DECIMATOR TEST VDD INTERPOLATOR VSS CDI CDO CCS1 OSDX/R[3:0] T7536 CONTROL INTERFACE CCS0 OSFS OSCK T7536 OVERSAMPLED INTERFACE 5-3795.c (F)r03 Figure 4. T7531A Block Diagram Lucent Technologies Inc. 5 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 General Description (continued) T7531A Description (continued) 8 kHz PCMRX /A-LAW TO LINEAR RECV FILTER ABS RDG REL RDG INTERPOLATOR BALANCE FILTER 8 kHz PCMTX LINEAR TO /A-LAW REL TGD XMT FILTER DIGITAL - 1.024 MHz CTZ FILTER 1.024 MHz DECIMATOR / 64 ABS TGD 5-3797.b (F) Figure 5. T7531A Digital ac Path OCTAL INTERFACE T7536 CODEC 0 CONTROL INTERFACE T7531A OSFS OSCK 8 kHz SYNC 4 MHz CLOCK OSFS OSCK OSDR0 4 CH RX DATA OSDR0 OSDR1 OSDX0 OSDX1 4 CH RX DATA OSDR1 4 CH TX DATA 4 CH TX DATA CHIP SELECT OSDX0 OSDX1 CCS0 CDI CDO CODEC 1 CLOCK UPCS UPDI CHIP SELECT CONTROL REGISTER IN UPDO CONTROL REGISTER OUT MICROPROCESSOR CCS0 CONTROL REGISTER CONTROL REGISTER CDO CDI DSP T7536 UPCK SCK SFS SDR SDX STSXB CDI CDO OSFS OSCK CCS1 CHIP SELECT CCS1 OSDR2 4 CH RX DATA OSDR2 OSDR3 4 CH RX DATA OSDR3 OSDX2 4 CH TX DATA OSDX2 OSDX3 4 CH TX DATA OSDX3 CLOCK FRAME SYNC DATA RECEIVE DATA TRANSMIT PCM BUS BACKPLANE DRIVER ENABLE PCM INTERFACE 5-4229.b (F) Figure 6. Control, PCM, and Octal Interfaces 6 Lucent Technologies Inc. T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 VTX7 VDDA VSSD OSDR1 OSDX1 OSDX0 OSDR0 OSCK OSFS RSTB TEST CDI CCS CDO VDDD VDDA VTX0 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 Pin Information VRTX7 10 60 VRTX0 VRP7 11 59 VRP0 VRN7 12 58 VRN0 VSSA 13 57 VSSA VRN6 14 56 VRN1 VRP6 15 55 VRP1 VRTX6 16 54 VRTX1 VTX6 17 53 VTX1 VDDA 18 52 VDDA T7536 VTX5 19 51 VTX2 VRTX5 20 50 VRTX2 VRP5 21 49 VRP2 VRN5 22 48 VRN2 37 38 39 40 NC VDDA NC NC 43 36 NC VTX3 35 NC 42 34 NC 41 33 NC NC 32 NC VDDA 31 VRTX3 VSSA VRP3 44 30 45 26 NC 25 29 VRP4 VRTX4 NC VRN3 28 VSSA 46 27 47 24 VDDA 23 VTX4 VSSA VRN4 5-4230.b (F) Figure 7. T7536 68-Pin PLCC Lucent Technologies Inc. 7 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 TDO TDI VDD VSS NC 63 62 61 1 64 VDD VSS 2 TMS FVDD 3 65 FILT1 4 66 FILT2 5 TSTCLK FVSS 6 TCK FILT3 7 67 VSS 8 68 VDD 9 Pin Information (continued) SCKSEL 10 60 NC VSS 11 59 VSS VDD 12 58 VDD SCK 13 57 CK16 SFS 14 56 TEST SDR 15 55 HIGHZB SDX 16 54 RSTB STSXB 17 53 VSS T7531A VDD 18 52 VDD VSS 19 51 T_SYNC UPCK 20 50 CDO UPCS 21 49 CCS1 33 34 35 36 37 38 39 40 41 42 43 OSCK OSFS VSS OSDR3 OSDX3 OSDR2 OSDX2 VDD VSS NC NC 32 44 OSDX0 26 OSDR0 NC 31 VSS 30 VDD 45 OSDX1 46 25 OSDR1 24 VSS 29 VDD 28 CDI VSS CCS0 47 VDD 48 23 27 22 NC UPDI UPDO 5-4231.b (F) Figure 8. T7531A 68-Pin PLCC 8 Lucent Technologies Inc. T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Pin Information (continued) Table 1. T7536 Pin Descriptions Number Name Type 9, 17, 19, 27, 43, 51, 53, 61 10, 16, 20, 26, 44, 50, 54, 60 11, 15, 21, 25, 45, 49, 55, 59 12, 14, 22, 24, 46, 48, 56, 58 8, 18, 28, 38, 42, 52, 62 VTX[7:0] AI Analog Input. Transmit signal voltage to be encoded. VRTX[7:0] AI VRP[7:0] AO VRN[7:0] AO VDDA -- Transmit Reference Voltage. +2.4 V reference. Each pin must have a separate supply associated with the corresponding VTX pin. Noninverting Receive Output. This pin can drive high-impedance loads either differentially or single ended. It is the complement of the VRN output. Inverting Receive Output. This pin can drive high-impedance loads either differentially or single ended. It is the complement of the VRP output. +5 V Analog Power Supply. Power supply decoupling capacitor (0.1 F) should be connected from each VDDA pin to analog ground. Capacitors should be located as close as possible to the device pins. Analog Ground. 13, 23, 31, 47, 57 63 VSSA -- VDDD -- 7 5, 4 VSSD OSDX[1:0] -- CO 6, 3 OSDR[1:0] CI 2 OSCK CI 1 OSFS CI 66 CDI CI 64 CDO CO 65 CCS CI 68 RSTB TIu 67 TEST TId 29, 30, 32--37, 39--41 NC -- Name/Function +5 V Digital Power Supply. Decouple with a 0.1 F capacitor to digital ground. Digital Ground. Oversampled Transmit Data. Four channels of 1.024 MHz - transmit data is transmitted to the T7531A through each of these pins. The data rate is 4.096 MHz. Oversampled Receive Data. Four channels of 1.024 MHz - receive data is received from the T7531A on each of these pins. The data rate is 4.096 MHz. Interface Clock. The 4.096 MHz clock that enters this pin from the T7531A serves as the bit clock for all the oversampled data transmission between this chip and the T7531A. This is the master clock input for the T7536. Interface Frame Sync. This signal serves as the frame sync for the oversampled data interface between the T7536 and the T7531A. Control Data Interface Input. The T7531A sends control register address and data to the T7536 through this pin. One address byte and one data byte are accepted each time CCS is toggled. Control Data Interface Output. Control register contents are clocked out through this pin. Control Interface Chip Select (Active-Low). This active-low input enables the control interface. Reset (Active-Low). This input must be pulled high for normal operation. When pulled momentarily low (at least 1 s) while OSCK is active, all programmable registers in the device are reset to the states specified under powerup initialization. This pin has an internal pull-up resistor. Test. This pin is for factory test purposes only. Connect to VDDD for normal operation. This pin has an internal pull-down resistor. No Connect. No connection to chip. These pins can be used as logic level tie points. Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; Id indicates a pull-down device is included on this lead, Iu indicates a pull-up device is included on this lead. Lucent Technologies Inc. 9 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Pin Information (continued) Table 2. T7531A Pin Descriptions Number Name Type Name/Function 22 UPDI TI 23 UPDO TO 20 UPCK TI 21 UPCS TI 38, 40, 31, 33 OSDX[3:0] CI 37, 39, 30, 32 OSDR[3:0] CO 34 35 OSCK OSFS CO CO 4 FILT1 -- 5 FILT2 -- 7 FILT3 -- 3 6 17 FVDD FVSS STSXB -- -- TO 13 SCK TI 10 SCKSEL TIu 15 SDR TI Control Data Interface Input. The microcontroller sends control register address and data to the T7531A through this pin. Control Data Interface Output. The microcontroller receives control register contents from this pin. Inactive state is high impedance. Control Data Interface Clock. Bit clock for the control interface. Speed is limited to 4.096 MHz. Control Interface Chip Select (Active-Low). This active-low input enables the control interface. Oversampled Transmit Data. Four channels of 1 Msamples/s - transmit data are received from the T7536 chips through each of these pins. The data rate is 4.096 MHz. Oversampled Receive Data. Four channels of 1 Msamples/s - receive data is transmitted to the T7536 chips on each of these pins. The data rate is 4.096 MHz. 4.096 MHz Clock. Clock for data transfer to/from T7536 chips. Oversampling Sync. 8 kHz synchronization pulse for data transfer to/from T7536 chips. Filter. External filter pin for the clock synthesizer block. Connect a 6.8 k, 10% resistor in series with a 0.1 F, 20% capacitor to ground. Placement of these components is not as critical as power supply decoupling capacitor placement. Filter. External filter pin for the clock synthesizer block. Connect a 6.8 k, 10% resistor in series with a 0.1 F, 20% capacitor to ground. Placement of these components is not as critical as power supply decoupling capacitor placement. Filter. External filter pin for the clock synthesizer's voltage regulator. Connect a 0.1 F, 20% capacitor to ground. Synthesizer VDD. Power supply for clock synthesizer block. Synthesizer Ground. Ground connection for the clock synthesizer block. Backplane Drive Enable (Active-Low). Active when SDX is transmitting valid data; high impedance otherwise. This pin provides an enable signal for a backplane line driver. Master Clock Input. This is the bit clock used to shift data into and out of the SDR and SDX pins. It is the input to the clock synthesizer and is used to generate all internal clocks. Rate is 4.096 MHz. Master Clock Select Input. A logic low selects the 2.048 MHz SCK. A logic high selects the 4.096 MHz SCK. An internal pull-up device is included, providing 4.096 MHz SCK operation with no external connections. Receive PCM Input. The data on this pin is shifted into the T7531A on the falling edges of SCK. Data is only entered for valid time slots as defined in the TSA registers. Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; Iu indicates a pull-up device is included on this lead. 10 Lucent Technologies Inc. T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Pin Information (continued) Table 2. T7531A Pin Descriptions (continued) Number Name Type Name/Function 16 SDX TO 14 SFS TI 50 CDO CO 47 CDI TIu 49, 48 CCS[1:0] CO 67 64 65 66 55 TCK TDI TDO TMS HIGHZB TI TIu TO TIu TIu 56 TEST CIu 57 68 CK16 TSTCLK CO CI 26, 27, 43, 44, 60, 61 51 NC -- Transmit PCM Output. This pin remains in the high-impedance state except during the transmit time slots as defined in the TSA registers. Data is shifted out on the rising edge of SCK. Frame Sync. Active-high pulse or square wave with an 8 kHz pulse repetition rate. The rising edge defines the start of the transmit and receive frames. T7536 Control Data Output. Control register information for the T7536 chips. Data is valid only when either CCS0 or CCS1 is low. T7536 Control Data Input. Control register information from the T7536 chips. Data is valid only when either CCS0 or CCS1 is low. An internal pull-up device is provided. Control Interface Chip Select. These active-low outputs select one of the associated T7536 chips. JTAG Common Test Clock. Rate 20 MHz. JTAG Serial Data Input. A pull-up device is provided. JTAG Serial Data Output. JTAG Mode Select. A pull-up device is provided. 3-State Control Pin (Active-Low). When pulled low, the device output pins go into a high-impedance state. A pull-up device is provided. Test Mode Input (Active-Low). This input allows bypass of clock synthesizer and uses TSTCLK to drive the chip. A pull-up device is provided. 16 MHz Clock Output. 16 MHz clock output (50% duty cycle). Test Clock. Test mode 98.304 MHz clock input for bypass of clock synthesizer. No Connect. Do not make any connections to these pins. T_SYNC CIu 54 RSTB TIu 2, 9, 12, 18, 24, 29, 41, 46, 52, 58, 63 1, 8, 11, 19, 25, 28, 36, 42, 45, 53, 59, 62 VDD -- VSS -- Test Sync (Active-Low). Used for factory testing. Do not make any connection to this pin. A pull-up device is provided. Reset (Active-Low). A logic low initiates reset. A pull-up device is provided. +5 V Digital Power Supply. Power supply decoupling capacitors (0.1 F) should be connected from each VDD pin to ground. Capacitors should be located as close as possible to the device pins. Digital Ground. Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; Iu indicates that a pull-up device is included on this lead. Lucent Technologies Inc. 11 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Chip Set Functional Description for TX gain equalization. For the case of 0 dB transmit gain, this level is found as: Transmit Path (3.2 V/log -1 (3.15/20)) = 2.23 Vp-p. Antialias Filter and - Converter This level is the worst-case 0 dBm0 level. The line interface circuit must provide a transmit signal, VTX, and a reference voltage, VRTX, which is the dc voltage of the VTX signal for that channel. Decimator The input signal goes into a programmable-gain amplifier. The signal is then passed through an antialias filter followed by a - A/D converter. The - converter operates at 1.024 MHz. The processed output signals are multiplexed into two groups of four channels each onto output pins OSDX[1:0], each of which operates at 4.096 MHz. A precision, on-chip voltage reference helps ensure accurate and highly stable transmission levels. It is important to understand the difference between how the gain levels should be set in the T7536 and how these levels would be set in a standard codec. The T7536 is best thought of as a data acquisition system, not a codec. Hybrid balance, fine gain adjust, - or A-law coding, filtering, and equalization are done after the A/D in the T7536 by the DSP processor in the T7531A. The analog gain adjust taps should not be used to set the absolute level at the PCM output. This can be done using the DSP gain adjust taps. The analog taps should be set so the signal at the input to the A/D converter is as close as possible to the full-scale input level of the A/D for the largest signal level that will be present at the VTX input. This optimizes the dynamic range of the A/D. The 0 dB gain tap should thus be used if the maximum signal level is in the range between 2.25 Vp-p and 3.2 Vp-p. The 3 dB tap should be used for signals with a maximum signal level in the range between 1.6 Vp-p and 2.25 Vp-p. The 6 dB tap should be used for signals with a maximum signal level in the range between 1.1 Vp-p and 1.6 Vp-p. Higher gain levels should be used for signals with smaller absolute levels. The signal level to produce a 0 dBm0 level at the digital transmit output of the T7531A is not a fixed quantity as explained above. For a line with a complex impedance or an RX echo signal, extra headroom must be allowed and the TX signal level must be set to account for the headroom. In this specification, the largest possible 0 dBm0 level for the TX signal is assumed. This guarantees that the distortion specification will not be exceeded for all practical 0 dBm signal levels. The largest possible 0 dBm signal is one that has no headroom 12 The decimator filters out the high-frequency components and down-samples to 16 kHz. It also reorders the 16 channels of transmit signals into a sequence that is determined by the time-slot assignment. Digital Transmit Gain Adjustment The transmit absolute and relative gains are specified as 15-bit binary numbers representing their linear magnitude. These gains default to 4000 Hex. This equates to a 0 dB gain for the relative gain but equates to a 1.65 dB gain for the absolute gain. For a 0 dB gain, program the absolute gain for 34ED Hex. Gain can be varied from minus infinity dB (off) (0000 Hex) to 6 dB relative gain or 7.65 dB absolute gain (7FFF Hex). The relative gain control allows TLP adjustment without hybrid balance or termination coefficient modification. Band Filtering The bandpass filter in the transmit path removes power line and ringing frequencies, and eliminates most of the signal energy at 4 kHz and above. This allows the encoder to transmit the filtered signal at 8 ksamples/s, the worldwide standard. The transmit filtering is implemented with a low-pass filter, followed by a high-pass filter. The data samples enter the filter at 16 ksamples/s. They are first low-pass filtered to 3.4 kHz. After low-pass filtering, the sampling rate is reduced to 8 ksamples/s. The samples are then high-pass filtered to 300 Hz. The low-pass filter also serves as an equalizer for complex termination impedance cases. A given set of equalizer coefficients that modify this filter are required for each complex termination impedance. These are supplied in the user manual. -Law, A-Law, and Linear PCM Modes In the transmit path, the 8 ksamples/s PCM signal output from the filter is processed prior to transmission over the system interface. The 16-bit linear PCM signal may be compressed according to either -law or A-law, or transmitted as two consecutive 8-bit words. The selection is programmable via the microprocessor interface. Please note, when using A-law, a linear value of 0 is always encoded as 7F. Lucent Technologies Inc. Data Sheet February 1999 Chip Set Functional Description (continued) Receive Path In the receive direction, the signal received from the system interface is converted to a 16-bit linear PCM signal. Receive Path Filtering The 16-bit linear PCM signal is filtered and interpolated to 16 ksamples/s to meet the receive signal loss characteristics. This filter smooths the data following interpolation from 8 ksamples/s to 16 ksamples/s. Digital Receive Gain The receive absolute and relative gains are specified as 15-bit binary numbers representing their linear magnitude. These gains default to 4000 Hex. This equates to a 0 dB gain for the relative gain but equates to a -0.211 dB gain for the absolute gain. For a 0 dB gain, program the absolute gain for 4193 Hex. Gain can be varied from minus infinity dB (0) (0000 Hex) to 6 dB relative gain or 5.8 dB absolute gain (7FFF Hex). The relative gain control allows TLP adjustment without hybrid balance or termination coefficient modification. Interpolator and Digital Sigma-Delta Modulator The sampling frequency of the receive signal from the digital gain adjustment is increased from 16 kHz to 64 kHz by the interpolator, which removes most of the high-frequency signal images above 8 kHz. The interpolator also maps each of 16 time slots to the appropriate line channel through the digital sigma-delta modulator. The digital sigma-delta modulator converts the interpolated signal to a 1.024 MHz bit stream which is then sent to the T7536 device. Decoder, Filters, and Receive Amplifier Receive data enters the T7536 on pins OSDR[1:0] at 4.096 MHz; four channels are time-division multiplexed onto each pin. The data is demultiplexed into eight individual channels. The processed signal for each channel passes through switched-capacitor D/A and reconstruct filters, followed by a smoothing filter. A programmable gain amplifier is included, followed by an output amplifier capable of driving a 50 k load to 1.58 V single-ended (relative to VOS) or 3.16 V differential at peak overload. For single-ended operation, the load must be ac coupled to VRP (or VRN). Lucent Technologies Inc. T7531A/T7536 16-Channel Programmable Codec Chip Set Other Chip Set Functions Voltage Reference The T7536 has a precision on-chip voltage reference which ensures accurate and highly stable transmission levels. Hybrid Balance The hybrid balance function is provided as a digital block in the T7531A. The T7531A implements a 9-tap FIR and a single-pole IIR digital balance filter in which a replica of the echo is digitally subtracted from the transmit plus near-end echo signal. The coefficients are user programmable on a per-line basis via the microprocessor interface. Analog Termination Impedance Synthesis Termination impedance matching is implemented to maximize the power transfer capability at the loop interface and to minimize signal reflections between the transmit and receive paths. The resistive component, implemented in the T7536 device, comprises a variable attenuated path between VTX and VRP. The capacitive component is implemented in the digital domain. Analog termination impedance (ATI) is provided with 16 gain settings to match a voltage drive/current sense line interface circuit with the following characteristics: ZT = 2RP + GTX * GRX * AT where ZT is the termination impedance in ohms, RP = 82.5 is the resistance of each protection resistor, GTX is the SLIC transmit gain (300 V/A for the L7585), GRX is the SLIC receive gain (2 for the L7585), and AT is the T7536 feedback gain. The polarity of the AT gain is positive (positive voltage swing on VTX gives a positive voltage swing on VRP). The gain values and the corresponding effective termination impedance are shown in Table 26; gain tolerances are 2%. Differential receive output is assumed. 13 T7531A/T7536 16-Channel Programmable Codec Chip Set Chip Set Functional Description (continued) Other Chip Set Functions (continued) Digital Termination Impedance Synthesis The CTZ filter in the T7531A synthesizes complex termination impedances. The CTZ filter utilizes alpha and beta coefficients (board control words 4 and 5, respectively) to perform the synthesis. One set of alpha and beta coefficients is required for each termination impedance and balance network. These are provided in the user manual. Alpha bits [9:0] represent the RC time constant of the impedance that the filter is going to synthesize. The bits are formatted as two's complement. Alpha bits must be a nonzero value. Beta bits [7:0] represent the dc gain of the filter. Beta coefficients are also formatted as two's complement. Setting beta equal to zero turns off the CTZ function. There is a constraint on the value of the protection resistor with regard to termination impedance synthesis and hybrid balance. For synthesis to operate properly, the total series Tip/Ring resistance must be 165 or greater. Coefficients for use with the L7585 SLIC are set up for a protection value resistance of 82.5 in Tip and 82.5 in Ring. Loopback Modes There are four loopback modes in the T7536. Data Sheet February 1999 back mode can be used to check T7536 functionality from the T7531A device. It is also used during the calibration sequence. There is one loopback mode in the T7531A. Loopback at the oversampled data interface is controlled by board control word 1. This mode allows the T7531A to test itself. When bit 0 of 0x1FFE is selected, all 16 channels of octal interface receive data (OSDRn) are looped back to the T7531A transmit inputs (OSDXn). Interchip Control Interface The control interface is a 4-pin interface used to send control information to the T7536 from the T7531A, and to read back the control register contents. The pins consist of a chip select input (CCS0/CCS1), a data input (CDI), and a data output (CDO). The transfer of control data is synchronous with the 4.096 MHz OSCK, which is also used for oversampled data transfer. T7531A Functional Blocks Clock Synthesizer The clock synthesizer block is a phase-lock loop (PLL) circuit which takes SCK supplied by the backplane and uses it to produce the 98.304 MHz DSP engine clock. The input clock, SCK, can be 2.048 MHz or 4.096 MHz. An on-chip clock synthesizer has the advantages shown below: The first two loopback modes are controlled by the all channel test (ACT) register. ACT bits 0 and 1 place all eight channels into loopback mode. Analog and digital loopback are described and shown in block diagram form in Table 29. Analog loopback allows one to check functionality from Tip/Ring up to and including the T7536. Digital loopback allows the T7531A to check T7536 functionality. Precludes the need for extra clocks to be fed over the backplane. Constrains the high-speed DSP engine clock within the device. Synchronizes all clocks used on the line card to the backplane clock, thus reducing board noise due to beat frequencies. The third loopback mode is used in the autocalibration sequence (control register 2). This mode provides a loopback between a selected channel and channel four of a given T7536. The channel to be calibrated is selected via control register 1 (see Table 27). Channel four is the only channel in the T7536 that is trimmed for gain accuracy. Every other channel uses channel four as a reference and is calibrated to it during the autocalibration sequence. A clock generator block takes the PLL output and divides it down to produce all the lower-frequency clocks used by the T7531A and T7536. The fourth loopback mode is a digital loopback mode located in control register 1. This operates like the digital loopback mode described in the notes for the ACT register (Table 29). Unlike the ACT register, this digital loopback mode is selectable per channel. This loop14 T7531A System Interface The system interface is a full-duplex interface used for the exchange of PCM data with the system. The system is the master of this bus. No control information is transmitted over the system interface; all control instructions are routed over the microprocessor interface. Lucent Technologies Inc. T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Chip Set Functional Description T7531A Microprocessor Interface (continued) This interface between the microprocessor (or other external controller) and the T7531A device carries user-supplied program variables and control and test instructions to both the T7531A and the T7536 octal converters. The external device is the master of the microprocessor interface. The interface is serial and asynchronous, and consists of four pins (UPCK, UPCS, UPDI, UPDO). The data rate is determined by the customer's choice of external device, but may not exceed 4.096 MHz. Microprocessor interface commands consist of two words, address and data. Address and data are 16 bits wide. The T7531A expects an address first. The first bit of the address word is the R/W flag, which tells the T7531A whether it must receive or send data (receive, R/W = 0; send, R/W = 1). T7531A Functional Blocks (continued) The system interface is used for all 16 lines serviced by the T7531A. The PCM data rate is 8 ksamples/s/line, so the total required channel capacity is 16 x 8 = 128 Kwords/s in each direction. At the 4.096 MHz rate, each word takes 1.95 s to transmit interleaved with 5.86 s of dead time. The frame sync, SFS, is presented to the system interface at an 8 kHz rate. A single bit clock and frame sync are used to control both the transmit and receive directions. The beginning of the first time slot in a frame is identified from the SFS input (see Figure 9). In nondelayed mode, SFS is active coincident with bit 0 of time slot 0 of the RX frame (and the TX frame if the programmed offset between TX and RX is 0). In delayed mode, SFS is active one cycle earlier. The amount of skew or offset between the transmit and receive frames and time slots is programmable via board control word 2, 0x1FFC. The bit offset is up to a frame, i.e., up to 511 bits in 4 MHz mode. See Table 36 for a listing of invalid bit offset values. The bit offset skew takes place in the system PCM interface block. Addresses less than 0x1400 refer to the DSP engine RAM space. If a read from the DSP engine is required, the microprocessor interface issues a read interrupt to the DSP engine. If it's a write to the DSP engine, the microprocessor interface shifts in the data word and saves it into the data register before sending a write interrupt to the DSP engine. Once in every 7.8 s time segment, the DSP engine checks whether an interrupt is outstanding from the microprocessor interface block. The active transmit and receive time slots are determined by the card address. The number of time slots within a frame varies according to the rate of SCK. Only 16 time slots are ever active in a frame, as shown in Table 3. If so, the DSP engine reads the address register. If it's a read, the DSP engine fetches the word from RAM, places it in the data register, and shifts it out to the microprocessor. If it's a write, it puts the contents of the data register into RAM. The T7531A obtains its card address in board control word 1, 0x1FFE. A pause therefore exists between the external controller issuing an address and receiving a data read back. The data rate of 2.048 MHz allows 256 SCK cycles in a frame, i.e., eight address/data pairs with no pause between words. Since the DSP engine can process only one interrupt every 7.8 s, the T7531A requires a separation between address and data on read and write instructions to the microprocessor interrupt (see Figure 10). This, in effect, requires UPCK to be gapped. In -law or A-law mode, each PCM word is only 8 bits long and occupies one time slot. In linear mode, the PCM word is 16 bits long and occupies two adjacent time slots. The MSB is the first bit clocked out in the valid time slot, and the LSB is the last bit of the following (invalid) time slot. Table 3. Active Time-Slot Spacing in a PCM Bus Frame SCK Rate (MHz) 2.048 Total # of Time Slots 32 4.096 64 Lucent Technologies Inc. Card Address 0 1 0 1 2 3 Valid Time Slots 0, 2, 4, . . . 30 1, 3, 5, . . . 31 0, 4, 8, . . . 60 1, 5, 9, . . . 61 2, 6, 10, . . . 62 3, 7, 11, . . . 63 Invalid Time Slots 1, 3, 5, . . . 31 0, 2, 4, . . . 30 1--3, 5--7, . . . 61--63 0, 2--4, 6--8, . . . 62--63 0--1, 3--5, 7--9, . . . 63 0--2, 4--6, 8--10, . . . 60--62 15 T7531A/T7536 16-Channel Programmable Codec Chip Set Chip Set Functional Description (continued) T7531A Functional Blocks (continued) Addresses 0x1400 refer to registers or TSA RAM external to the DSP engine. If the address word from the microprocessor is 0x1400 through 0x140F, it activates the TSA state machine. If the address word from the microprocessor is 0x1500 through 0x15FF, it activates the T7536 control state machine. Microprocessor data and address words can be flushed out of the T7531A by addressing 0x7FFF with data word 0xFFFF (see Table 40). T7536 Octal Control Interface The two T7536 chips cannot be accessed by the microcontroller directly; the T7536's registers are all accessed via the T7531A microprocessor interface. The microprocessor communicates serially with the T7536 by simply writing or reading 16-bit address and 16-bit data. The octal control interface block translates this address and data into 8-bit address and 8-bit data needed by the T7536. The octal control interface block waits until the microprocessor interface block receives all 16 bits of the address word and determines whether this is a read or write operation by looking at bit 15. If this is a write operation for a T7536 chip, it receives another 16-bit data word. Data Sheet February 1999 to write to all 16 locations of the TSA RAM at start-up to ensure proper operation. Twice a frame, the TSA state machine reads the entire TSA RAM from top to bottom in sequence and sends the contents of each RAM location to the interpolator as channel numbers for RX channels. The TSA state machine performs the same procedure for the decimator to provide it with the TX channel numbers. By performing TSA at the oversampled sigma-delta rate, round trip group delay is significantly minimized. DSP Engine Timing The DSP engine processes all 16 lines every frame. In order to simplify synchronization of data exchanges, the processing frame is broken into 16 equal time segments of 7.8 s each. The ROM code is identical for each time segment. Synchronization between the engine and the rest of the chip is enforced by the system interface block, which issues an interrupt every 7.8 s. This interrupt is the only unmasked interrupt processed by the engine. The interrupt service routine forces the ROM code to branch to the start of the processing loop. T7531A Program Structure The DSP engine firmware performs three types of operations: T7531A Time-Slot Assignment (TSA) 1. Signal processing of the ac path data. The TSA block contains a 16 x 6 dual-port RAM which is readable or writable via the microprocessor interface. Table 18 gives the bit map for TSA RAM words. The TSA RAM is in time-slot order, i.e., location 0x1400 is for time slot 0 and 0x1401 for time slot 1 and so on. The low 4 bits (B3--B0) indicate which of the 16 possible channel numbers is assigned to this time slot. The time-slot assignment is controlled by the microprocessor writing to address 0x1400 through 0x140F. 2. RAM accesses initiated by the microprocessor interface. The TSA block also generates the control signals and flags used to synchronize the TSA, interpolator and decimator, and T7536 interface blocks. The TSA RAM is not preinitialized, so the microprocessor is required 16 3. Data and program flow operations. The signal processing algorithms performed by the T7531A are implemented in firmware and are held in ROM. Many firmware parameters are user programmable via the microprocessor interface. Interrupts from the microprocessor interface are handled once every time segment (7.8 s), and the appropriate accesses are made to the DSP engine RAM registers. Lucent Technologies Inc. Data Sheet February 1999 Chip Set Functional Description (continued) Control of the DSP Engine via the Microprocessor Interface There are four types of commands that the external controlling device may issue to the DSP engine: 1. Downloading data to RAM. 2. Activating and deactivating lines. 3. Changing the RX and TX routine to be run. 4. Periodic read and/or refresh of RAM space. All of these commands must only involve reading and writing to the DSP RAM so that the DSP engine does not have to perform test- and branch-type operations when a microprocessor interface command is received. The complete memory map for the DSP engine RAM is given in Table 18. The microprocessor interface is allowed to read any RAM location in the DSP engine and to write to specified addresses. The DSP Engine Time-Slot Information Tables In the T7531A, the DSP engine RAM has been set up to contain 16 tables which hold the pointers to the ac coefficients and data buffers required to process each time slot. Each table starts on a 32-word boundary and is accessed in the firmware using direct addressing instructions. Each table has an RX part and a TX part (see Table 18). T7531A/T7536 16-Channel Programmable Codec Chip Set The DSP Engine ac Path Coefficient Table The microprocessor interface can control the DSP coefficients, shown in Table 4. The DSP engine RAM contains space to hold separate sets of coefficients for each channel, labeled channel_0 through channel_15. The coefficients are held in channel order, since they hold information that is channel specific and does not change with the time slot (see Table 18). Table 4 shows the ac path coefficient space for channel_0. Table 4. DSP Engine RAM Map for Channel_0 ac Path Coefficients RAM Address rgain_rel_0 Reserved rgain_abs_0 tgain_abs_0 bf_coef_0 Reserved tgain_rel_0 Purpose RX path relative gain -- RX path absolute gain TX path absolute gain Balance filter coefficients -- TX path relative gain Number Initial of Words Value 1 1 (4000 H) 1 1 -- 1 (4000 H) 1 1 (4000 H) 10 Not initialized -- 1 (4000 H) 1 1 The tables are labeled 0 through 15 and are in time-slot order, i.e., table 0 is used when processing data for time slot 0. Time-slot number can vary between 0 and 15 and is used in conjunction with the card address to provide up to 63 time-slot positions on the PCM bus (see Table 3). Lucent Technologies Inc. 17 T7531A/T7536 16-Channel Programmable Codec Chip Set Chip Set Functional Description (continued) The Time-Slot Control Word The DSP engine works in time-slot order. The TSA function is performed by the decimator/interpolator. The DSP engine is not required to reorder the data in any way. The advantages of this approach are that the group delay introduced by the TSA function is very small, and the DSP code needed for context switching is small. When the microprocessor assigns a time slot via the TSA RAM, it also has to issue a new time-slot control word (TCW) instruction to the DSP engine to enable the time slot to link to the correct ac coefficients. The TCW contains the information shown in Tables 5A and 5B. The TCW is only looked at when a time slot is inactive. The initial setup of the TCWs assumes channel-order time-slot assignment. Data Sheet February 1999 Operations Performed by the DSP Engine at T7531A Start-Up The DSP engine performs its start-up code after it has been reset. All interrupts are disabled. First, the DSP engine computes the checksum for its ROM and RAM to verify their integrity. Next, the DSP engine walks through each time-slot information table and sets the data buffer and coefficient pointers. The DSP engine RAM is set up for channel-order time-slot assignment, i.e., table 0 points to channel_0 and so on. The start-up settings for the Time-Slot Information Table (i.e., for time slot 0) are shown in Table 6. The first 16 locations of RAM bank 1 hold the channel address table, where pointers to the start of the coefficient space for each channel are held. These pointers are set up during the start-up routine. Pointers to the three sets of default coefficients are also set up. The DSP engine then walks through all 16 ac coefficient tables and sets them to their initial values as shown in the previous section. The RX and TX filter coefficients (one set for all 16 lines) are taken from ROM and written to their RAM locations. The DSP engine takes about 3 ms to execute the startup code. At the end of the code, the interrupt system is enabled and the DSP engine enters sleep mode. Table 5A. Bit Maps for DSP Engine Time-Slot Control Word Register Bit 0--3 4 5 6--7 Function Channel Number Go to Powerup Modify Coefficients Use Default Per-Board Coefficient Tables Initial Value channel_(time-slot number) 0 0 0 Table 5B. Bit Map for Default Per-Board Coefficient Tables Bit 7 0 0 1 1 Bit 6 0 1 0 1 Mode Do Not Select Default Tables Default Table 1 Coefficient Set Default Table 2 Coefficient Set Default Table 2 Coefficient Set Table 6. DSP Engine RAM Map for Time-Slot Information Table 0 Variable tcw_0 rx_rtn_0 tx_rtn_0 data storage 18 Function Time-slot Control Word Address of Receive ac Routine Address of Transmit ac Routine Reserved Initialized Address See above rpath_inactive tpath_inactive NA Lucent Technologies Inc. Data Sheet February 1999 Chip Set Functional Description (continued) Microprocessor Start-Up of the DSP Engine Once the interrupt system is enabled, the DSP engine looks for a read or write interrupt from the microprocessor interface once every time segment, i.e., 16 times a frame. If the ac coefficients for every channel are to be independently controlled, the microprocessor can write directly to the addresses of the 16 ac coefficient tables. This requires a total of 16 microprocessor commands to set up each channel, i.e., 16 frames to set up all 16 channels. Prior to activating any time slots, the microprocessor has the option of bulk downloading the coefficients to set up the ac coefficient tables. When a channel needs to be set up and linked to its time slot, the microprocessor must send the TCW for that time slot with the modify coefficient (MC) bit (see Table 5A). The MC bit causes the inactive routine for that time slot to set pointers from that time-slot space to the channel space in RAM. The MC bit also causes the inactive routine to check the default coefficient bits of the TCW. If set, the appropriate default table coefficients are copied over to the RAM space for the channel. This mechanism allows the microprocessor to download a set of coefficients that can be used by multiple channels. A mix-and-match approach can be used, i.e., some channels are set up with independent sets of coefficients, while other channels get a default setting. During start-up, the microprocessor must also download the 16 TSA commands used by the TSA block to map physical channels to time slots. This is required to initialize the TSA RAM to known values. When all 16 locations have been set up, the microprocessor must send BCW2 (0x1FFC). This flags the TSA control to start normal operation. T7531A/T7536 16-Channel Programmable Codec Chip Set If dynamic time-slot assignment is used, the microprocessor must next download a TSA command, which the TSA block uses to map the time slot to the required channel number. The microprocessor must enable the time slot by setting the go to powerup bit of the TCW. This causes the DSP engine to change the TX and RX ac routine addresses to active. A maximum of 17 commands or a minimum of one command is therefore needed to power up a channel. Disabling a Time Slot in the T7531A To disable a time slot, the microprocessor must send a command that sets the address of either the TX or RX ac routine to TX_inactive and RX_inactive, respectively. The inactive routines come into use in the next TX or RX time segment for this time slot. Upon returning from the inactive routine, the DSP engine checks for a microprocessor interrupt and then enters sleep mode for the rest of the time segment. T7536 Powerup/Powerdown Each channel can be powered up independently. There are two control register addresses that can be used to control the power for each channel. In both cases, the first bit of the address word controls the power. P = 1 for powerup, and P = 0 for powerdown. One address is provided for each channel which controls the power (0x1508--0x150F and 0x1548-- 0x154F), and the address is followed by a data word which controls the other programmable functions for the same channel. A second address (0x1500-- 0x1507 and 0x1540--0x1547) is provided for each channel that controls only the power. Powering Up a Time Slot in the T7531A Depending on the application, the microprocessor may choose to set up the ac coefficients for a channel just prior to enabling it for use. This requires 16 microprocessor commands if the coefficients must be set up from scratch, or no commands if an appropriate default set has already been set up. In either case, the microprocessor must ensure that all the TX and RX parts of a channel are set up prior to enabling the time slot. Lucent Technologies Inc. 19 T7531A/T7536 16-Channel Programmable Codec Chip Set Chip Set Functional Description (continued) Changing DSP RAM Space of an Active Time Slot The microprocessor is only allowed to change four RAM locations for an active time slot: Relative transmit gain Relative receive gain Address of receive ac routine Address of transmit ac routine Absolute gains and time-slot assignment can only be altered when the time slot is inactive. Note that the DSP engine does not check the TCW of active time slots. Following the initial powerup, the line card is likely to be in service without being reset for as long as it continues to operate trouble-free. Therefore, the microprocessor has the option of continuously monitoring the variables it has programmed by reading them back from the DSP engine/microprocessor interface and rewriting them. DSP Engine Memory Requirements The size of the DSP engine internal dual-port RAM is 2K x 16-bit words per DSP engine. RAM storage is used for user-programmable variables and for intermediate storage of the data being processed by the device. The RAM memory map is given in Table 18. Data Sheet February 1999 T7531A Reset and Start-Up The chips support both hardware and software reset. Hardware Reset The T7531A reset functions are handled by the reset control block. Hardware reset occurs if the board is powered up with RSTB low. Since RSTB has a Schmitt trigger buffer with an internal pull-up, a capacitor attached external to the RSTB pin causes the pin to pull high after a specified period of time. For power-on reset, the T7531A requires that this period of time be >1 ms to give the on-chip clock synthesizer block time to start producing clock edges for the T7531A and T7536 chips (although it may not have reached its final accuracy yet). Successful hardware reset of the device requires that: 1. The PCM bus signals SCK and SFS should be valid at the start of the 1 ms power-on reset period. 2. VDD (and therefore RSTB) should have been low for at least 200 ms prior to commencing power-on reset to ensure that the JTAG controller powerup reset circuit has had time to clear the JTAG controller. If, during normal operation, VDD falls below the defined minimum value, VDD min, the power-on reset procedure described above must be repeated. Hardware reset occurs if RSTB is pulsed high-low-high for 1 ms during normal operation (i.e., no loss of power). The on-chip ROM is used for both program and data. The DSP engine firmware is ROM based. The hardware development system code is also ROM based. The DSP engine ROM memory map is given in Table 41. Table 7. Summary of Microprocessor Commands for Control of T7531A Data Processing Function Required Number of Commands Bulk TSA register download & BCW2 17 Individual TSA register download 1 Coefficient download 16 per channel Set TCW to use/share coefficients 1 already downloaded to default tables Enable time slot via TCW (fixed TSA) 1 Enable time slot via TCW (dynamic TSA) 2 Disable time slot 1 Change gain value 1 per gain 20 When Issued Start-up Prior to activating a time slot via the TCW Start-up or when time slot is inactive Start-up or when time slot is inactive When time slot is inactive When time slot is inactive When time slot is active Any time Lucent Technologies Inc. Data Sheet February 1999 Chip Set Functional Description (continued) Internal Reset Internal reset is defined as the process that starts when the internal reset line is brought low. This happens as a consequence of hardware (RTSB) or software (BCW1) reset. The internal reset process performs the following functions: 1. The frequency synthesizer does not receive any reset signal, and is thus unaffected by reset. Following power-on reset of the T7531A, the frequency synthesizer takes the mode determined by the SCKSEL pin. 2. The T7531A custom logic jams all resettable latches, counters, and registers to their default values. No data is latched on any of the T7531A interfaces during internal reset. 3. The DSP engine is held in reset state. 4. The internal reset line is held low for a minimum of 18 ms to allow the frequency synthesizer to reach its final accuracy. An internal counter is started when the internal reset line goes low. It counts 80 frame sync pulses on SFS before releasing the internal reset line. 5. When the internal reset line goes high and the EXM (internal) signal is held low, the DSP engine begins its start-up routine by fetching the first instruction from location 0 of the internal ROM. 6. At the rising edge of the internal reset line, all the T7531A custom logic blocks commence their normal operation. Reset of the T7536 Devices There are two options for reset of the T7536 chips. The T7536s can make use of the same hardware reset pulse as the T7531A. The T7531A supplies OSCK to the T7536s as soon as it is available, i.e., before the hardware reset has gone away. It is recommended that hardware reset be applied to all chips simultaneously. T7531A/T7536 16-Channel Programmable Codec Chip Set Start-Up After Internal Reset There is a specific sequence of microprocessor interface instructions that must be followed after internal reset in order to properly configure the T7531A and T7536s for normal operation. 1. If nondefault values are required, the T7531A board control word 1 (address 0x1FFE) must be updated. 2. The 16 TSA RAM locations must be written before 0x1FFC. CTZ must be disabled (see Table 20B). 3. The all channel test register must be set for normal operation (addresses 0x1510 and 0x1550 set to 0x0004). 4. The T7531A control registers must be set. All 16 channels must be powered up (addresses 0x1500--0x1507 and 0x1540--0x1547 must be set to 0x8000). 5. The amplitude of the calibration sine wave must be set by writing address 0x0580 to coefficient 0xAA20, and address 0x0581 to coefficient 0xF49D. 6. All 16 channels must be put into initialization mode (addresses 0x1518--0x151F and 0x1558--0x155F must be set to 0x0080). 7. The DSP engine RAM address 0x0002 must be set to 0x0700 to begin the first part of the T7536 calibration start-up sequence. 8. After 70 ms, all 16 T7536 channels must be put into loopback mode (addresses 0x1508--0x151F and 0x1548--0x154F must be set to 0x8001). 9. The DSP engine RAM address 0x0002 must be set to 0x0720 to begin the second part of the T7536 calibration start-up sequence. 10. After 70 ms, both T7536s should be sent a soft reset (addresses 0x1517 and 0x1557 set to 0x8000) and the all channel test register should be set for normal operation (addresses 0x1510 and 0x1550 set to 0x0004). Normal T7531A operation commences with the next SFS frame sync. The chips are now ready for channels to be enabled and filter coefficients to be set. Alternatively, the T7536s can be reset through software reset (Tables 21 and 22), which is generated by the external controlling device and routed to the T7536s via the T7531A. This can only occur when OSCK is guaranteed to be valid, i.e., not within 10 ms of power-on hardware reset. Lucent Technologies Inc. 21 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Chip Set Functional Description Off-Line Programmable System Test Capability (continued) The T7531A has a standard 4-pin test access port known as JTAG that can be used for testing and debugging. The user has the option of downloading custom firmware to the DSP engine RAM via the JTAG port, and running it in the DSP engine in place of the normal ROM-based code. The DSP16 hardware development tool provides a powerful user interface for real-time code development and debug. The user can also execute the self-test ROM routine which exercises significant portions of the T7531A and T7536 devices. Autocalibration Autocalibration is an analog self-test and trimming procedure controlled by the DSP core. Sine wave signals are generated in the receive direction. These signals are looped back at the analog side of the T7536, and the return signal amplitudes are measured in the transmit path. This procedure provides on-the-spot fault coverage of the transmit and receive paths. It also calibrates the octal devices by modifying the gain on each channel. Channel four of the T7536 is the only channel trimmed at the factory for absolute gain accuracy. When autocalibration is run, all channels are trimmed with reference to channel four. That is, the gain on each channel is adjusted so that its absolute gain is equivalent to that of the trimmed channel. Performing trimming in this manner provides channel-tochannel gain matching of better than 0.01 dB. This is a much better performance than could be achieved using conventional trimming. Trimmed values are placed in data storage, and absolute gain values are then modified accordingly any time the absolute gain register is changed. The calibration sequence measures the looped-back power result and compares it to the calibrated channel. The trim window is 0.2 dB. If any channel exhibits a power value which is greater than 0.2 dB, the calibration procedure sets a failure flag for that channel. Trimming will not be performed on the failed channel, and the channel's trimmed gain will be left at 0 dB. The failed channel, therefore, is left in its previous state and can still be used. The results of calibration are held in RAM address 0x07F4 for transmit (pass 1) and 0x07F5 for receive (pass 2). A bit is set high for every failed channel. The preceding section discussed the sequence of instructions that must be followed in order to properly configure the T7531A for normal operation. The autocalibration procedure is mandatory after hardware reset. On-Line Per-Channel Test Capability In addition to the active (i.e., normal voice processing functions) and inactive routines, the user can select the routines listed in Table 41 by altering the TX and RX routines address in the time-slot information table (see Table 6). Inactive Mode with Loopback This is a pair of routines that are used for the TX and RX parts of the channel. Data from SDR is looped back without modification to SDX. Self-Test and Board-Test Routines Using the following routines, programs can be written to test not only the codec function but also all attached circuitry, like the SLIC, relays, protection devices, and cabling. Tone Generation In tone generation mode, the RX part of the channel is used to send a sine wave signal out to the line. The sine wave can be up to 4 kHz in frequency, and up to 1024 points long. The RX filter is not implemented in tone generation. User Test Features This section outlines the T7531A test features and architecture. For more information on the board-test capabilities, see the T7531A/T7536 User Manual. 22 Lucent Technologies Inc. Data Sheet February 1999 T7531A/T7536 16-Channel Programmable Codec Chip Set Chip Set Functional Description Peak Detection (continued) This routine examines the incoming TX signal and saves the maximum and minimum signal values. Self-Test and Board-Test Routines (continued) Handling Precautions Tone Detection In tone detection mode, the TX part of the channel can be used to detect signal energy from the line at a given frequency up to 4 kHz. This routine performs discrete Fourier transform (DFT) to capture and analyze the reflected tone. The routine does not employ the transmit bandpass filters. The number of frames to sample the reflected tone must be defined. The number of frames that DFT is run must be a power of 2 and should be complete cycles of tone value. dc Generation This routine generates a dc signal (value defined by user) in the RX path. Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for the CDM. A standard HBM (resistance = 1500 , capacitance = 100 pF) is widely accepted and can be used for comparison. The HBM ESD threshold presented here was obtained by using these circuit parameters: HBM ESD Threshold Device Voltage (V) T7531A >1000 T7536 >1000 Variance Computation The variance routine computes the variance of small noise signals from the TX path around the computed mean level. This routine employs the transmit bandpass filters for out-of-band noise reduction. Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational section of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Ambient Operating Temperature Operating Junction Temperature Thermal Resistance, Junction to Case Storage Temperature Range Power Supply Voltage Voltage on Any Pin with Respect to Ground Package Power Dissipation Lucent Technologies Inc. Symbol TA TJ RJC Tstg VDD VSS PD Min -40 -40 -- -55 4.75 -0.25 -- Max 85 125 35 150 5.25 5.25 1 Unit C C C/W C V V W 23 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Electrical Characteristics For all specifications: TA = -40 C to +85 C, VDD = 5 V 5%, unless otherwise noted. Typical values are for TA = 25 C and VDD = 5 V. Input signal frequency is 1020 Hz, unless otherwise noted. dc Characteristics Table 8. Digital Interface Parameter Input Voltage Output Voltage Input Current Symbol VIL VIH VOL VOH VOHC Low IIL High IIH Low High Low High Test Conditions TTL-compatible inputs TTL-compatible inputs IL = 10 mA IL = -10 mA IL = -320 A GND < VIN < VIL VIH < VIN < VDD Min -- 2.0 -- 2.4 3.5 -10 -- Typ -- -- -- -- -- -- -- Max 0.7 -- 0.4 -- -- -- 10 Unit V V V V V A A Pins Without a Pull-up or Pull-down Pins with a Pull-up Low High IIL IIH GND < VIN < VIL VIH < VIN < VDD -120 -- -- -- -2 10 A A Pins with a Pull-down Low High IIL IIH GND < VIN < VIL VIH < VIN < VDD -10 2 -- -- -- 120 A A -- IOZ UPDO, SDX -40 C to 0 C UPDO, SDX 0 C to 85 C -30 -10 -- -- 30 10 A A Output Current in High-impedance State Table 9. Analog Interface Parameter Symbol Input Resistance RVTX Input Resistance RVRTX (dependent on the setting of the termination impedance) Common-mode Reference Voltage VVRTX CMT Input Sink Current IVRTX Input Voltage Swing VVTX Load Resistance at VRP and VRN RL (differential) Load Capacitance CL Output Resistance RO Output Offset Voltage Between VRP and VRN Output Offset Voltage Between VRP and VRN, Powerdown Output Voltage Swing (differential) 24 VOS VOSPD VRSW Test Conditions 0.25 V < VTX < 4.75 V 2.3 V < VRTX < 2.5 V Min 10 7 Typ -- -- Max -- -- Unit M k -- 2.3 V < VRTX < 2.5 V -- -- 2.2 -- -- 4.0 2.4 -- -- -- 2.6 400 3.2 -- V A Vp-p k CL from VRP or VRN to VSSA Digital input code corresponding to 0 dBm PCM code at 1.02 kHz Digital pattern corresponding to idle PCM code (-law) Channel powered down 10 A max dc load RL = 100 k differential maximum receive gain -- -- -- 2 100 10 pF -100 0 100 mV -20 0 20 mV 5.28 -- -- Vp-p Lucent Technologies Inc. T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Electrical Characteristics (continued) dc Characteristics (continued) Table 10. T7536 Power Dissipation Parameter Powerdown Current Powerup Current Symbol Test Conditions IDD0 OSCK and OSFS present, 8 channels powered down IDD1 OSCK and OSFS present, 8 channels powered up, normal operation Min -- -- Typ 9 61 Max 12 88 Unit mA mA Min -- Typ 105 Max -- Unit mA -- 175* 190 mA Table 11. T7531A Power Dissipation Parameter Powerdown Current Symbol IDD0 Powerup Current IDD1 Test Conditions SCK and SFS present, 16 channels powered down and inactive SCK and SFS present, 16 channels powered up and active * Powerup current exhibits a negative temperature coefficient. Transmission Characteristics Table 12. Gain and Dynamic Range Parameter Absolute Levels Transmit Gain Absolute Accuracy Transmit Gain Variation with Programmed Gain Symbol GAL GXA GXAG Lucent Technologies Inc. Test Conditions Maximum 0 dBm0 levels (1.02 kHz): VTX (encoder milliwatt) (T7536 TX gain = 0 dB; T7531A gain = -1.65 dB) VRP--VRN (decoder milliwatt) (T7536 RX gain = 6.02 dB; T7531A gain = 0.21 dB) Termination impedance off Minimum 0 dBm0 levels (1.02 kHz): VTX (T7536 TX gain =12.04 dB; T7531A gain = -1.65 dB) VRP--VRN (T7536 RX gain = -12.04 dB; T7531A gain = 0.21 dB) Termination impedance off Transmit gain programmed for maximum 0 dBm0 test level, measured deviation of digital code from ideal 0 dBm0 level at OSDX[1:0] digital outputs, with transmit gain set to 0 dB: 0 C to 85 C -40 C to +85 C Measured transmit gain over the range from maximum to minimum, calculated deviation from the programmed gain relative to GXA at 0 dB: VDD = 5 V Min Typ Max Unit -- 2.23 -- Vp-p -- 4.38 -- Vp-p -- 557.0 -- mVp-p -- 548.0 -- mVp-p -0.25 -0.30 -- -- 0.25 0.30 dB dB -0.1 -- 0.1 dB 25 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Transmission Characteristics (continued) Table 12. Gain and Dynamic Range (continued) Parameter Symbol Test Conditions Transmit Gain Variation GXAF Relative to 1016 Hz, minimum gain < GX < with Frequency maximum gain, VTX = 0 dBm0 signal, TZ = 600 , path gain set to 0 dB: f = 16.67 Hz f = 40 Hz f = 50 Hz f = 60 Hz f = 200 Hz f = 300 Hz to 3000 Hz f = 3140 Hz f = 3380 Hz f = 3860 Hz f = 4600 Hz and above Transmit Gain Variation GXAL Sinusoidal test method reference with Signal Level level = 0 dBm0: VTX = -37 dBm0 to +3 dBm0 VTX = -50 dBm0 to -37 dBm0 VTX = -55 dBm0 to -50 dBm0 Receive Gain Absolute GRA Receive gain programmed to 0 dB, apply Accuracy 0 dBm0 oversampled data to OSDR0 or OSDR1, measure VRP, RL = 100 k differential: 0 to 85 C -40 C to +85 C Relative Gain: -- Digital input 0 dBm0 signal VRP to VRN f = 300 Hz to 3400 Hz Relative Phase: -- Digital input 0 dBm0 signal VRP to VRN f = 300 Hz to 3400 Hz Receive Gain Variation GRAG Measure receive gain over the range from maximum to minimum setting, calculated with Programmed deviation from the programmed gain relative Gain to GRA at 0 dB, VDD = 5 V Receive Gain Variation GRAF Relative to 1016 Hz, digital input = 0 dBm0 with Frequency code, minimum gain < GR < maximum gain: 0 dB path gain f = below 3000 Hz f = 3140 Hz f = 3380 Hz f = 3860 Hz f = 4600 Hz and above Receive Gain Variation GRAL Sinusoidal test method, reference with Signal Level level = 0 dBm0: OSDR = -37 dBm0 to +3 dBm0 OSDR = -50 dBm0 to -37 dBm0 Relative Termination AT -- Impedance Gain 26 Min Typ Max Unit -30 -50 -- -26 -38 -- -30 -44 -- -30 -45 -- 0 -0.5 -1.8 -0.125 0.04 0.125 0.01 0.125 -0.57 -0.735 -0.550 0.015 -9.9 -8.98 -- -32 -- -- dB dB dB dB dB dB dB dB dB dB -0.25 -0.50 -1.4 -- -- -- 0.25 0.50 1.4 dB dB dB -0.25 -0.30 -0.01 -- -- -- 0.25 0.30 0.01 dB dB dB -0.25 -- 0.25 Deg -0.1 -- 0.1 dB -0.125 0.04 0.125 0.04 0.125 -0.57 -0.735 -0.550 0.015 -10.7 -8.98 -- -28 -- -- dB dB dB dB dB -0.25 -0.50 -0.2 dB dB dB -- -- -- 0.25 0.50 0.2 Lucent Technologies Inc. Data Sheet February 1999 T7531A/T7536 16-Channel Programmable Codec Chip Set Transmission Characteristics (continued) Table 13. Noise (per Channel) Parameter Symbol Test Conditions 0 dB transmit gain Transmit Noise, NXC C-message Weighted Transmit Noise, NXP 0 dB transmit gain P-message Weighted 0 dB receive gain, digital pattern correReceive Noise, NRC sponding to idle PCM code, -law C-message Weighted Receive Noise, NRP 0 dB receive gain, digital pattern correP-message Weighted sponding to idle PCM code, -law Noise, Single Frequency NRS f = 0 kHz to 100 kHz, loop around measurement, VTX = 0 Vrms VDD = 5.0 Vdc + 100 mVrms Power Supply Rejection, PSRX f = 0 kHz to 4 kHz Transmit f = 4 kHz to 50 kHz* C-message weighted Power Supply Rejection, PSRR Measured on VRP Receive VDD = 5.0 Vdc + 100 mVrms f = 0 kHz to 4 kHz f = 4 kHz to 25 kHz f = 25 kHz to 50 kHz Digital pattern corresponding to idle PCM code, -law, C-message weighted Spurious Out-of-band SOS 0 dBm0, 300 Hz to 3400 Hz input Signals at the Channel oversampled data code applied at OSDR0 Outputs (or OSDR1): 4600 Hz to 7600 Hz 7600 Hz to 8400 Hz 8400 Hz to 50 kHz Min -- Typ -- Max 18 Unit dBrnC0 -- -- -68 dBm0p -- -- 13 dBrnC0 -- -- -75 dBm0p -- -- -53 dBm0 36 30 -- -- -- -- dBC dBC 36 40 36 -- -- -- -- -- -- dBC dBC dBC -- -- -- -- -- -- -30 -40 -30 dB dB dB * Measured with a -50 dBm0 activation signal applied to VFXI input of channel under test. Lucent Technologies Inc. 27 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Transmission Characteristics (continued) Table 14. Distortion and Group Delay Parameter Signal to Total Distortion Transmit or Receive C-message Weighted Single Frequency Distortion, Transmit Symbol STDX STDR Single Frequency Distortion, Receive SFDR SFDX Intermodulation Distortion IMD TX Group Delay, Absolute DXA RX Group Delay, Absolute DRA Test Conditions Sinusoidal test method level: 3.0 dBm0 0 dBm0 0 dBm0 single frequency input, 200 Hz fIN 3400 Hz; measure at any other single frequency 0 dBm0 single frequency input, 200 Hz fIN 3400 Hz; measure at any other single frequency Transmit or receive, two frequencies in the range (300 Hz to 3400 Hz) f = 1600 Hz, SCK = 4.096 MHz, bit offset = 419 f = 1600 Hz Min Typ Max Unit 33 36 -- -- -- -- -- -- -46 dB dB dB -- -- -46 dB -- -- -41 dB -- 250* 300 s -- 250 300 s * Varies as a function of bit offset. Table 15. Crosstalk Parameter Symbol Test Conditions Min Typ Max Unit Transmit to Transmit Crosstalk, 0 dBm0 Level CTX-X f = 300 Hz to 3400 Hz, Any channel to any channel -- -- -75 dB Transmit to Receive Crosstalk, 0 dBm0 Level CTX-R f = 300 Hz to 3400 Hz, Any channel to any other channel In-channel -- -- -- -- -75 -50 dB dB Receive to Transmit Crosstalk, 0 dBm0 Level CTR-X f = 300 Hz to 3400 Hz, Any channel to any other channel In-channel -- -- -- -- -75 -50 dB dB Receive to Receive Crosstalk, 0 dBm0 Level CTR-R f = 300 Hz to 3400 Hz, Any channel to any channel -- -- -75 dB 28 Lucent Technologies Inc. T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Timing Characteristics A signal is valid if it is above VIH or below VIL and invalid if it is between VIL and VIH. For the purposes of this specification, the following conditions apply: All input signals are defined as VIL = 0.4 V, VIH = 2.7 V, tR < 10 ns, tF < 10 ns. tR is measured from VIL to VIH. tF is measured from VIH to VIL. Delay times are measured from the input signal valid to the output signal valid. Setup times are measured from the data input valid to the clock input invalid. Hold times are measured from the clock signal valid to the data input invalid. Pulse widths are measured from VIL to VIL or from VIH to VIH. Table 16. PCM Interface Timing (See Figure 9.) Symbol Parameter Test Conditions Min Typ Max Unit fSCK Frequency of SCK (Selection frequency is pin-strap programmable.) Period of SCK Jitter of SCK -- -- -- 2.048 4.096 -- -- MHz MHz Measured from VIL to VIL -- -- -- 1/fSCK -- ns -- -- -- -- -- -- 100 ns in 100 ms = 1 ppm -- -- 15 15 ns ns ns ns -- -- -- -- 9 -- -- 62.5 62.5 -- -- 90 -- -- s s ns ns ns ns ns tSCK -- tSCHSCL tSCLSCH tSCH1SCH2 tSCL2SCL1 tFSHFSL tSFHSCL tSCLSFL tSCHDXV tDRVSCL tSCLDRX Period of SCK High Period of SCK Low Rise Time of SCK Fall Time of SCK Period of SFS High Frame Sync High Setup Frame Sync Hold Time Data Enabled on TS Entry Receive Data Setup Receive Data Hold Lucent Technologies Inc. 80 Measured from VIH to VIH 80 Measured from VIL to VIL Measured from VIL to VIH -- Measured from VIH to VIL -- Measured from VIH to VIL: 2.048 MHz 0.488 4.096 MHz 0.244 -- 30 -- 30 0 < CLOAD < 100 pF 0 -- 30 -- 30 29 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Timing Characteristics (continued) TIME SLOT 0 A TIME SLOT 1 B tFSHFSL SFS tSFHSCL tSCLSFL SCK 1 2 tSCHSCL 3 4 5 6 7 8 9 1 2 11 12 13 14 15 1 16 tSCLSCH tSCHDXV SDX* 10 3 4 5 6 7 1 8 tDRVSCL SDR 1 2 3 4 5 6 7 1 8 tSCLDRX 5-4233.a (F) * Card address 0, bit offset 0 assumed. Card address 0 assumed. Notes: A is the position of the frame sync pulse in the delayed mode. B is the position of the frame sync pulse in the nondelayed mode. Figure 9. Timing Characteristics of PCM Interface Assuming 2.048 MHz SCK Rate 30 Lucent Technologies Inc. T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Timing Characteristics (continued) Table 17. Serial Control Port Timing (See Figure 10.) Symbol Parameter tCSHLSET tCSLHHOD tUPDIST tUPDIHD tUPDODEL tUPDOHZDL tCKCSH tCKCSH1 UPCS to UPCK Setup UPCS to UPCK Hold UPDI to UPCK Setup UPDI to UPCK Hold UPCK to UPDO Delay UPCS to UPDO High-Z Duration of UPCK and UPCS High: Write Cycle Read Cycle Duration of UPCK and UPCS High Test Conditions Min Typ Max Unit -- -- -- -- CL = 50 pF CL = 50 pF 25 20 ns 25 20 -- -- -- -- -- -- -- -- -- UPCK Period/2 -- -- 42 34 ns -- ns ns ns ns -- -- -- 1 9 9 -- -- -- -- -- -- s s s tCKCSH UPCK tCSLHHOD tCKCSH1 tCSHLSET UPCS tUPDIST tUPDIHD UPDI 15 14 13--2 tUPDIHD 1 15 0 14 13--1 0 ADDRESS DATA (16 bits) ADDRESS (16 bits) tUPDODEL tUPDOHZDL HIGH-Z STATE UPDO 15 14 13--1 0 DATA (16 bits) 5-4232a (F) Notes: UPDI and UPCS change at the rising edge of UPCK by the microprocessor and are sampled at the falling edge of UPCK by the DSP. UPDO changes at the rising edge of UPCK by the DSP and is sampled at the falling edge of UPCK by the microprocessor. Figure 10. Timing Diagram for Microprocessor Write/Read to/from the DSP on the Control Interface Lucent Technologies Inc. 31 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Software Interface Table 18 lists the RAM data space for the DSP engine. Space for up to 16 channels is allocated. The total T7531A RAM size is 2 Kwords, arranged as 2 x 1 Kbanks. Address bit 15 is used as a read/write flag (1 = read). The microprocessor interface can read any address in the DSP engine RAM space. Table 18. DSP Engine RAM Memory Map Address Range RAM Bank 0 0x0000 0x00011 0x00021 0x0003--0x003F 0x00402 0x0080 0x00C0 0x0100 0x0140 0x0180 0x01C0 0x0200 0x0240 0x0280 0x02C0 0x0300 0x0340 0x0380 0x03C0 RAM Bank 1 0x0400--0x040F 0x0410--0x0413 0x0414--0x0434 0x0435 0x0436 0x0437 0x0438 0x0439--0x0442 0x0443 0x0444 Memory Contents Write by Microprocessor Interface Time-Slot Information Tables (See page 17.) Time-slot control word (time slot 0) Y Receive ac routine address (time slot 0) Y Transmit ac routine address (time slot 0) Y Data storage (time slot 0) Selected locations Time slot 1 information table As shown for time slot 0 Time slot 2 information table As shown for time slot 0 Time slot 3 information table As shown for time slot 0 Time slot 4 information table As shown for time slot 0 Time slot 5 information table As shown for time slot 0 Time slot 6 information table As shown for time slot 0 Time slot 7 information table As shown for time slot 0 Time slot 8 information table As shown for time slot 0 Time slot 9 information table As shown for time slot 0 Time slot 10 information table As shown for time slot 0 Time slot 11 information table As shown for time slot 0 Time slot 12 information table As shown for time slot 0 Time slot 13 information table As shown for time slot 0 Time slot 14 information table As shown for time slot 0 Time slot 15 information table As shown for time slot 0 ac Coefficient Reference Tables (See page 16.) Channel coefficient address table N Default coefficient address table N Reserved N ac Per-Channel Coefficients (See page 16.) Receive path relative gain (channel 0) Y Data storage (channel 0) N Receive path absolute gain (channel 0) Y Transmit path absolute gain (channel 0) Y Balance filter coefficients (channel 0) Y Data storage (channel 0) N Transmit path relative gain (channel 0) Y 1. The receive and transmit ac routine addresses are the only addresses that can address ROM code. 2. For time slots 1--15, the address shown is the first address. Refer to time slot 0 for range information. 32 Lucent Technologies Inc. T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Software Interface (continued) Table 18. DSP Engine RAM Memory Map (continued) Address Range 3 0x0445 0x0455 0x0465 0x0475 0x0485 0x0495 0x04A5 0x04B5 0x04C5 0x04D5 0x04E5 0x04F5 0x0505 0x0515 0x0525 0x0535--0x053E 0x053F--0x0552 0x0553 0x0554--0x0560 0x0561 0x0562 0x0563 0x0564-0x056D 0x056E 0x056F--0x057C 0x057D--0x05EE 0x05EF--0x07EF 0x07F0 0x07F2 0x07F4 0x07F5 0x07F6 Memory Contents Channel 1 ac filter coefficients Channel 2 ac filter coefficients Channel 3 ac filter coefficients Channel 4 ac filter coefficients Channel 5 ac filter coefficients Channel 6 ac filter coefficients Channel 7 ac filter coefficients Channel 8 ac filter coefficients Channel 9 ac filter coefficients Channel 10 ac filter coefficients Channel 11 ac filter coefficients Channel 12 ac filter coefficients Channel 13 ac filter coefficients Channel 14 ac filter coefficients Channel 15 ac filter coefficients Write by Microprocessor Interface As shown for channel 0 As shown for channel 0 As shown for channel 0 As shown for channel 0 As shown for channel 0 As shown for channel 0 As shown for channel 0 As shown for channel 0 As shown for channel 0 As shown for channel 0 As shown for channel 0 As shown for channel 0 As shown for channel 0 As shown for channel 0 As shown for channel 0 ac Per-Board4 Coefficients Receive filter coefficients Transmit (equalizer) filter coefficients Transmit gain coefficients for filter compensation Unused Default Per-Board4 Coefficient Tables Default Table 1 receive path relative gain Default Table 1 receive path absolute gain Default Table 1 transmit path absolute gain Default Table 1 balance filter coefficients Default Table 1 transmit path relative gain Default Table 2 coefficient set Self-Test Flags Temporary storage for self-test routines Unused Result of ROM checksum test Result of RAM checksum test Result of TX path self-test Result of RX path self-test ROM code version number Y Y Y Y Y Y Y Y Y Y Y Y N N N N N 1. The receive and transmit ac routine addresses are the only addresses that can address ROM code. 2. For time slots 1--15, the address shown is the first address. Refer to time slot 0 for range information. 3. For channels 1--15, the address shown is the first address. Refer to channel 0 for range information. 4. Per-board refers to a function that is common to all 16 channels in a single chip set. Lucent Technologies Inc. 33 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Software Interface (continued) Table 19. T7531A Time-Slot Assignment Memory Map All registers can be written by the microprocessor interface. Address Range 0x1400 0x1401 0x1402 0x1403 0x1404 0x1405 0x1406 0x1407 0x1408 0x1409 0x140A 0x140B 0x140C 0x140D 0x140E 0x140F Memory Contents Time slot 0 channel assignment Time slot 1 channel assignment Time slot 2 channel assignment Time slot 3 channel assignment Time slot 4 channel assignment Time slot 5 channel assignment Time slot 6 channel assignment Time slot 7 channel assignment Time slot 8 channel assignment Time slot 9 channel assignment Time slot 10 channel assignment Time slot 11 channel assignment Time slot 12 channel assignment Time slot 13 channel assignment Time slot 14 channel assignment Time slot 15 channel assignment Table 20A. Bit Map for T7531A Time-Slot Assignment Registers at 0x1400--0x140F 15--6 Not used 5 CTZ disable Bit Number and Function 4 3 2 1 Null channel Binary-coded channel number 0--15 0 Table 20B. Bit Map for CTZ Disable and Null Channel Bit 5 Bit 4 Function X X 0 1 0 1 X X Disables null pointer Nulls channel Enables CTZ Disables CTZ Notes: X = Don't care. Bits 4 and 5 default to 1 upon reset. 34 Lucent Technologies Inc. T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Software Interface (continued) Table 21. T7531A Channel Register Memory Map for T7536 Device 0 Table 22. T7531A Channel Register Memory Map for T7536 Device 1 All registers can be written by the microprocessor interface. All registers can be written by the microprocessor interface. Address Range 0x1500 0x1501 0x1502 0x1503 0x1504 0x1505 0x1506 0x1507 0x1508 0x1509 0x150A 0x150B 0x150C 0x150D 0x150E 0x150F 0x1510 0x1517 0x1518 0x1519 0x151A 0x151B 0x151C 0x151D 0x151E 0x151F Memory Contents Channel 0 powerup/powerdown register Channel 1 powerup/powerdown register Channel 2 powerup/powerdown register Channel 3 powerup/powerdown register Channel 4 powerup/powerdown register Channel 5 powerup/powerdown register Channel 6 powerup/powerdown register Channel 7 powerup/powerdown register Channel 0 control register 1 Channel 1 control register 1 Channel 2 control register 1 Channel 3 control register 1 Channel 4 control register 1 Channel 5 control register 1 Channel 6 control register 1 Channel 7 control register 1 All channel test register Single-byte soft reset (no data word) Channel 0 control register 2 Channel 1 control register 2 Channel 2 control register 2 Channel 3 control register 2 Channel 4 control register 2 Channel 5 control register 2 Channel 6 control register 2 Channel 7 control register 2 Address Range 0x1540 0x1541 0x1542 0x1543 0x1544 0x1545 0x1546 0x1547 0x1548 0x1549 0x154A 0x154B 0x154C 0x154D 0x154E 0x154F 0x1550 0x1557 0x1558 0x1559 0x155A 0x155B 0x155C 0x155D 0x155E 0x155F Memory Contents Channel 8 powerup/powerdown register Channel 9 powerup/powerdown register Channel 10 powerup/powerdown register Channel 11 powerup/powerdown register Channel 12 powerup/powerdown register Channel 13 powerup/powerdown register Channel 14 powerup/powerdown register Channel 15 powerup/powerdown register Channel 8 control register 1 Channel 9 control register 1 Channel 10 control register 1 Channel 11 control register 1 Channel 12 control register 1 Channel 13 control register 1 Channel 14 control register 1 Channel 15 control register 1 All channel test register Single-byte soft reset (no data word) Channel 8 control register 2 Channel 9 control register 2 Channel 10 control register 2 Channel 11 control register 2 Channel 12 control register 2 Channel 13 control register 2 Channel 14 control register 2 Channel 15 control register 2 Table 23. Bit Map for T7536 Powerup/Powerdown Registers at 0x1500--0x1507 and 0x1540--0x1547 Bit Number and Function 15 14--0 PWR Not used Notes: PWR = 0: powerdown. PWR = 1: powerup--normal operation. Lucent Technologies Inc. 35 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Software Interface (continued) Table 24. Bit Map for T7536 Channel Control Register 1 at 0x1508--0x150F and 0x1548--0x154F 15 PWR 14--8 Not used Bit Number and Function 6 5 4 3 2 TX gain Termination impedance 7 1 0 LPBK Table 25. T7536 Control Register 1: Transmit Gain Bit 7 TXGAIN2 0 0 0 0 1 1 1 1 Bit 6 TXGAIN1 0 0 1 1 0 0 1 1 Bit 5 TXGAIN0 0 1 0 1 0 1 0 1 Mode 0 dB transmit gain 3.01 dB transmit gain 6.02 dB transmit gain 9.03 dB transmit gain 12.04 dB transmit gain 12.04 dB transmit gain 12.04 dB transmit gain 12.04 dB transmit gain Table 26. T7536 Control Register 1: Analog Termination Impedance Bit 4 TI3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 3 TI2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 2 TI1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 1 TI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gain (See equation on page 12.) Analog Termination Impedance () 0.0000 0.0583 0.1417 0.2250 0.3083 0.3917 0.5000 0.5583 0.6417 0.7083 0.8083 0.8917 0.9750 1.0583 1.2167 2.0000 165* 200 250 300 350 400 465 500 550 600 650 700 750 800 895 1365 * This value is equivalent to the protection resistor value multiplied by 2. 36 Lucent Technologies Inc. T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Software Interface (continued) Table 27. T7536 Control Register 1: Digital Loopback Bit 0 LPBK 0 1 Mode Normal operation Digital loopback Table 28. Bit Map for T7536 All Channel Test Register at 0x1510 and 0x1550 Bit Number and Function 15--4 3 2 1 0 Not used Read out address Reserved Analog loopback Digital loopback Table 29. Bits 3:0 of T7536 All Channel Test Register at 0x1510 and 0x1550 Bit Number Function 3 2 1 0 0 -- -- -- Normal operation 1 -- -- -- Read out address -- 0 -- -- Reserved -- 1 -- -- Normal operation -- -- 0 -- Normal operation -- -- 1 -- Analog loopback -- -- -- 0 Normal operation -- -- -- 1 Digital loopback Notes: Read out address provides the previous read or write address to CDO whenever a new address is being written into the register. When analog loopback is high, data that enters the analog transmit path (VTX) is converted to a 1.024 MHz digital bit stream and routed back to the analog receive path (VRP, VRN). The output of the transmit path is available on the oversampled data interface, but receive path oversampled data is ignored. VTX A/D, D/A VRP OVERSAMPLED DATA INTERFACE OSDX OSDR 5-5134 (F) When digital loopback is high, oversampled data receive (OSDR) is routed to oversampled data transmit (OSDX). The receive signal is propagated to VRN/VRP, but any transmit signal from VTX is disconnected. A reference voltage on VRTX is still required in this mode. VTX A/D, D/A VRP OVERSAMPLED DATA INTERFACE OSDX OSDR 5-5135 (F) Lucent Technologies Inc. 37 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Software Interface (continued) Table 30. Bit Map for T7536 Channel Control Register 2 at 0x1518--0x151F and 0x1558--0x155F 15--8 Not used 7 SUSEQ Bit Number and Function 6--3 2 Not used 1 Receive gain 0 Notes: SUSEQ = 0: normal operation. SUSEQ = 1: start-up calibration sequence. Table 31. T7536 Control Register 2: Receive Gain Bit 2 RXGAIN2 0 0 0 0 1 1 1 1 Bit 1 RXGAIN1 0 0 1 1 0 0 1 1 Bit 0 RXGAIN0 0 1 0 1 0 1 0 1 Mode TLP Levels, Termination Impedance Is On 6.02 dB receive gain 3.01 dB receive gain 0.0 dB receive gain -3.01 dB receive gain -6.02 dB receive gain -9.03 dB receive gain -12.04 dB receive gain -12.04 dB receive gain Table 32. T7531A Control Register Map Address Range 0x1FFE 0x1FFC 0x1FFA 0x1FF8 0x1FF6 Register Contents Board control word 1 Board control word 2 Board control word 3 Board control word 4 Board control word 5 Write by Microprocessor Interface Y Y Y Y Y Note: A board control word controls a function that is common to all 16 channels of a given chip set. 38 Lucent Technologies Inc. T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Software Interface (continued) Table 33. Bits 15:8 of T7531A Board Control Word 1 at 0x1FFE 15 0 1 -- -- -- -- -- -- -- -- 14 -- -- -- -- -- -- -- -- -- -- 13 -- -- -- -- -- -- -- -- -- -- Bit Number 12 11 -- -- -- -- -- 0 -- 1 -- -- -- -- -- -- -- -- -- -- -- -- Function 10 -- -- -- -- 0 1 -- -- -- -- 9 -- -- -- -- -- -- 0 1 -- -- 8 -- -- -- -- -- -- -- -- 0 1 Normal operation Soft reset Normal operation TZ test mode Normal operation RX dither circuit off Normal operation Nodecim test mode Normal operation Linear mode Table 34. Bits 7:0 of T7531A Board Control Word 1 at 0x1FFE 7 0 1 -- -- -- -- -- -- -- -- 6 X X X X X X X X X X 5 -- -- 0 1 1 -- -- -- -- -- Bit Number 4 3 -- -- -- -- x -- 0 -- 1 -- -- C1 -- -- -- -- -- -- -- -- Function 2 -- -- -- -- -- C0 -- -- -- -- 1 -- -- -- -- -- -- 0 1 -- -- 0 -- -- -- -- -- -- -- -- 0 1 Delayed data timing Nondelayed data timing -law A-law, including even bit inversion A-law, no even bit inversion C1C0 = card address in binary Reserved Normal operation Normal operation Loopback at OSD Notes: All bits in board control register 1 will be zeros upon hardware reset. In OSD loopback mode, OSDR0, OSDR1, OSDR2, and OSDR3 are looped back with a delay of two OSCLK clock cycles to OSDX0, OSDX1, OSDX2, and OSDX3, respectively. Test modes are for production testing only. -law/A-law companding mode provides 8 bits of PCM data with the first bit (bit 1) defined as the MSB and the last bit (bit 8) as the LSB. Bit 1 is the sign bit, bits 2 through 4 are the chord bits, and bits 5 through 8 are the interval bits. In linear mode, the -law/A-law conversion in the PCM interface block is disabled and 16 bits of linear PCM data are provided. In linear mode, bit 1 is the MSB and the sign bit, bits 2 through 14 are the intervals, and bits 15 and 16 are insignificant. Each interval represents 0.0001362745 Vrms with 8031 intervals being the maximum signal output of 3 dBm0. Negative values are two's complement of positive values. X = don't care. Lucent Technologies Inc. 39 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Software Interface (continued) Table 35. Bits 15:9 of T7531A Board Control Word 2 at 0x1FFC Bit Number and Function 15--9 Not used Table 36. Bits 8:0 of T7531A Board Control Word 2 at 0x1FFC 8 BOF8 7 BOF7 6 BOF6 Bit Number 5, 4, 3 BOF5--3 Function 2 BOF2 1 BOF1 0 BOF0 BOF8--0 = Bit offset in binary* * The following bit offset values are not valid and should not be used: When using a 2.048 MHz SCK: bit offset = 0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, and 240. When using a 4.096 MHz SCK: bit offset = 0, 32, 64, 96, 128, 160, 192, 224, 256, 288, 320, 352, 384, 416, 448, 480. Note: Bits 15 through 9 are not used; assumed to be zeros. BOF[8:0] provide a fixed offset, relative to the frame synchronization strobe (SFS), for the first bit transmitted in each time slot. The offset is the number of data periods by which transmission of the first bit on SDX is delayed. All subsequent transmissions also follow this offset. The default value after hardware reset or powerup is 1A3; however, this register must still be written after reset. Table 37. Bits 15:0 of T7531A Board Control Word 3 at 0x1FFA Bit Number and Function 15--5 Not used 4--0 TZ test bits Note: For test use only, do not use in normal operation. The default value after hardware reset or powerup is 0. Table 38. Bits 15:0 of T7531A Board Control Word 4 at 0x1FF8 Bit Number and Function 15--10 Not used 9--0 CTZ alpha coefficients Note: The default value after hardware reset or powerup is A4. Table 39. Bits 15:0 of T7531A Board Control Word 5 at 0x1FF6 Bit Number and Function 15--8 Not used 7--0 CTZ beta coefficients Note: The default value after hardware reset or powerup is 0. Table 40. Bits 15:0 of T7531A Reset of Microprocessor Commands at 0x7FFF 15 1 40 14 1 13 1 12 1 11 1 10 1 Bit Number 9 8 7 6 1 1 1 1 Function 5 1 4 1 3 1 2 1 1 1 0 1 Clear address and data words in T7531A Lucent Technologies Inc. T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Software Interface (continued) Table 41 shows the memory map for the DSP engine ROM. The ROM information is not accessible via the microprocessor. The total ROM size is 4 Kwords. Table 41. DSP Engine ROM Memory Map Address Range 0x0003 0x0008 0x000B 0x0380 0x03B0 0x03B8 0x0400 0x0500 0x0600 0x0610 0x0680 0x0690 0x0700 0x0720 0x07A0 0x0860 0x0A80 0x0B00 0x0B60 0x0B80 0x0C00 0x0E00 0x0F00 0x0F10 0x0F20 0x0F30 0x0F40 0x0F60 0x0FFE 0x0FFF Memory Contents HDS interrupt service routine Time-slot sync interrupt service routine Start-up routine Time segment controller (ts_proc) Reserved Reserved Transmit path active routine Receive path active routine Transmit path inactive/loopback routine Transmit path inactive routine Receive path inactive/loopback routine Receive path inactive routine Self-test pass 1 setup (TX) Self-test pass 2 setup (RX) Tone generation start-up Tone detection start-up Variance calculation Peak detection dc generation ROM checker RAM checker Variance calculation with TX filters Simultaneous start-up of tone generator and DFT routine Simultaneous start-up of tone generator and original variance routine Routine places TX and RX halves of a time slot into inactive loopback Places TX and RX halves of a time slot into inactive routine Routine for copying values in channel coefficient table 0 to all 16-channel tables Approximate location of HDS code Checksum for ROM 0x0000 : 0x07FF Checksum for ROM 0x0800 : 0x0FFD Lucent Technologies Inc. 41 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Applications 4.096 MHz rate. The microprocessor control interface is a standard 4-wire serial port connection, microprocessor clock (UPCK), chip select (UPCS), data input (UPDI), and output (UPDO). The T7531A generates a 16 MHz clock for microprocessor use. This clock is always present. The PCM interface consists of a system clock (SCK) input of either 2.048 MHz or 4.096 MHz, an 8 kHz system frame sync (SFS) input, a system data transmit port (DX), and a system data receive (DR) port. Other than power supply decoupling, the only external components required by the codec chip set are the two 6.8 k resistors and the three 0.1 F capacitors. These are required by the internal clock synthesizer filter circuit of the T7531A. The clock synthesizer generates a 98.304 MHz master clock for DSP use. Figure 11 shows a full line card implementation using the T7531A/T7536 codec and the L7585 SLIC with integrated relays. One T7531A and two T7536 devices support 16 SLIC devices (only one L7585 SLIC is illustrated). Figure 11 portrays only the transmission paths inside the L7585 SLIC. L7585 functionality includes eight solid-state relays, performing ring, test, and break functions, a ring-trip detector, quiet polarity reversal, 13 operating states, and more. For complete functionality of this SLIC, refer to the L7585 data sheet. The analog connection between the SLIC and the codec is direct; no external components are required. The transfer of control data on the octal interface between the T7531A and T7536 devices is also direct. Data is synchronous with OSCK and transmits at a 11 12 1 44 13 35 10, 36 VSP VBAT BGND VCCA AGND 9 FB1 17, 34 SLIC 0 DGND 8 L7585 FB2 CVD 7 0.1 F CF1 33 VCCD RS1 400 RRTF 1 M RPR 82.5 RPT 82.5 20 RSW CRTF 0.1 F 19 RTS 22 PR 260 V SURGE PROTECTOR 25 PT CF2 DCR 5 DCOUT TEST-IN BUS 1 MHz CLOCK 15 CLK +5 V RPROG 64.9 k IPROG 3 RLCTH 24.9 k 0.1 F 2 LCTH CHANNEL 0 VRN0 RCVN 43 RCVP 42 VRP0 VTX 40 VTX0 VRTX 41 VRTX0 23 RTI 24 TTI CF2 0.1 F 4 2.4 V TXI 39 TIP CF1 0.22 F 6 VITR 38 +5 V +5 V 0.1 F VSSD RINGING BUS FB2* 0.047 F VSSA RELAY 18 RDO K1 26 TRNG 21 RRNG FB1* 0.047 F VDDD +5 V RING +5 V CVA 0.1 F VDDA +10 V -48 V CVB 0.1 F CODEC 0 T7536 CHANNELS 1--7 CB1 0.1 F RGX1 ITR 37 8.25 k TEST VDDD TEST NDET NCS B5 B4 B3 B2 B1 B0 16 14 27 28 29 30 31 32 OCTAL 0.1 F INTERFACE VDD OSFS OSFS OSCK OSCK OSDR0 OSDR0 OSDR1 OSDR1 OSDX0 OSDX0 OSDX1 OSDX1 CCS0 CCS0 CDI CDO CDO CDI RSTB RSTB RSTB CDI CDO OSFS OSCK 0.1 F +5 V VSSD VDDD VDDA VSSA CODEC 1 T7536 UPCK UPCS UPDI UPDO CK16 MICROPROCESSOR SCKSEL RSTB RSTB SCK SFS SDR SDX STSXB PCM BUS PCM INTERFACE CCS1 OSDR2 CCS1 OSDR2 OSDR3 OSDX2 OSDX3 OSDR3 OSDX2 OSDX3 0.1 F CONTROL INTERFACE FVDD DSP T7531A PARALLEL DATA BUS TO MICROPROCESSOR CHANNELS 8--15 0.1 F 0.1 F FILT1 6.8 k 0.1 F FILT2 6.8 k 0.1 F FILT3 VSS FVSS +5 V 12-3351.d (F) * Optional for quiet reverse battery. 4.096 MHz operation; for 2.048 MHz operation, tie SCKSEL to VSS. Figure 11. 16-Channel Line Card Solution 42 Lucent Technologies Inc. T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Outline Diagram 68-Pin PLCC Dimensions are in millimeters. The controlling dimensions are in inches. Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Lucent Technologies Sales Representative. 25.146 0.127 24.231 0.102 PIN #1 IDENTIFIER ZONE 9 1 61 10 60 24.231 0.102 25.146 0.127 26 44 27 43 5.080 MAX SEATING PLANE 0.10 1.27 TYP 0.330/0.533 0.51 MIN, TYP 5-2139.r13 (F) Lucent Technologies Inc. 43 T7531A/T7536 16-Channel Programmable Codec Chip Set Data Sheet February 1999 Ordering Information Device Code T-7531A - - - ML T-7531A - - - ML-TR T-7536 - - - ML T-7536 - - - ML-TR Package 68-Pin PLCC 68-Pin PLCC 68-Pin PLCC 68-Pin PLCC Temperature -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C Comcode 107529729 107578627 107393993 107412041 For additional information, contact your Microelectronics Group Account Manager or the following: http://www.lucent.com/micro INTERNET: docmaster@micro.lucent.com E-MAIL: N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright (c) 1999 Lucent Technologies Inc. All Rights Reserved February 1999 DS99-093ALC (Replaces DS98-272ALC)