Complete, Dual, 12-/14-/16-Bit, Serial Input,
Unipolar/Bipolar, Voltage Output DACs
Data Sheet AD5722R/AD5732R/AD5752R
Rev. F Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2008–2017 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Complete, dual, 12-/14-/16-bit digital-to-analog converter (DAC)
Operates from single/dual supplies
Software programmable output range
+5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V
INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum
Total unadjusted error (TUE): 0.1% FSR maximum
Settling time: 10 μs typical
Integrated reference: 5 ppm/°C maximum
Integrated reference buffers
Output control during power-up/brownout
Simultaneous updating via LDAC
Asynchronous CLR to zero scale or midscale
DSP-/microcontroller-compatible serial interface
24-lead TSSOP
Operating temperature range: −40°C to +85°C
iCMOS process technology1
APPLICATIONS
Industrial automation
Closed-loop servo control, process control
Automotive test and measurement
Programmable logic controllers
GENERAL DESCRIPTION
The AD5722R/AD5732R/AD5752R are dual, 12-/14-/16-bit,
serial input, voltage output digital-to-analog converters. They
operate from single supply voltages of +4.5 V up to +16.5 V or
dual supply voltages from ±4.5 V up to ±16.5 V.
Nominal full-scale output range is software selectable from
+5 V, +10 V, +10.8 V, ±5 V, ±10 V, or ±10.8 V. Integrated output
amplifiers, reference buffers, and proprietary power-up/power-
down control circuitry are also provided.
The devices offer guaranteed monotonicity, integral
nonlinearity (INL) of ±16 LSB maximum, low noise, 10 μs
maximum settling time, and an on-chip +2.5 V reference.
The AD5722R/AD5732R/AD5752R use a serial interface that
operates at clock rates up to 30 MHz and are compatible with
DSP and microcontroller interface standards. Double buffering
allows the simultaneous updating of all DACs. The input coding
is user-selectable twos complement or offset binary for a bipolar
output (depending on the state of Pin BIN/2sComp), and
straight binary for a unipolar output. The asynchronous clear
function clears all DAC registers to a user-selectable zero-scale
or midscale output. The devices are available in a 24-lead
TSSOP and offer guaranteed specifications over the −40°C to
+85°C industrial temperature range.
Table 1. Pin Compatible Devices
Device Number Description
AD5722/AD5732/AD5752 AD5722R/AD5732R/AD5752R
without internal reference.
AD5724/AD5734/AD5754 Complete, quad, 12-/14-/16-bit,
serial input, unipolar/bipolar,
voltage output DACs.
AD5724R/AD5734R/AD5754R AD5724/AD5734/AD5754 with
internal reference.
.
FUNCTIONAL BLOCK DIAGRAM
DAC B
INPUT
REGISTER A
INPUT
REGISTER B
n
AD5722: n = 12-BIT
AD5732: n = 14-BIT
AD5752: n = 16-BIT
n
nDAC A
LDAC
REFIN/REFOUT
V
OUT
B
V
OUT
A
REFERENCE
BUFFERS
SDIN
SCLK
SYNC
SDO
DVCC 2.5V
REFERENCE
GND DAC_GND (2) SIG_GND (2)
AD5722R/AD5732R/AD5752R
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
A
VDD
AVSS
DAC
REGI STER A
DAC
REGI STER B
CLR
BIN/2sCOMP
06466-001
Figure 1.
1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS® is a technology
platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and
package size, as well as increased ac and dc performance.
AD5722R/AD5732R/AD5752R Data Sheet
Rev. F | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Performance Characteristics ................................................ 5
Timing Characteristics ................................................................ 6
Timing Diagrams .......................................................................... 7
Absolute Maximum Ratings ............................................................ 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 20
Architecture ................................................................................. 20
Serial Interface ............................................................................ 20
Load DAC (LDAC)..................................................................... 22
Asynchronous Clear (CLR) ....................................................... 22
Configuring the AD5722R/AD5732R/AD5752R .................. 22
Transfer Function ....................................................................... 22
Input Shift Register .................................................................... 26
DAC Register .............................................................................. 27
Output Range Select Register ................................................... 27
Control Register ......................................................................... 28
Power Control Register.............................................................. 28
Design Features ............................................................................... 29
Analog Output Control ............................................................. 29
Power-Up Sequence ................................................................... 20
Power-Down Mode .................................................................... 29
Overcurrent Protection ............................................................. 29
Thermal Shutdown .................................................................... 29
Internal Reference ...................................................................... 29
Applications Information .............................................................. 30
+5 V/±5 V Operation ................................................................ 30
Layout Guidelines....................................................................... 30
Galvanically Isolated Interface ................................................. 31
Microprocessor Interfacing ....................................................... 31
Outline Dimensions ....................................................................... 32
Ordering Guide .......................................................................... 32
REVISION HISTORY
2/2017Rev. E to Rev. F
Added Power-Up Sequence Section ............................................. 20
Changes to Table 8 and Table 9 ..................................................... 23
Changes to Table 11 and Table 12 ................................................ 24
Changes to Table 14 and Table 15 ................................................ 25
Change to Analog Output Section ............................................... 29
Added Alternative Power-Up Sequence Support Section ......... 30
2/2016Rev. D to Rev. E
Changes to Table 1 ............................................................................ 3
7/2011Rev. C to Rev. D
Changes to Table 4: t7, t8, t10 Limits ....................................................... 6
3/2011Rev. B to Rev. C
Changes to Configuring the AD5722R/AD5732R/
AD5752R Section ........................................................................... 22
8/2010Rev. A to Rev. B
Changes to Table 28 ....................................................................... 28
4/2010Rev. 0 to Rev. A
Changes to Junction Temperature, TJ max Parameter, Table 5 ... 9
Changes to Exposed Paddle Description, Table 6 ...................... 10
11/2008Revision 0: Initial Version
Data Sheet AD5722R/AD5732R/AD5752R
Rev. F | Page 3 of 32
SPECIFICATIONS
AVDD = 4.5 V1 to 16.5 V; AVSS = −4.5 V1 to −16.5 V, or AVSS = 0 V; GND = 0 V; REFIN= 2.5 V external; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ;
CLOAD = 200 pF; all specifications TMIN to TMAX unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
ACCURACY
Outputs unloaded
Resolution
AD5752R 16 Bits
AD5732R 14 Bits
AD5722R 12 Bits
Total Unadjusted Error (TUE)
−0.1
+0.1
% FSR
±10 V range
Integral Nonlinearity (INL)2
AD5752R −16 +16 LSB
AD5732R −4 +4 LSB
AD5722R −1 +1 LSB
Differential Nonlinearity (DNL) −1 +1 LSB All models, guaranteed monotonic
Bipolar Zero Error −6 +6 mV ±10 V range, TA = 25 C, error at other temperatures
obtained using bipolar zero TC
Bipolar Zero TC3 ±4 ppm FSR/°C
Zero-Scale Error −6 +6 mV ±10 V range, TA = 25°C, error at other temperatures
obtained using zero-scale TC
Zero-Scale TC3 ±4 ppm FSR/°C
Offset Error −6 +6 mV 10 V range, TA = 25°C, error at other temperatures
obtained using offset error TC
Offset Error TC3 ±4 ppm FSR/°C
Gain Error −0.025 +0.025 % FSR ±10 V range, TA = 25°C, error at other temperatures
obtained using gain TC
Gain Error3 −0.065 0 % FSR +10 V and +5 V ranges, TA = 25°C, error at other
temperatures obtained using gain TC
Gain Error3 0 0.08 % FSR ±5 V range, TA = 25°C, error at other temperatures
obtained using gain TC
Gain TC3 ±4 ppm FSR/°C
DC Crosstalk3 120 µV
REFERENCE INPUT/OUTPUT
Reference Input3
Reference Input Voltage 2.5 V ±1% for specified performance
DC Input Impedance 1 5 MΩ
Input Current −2 ±0.5 +2 µA
Reference Range +2 +3 V
Reference Output
Output Voltage
+2.497
+2.501
V
T
A
= 25°C
Reference TC3 −5 ±1.8 +5 ppm/°C 0°C to +85°C
−10 ±2.2 +10 ppm/°C −40°C to +85°C
Output Noise (0.1 Hz to 10 Hz)3 5 µV p-p
Noise Spectral Density3 75 nV/√Hz 10 kHz
OUTPUT CHARACTERISTICS3
Output Voltage Range −10.8 +10.8 V AVDD/AVSS = ±11.7 V min, REFIN = 2.5 V
−12 +12 V AVDD/AVSS = ±12.9 V min, REFIN = 3 V
Headroom 0.5 0.9 V
Output Voltage TC ±4 ppm FSR/°C
Short-Circuit Current 20 mA
Load 2 kΩ For specified performance
Capacitive Load Stability 4000 pF
DC Output Impedance 0.5
AD5722R/AD5732R/AD5752R Data Sheet
Rev. F | Page 4 of 32
Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUTS3 DVCC = 2.7 V to 5.5 V, JEDEC compliant
Input High Voltage, VIH 2 V
Input Low Voltage, VIL 0.8 V
Input Current ±1 µA Per pin
Pin Capacitance
5
pF
Per pin
DIGITAL OUTPUTS (SDO) 3
Output Low Voltage, VOL 0.4 V DVCC = 5 V ± 10%, sinking 200 µA
Output High Voltage, VOH DVCC − 1 V DVCC = 5 V ± 10%, sourcing 200 µA
Output Low Voltage, VOL 0.4 V DVCC = 2.7 V to 3.6 V, sinking 200 µA
Output High Voltage, VOH DVCC − 0.5 V DVCC = 2.7 V to 3.6 V, sourcing 200 µA
High Impedance Leakage Current ±1 µA
High Impedance Output
Capacitance
5 pF
POWER REQUIREMENTS
AVDD 4.5 16.5 V
AVSS −4.5 −16.5 V
DVCC 2.7 5.5 V
Power Supply Sensitivity3
∆VOUT/∆ΑVDD −65 dB
AIDD 3.25 mA/channel Outputs unloaded
2.4 mA/channel AVSS = 0 V, outputs unloaded
AI
SS
2.5
mA/channel
Outputs unloaded
DICC 0.5 3 µA VIH = DVCC, VIL = GND
Power Dissipation 190 mW ±16.5 V operation, outputs unloaded
79 mW +16.5 V operation, AVSS = 0 V, outputs unloaded
Power-Down Currents
AIDD 40 µA
AISS 40 µA
DICC 300 nA
1 For specified performance, the headroom requirement is 0.9 V.
2 INL is the relative accuracy. It is measured from Code 512, Code 128, and Code 32 for the AD5752R, AD5732R, and AD5722R, respectively.
3 Guaranteed by characterization; not production tested.
Data Sheet AD5722R/AD5732R/AD5752R
Rev. F | Page 5 of 32
AC PERFORMANCE CHARACTERISTICS
AVDD = 4.5 V1 to 16.5 V; AVSS = −4.5 V to −16.5 V, or AVSS = 0 V; GND = 0 V; REFIN = 2.5 V external; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ;
CLOAD = 200 pF; all specifications TMIN to TMAX unless otherwise noted.
Table 3.
B Version
Parameter2 Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time 10 12 µs 20 V step to ±0.03% FSR
7.5 8.5 µs 10 V step to ±0.03% FSR
5 µs 512 LSB step settling (16-bit resolution)
Slew Rate 3.5 V/µs
Digital-to-Analog Glitch Energy 13 nV-sec
Glitch Impulse Peak Amplitude 35 mV
Digital Crosstalk 10 nV-sec
DAC-to-DAC Crosstalk
nV-sec
Digital Feedthrough 0.6 nV-sec
Output Noise
0.1 Hz to 10 Hz Bandwidth 15 µV p-p 0x8000 DAC code
100 kHz Bandwidth 80 µV rms
Output Noise Spectral Density 320 nV/√Hz Measured at 10 kHz, 0x8000 DAC code
1 For specified performance, the headroom requirement is 0.9 V.
2 Guaranteed by design and characterization; not production tested.
AD5722R/AD5732R/AD5752R Data Sheet
Rev. F | Page 6 of 32
TIMING CHARACTERISTICS
AVDD = 4.5 V to 16.5 V; AVSS = −4.5 V to −16.5 V, or AVSS = 0 V; GND = 0 V; REFIN = 2.5 V external; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ;
CLOAD = 200 pF; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1, 2, 3 Limit at tMIN, tMAX Unit Description
t1 33 ns min SCLK cycle time
t2 13 ns min SCLK high time
t3 13 ns min SCLK low time
t4 13 ns min SYNC falling edge to SCLK falling edge setup time
t
5
13
ns min
SCLK falling edge to
SYNC
rising edge
t6 100 ns min Minimum SYNC high time (write mode)
t7 7 ns min Data setup time
t8 2 ns min Data hold time
t9 20 ns min LDAC falling edge to SYNC falling edge
t10 130 ns min SYNC rising edge to LDAC falling edge
t11 20 ns min LDAC pulse width low
t12 10 µs typ DAC output settling time
t13 20 ns min CLR pulse width low
t14 2.5 µs max CLR pulse activation time
t154 13 ns min SYNC rising edge to SCLK rising edge
t
164
40
ns max
SCLK rising edge to SDO valid (C
L SDO5
= 15 pF)
t17 200 ns min Minimum SYNC high time (readback/daisy-chain mode)
1 Guaranteed by characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 Daisy-chain and readback mode.
5 CL SDO = capacitive load on SDO output.
Data Sheet AD5722R/AD5732R/AD5752R
Rev. F | Page 7 of 32
TIMING DIAGRAMS
06466-002
DB23
SCLK
SYNC
SDIN
LDAC
CLR
V
OUT
x
V
OUT
x
V
OUT
x
4221
DB0
t12
t12
t10 t11
t14
t13
t9
t8
t7
t4
t6t3t2
t1
t5
Figure 2. Serial Interface Timing Diagram
06466-003
t4
t10
t16
t8
t7
t11
t3t2t5
t1
t15
LDAC
SDO
SDIN
SYNC
SCLK 8442
D0BD32BD0BD32B
DB23
INPUT WORD FOR DAC NUNDEFINED
INPU T WO RD FOR DAC N – 1INPUT WORD FOR DAC N
DB0
t17
Figure 3. Daisy-Chain Timing Diagram
AD5722R/AD5732R/AD5752R Data Sheet
Rev. F | Page 8 of 32
SDO
SDIN
SYNC
SCLK 24 24
DB23 DB0 DB23 DB0
SELECTED REGISTER DATA
CLO CKE D OUT
UNDEFINED
NOP CONDITI ONINPUT WORD SPECIFIES
REGISTER T O BE RE AD
11
DB23 DB0 DB23 DB0
t
17
06466-004
Figure 4. Readback Timing Diagram
Data Sheet AD5722R/AD5732R/AD5752R
Rev. F | Page 9 of 32
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 5.
Parameter Rating
AVDD to GND 0.3 V to +17 V
AVSS to GND +0.3 V to 17 V
DVCC to GND 0.3 V to +7 V
Digital Inputs to GND 0.3 V to DVCC + 0.3 V or to
7 V (whichever is less)
Digital Outputs to GND
0.3 V to DV
CC
+ 0.3 V or to
7 V (whichever is less)
REFIN/REFOUT to GND 0.3 V to +5 V
VOUTA or VOUTB to GND AVSS to AVDD
DAC_GND to GND −0.3 V to +0.3 V
SIG_GND to GND −0.3 V to +0.3 V
Operating Temperature Range, T
A
Industrial 40°C to +85°C
Storage Temperature Range 65°C to +150°C
Junction Temperature, TJ max 150°C
24-Lead TSSOP Package
θJA Thermal Impedance 42°C/W
θJC Thermal Impedance C/W
Power Dissipation (TJ max − TA)/θJA
Lead Temperature JEDEC industry standard
Soldering J-STD-020
ESD (Human Body Model) 3.5 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
AD5722R/AD5732R/AD5752R Data Sheet
Rev. F | Page 10 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD5722R/
AD5732R/
AD5752R
CLR
LDAC
AVSS
NC
VOUTA
NC
SYNC
NC
BIN/2sCOMP
GND
SDO
REFIN/REFOUT
SIG_GND
SCLK
SDIN
NC
NOTES
1. NC = NO CO NNE CT
2. I T I S RE COMM E NDED THAT THE E X P O S E D P AD BE
THERMALLY CONNECT E D TO A COPPE R P LANE
FOR ENHANCED THERM AL PERFO RM ANCE .
AVDD
VOUTB
NC
SIG_GND
DAC_GND
DAC_GND
DVCC
NC
TOP VIEW
(No t t o Scal e)
06466-005
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 AVSS Negative Analog Supply. Voltage ranges from −4.5 V to −16.5 V. This pin can be connected to 0 V if output
ranges are unipolar.
2, 4, 6, 12,
13, 22
NC Do not connect to these pins.
3 VOUTA Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
5 BIN/2sCOMP Determines the DAC coding for a bipolar output range. This pin must be hardwired to either DVCC or GND.
When hardwired to DVCC, input coding is offset binary. When hardwired to GND, input coding is twos
complement. (For unipolar output ranges, coding is always straight binary.)
7 SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred on the falling edge of SCLK. Data is latched on the rising edge of SYNC.
8 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock
speeds up to 30 MHz.
9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK.
10 LDAC Load DAC, Logic Input. This is used to update the DAC registers and, consequently, the analog output. When
this pin is tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is
held high during the write cycle, the DAC input register is updated, but the output update is held off until the
falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of
LDAC. The LDAC pin must not be left unconnected.
11 CLR Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or midscale code (user selectable).
14 DVCC Digital Supply. Voltage ranges from 2.7 V to 5.5 V.
15 GND Ground Reference.
16 SDO Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is
clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
17 REFIN/REFOUT External Reference Voltage Input and Internal Reference Voltage Output. Reference input range is 2 V to 3 V.
REFIN = 2.5 V for specified performance. REFOUT = 2.5 V ± 2 mV.
18, 19 DAC_GND Ground Reference for the Four Digital-to-Analog Converters.
20, 21 SIG_GND Ground Reference for the Four Output Amplifiers.
23 VOUTB Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
24
AV
DD
Positive Analog Supply. Voltage ranges from 4.5 V to 16.5 V.
Exposed
Paddle
This exposed paddle must be connected to the potential of the AVSS pin, or alternatively, it can be left electrically
unconnected. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal
performance.
Data Sheet AD5722R/AD5732R/AD5752R
Rev. F | Page 11 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
CODE
INL E RROR (LSB)
010,000 20,000 30,000 40,000 50,000 60,000
–8
–6
–4
–2
0
2
4
6AVDD/AVSS = + 12V /0V, RANGE = + 10V
AVDD/AVSS = ± 12V , RANGE = ± 10V
AVDD/AVSS = ± 6.5V, RANGE = ±5V
AVDD/AVSS = + 6.5V/0V, RANGE = + 5V
06466-013
Figure 6. AD5752R Integral Nonlinearity Error vs. Code
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
CODE
INL E RROR (LSB)
AV
DD
/AV
SS
= +12V/0V, RANGE = + 10V
AV
DD
/AV
SS
= ±12V, RANGE = ± 10V
AV
DD
/AV
SS
= ±6. 5V , RANGE = ± 5V
AV
DD
/AV
SS
= +6. 5V /0V, RANGE = + 5V
02000 4000 6000 8000 10,000 12,000 14,000 16,000
06466-014
Figure 7. AD5732R Integral Nonlinearity Error vs. Code
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0500 1000 1500 2000 2500 3000 3500 4000
06466-015
CODE
INL E RROR (LSB)
AV
DD
/AV
SS
= +12V/0V, RANGE = + 10V
AV
DD
/AV
SS
= ±12V, RANGE = ± 10V
AV
DD
/AV
SS
= ±6. 5V , RANGE = ± 5V
AV
DD
/AV
SS
= +6. 5V /0V, RANGE = + 5V
Figure 8. AD5722R Integral Nonlinearity Error vs. Code
CODE
DNL ERROR (LSB)
AV
DD
/AV
SS
= +12V/0V, RANGE = + 10V
AV
DD
/AV
SS
= ±12V, RANGE = ± 10V
AV
DD
/AV
SS
= ±6. 5V , RANGE = ± 5V
AV
DD
/AV
SS
= +6. 5V /0V, RANGE = + 5V
010,000 20,000 30,000 40,000 50,000 60,000
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
06466-016
Figure 9. AD5752R Differential Nonlinearity Error vs. Code
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
CODE
DNL ERROR (LSB)
AV
DD
/AV
SS
= +12V/0V, RANGE = + 10V
AV
DD
/AV
SS
= ±12V, RANGE = ± 10V
AV
DD
/AV
SS
= ±6. 5V , RANGE = ± 5V
AV
DD
/AV
SS
= +6. 5V /0V, RANGE = + 5V
02000 4000 6000 8000 10,000 12,000 14,000 16,000
06466-017
Figure 10. AD5732R Differential Nonlinearity Error vs. Code
–0.05
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
0.03
0.04
0500 1000 1500 2000 2500 3000 3500 4000
AVDD/AVSS = + 12V /0V, RANGE = + 10V
AVDD/AVSS = ± 12V , RANGE = ± 10V
AVDD/AVSS = ± 6.5V, RANGE = ±5V
AVDD/AVSS = + 6.5V/0V, RANGE = +5V
06466-018
CODE
DNL ERROR (LSB)
Figure 11. AD5722R Differential Nonlinearity Error vs. Code
AD5722R/AD5732R/AD5752R Data Sheet
Rev. F | Page 12 of 32
TEMPERATURE (°C)
INL E RROR (LSB)
–8
–6
–4
–2
0
2
4
6
8
–40 –20 020 40 60 80
MAX I NL ±10V
MAX I NL ±5V
MI N I NL ±10V
MI N I NL ±5V
MAX I NL +10V
MI N I NL +10V
MAX I NL +5V
MI N I NL +5V
06466-044
Figure 12. AD5752R Integral Nonlinearity Error vs. Temperature
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
TEMPERATURE (°C)
DNL ERROR (LSB)
–40 –20 020 40 60 80
MAX DNL ±10V
MAX DNL ±5V
MI N DNL ±10V
MI N DNL ±5V
MAX DNL +10V
MI N DNL +10V
MAX DNL +5V
MI N DNL +5V
06466-045
Figure 13. AD5752R Differential Nonlinearity Error vs. Temperature
–10
–8
–6
–4
–2
0
2
4
6
8
10
SUPPLY VOLT AGE (V)
INL E RROR (LSB)
11.5 12.512.0 13.5 14.013.0 14.5 15.0 15.5 16.0 16.5
BIPOL AR 10V M IN
UNIPOL AR 10V M IN
BIPOL AR 10V M AX
UNIPOL AR 10V M AX
06466-034
Figure 14. AD5752R Integral Nonlinearity Error vs. Supply Voltage
SUPPLY VOLT AGE (V)
DNL ERROR (LSB)
11.5 12.5
12.0 13.5 14.013.0 14.5 15.0 15.5 16.0 16.5
0
0.6
0.4
0.2
1.0
0.8
–0.6
–0.4
–0.2
–1.0
–0.8
BIPOL AR 10V M IN
UNIPOL AR 10V M IN
BIPOL AR 10V M AX
UNIPOL AR 10V M AX
06466-032
Figure 15. AD5752R Differential Nonlinearity Error vs. Supply Voltage
SUPPLY VOLT AGE (V)
5.5 8.56.5 7.5 10.5 11.59.5 12.5 13.5 14.5 15.5 16.5
–10
–8
–6
–4
–2
0
2
4
6
8
10
INL E RROR (LSB)
BIPOL AR 5V M IN
UNIPOL AR 5V M IN
BIPOL AR 5V M AX
UNIPOL AR 5V M AX
06466-035
Figure 16. AD5752R Integral Nonlinearity Error vs. Supply Voltage
SUPPLY VOLT AGE (V)
DNL ERROR (LSB)
5.5 8.56.5 7.5 10.5 11.59.5 12.5 13.5 14.5 15.5 16.5
0
0.6
0.4
0.2
1.0
0.8
–0.6
–0.4
–0.2
–1.0
–0.8
BIPOL AR 5V M IN
UNIPOL AR 5V M IN
BIPOL AR 5V M AX
UNIPOL AR 5V M AX
06466-033
Figure 17. AD5752R Differential Nonlinearity Error vs. Supply Voltage
Data Sheet AD5722R/AD5732R/AD5752R
Rev. F | Page 13 of 32
SUPPLY VOLT AGE (V)
11.5 12.512.0 13.5 14.013.0 14.5 15.0 15.5 16.0 16.5
BIPOL AR 10V M IN
UNIPOL AR 10V M IN
BIPOL AR 10V M AX
UNIPOL AR 10V M AX
TUE (%)
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
06466-036
Figure 18. AD5752R Total Unadjusted Error vs. Supply Voltage
SUPPLY VOLT AGE (V)
5.5 8.5
6.5 7.5 10.5 11.59.5 12.5 13.5 14.5 15.5 16.5
–0.05
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
0.03
0.04
TUE (%)
BIPOL AR 5V M IN
UNIPOL AR 5V M IN
BIPOL AR 5V M AX
UNIPOL AR 5V M AX
06466-037
Figure 19. AD5752R Total Unadjusted Error vs. Supply Voltage
–3
–2
–1
0
1
2
3
4
TEMPERATURE (°C)
ZE RO -SCAL E E RROR (mV )
06466-046
–40 –20 020 40 60 80
±10V
±5V
+10V
Figure 20. Zero-Scale Error vs. Temperature
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
TEMPERATURE (°C)
BIPOL AR ZERO-SCALE E RROR (mV)
06466-047
–40 –20 020 40 60 80
±5V RANG E
±10V RANG E
Figure 21. Bipolar Zero-Scale Error vs. Temperature
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
±10V
±5V
+10V
TEMPERATURE (°C)
GAI N E RROR (% FSR)
06466-048
–40 –20 020 40 60 80
Figure 22. Gain Error vs. Temperature
06466-043
V
LOGIC
(V)
DI
CC
(µA)
–100
0
100
200
300
400
500
600
700
800
900
1000
0 1 2 3 4 5 6
DV
CC
= 5V
DV
CC
= 3V
Figure 23. Digital Current vs. Logic Input Voltage
AD5722R/AD5732R/AD5752R Data Sheet
Rev. F | Page 14 of 32
06466-040
OUT P UT CURRENT (mA)
OUTPUT VOLTAGE DELTA (V)
–0.020
–0.015
–0.010
–0.005
0
0.005
0.010
–25 –20 –15 –10 –5 0510 15 20 25
±5V RANG E , CODE = 0xFF FF
±10V RANG E , CODE = 0xFF FF
+10V RANG E , CO DE = 0xFFFF
+5V RANG E , CO DE = 0xFFFF
±5V RANG E , CODE = 0x0000
±10V RANG E , CODE = 0x0000
Figure 24. Output Source and Sink Capability
–15
–10
–5
0
5
10
15
–3 –1 135 7 9 11
06466-022
TIME (µs)
OUTPUT VOLTAGE (V)
Figure 25. Full-Scale Settling Time, ±10 V Range
–7
–5
–3
–1
1
3
5
7
–3 –1 1 3 5 7 9 11
06466-023
TIME (µs)
OUTPUT VOLTAGE (V)
Figure 26. Full-Scale Settling Time, ±5 V Range
0
2
4
6
8
10
12
–3 –1 1 3 5 7 9 11
06466-024
TIME (µs)
OUTPUT VOLTAGE (V)
Figure 27. Full-Scale Settling Time, +10 V Range
0
1
2
3
4
5
6
–3 –1 1 3 5 7 911
06466-025
TIME (µs)
OUTPUT VOLTAGE (V)
Figure 28. Full-Scale Settling Time, +5 V Range
06466-039
TIME (µs)
OUTPUT VOLTAGE (V)
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
0.020
–1 01 2 3 4 5
±
±
±
±
±10V RANG E , 0x7FFF TO 0x8000
±10V RANG E , 0x8000 TO 0x7F FF
±5V RANG E , 0x7FFF TO 0x8000
±5V RANG E , 0x8000 TO 0x7F FF
+10V RANG E , 0x7F FF TO 0x8000
+10V RANG E , 0x8000 T O 0x7FFF
+5V RANG E , 0x7F FF TO 0x8000
+5V RANG E , 0x8000 T O 0x7FFF
Figure 29. Digital-to-Analog Glitch Energy
Data Sheet AD5722R/AD5732R/AD5752R
Rev. F | Page 15 of 32
CH1 5µV M 5s LINE 73.8V
1
RANGE = + 10V
RANGE = ±10V
RANGE = ±5V
RANGE = +5V
0
6466-026
Figure 30. Peak-to-Peak Noise, 0.1 Hz to 10 Hz Bandwidth
CH1V M 5s LINE 73.8V
1
RANGE = +10V
RANGE = ±10V
RANGE = ±5V
RANGE = +5V
06466-027
Figure 31. Peak-to-Peak Noise, 100 kHz Bandwidth
06466-041
TIME (µs)
OUTPUT VOLTAGE (V)
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
5030101030507090
AV
DD
/AV
SS
= ±16.5V
AV
DD
= +16.5V, AVSS = 0V
Figure 32. Output Glitch on Power-Up
06466-028
CH1 5V CH2 50 0mV M 200µ s CH1 2. 9V
2
1
Figure 33. REFOUT Turn-On Transient
06466-029
CH1 100mV M 5s LINE 1.2V
1
Figure 34. REFOUT Output Noise (100 kHz Bandwidth)
06466-030
CH1 10mV M 5s LINE 1.2V
1
Figure 35. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth)
AD5722R/AD5732R/AD5752R Data Sheet
Rev. F | Page 16 of 32
–0.18 –0.13 –0.08 –0.03 0.02 0.07 0.12 0.17
06466-031
LO AD CURRE NT (mA)
REF
OUT
VOLTAGE (V)
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
Figure 36. REFOUT Voltage vs. Load Current
06466-019
CODE
TUE (LSB)
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
01000 2000 3000 4000 5000 6000
AV
DD
/AV
SS
= +12V/0V, RANGE = + 10V
AV
DD
/AV
SS
= ±12V, RANGE = ± 10V
AV
DD
/AV
SS
= ±6. 5V , RANGE = ± 5V
AV
DD
/AV
SS
= +6. 5V /0V, RANGE = + 5V
Figure 37. AD5752R Total Unadjusted Error vs. Code
–10
–8
–6
–4
–2
0
2
4
02000 4000 6000 8000 10,000 12,000 14,000 16,000
CODE
TUE (LSB)
AV
DD
/AV
SS
= +12V/0V, RANGE = + 10V
AV
DD
/AV
SS
= ±12V, RANGE = ± 10V
AV
DD
/AV
SS
= ±6. 5V , RANGE = ± 5V
AV
DD
/AV
SS
= +6. 5V /0V, RANGE = + 5V
06466-020
Figure 38. AD5732R Total Unadjusted Error vs. Code
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
0500 1000 1500 2000 2500 3000 3500 4000
06466-021
CODE
TUE (LSB)
AV
DD
/AV
SS
= +12V/0V, RANGE = + 10V
AV
DD
/AV
SS
= ±12V, RANGE = ± 10V
AV
DD
/AV
SS
= ±6. 5V , RANGE = ± 5V
AV
DD
/AV
SS
= +6. 5V /0V, RANGE = + 5V
Figure 39. AD5722R Total Unadjusted Error vs. Code
40
35
30
25
20
15
10
5
01.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
TEMPERATURE COEFFICIENT (ppm/°C)
POPULATION (%)
06466-049
Figure 40. Reference Output TC (−40°C to +85°C)
40
35
30
25
20
15
10
5
01.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TEMPERATURE COEFFICIENT (ppm/°C)
POPULATION (%)
06466-052
Figure 41. Reference Output TC (0°C to 85°C)