HUF75307P3, HUF75307D3, HUF75307D3S Data Sheet December 2001 15A, 55V, 0.090 Ohm, N-Channel UltraFET Power MOSFETs These N-Channel power MOSFETs are manufactured using the innovative UltraFET(R) process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and battery-operated products. Features * 15A, 55V * Simulation Models - Temperature Compensated PSPICE (R) and SABERTM Models - SPICE and SABER Thermal Impedance Models Available on the WEB at: www.fairchildsemi.com * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol Formerly developmental type TA75307. D Ordering Information PART NUMBER HUF75307P3 PACKAGE BRAND TO-220AB 75307P HUF75307D3 TO-251AA 75307D HUF75307D3S TO-252AA 75307D G S NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-252AA variant in tape and reel, e.g., HUF75307D3ST. Packaging JEDEC TO-220AB JEDEC TO-251AA SOURCE DRAIN GATE SOURCE DRAIN GATE DRAIN (FLANGE) DRAIN (FLANGE) JEDEC TO-252AA DRAIN (FLANGE) GATE SOURCE Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html For severe environments, see our Automotive HUFA series. All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification. (c)2001 Fairchild Semiconductor Corporation HUF75307P3, HUF75307D3, HUF75307D3S Rev. B HUF75307P3, HUF75307D3, HUF75307D3S Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg UNITS V V V 55 55 20 15 Figure 4 Figures 6, 14, 15 45 0.3 -55 to 175 A W W/oC oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 55 - - V VDS = 50V, VGS = 0V - - 1 A VDS = 45V, VGS = 0V, TC = 150oC - - 250 A VGS = 20V - - 100 nA OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current BVDSS IDSS IGSS ID = 250A, VGS = 0V (Figure 11) ON STATE SPECIFICATIONS Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250A (Figure 10) 2 - 4 V Drain to Source On Resistance rDS(ON) ID = 15A, VGS = 10V (Figure 9) - 0.075 0.090 THERMAL SPECIFICATIONS Thermal Resistance Junction to Case RJC (Figure 3) - - 3.3 oC/W Thermal Resistance Junction to Ambient RJA TO-220AB - - 62 oC/W TO-251AA, TO-252AA - - 100 oC/W VDD = 30V, ID 15A, RL = 2.0, VGS = 10V, RGS = 100 - - 60 ns - 7 - ns tr - 40 - ns td(OFF) - 35 - ns tf - 45 - ns tOFF - - 100 ns - 16 20 nC - 9 11 nC - 0.6 0.8 nC SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) GATE CHARGE SPECIFICATIONS Qg(TOT) VGS = 0V to 20V Gate Charge at 10V Qg(10) VGS = 0V to 10V Threshold Gate Charge Qg(TH) VGS = 0V to 2V Total Gate Charge VDD = 30V, ID 15A, RL = 2.0 Ig(REF) = 1.0mA (Figure13) Gate to Source Gate Charge Qgs - 1.2 - nC Reverse Transfer Capacitance Qgd - 4 - nC (c)2001 Fairchild Semiconductor Corporation HUF75307P3, HUF75307D3, HUF75307D3S Rev. B HUF75307P3, HUF75307D3, HUF75307D3S TC = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 250 - pF - 100 - pF - 25 - pF CAPACITANCE SPECIFICATIONS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage MIN TYP MAX UNITS ISD = 15A - - 1.25 V trr ISD = 15A, dISD/dt = 100A/s - - 45 ns QRR ISD = 15A, dISD/dt = 100A/s - - 55 nC VSD Reverse Recovery Time Reverse Recovered Charge TEST CONDITIONS Typical Performance Curves 20 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 15 10 5 0.2 0 0 0 25 50 75 100 125 150 25 175 50 TC , CASE TEMPERATURE (oC) ZJC, NORMALIZED THERMAL IMPEDANCE 1 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 2 75 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE (c)2001 Fairchild Semiconductor Corporation HUF75307P3, HUF75307D3, HUF75307D3S Rev. B HUF75307P3, HUF75307D3, HUF75307D3S Typical Performance Curves (Continued) IDM, PEAK CURRENT (A) 200 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 100 175 - TC I = I25 150 VGS = 10V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY 100 200 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) TJ = MAX RATED TC = 25oC 100s 10 1ms 1 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC VDSS(MAX) = 55V 0.1 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 10 1 100 200 0.001 0.01 VDS, DRAIN TO SOURCE VOLTAGE (V) 0.1 1 10 tAV, TIME IN AVALANCHE (ms) NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 25 VGS = 20V VGS = 10V 20 VGS = 7V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 25 VGS = 6V 15 10 VGS = 5V 5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC 0 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 7. SATURATION CHARACTERISTICS (c)2001 Fairchild Semiconductor Corporation PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 20 -55oC 25oC 15 175oC 10 5 0 5 0 1.5 3.0 4.5 6.0 7.5 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 8. TRANSFER CHARACTERISTICS HUF75307P3, HUF75307D3, HUF75307D3S Rev. B HUF75307P3, HUF75307D3, HUF75307D3S Typical Performance Curves (Continued) 1.2 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 15A VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.5 2.0 1.5 1.0 0.5 1.0 0.8 0.6 -80 -40 0 40 80 120 160 200 -80 -40 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 40 80 120 160 200 FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 1.2 400 VGS = 0, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD ID = 250A C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 0 TJ, JUNCTION TEMPERATURE (oC) 1.1 1.0 300 CISS 200 COSS 100 CRSS 0.9 0 -80 -40 0 40 80 120 160 200 0 10 TJ , JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE VGS , GATE TO SOURCE VOLTAGE (V) 20 30 40 50 60 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 8 6 4 2 VDD = 30V 0 0 2 4 WAVEFORMS IN DESCENDING ORDER: ID = 15A ID = 12A ID = 7.5A ID = 4A 6 8 10 Qg, GATE CHARGE (nC) NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT (c)2001 Fairchild Semiconductor Corporation HUF75307P3, HUF75307D3, HUF75307D3S Rev. B HUF75307P3, HUF75307D3, HUF75307D3S Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01 tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD VGS = 10V VGS DUT VGS = 2V IG(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM VDS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + VGS - VDD 10% 0 10% DUT 90% RGS VGS VGS 0 FIGURE 18. SWITCHING TIME TEST CIRCUIT (c)2001 Fairchild Semiconductor Corporation 10% 50% 50% PULSE WIDTH FIGURE 19. RESISTIVE SWITCHING WAVEFORMS HUF75307P3, HUF75307D3, HUF75307D3S Rev. B HUF75307P3, HUF75307D3, HUF75307D3S PSPICE Electrical Model .SUBCKT HUF75307 2 1 3 ; rev June 1997 CA 12 8 4.5e-10 CB 15 14 4.1e-10 CIN 6 8 2.154e-10 LDRAIN DPLCAP 10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD DBREAK + RSLC2 5 51 ESLC 11 - RDRAIN 6 8 ESG EVTHRES + 19 8 + GATE 1 LDRAIN 2 5 1e-9 LGATE 1 9 5.97e-10 LSOURCE 3 7 2.39e-9 K1 LGATE LSOURCE 0.131 + 17 EBREAK 18 50 - LGATE EVTEMP RGATE + 18 22 9 20 21 DBODY - 16 MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 SOURCE 3 7 RSOURCE MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RLSOURCE S1A 12 RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1e-3 RGATE 9 20 1.9 RLDRAIN 2 5 10 RLGATE 1 9 60 RLSOURCE 3 7 24 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 5.5e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B RLDRAIN RSLC1 51 EBREAK 11 7 17 18 56 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 DRAIN 2 5 S2A 14 13 13 8 S1B 17 18 RVTEMP S2B 13 CA RBREAK 15 CB 6 8 EGS - 19 - IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*35),4))} .MODEL DBODYMOD D (IS=1.6e-13 RS=1.28e-2 IKF=5.5 N=0.985 TRS1=2.9e-3 TRS2=-4e-6 CJO=3.5e-10 TT=3.1e-8 M=0.45 XTI=6) .MODEL DBREAKMOD D (RS=2.5e- 1IKF=0.1 TRS1=-4e- 3TRS2=3e-5) .MODEL DPLCAPMOD D (CJO=5e-1 0IS=1e-3 0N=10 M=0.95) .MODEL MMEDMOD NMOS (VTO=3.25 KP=2.2 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.9) .MODEL MSTROMOD NMOS (VTO=3.75 KP=14.75 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MWEAKMOD NMOS (VTO=2.88 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=19 RS=0.1) .MODEL RBREAKMOD RES (TC1=1.12e- 3TC2=1e-6) .MODEL RDRAINMOD RES (TC1=2.3e-1 TC2=6e-4) .MODEL RSLCMOD RES (TC1=4e-3 TC2=1e-6) .MODEL RSOURCEMOD RES (TC1=1e-3 TC2=6e-6) .MODEL RVTHRESMOD RES (TC=-3.31e-3 TC2=-1.49e-5) .MODEL RVTEMPMOD RES (TC1=-1.4e- 3TC2=1e-9) .MODEL S1AMOD VSWITCH (RON=1e-5 .MODEL S1BMOD VSWITCH (RON=1e-5 .MODEL S2AMOD VSWITCH (RON=1e-5 .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 ROFF=0.1 ROFF=0.1 ROFF=0.1 VON=-8.1 VOFF=-4) VON=-4 VOFF=-8.1) VON=0 VOFF=2) VON=2 VOFF=0) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2001 Fairchild Semiconductor Corporation HUF75307P3, HUF75307D3, HUF75307D3S Rev. B HUF75307P3, HUF75307D3, HUF75307D3S SABER Electrical Model REV February 1999 template huf75307 n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 1.6e-13, xti = 6, cjo = 3.5e-10, tt = 3.1e-8, n = 0.985, m = 0.45) d..model dbreakmod = () DPLCAP d..model dplcapmod = (cjo = 5e-10, is = 1e-30, n = 10, m = 0.95) m..model mmedmod = (type=_n, vto = 3.25, kp = 2.2, is = 1e-30, tox = 1) 10 m..model mstrongmod = (type=_n, vto = 3.75, kp = 14.75, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.88, kp = 0.03, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -8.1, voff = -4) RSLC2 sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -4, voff = -8.1) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 2) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 2, voff = 0) GATE 1 i.it n8 n17 = 1 EVTEMP RGATE + 18 22 9 20 21 MWEAK DBODY EBREAK + 17 18 MMED MSTRO CIN 71 11 16 6 - 8 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 5.97e-10 l.lsource n3 n7 = 2.39e-9 RDBODY DBREAK RDRAIN RLGATE LSOURCE 7 SOURCE 3 RSOURCE RLSOURCE S1A 12 m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u res.rbreak n17 n18 = 1, tc1 = 1.12e-3, tc2 = 1e-6 res.rdbody n71 n5 = 1.28e-2, tc1 = 2.9e-3, tc2 = -4e-6 res.rdbreak n72 n5 = 0.25, tc1 = -4e-3, tc2 = 3e-5 res.rdrain n50 n16 = 1e-3, tc1 = 2.31-1, tc2 = 6e-4 res.rgate n9 n20 = 1.9 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 60 res.rlsource n3 n7 = 24 res.rslc1 n5 n51 = 1e-6, tc1 = 4e-3, tc2 = 1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 5.5e-2, tc1 = 1e-3, tc2 = 6e-6 res.rvtemp n18 n19 = 1, tc1 = -1.4e-3, tc2 = 1e-9 res.rvthres n22 n8 = 1, tc1 = -3.31e-3, tc2 = -1.49e-5 72 ISCL EVTHRES + 19 8 + LGATE RLDRAIN RDBREAK 50 6 8 ESG DRAIN 2 RSLC1 51 - c.ca n12 n8 = 4.5e-10 c.cb n15 n14 = 4.1e-10 c.cin n6 n8 = 2.154e-10 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod LDRAIN 5 S2A 14 13 13 8 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 - - IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES spe.ebreak n11 n7 n17 n18 = 56 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc = 1 equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/35))** 4)) } } (c)2001 Fairchild Semiconductor Corporation HUF75307P3, HUF75307D3, HUF75307D3S Rev. B HUF75307P3, HUF75307D3, HUF75307D3S SPICE Thermal Model th REV February 1999 JUNCTION HUF75307 CTHERM1 th 6 8.0e-4 CTHERM2 6 5 1.6e-3 CTHERM3 5 4 1.9e-3 CTHERM4 4 3 2.6e-3 CTHERM5 3 2 5.5e-3 CTHERM6 2 tl 1.8e-2 RTHERM1 th 6 8.0e-3 RTHERM2 6 5 2.1e-2 RTHERM3 5 4 2.2e-1 RTHERM4 4 3 6.4e-1 RTHERM5 3 2 7.7e-1 RTHERM6 2 tl 1.0 SABER Thermal Model CTHERM1 RTHERM1 6 CTHERM2 RTHERM2 5 CTHERM3 RTHERM3 SABER thermal model HUF75307 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 8.0e-4 ctherm.ctherm2 6 5 = 1.6e-3 ctherm.ctherm3 5 4 = 1.9e-3 ctherm.ctherm4 4 3 = 2.6e-3 ctherm.ctherm5 3 2 = 5.5e-3 ctherm.ctherm6 2 tl = 1.8e-2 rtherm.rtherm1 th 6 = 8.0e-3 rtherm.rtherm2 6 5 = 2.1e-2 rtherm.rtherm3 5 4 = 2.2e-1 rtherm.rtherm4 4 3 = 6.4e-1 rtherm.rtherm5 3 2 = 7.7e-1 rtherm.rtherm6 2 tl = 1.0 } 4 CTHERM4 RTHERM4 3 CTHERM5 RTHERM5 2 CTHERM6 RTHERM6 tl (c)2001 Fairchild Semiconductor Corporation CASE HUF75307P3, HUF75307D3, HUF75307D3S Rev. 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FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4