Asymmetric Dual N-channel Trench MOSFET 30V General Description Features The MDV5524 uses advanced MagnaChip's MOSFET Technology, which provides high performance in on-state resistance, fast switching performance and excellent quality. MDV5524 is suitable for DC/DC converter and general purpose applications. FET1 VDS = 30V ID = 24.5A RDS(ON) < 14.4m < 21.3m 100% UIL Tested 100% Rg Tested FET2 VDS = 30V ID = 31.2A @VGS = 10V < 12.6m @VGS = 10V < 15.6m @VGS = 4.5V S2 S2 5 6 S2 G2 7 8 D D1 S1/D2 D1 G G1 D S S1/D2 4 D1 D13 2 1 D1 G1 G G2 S2 S Absolute Maximum Ratings (Ta = 25oC) Characteristics Symbol Drain-Source Voltage FET1 VDSS Gate-Source Voltage VGSS TC=25oC TC=100oC Continuous Drain Current (1) o ID TA=25 C TA=70oC Pulsed Drain Current IDM o TC=25 C o TC=100 C Power Dissipation TA=25oC PD TA=70oC Single Pulse Avalanche Energy (2) EAS Junction and Storage Temperature Range FET2 Unit 30 V 20 12 24.5 31.2 15.5 19.7 8.5 9.9 6.8 7.9 100 125 14.7 20.8 5.9 8.3 1.8 2.1 1.1 1.3 12.1 TJ, Tstg V A A W 25.6 mJ o -55~150 C Thermal Characteristics Characteristics Thermal Resistance, Junction-to-Ambient Symbol (1) Thermal Resistance, Junction-to-Case Apr 2012. Version 1.2 1 FET1 FET2 RJA 70 60 RJC 8.5 6.0 Unit o C/W MagnaChip Semiconductor Ltd. MDV5524 - Asymmetric Dual N-Channel Trench MOSFET 30V MDV5524 Part Number Temp. Range MDV5524URH o -55~150 C Package Packing Rohs Status Dual PDFN33 Tape & Reel Halogen Free FET1 Electrical Characteristics (Ta =25oC) Characteristics Symbol Test Condition Min Typ Max Unit Static Characteristics Drain-Source Breakdown Voltage BVDSS ID = 250A, VGS = 0V 30 - - Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250A 1.3 1.8 2.4 Drain Cut-Off Current IDSS VDS = 30.0V, VGS = 0V - - 1 Gate Leakage Current IGSS VGS = 20.0V, VDS = 0V - - 0.1 VGS = 10.0V, ID = 6.0A - 12.0 14.4 VGS = 4.5V, ID = 5.0A - 17.0 21.3 VDS = 5.0V, ID = 6.0A - 19.5 - Drain-Source ON Resistance Forward Transconductance RDS(ON) gfs V A m S Dynamic Characteristics Total Gate Charge Qg(10V) 5.7 7.2 8.6 Total Gate Charge Qg(4.5V) 2.8 3.6 4.3 - 1.4 - Gate-Source Charge Qgs VDS = 15.0V, ID = 6.0A, VGS = 10.0V Gate-Drain Charge Qgd - 1.2 - Input Capacitance Ciss 290 386 483 Reverse Transfer Capacitance Cosss 68 91 113 VDS = 15.0V, VGS = 0V, f = 1.0MHz Output Capacitance Crss 35 47 60 Turn-On Delay Time td(on) - 6.7 - - 10.2 - - 17.3 - - 6.5 - Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD=15.0V, ID=6.0A, VGS=10.0V, Rg=6.0 tf nC pF ns Rg f=1 MHz - 3.0 - Source-Drain Diode Forward Voltage VSD IS = 1.0A, VGS = 0V - 0.7 1.2 V Body Diode Reverse Recovery Time trr - 16.0 20.0 ns Body Diode Reverse Recovery Charge Qrr - 8.0 10.0 nC Gate Resistance Drain-Source Body Diode Characteristics IF = 6.0A, dl/dt = 100A/s Note : 1. Surface mounted FR-4 board by JEDEC (jesd51-7). Continuous current at TC=25 is silicon limited. 2. EAS is tested at starting Tj = 25, L = 0.1mH, IAS = 11.0A, VDD = 27V, VGS = 10V (100% UIL Test). Apr 2012. Version 1.2 2 MagnaChip Semiconductor Ltd. MDV5524 - Asymmetric Dual N-Channel Trench MOSFET 30V Ordering Information Drain-Source On-Resistance [m] VGS = 10V 8.0V ID, Drain Current [A] 5.0V 4.5V 30 4.0V 20 3.5V 10 20 VGS = 4.5V 15 VGS = 10V 10 3.0V 5 0 0 1 2 5 3 10 15 20 25 30 35 40 VDS, Drain-Source Voltage [V] 50 Fig.2 On-Resistance Variation with Drain Current and Gate Voltage Fig.1 On-Region Characteristics 1.8 40 Notes : Notes : 1. VGS = 10 V 2. ID = 6 A 1.6 35 RDS(ON) [m ], Drain-Source On-Resistance RDS(ON), (Normalized) Drain-Source On-Resistance 45 ID, Drain Current [A] 1.4 1.2 1.0 ID = 6A 30 25 20 TA = 25 15 0.8 10 0.6 -50 5 -25 0 25 50 75 100 125 2 150 4 6 8 10 VGS, Gate to Source Volatge [V] o TJ, Junction Temperature [ C] Fig.3 On-Resistance Variation with Temperature Area Fig.4 On-Resistance Variation with Gate to Source Voltage 20 Notes : Notes : VGS = 0V IDR, Reverse Drain Current [A] ID, Drain Current [A] VDS = 5V 15 10 TJ=25 5 0 1 10 TJ=25 0 10 -1 1 2 3 4 10 5 VGS, Gate-Source Voltage [V] 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VSD, Source-Drain voltage [V] Fig.5 Transfer Characteristics Apr 2012. Version 1.2 0.3 Fig.6 Body Diode Forward Voltage Variation with Source Current and Temperature 3 MagnaChip Semiconductor Ltd. MDV5524 - Asymmetric Dual N-Channel Trench MOSFET 30V 25 40 600 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd Note : ID = 6.0A 500 VGS, Gate-Source Voltage [V] 8 Capacitance [F] Ciss 6 4 400 300 200 Notes ; Coss 2 1. VGS = 0 V 2. f = 1 MHz Crss 100 0 0 2 4 6 0 8 0 QG, Total Gate Charge [nC] 10 Fig.7 Gate Charge Characteristics 10 3 10 2 10 1 10 0 28 24 1 ms ID, Drain Current [A] ID, Drain Current [A] 30 Fig.8 Capacitance Characteristics Operation in This Area is Limited by R DS(on) 10 ms 100 ms 1s 10 s DC 10 20 VDS, Drain-Source Voltage [V] 20 16 12 8 -1 Single Pulse TJ=Max Rated TC=25 4 10 -2 10 -1 10 0 10 1 10 0 25 2 50 75 100 125 150 TC, Case Temperature [ ] VDS, Drain-Source Voltage [V] Fig.10 Maximum Drain Current vs. Case Temperature Fig.9 Maximum Safe Operating Area 1 10 0.2 0.1 0 10 0.05 0.02 Notes : Duty Factor, D=t 1/t2 PEAK TJ = PDM * Z JC* R JC(t) + TC 0.01 -1 10 Z JC , Thermal Response D=0.5 single pulse -2 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 10 t1, Rectangular Pulse Duration [sec] Fig.11 Transient Thermal Response Curve Apr 2012. Version 1.2 4 MagnaChip Semiconductor Ltd. MDV5524 - Asymmetric Dual N-Channel Trench MOSFET 30V 10 Characteristics Symbol Test Condition Min Typ Max Unit Static Characteristics Drain-Source Breakdown Voltage BVDSS ID = 250A, VGS = 0V 30 - - Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250A 1.0 1.5 2.0 Drain Cut-Off Current IDSS VDS = 30.0V, VGS = 0V - - 1 Gate Leakage Current IGSS VGS = 12.0V, VDS = 0V - - 0.1 VGS = 10.0V, ID = 9.0A - 10.5 12.6 VGS = 4.5V, ID = 7.0A - 12.5 15.6 VDS = 5.0V, ID = 9.0A - 38.6 - 14.3 18.0 21.5 6.4 8.1 9.7 - 2.5 - - 2.0 - 778 1037 1297 107 143 179 56 70 Drain-Source ON Resistance Forward Transconductance RDS(ON) gfs V A m S Dynamic Characteristics Total Gate Charge Qg(10V) Total Gate Charge Qg(4.5V) Gate-Source Charge Qgs Gate-Drain Charge Qgd VDS = 15.0V, ID = 9.0A, VGS = 10V Input Capacitance Ciss Reverse Transfer Capacitance Coss Output Capacitance Crss 42 Turn-On Delay Time td(on) - 9.3 - tr - 10.4 - - 41.8 - Rise Time Turn-Off Delay Time Fall Time td(off) VDS = 15.0V, VGS = 0V, f = 1.0MHz VDD=15.0V, ID=9.0A, VGS=10.0V, Rg=6.0 pF ns - 7.1 - Rg f=1 MHz - 2.0 3.0 Source-Drain Diode Forward Voltage VSD IS = 1.0A, VGS = 0V - 0.7 1.2 V Body Diode Reverse Recovery Time trr - 19.1 23.8 ns Body Diode Reverse Recovery Charge Qrr - 12.0 15.0 nC Gate Resistance tf nC Drain-Source Body Diode Characteristics IF = 9.0A, dl/dt = 100A/s Note : 1. Surface mounted FR-4 board by JEDEC (jesd51-7). Continuous current at TC=25 is silicon limited. 2. EAS is tested at starting Tj = 25, L = 0.1mH, IAS = 16.0A, VDD = 27V, VGS = 10V (100% UIL Test). Apr 2012. Version 1.2 5 MagnaChip Semiconductor Ltd. MDV5524 - Asymmetric Dual N-Channel Trench MOSFET 30V FET2 Electrical Characteristics (Ta =25oC) 16 Drain-Source On-Resistance [m] 4.5V 4.0V VGS = 10V ID, Drain Current [A] 3.5V 30 20 3.0V 10 14 VGS = 4.5V 12 VGS = 10V 10 8 0 0.0 0.5 1.0 1.5 5 2.0 10 15 20 25 30 ID, Drain Current [A] VDS, Drain-Source Voltage [V] Fig.2 On-Resistance Variation with Drain Current and Gate Voltage Fig.1 On-Region Characteristics 1.8 40 Notes : Notes : 1. VGS = 10 V 2. ID = 9 A 1.6 RDS(ON) [m ], Drain-Source On-Resistance RDS(ON), (Normalized) Drain-Source On-Resistance MDV5524 - Asymmetric Dual N-Channel Trench MOSFET 30V 40 1.4 1.2 1.0 0.8 0.6 -50 ID = 9A 30 20 10 TA = 25 0 -25 0 25 50 75 100 125 2 150 4 6 8 10 VGS, Gate to Source Volatge [V] o TJ, Junction Temperature [ C] Fig.3 On-Resistance Variation with Temperature Area Fig.4 On-Resistance Variation with Gate to Source Voltage 20 Notes : Notes : VGS = 0V IDR, Reverse Drain Current [A] ID, Drain Current [A] VDS = 5V 15 10 TJ=25 5 0 1 10 TJ=25 0 10 -1 1 2 3 4 10 5 VGS, Gate-Source Voltage [V] 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VSD, Source-Drain voltage [V] Fig.5 Transfer Characteristics Apr 2012. Version 1.2 0.3 Fig.6 Body Diode Forward Voltage Variation with Source Current and Temperature 6 MagnaChip Semiconductor Ltd. 1600 Note : ID = 9.0A Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 8 1200 Capacitance [F] VGS, Gate-Source Voltage [V] 1400 6 4 Ciss 1000 800 600 Notes ; 400 2 200 0 0 2 4 6 8 10 12 14 16 18 1. VGS = 0 V 2. f = 1 MHz Coss Crss 0 20 0 10 QG, Total Gate Charge [nC] Fig.7 Gate Charge Characteristics 10 35 3 1 ms ID, Drain Current [A] ID, Drain Current [A] 30 2 10 ms 10 1 100 ms 1s 10 30 Fig.8 Capacitance Characteristics Operation in This Area is Limited by R DS(on) 10 20 VDS, Drain-Source Voltage [V] 10 s 0 25 20 15 10 DC Single Pulse TJ=Max Rated TC=25 5 10 -1 10 -1 10 0 10 1 10 0 25 2 50 75 100 125 150 TC, Case Temperature [ ] VDS, Drain-Source Voltage [V] Fig.10 Maximum Drain Current vs. Case Temperature Fig.9 Maximum Safe Operating Area 1 10 0.2 0 10 0.1 0.05 Notes : 0.02 Duty Factor, D=t 1/t2 PEAK TJ = PDM * Z JC* R JC(t) + TC -1 10 Z JC , Thermal Response D=0.5 0.01 single pulse -2 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 10 t1, Rectangular Pulse Duration [sec] Fig.11 Transient Thermal Response Curve Apr 2012. Version 1.2 7 MagnaChip Semiconductor Ltd. MDV5524 - Asymmetric Dual N-Channel Trench MOSFET 30V 10 MDV5524 - Asymmetric Dual N-Channel Trench MOSFET 30V Package Dimension Dual PDFN33 (3x3mm) Dimensions are in millimeters, unless otherwise specified Apr 2012. Version 1.2 8 MagnaChip Semiconductor Ltd. MDV5524 - Asymmetric Dual N-Channel Trench MOSFET 30V DISCLAIMER: The Products are not designed for use in hostile environments, including, without limitation, aircraft, nuclear power generation, medical appliances, and devices or systems in which malfunction of any Product can reasonably be expected to result in a personal injury. Seller's customers using or selling Seller's products for use in such applications do so at their own risk and agree to fully defend and indemnify Seller. MagnaChip reserves the right to change the specifications and circuitry without notice at any time. MagnaChip does not consider responsibility for use of any circuitry other than circuitry entirely included in a MagnaChip product. is a registered trademark of MagnaChip Semiconductor Ltd. Apr 2012. Version 1.2 9 MagnaChip Semiconductor Ltd.