IS34ML01G081
IS35ML01G081
1Gb SLC-1b ECC
3.3V X8 NAND FLASH MEMORY STANDARD NAND INTERFACE
IS34/35ML01G081
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Rev. A3
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FEATURES
Flexible & Efficient Memory
Architecture
- Organization: 128Mb x8
- Memory Cell Array: (128M + 4M) x 8bit
- Data Register: (2K + 64) x 8bit
- Page Size: (2K + 64) Byte
- Block Erase: (128K + 4K) Byte
- Memory Cell: 1bit/Memory Cell
Highest performance
- Read Performance
- Random Read: 25us (Max.)
- Serial Access: 25ns (Max.)
- Write Performance
- Program time: 400us - typical
- Block Erase time: 3ms – typical
Low Power with Wide Temp. Ranges
- Single 3.3V (2.7V to 3.6V) Voltage
Supply
- 15 mA Active Read Current
- 10 µA Standby Current
- Temp Grades:
- Industrial: -40°C to +85°C
- Extended: -40°C to +105°C
- Automotive, A1: -40°C to +85°C
- Automotive, A2: -40°C to +105°C
Reliable CMOS Floating Gate
Technology
- ECC Requirement: X8 - 1bit/512Byte
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
Efficient Read and Program modes
- Command/Address/Data Multiplexed I/O
Interface
- Command Register Operation
- Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
- NOP: 4 cycles
- Cache Program Operation for High
Performance Program
- Cache Read Operation
- Copy-Back Operation
- EDO mode
- OTO Operation
- Bad-Block-Protect
Advanced Security Protection
- Hardware Data Protection
- Program/Erase Lockout during Power
Transitions
Industry Standard Pin-out & Packages
- T =48-pin TSOP1
- B =63-ball VFBGA
1Gb (x8) 3.3V NAND FLASH MEMORY with 1b ECC
IS34/35ML01G081
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Rev. A3
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GENERAL DESCRIPTION
The IS34/35ML1G081 is a 128Mx8bit with spare 4Mx8bit capacity. The device is offered in 3.3V Vcc Power
Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid
data while old data is erased.
The device contains 1,024 blocks, composed by 64 pages consisting in two NAND structures of 32
series connected Flash cells. A program operation allows to write the 2,112-Byte page in typical 400us
and an erase operation can be performed in typical 3ms on a 128K-Byte for X8 device block.
Data in the page mode can be read out at 25ns cycle time per Byte. The I/O pins serve as the ports for
address and command inputs as well as data input/output.
The copy back function allows the optimization of defective blocks management: when a page program
operation fails, the data can be directly programmed in another page inside the same array section
without the time consuming serial data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is
copied into the Flash array.
This pipelined program operation improves the program throughput when long files are written inside
the memory. A cache read feature is also implemented. This feature allows to dramatically improving
the read throughput when consecutive pages have to be streamed out. This device includes extra
feature: Automatic Read at Power Up.
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TABLE OF CONTENTS
FEATURES ............................................................................................................................................................ 2
GENERAL DESCRIPTION .................................................................................................................................... 3
TABLE OF CONTENTS ......................................................................................................................................... 4
1. PIN CONFIGURATION ................................................................................................................................... 6
2. PIN DESCRIPTIONS ...................................................................................................................................... 8
3. BLOCK DIAGRAM .......................................................................................................................................... 9
4. OPERATION DESCRIPTION ....................................................................................................................... 11
5. ELECTRICAL CHARACTERISTICS ............................................................................................................. 13
5.1 ABSOLUTE MAXIMUM RATINGS (1) ..................................................................................................... 13
5.2 Recommended Operating Conditions .................................................................................................... 13
5.3 DC CHARACTERISTICs ........................................................................................................................ 14
5.4 Valid Block .............................................................................................................................................. 14
5.5 AC Measurement Condition .................................................................................................................... 15
5.6 AC PIN CAPACITANCE (TA = 25°C, VCC=3.3V, 1MHz) ...................................................................... 15
5.7 Mode Selection ....................................................................................................................................... 15
5.8 ROGRAM/ERASE PERFORMANCne .................................................................................................... 16
5.9 AC CHARACTERISTICS for address/ command/data input .................................................................. 16
5.10 AC CHARACTERISTICS for operation ................................................................................................ 17
6. TIMING DIAGRAMS FOR OPERATION ...................................................................................................... 18
6.1 Command latch cycle ............................................................................................................................. 18
6.2 Address Latch Cycle ............................................................................................................................... 18
6.3 Input Data Latch Cycle ........................................................................................................................... 19
6.4 Serial Access Cycle after Read (CLE=L, WE#=H, ALE=L) .................................................................... 19
6.5 Serial Access Cycle after Read (EDO Type CLE=L, WE#=H, ALE=L) .................................................. 20
6.6 Status Read Cycle .................................................................................................................................. 20
6.7 Read Operation ....................................................................................................................................... 21
6.8 Read Operation (Intercepted by CE#) .................................................................................................... 21
6.9 Random Data Output In a Page ............................................................................................................. 22
6.10 Page program operation ....................................................................................................................... 23
6.11 Page Program Operation with Random Data Input .............................................................................. 24
6.12 Copy-Back Operation with Random Data InpuT .................................................................................. 25
6.13 Cache Program Operation .................................................................................................................... 26
6.14 Block Erase Operation .......................................................................................................................... 26
6.15 Cache read operaTION ........................................................................................................................ 27
7. ID Definition Table ........................................................................................................................................ 28
8. DEVICE OPERATION .................................................................................................................................. 30
8.1 Page READ OPERATION ...................................................................................................................... 30
8.2 Page Program ......................................................................................................................................... 32
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8.3 Cache Program ....................................................................................................................................... 33
8.4 Copy-Back Program................................................................................................................................ 34
8.5 Block Erase ............................................................................................................................................. 35
8.6 Read Status ............................................................................................................................................ 35
8.7 Read ID ................................................................................................................................................... 37
8.8 Reset ....................................................................................................................................................... 38
8.9 Cache Read ............................................................................................................................................ 39
8.10 Ready/Busy# ......................................................................................................................................... 40
8.11 Data Protection and Power Up Sequence ............................................................................................ 41
8.12 Write Protect Operation ........................................................................................................................ 42
9. INVALID BLOCK AND ERROR MANAGEMENT ......................................................................................... 44
9.1 Mask Out Initial Invalid Block(s) ........................................................................................................... 44
9.2 Identifying Initial Invalid Block(s) and Block Replacement Management ............................................... 44
9.3 ERRor in Read or Write operation .......................................................................................................... 46
9.4 Addressing for PROGRAM operation ..................................................................................................... 51
9.5 System Interface Using CE# NOT Care operation ................................................................................. 52
10. PACKAGE TYPE INFORMATION ........................................................................................................... 53
10.1 48-Pin TSOP (TYPE I) Package (T) ..................................................................................................... 53
10.2 63-BALL VFBGA Package (B) .............................................................................................................. 54
11. ORDERING INFORMATION – Valid Part Numbers ................................................................................ 55
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1. PIN CONFIGURATION
48-pin TSOP (Type I)
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
VSS
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
VCC
VCC
NC
VSS
NC
VCC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
12
13 36
37
NC
NC
NC
VSS
1
24 25
48 (1)
(1)
(1)
(1)
Note:
1. These pins might not be bonded in the package; however it is recommended to connect these pins to the designated
external sources for ONFI compatibility.
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63-ball VFBGA
ALE VSS CE#
NC RE# CLE NC
NC NC NC NC
NC NC NC NC
NC VCC NC NC
WE#
NC
NC
VSS
Balls Down, Top View
NC
C4 C5 C6
D3 D4 D5 D6
E3 E4 E5 E6
F3 F4 F5 F6
G3 G4 G5 G6
C7
D7
E7
F7
G7
R/B#
NC
NC
NC
NC
C8
D8
E8
F8
G8
NC I/O0 NC NC
NC I/O1 NC VCC
VSS I/O2 I/O3 I/O4
NC
I/O5
I/O6
H3 H4 H5 H6
J3 J4 J5 J6
K3 K4 K5 K6
H7
J7
K7
VCC
I/O7
VSS
H8
J8
K8
NC
NC
A9
B9
NC
NC
A
10
B
10
WP#
C3
NC
NC
A2
B1
NC
A1
NC
NC
L9
M9
NC
NC
L
10
M
10
NC NC
L1 L2
NC NC
M1 M2
(1)
(1)
Note:
1. These pins might not be bonded in the package; however it is recommended to connect these pins to the designated
external sources for ONFI compatibility.
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2. PIN DESCRIPTIONS
Pin Name
Pin Function
I/O0 ~ I/O7 (X8)
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data
during read operations. The I/O pins float to high-z when the chip is deselected or
when the outputs are disabled.
CLE
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the internal
command registers. Commands are latched into the command register through the
I/O ports on the rising edge of the WE# signal with CLE high.
ALE
ADDRESS LATCH ENABLE
The ALE input controls the activating path for addresses sent to the internal
address registers. Addresses are latched into the address register through the I/O
ports on the rising edge of WE# with ALE high.
CE#
CHIP ENABLE
The CE# input is the device selection control. When the device is in the Busy state,
CE# high is ignored, and the device does not return to standby mode in program or
erase operation. Regarding CE# control during read operation, refer to ’Page read’
section of Device operation.
RE#
READ ENABLE
The RE# input is the serial data-out control, and when it is active low, it drives the
data onto the I/O bus. Data is valid tREA after the falling edge of RE# which also
increments the internal column address counter by one.
WE#
WRITE ENABLE
The WE# input controls writes to the I/O ports. Commands, address and data are
latched on the rising edge of the WE# pulse.
WP#
WRITE PROTECT
The WP# pin provides inadvertent write/erase protection during power transitions.
The internal high voltage generator is reset when the WP# pin is active low.
R/B#
READY/BUSY OUTPUT
The R/B# output indicates the status of the device operation. When low, it indicates
that a program, erase or random read operation is in progress and returns to high
state upon completion. It is an open drain output and does not float to high-z
condition when the chip is deselected or when outputs are disabled.
VCC
POWER
VCC is the power supply for device.
VSS
GROUND
N.C.
NO CONNECTION
Lead is not internally connected.
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3. BLOCK DIAGRAM
Figure 3.1 Functional Block Diagram
1,024 Blocks
Page Buffer
2048B 64B
1 Block = 64 Pages
1 Device = 1,024 Blocks
= 1024 x (128K+4K) Bytes
1 Page = (2K + 64) Bytes
I/O
[7:0]
1 Block = 64 Pages
= (128K+4K) Bytes
Figure 3.2 Array Organization
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Table 3.1 ARRAY Address (x8)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Address
1st cycle
A0
A1
A2
A3
A4
A5
A5
A7
Column Address
2nd cycle
A8
A9
A10
A11
*L
*L
*L
*L
Column Address
3rd cycle
A12
A13
A14
A15
A16
A17
A18
A19
Row Address
4th cycle
A20
A21
A22
A23
A24
A25
A26
A27
Row Address
Notes:
1. Column Address: Starting Address of the Register.
2. *L must be set to “Low”.
3. The device ignores any additional input of address cycles than required.
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4. OPERATION DESCRIPTION
The IS34/35ML01G081 is a 1Gbit memory organized as 128K rows (pages) by 2,112x8 columns.
Spare 64x8 columns are located from column address of 2,048~2,111. A 2,112-byte data register is
connected to memory cell arrays accommodating data transfer between the I/O buffers and memory
during page read and page program operations. The program and read operations are executed on a
page basis, while the erase operation is executed on a block basis. The memory array consists of 1,024
separately erasable 128K-byte blocks. It indicates that the bit-by-bit erase operation is prohibited on the
IS34/35ML01G081.
The device has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and
allows system upgrades to future densities by maintaining consistency in system board design.
Command, address and data are all written through I/O's by bringing WE# to low while CE# is low. Those
are latched on the rising edge of WE#. Command Latch Enable (CLE) and Address Latch Enable (ALE)
are used to multiplex command and address respectively, via the I/O pins. Some commands require one
bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some
other commands, like page read and block erase and page program, require two cycles: one cycle for
setup and the other cycle for execution.
In addition to the enhanced architecture and interface, the device incorporates copy-back program
feature from one page to another page without need for transporting the data to and from the external
buffer memory.
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Table 4.1 Command Set
Function
1st Cycle
2nd Cycle
Acceptable Command during
Busy
Read
00h
30h
Read for Copy-Back
00h
35h
Read ID
90h
-
Reset
FFh
-
O
Page Program
80h
10h
Copy-Back Program
85h
10h
Block Erase
60h
D0h
Random Data Input (1)
85h
-
Random Data Output (1)
05h
E0h
Read Status
70h
-
O
Cache Program
80h
15h
Cache Read
31h
-
Read Start For Last Page Cache Read
3Fh
-
Note:
1. Random Data Input/Output can be executed in a page.
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5. ELECTRICAL CHARACTERISTICS
5.1 ABSOLUTE MAXIMUM RATINGS (1)
Storage Temperature
-65°C to +150°C
Surface Mount Lead Soldering Temperature
Standard Package
240°C 3 Seconds
Lead-free Package
260°C 3 Seconds
Input Voltage with Respect to Ground on All Pins
-0.6V to +4.6V
All I/O Voltage with Respect to Ground
-0.6V to VCC + 0.3V( < 4.6V)
VCC
-0.6V to +4.6V
Short Circuit Current
5mA
Electrostatic Discharge Voltage (Human Body Model)(2)
-2000V to +2000V
Notes:
1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. ANSI/ESDA/JEDEC JS-001
5.2 RECOMMENDED OPERATING CONDITIONS
Part Number
IS34/35ML01G081
Operating Temperature (Industrial Grade)
-40°C to 85°C
Operating Temperature (Extended Grade)
-40°C to 105°C
Operating Temperature (Automotive Grade A1)
-40°C to 85°C
Operating Temperature (Automotive Grade A2)
-40°C to 105°C
VCC Power Supply
2.7V (VMIN) – 3.6V (VMAX); 3.3V (Typ)
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5.3 DC CHARACTERISTICS
(Under operating range)
Parameter
Symbol
Test Conditions
Min
Typ.
Max
Unit
Operating
Current
Page Read
with Serial Access
ICC1
tRC=tRCMIN,
CE#=VIL, IOUT=0mA
-
15
30
mA
Program
ICC2
-
-
15
Erase
ICC3
-
-
15
Stand-by Current (TTL)
ISB1
CE#=VIH, WP#=0V/VCC
-
-
1
Stand-by Current (CMOS)
ISB2
CE#=VCC-0.2,
WP#=0V/VCC
-
10
50
uA
Input Leakage Current
ILI
VIN=0 to Vcc (max)
-
-
+/-10
Output Leakage Current
ILO
VOUT=0 to Vcc (max)
-
-
+/-10
Input High Voltage
VIH (1)
0.8xVCC
-
Vcc+0.3
V
Input Low Voltage, All inputs
VIL (1)
-0.3
-
0.2xVCC
Output High Voltage Level
VOH
IOH=-400 uA
2.4
-
-
Output Low Voltage Level
VOL
IOL=2.1mA
-
-
0.4
Output Low Current (R/B#)
IOL
(R/B#)
VOL=0.4V
8
10
-
mA
Notes:
1. VIL can undershoot to -2V and VIH can overshoot to VCC + 2V for durations of 20 ns or less.
2. Typical value are measured at Vcc=3.3V, TA=25℃. Not 100% tested.
5.4 VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
Unit
IS34/35ML01G081
NVB
1,004
-
1,024
Block
Notes:
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used.
The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks
that contain one or more bad bits which cause status failure during program and erase operation. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for appropriate management of initial invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment and is
guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.
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5.5 AC MEASUREMENT CONDITION
Symbol
Parameter
Min
Max
Units
CL
Output Load
1 TTL GATE and CL = 50pF
pF
TR,TF
Input Rise and Fall Times
-
5
ns
VIN
Input Pulse Voltages
0V to VCC
V
VREFI
Input Timing Reference Voltages
0.5VCC
V
VREFO
Output Timing Reference Voltages
0.5VCC
V
Note:
1. Refer to 8.10 Ready/Busy#, R/B#’s Busy to Ready time is decided by pull up register (Rp) tied to R/B# pin.
5.6 AC PIN CAPACITANCE (TA = 25°C, VCC=3.3V, 1MHZ)
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
CIN
Input Capacitance
VIN = 0V
-
-
8
pF
CI/O
Input /Output Capacitance
VI/O = 0V
-
-
8
pF
Note:
1. These parameters are characterized and not 100% tested.
5.7 MODE SELECTION
CLE
ALE
CE#
WE#
RE#
WP#
Mode
H
L
L
H
X
Read Mode
Command Input
L
H
L
H
X
Address Input (4 clock)
H
L
L
H
H
Write Mode
Command Input
L
H
L
H
H
Address Input (4 clock)
L
L
L
H
H
Data Input
L
L
L
H
X
Data Output
X
X
X
X
H
X
During Read (Busy)
X
X
X
X
X
H
During Program (Busy)
X
X
X
X
X
H
During Erase (Busy)
X
X(1)
X
X
X
L
Write Protect
X
X
H
X
X
0V/VCC(2)
Stand-by
Notes:
1. X can be VIL or VIH.
2. WP# should be biased to CMOS high or CMOS low for standby.
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5.8 ROGRAM/ERASE PERFORMANCNE
(Industrial: TA=-40 to 85℃, Automotive, A1: TA=-40 to 85℃, Vcc=2.7V ~ 3.6V)
Parameter
Symbol
Min
Typ
Max
Unit
Average Program Time
tPROG
-
400
950
us
Dummy Busy Time for Cache Operation
tCBSY
-
3
950
us
Number of Partial Program Cycles in the Same Page
Nop
-
-
4
cycle
Block Erase Time
tBERS
-
2
10
ms
Notes:
1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc
and 25℃ temperature.
2. tPROG is the average program time of all pages. Users should be noted that the program time variation from
page to page is possible.
3. tCBSY max.time depends on timing between internal program completion and data-in.
5.9 AC CHARACTERISTICS FOR ADDRESS/ COMMAND/DATA INPUT
Parameter
Symbol
Min
Max
Unit
CLE Setup Time
tCLS(1)
12
-
ns
CLE Hold Time
tCLH
5
-
ns
CE# Setup Time
tCS(1)
20
-
ns
CE# Hold Time
tCH
5
-
ns
WE# Pulse Width
tWP
12
-
ns
ALE Setup Time
tALS(1)
12
-
ns
ALE Hold Time
tALH
5
-
ns
Data Setup Time
tDS(1)
12
-
ns
Data Hold Time
tDH
5
-
ns
Write Cycle Time
tWC
25
-
ns
WE# High Hold Time
tWH
10
-
ns
Address to Data Loading Time
tADL(2)
70(2)
-
ns
Note:
1. The transition of the corresponding control pins must occur only once while WE# is held low.
2. tADL is the time from the WE rising edge of final address cycle to the WE# rising edge of first data cycle.
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5.10 AC CHARACTERISTICS FOR OPERATION
Parameter
Symbol
Min
Max
Unit
Data Transfer from Cell to Register
tR
-
25
us
ALE to RE# Delay
tAR
10
-
ns
CLE to RE# Delay
tCLR
10
-
ns
Ready to RE# Low
tRR
20
-
ns
RE# Pulse Width
tRP
12
-
ns
WE# High to Busy
tWB
-
100
ns
WP# Low to WE# Low (disable mode)
tWW
100
-
ns
WP# High to WE# Low (enable mode)
Read Cycle Time
tRC
25
-
ns
RE# Access Time
tREA
-
20
ns
CE# Access Time
tCEA
-
25
ns
RE# High to Output Hi-Z
tRHZ
-
100
ns
CE# High to Output Hi-Z
tCHZ
-
30
ns
CE# High to ALE or CLE Don’t care
tCSD
0
ns
RE# High to Output Hold
tRHOH
15
-
ns
RE# Low to Output Hold
tRLOH
5
ns
CE# High to Output Hold
tCOH
15
-
ns
RE# High Hold Time
tREH
10
-
ns
Output Hi-Z to RE# Low
tIR
0
-
ns
RE# High to WE# Low
tRHW
100
-
ns
WE# High to RE# Low
tWHR
60
-
ns
Device
Resetting
Time
during…
Read
tRST
-
5
us
Program
-
10
us
Erase
-
500
us
Ready
-
5 (1)
us
Cache Busy in Read Cache
(following 31h and 3Fh)
tDCBSYR
-
30
us
Note: If reset command (FFh) is written at Ready state, the device goes into Busy for maximum 5us.
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6. TIMING DIAGRAMS FOR OPERATION
6.1 COMMAND LATCH CYCLE
CE#
CLE
WE#
Command
tCLS tCLH
tCS tCH
tWP
tALS tALH
tDS tDH
ALE
I/Ox
Figure 6.1 Command Latch Cycle
6.2 ADDRESS LATCH CYCLE
Col Add1 Col Add2 Row Add1 Row Add2 Row Add3
tCS
tCLS
tWP tWH
tWC
tALS tALH
tDS tDH
CE#
CLE
WE#
ALE
I/Ox
Figure 6.2 Address Latch Cycle
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6.3 INPUT DATA LATCH CYCLE
DIN M DIN M+1 DIN N-1 DIN N
ALS
tWP tWH
tWC
tDS tDH
ALE
CE#
WE#
I/Ox
tCH
tCLH
CLE
Figure 6.3 Input Data Latch Cycle
6.4 SERIAL ACCESS CYCLE AFTER READ (CLE=L, WE#=H, ALE=L)
DOUT DOUT DOUT
tCEA
tRP tREH
tREA
CE#
RE#
I/Ox tRHOH
tRHZ
tCOH
tCHZ
R/B# tRR tRC
Note:
1. Dout transition is measured at ±200mV from steady state voltage at I/O with load.
2. tRHOH starts to be valid when frequency is lower than 33MHz.
Figure 6.4 Serial Access Cycle after Read
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6.5 SERIAL ACCESS CYCLE AFTER READ (EDO TYPE CLE=L, WE#=H, ALE=L)
DOUT DOUT DOUT
tRP tREH
tREA
CE#
RE#
I/Ox tRHOH
tRHZ
tCOH
tCHZ
R/B# tRR
tRC
tCEA
tRLOH
tREA
Notes:
1. Transition is measured at +/-200mV from steady state voltage with load.
This parameter is sample and not 100% tested. (tCHZ, tRHZ)
2. tRLOH is valid when frequency is higher than 33MHZ.
tRHOH starts to be valid when frequency is lower than 33MHZ.
Figure 6.5 Serial Access Cycle after Read (EDO Type CLE=L, WE#=H, ALE=L)
6.6 STATUS READ CYCLE
70h/F1h Status out
tCS
tWP
tDS tDH
CE#
WE#
I/Ox tRHOH
tRHZ
tCH
tIR tREA
RE#
tCEA
tCLH
tCLS tCLR
tCHZ
CLE
tWHR
Figure 6.6 Status Read Cycle
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6.7 READ OPERATION
Busy
WE#
00hCol Add2 Row Add2 30h
tWB
tR
Col Add1 Row Add1 Row Add3 Dout N Dout N+1 Dout M
RE#
ALE
tRR
tAR
tCLR
tRHZ
tRC
CLE
I/Ox
CE#
R/B#
tCDS
tWC
Figure 6.7 Read Operation (One Page)
6.8 READ OPERATION (INTERCEPTED BY CE#)
Busy
WE#
00hCol Add2 Row Add2 30h
tWB
tR
Col Add1 Row Add1 Row Add3 Dout N Dout N+1 Dout M
RE#
ALE
tRR
tAR
tCLR
tCHZ
tRC
CLE
I/Ox
CE#
R/B#
tCDS
tWC tCOH
Figure 6.8 Read Operation (Intercepted by CE#)
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6.9 RANDOM DATA OUTPUT IN A PAGE
WE#
05hCol Add2
Col Add1
RE#
ALE
CLE
I/Ox
CE#
R/B#
Busy
WE#
00hCol Add2 Row Add2 30h
tWB
tR
Col Add1 Row Add1 Row Add3 Dout N Dout N+1
RE#
ALE
tRR
tAR
tCLR
tRC
CLE
I/Ox
CE#
R/B#
tRHW
E0h Dout M Dout M+1
tWHR
tREA
1
1
1
1
05h
Figure 6.9 Random Data Output in a Page
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6.10 PAGE PROGRAM OPERATION
Busy
WE#
80hCol Add2 Row Add2
I/O0 = 0 Successful Program
I/O0 = 1 Error in Program
tWB
tWHR
Col Add1 Row Add1 Row Add3
RE#
ALE
tADL
CLE
I/Ox
CE#
R/B#
tWC
10h
Din N Din M 70hI/O0
tPROG
tWC
Note:
1. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
Figure 6.10 Page Program Operation
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6.11 PAGE PROGRAM OPERATION WITH RANDOM DATA INPUT
Note: tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of the first data cycle.
Figure 6.11 Page Program Operation with Random Data Input