030 Data Sheet
Modules
0
ARTIK 030 Mesh Networking Module
Data Sheet
The ARTIK 030 is a fully-integrated, pre-certified module, enabling rapid development of
wireless mesh networking solutions. The ARTIK 030 combines an energy-efficient, multi-
protocol wireless SoC with a proven RF/antenna design and industry-leading wireless
software stacks. This integration accelerates time-to-market and saves months of
engineering effort and development costs.
ARTIK 030 can be used in a wide variety of applications:
KEY FEATURES
• Industry-leading mesh networking (ZigBee/
Thread) software and development tools
• Antenna: internal chip and U.FL variants
• TX power: up to +10 dBm
• RX sensitivity: down to -99 dBm
• 32-bit ARM® Cortex®-M4 at 40 MHz
• Flash memory: 256 kB
• RAM: 32 kB
• Autonomous Hardware Crypto Accelerator
and Random Number Generator
• Integrated DC-DC Converter
• Connected Home
• Building Automation
• Lighting
• Security and Monitoring
• Smart Grid / Metering
• Industrial Automation
• Others
Timers and Triggers
RTCC
Cryotimer
Timer/Counter
Low energy timer
Pulse Counter
Watchdog Timer
Protocol Timer
32-bit bus
Peripheral Reflex System
Serial Interfaces
I/O Ports
Analog I/F
Lowest power mode with peripheral operational:
USART
Low Energy
UART
I2 C
External
Interrupts
General Purpose
I/O
Pin Reset
Pin Wakeup
ADC
IDAC
Analog
Comparator
Radio Transceiver
DEMOD
AGC
IFADC
CRC
BUFC
FRC
RAC
EM3— Stop EM2— Deep Sleep EM1— Sleep EM4— Hibernate EM4— Shutoff EM0— Active
I
Q
RF Frontend
LNA
MOD
Frequency
Synthesizer
PGA
BALUN
Core / Memory
ARM Cortex M4 Processor
with DSP Extensions and FPU
Energy Management
Brown-Out
Detector
DC-DC
Converter
Voltage
Regulator Voltage Monitor
Power-On Reset
Other
CRYPTO
CRC
Clock Management
High Frequency
Crystal Oscillator
Low Frequency
Crystal Oscillator
Low Frequency
RC Oscillator
High Frequency
RC Oscillator
Ultra Low
Frequency
RC Oscillator
Auxiliary
High Frequency
RC Oscillator
Flash Program
Memory
RAM Memory
Debug Interface
DMA Controller
Memory
Protection Unit
Antenna
Crystals
32.768 kHz
38.4 MHz
Chip Antenna
Matching
Ext. Antenna
(ARTIK-030A)
(ARTIK-030E)
PA
u.FL Connector
Preliminary Rev. 0.5 Samsung ARTIK™ Modules | artik.io
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Table of Contents
1. Feature List ................................
1
2. Ordering Information ............................2
3. System Overview ..............................3
3.1 Introduction...............................3
3.2 Radio.................................3
3.2.1 Antenna Interface ............................3
3.2.2 Packet and State Trace ..........................4
3.2.3 Random Number Generator ........................4
3.3 Power ................................5
3.3.1 Energy Management Unit (EMU) .......................5
3.3.2 DC-DC Converter ............................5
3.4 General Purpose Input/Output (GPIO)......................6
3.5 Clocking ................................6
3.5.1 Clock Management Unit (CMU) .......................6
3.5.2 Internal Oscillators............................6
3.6 Counters/Timers and PWM .........................6
3.6.1 Timer/Counter (TIMER) ..........................6
3.6.2 Real Time Counter and Calendar (RTCC) ....................6
3.6.3 Low Energy Timer (LETIMER)........................6
3.6.4 Ultra Low Power Wake-up Timer (CRYOTIMER) .................7
3.6.5 Pulse Counter (PCNT) ..........................7
3.6.6 Watchdog Timer (WDOG) .........................7
3.7 Communications and Other Digital Peripherals ...................7
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) ..........7
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) ..........7
3.7.3 Inter-Integrated Circuit Interface (I2C) .....................7
3.7.4 Peripheral Reflex System (PRS) .......................7
3.8 Security Features.............................7
3.8.1 GPCRC (General Purpose Cyclic Redundancy Check) ...............7
3.8.2 Crypto Accelerator (CRYPTO)........................8
3.9 Analog ................................8
3.9.1 Analog Port (APORT) ..........................8
3.9.2 Analog Comparator (ACMP) ........................8
3.9.3 Analog to Digital Converter (ADC) ......................8
3.9.4 Digital to Analog Current Converter (IDAC) ...................8
3.10 Reset Management Unit (RMU) .......................8
3.11 Core and Memory ............................8
3.11.1 Processor Core ............................8
3.11.2 Memory System Controller (MSC) ......................9
3.11.3 Linked Direct Memory Access Controller (LDMA) .................9
3.12 Memory Map ..............................10
3.13 Configuration Summary ..........................11
ARTIK 030 Mesh Networking Module Data Sheet
Table of Contents ii
4. Electrical Specifications ..........................12
4.1 Electrical Characteristics ..........................12
4.1.1 Absolute Maximum Ratings ........................12
4.1.2 General Operating Conditions ........................13
4.1.3 DC-DC Converter ............................14
4.1.4 Current Consumption...........................15
4.1.4.1 Current Consumption 3.3 V using DC-DC Converter ...............15
4.1.4.2 Current Consumption Using Radio .....................16
4.1.5 Wake up times .............................16
4.1.6 Brown Out Detector ...........................17
4.1.7 Frequency Synthesizer Characteristics .....................17
4.1.8 2.4 GHz RF Transceiver Characteristics ....................18
4.1.8.1 RF Transmitter General Characteristics for the 2.4 GHz Band ............18
4.1.8.2 RF Receiver General Characteristics for the 2.4 GHz Band .............18
4.1.8.3 RF Receiver Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band.......19
4.1.9 Oscillators ..............................21
4.1.9.1 LFXO ...............................21
4.1.9.2 HFXO ...............................21
4.1.9.3 LFRCO ...............................21
4.1.9.4 HFRCO and AUXHFRCO ........................22
4.1.9.5 ULFRCO ..............................22
4.1.10 Flash Memory Characteristics .......................23
4.1.11 GPIO................................24
4.1.12 VMON ...............................25
4.1.13 ADC ................................26
4.1.14 IDAC ................................29
4.1.15 Analog Comparator (ACMP) ........................31
4.1.16 I2C ................................33
4.1.17 USART SPI .............................35
5. Typical Connection Diagrams ........................37
5.1 Network Co-Processor (NCP) Application with UART Host ...............37
5.2 Network Co-Processor (NCP) Application with SPI Host................37
5.3 SoC Application .............................38
6. Layout Guidelines ............................39
6.1 Module Placement and Application PCB Layout Guidelines ..............39
6.2 Effect of Plastic and Metal Materials ......................40
6.3 Locating the Module Close to Human Body ....................40
6.4 2D Radiation Pattern Plots .........................41
7. Hardware Design Guidelines ........................43
7.1 Power Supply Requirements .........................43
7.2 Reset Functions .............................43
7.3 Debug and Firmware Updates ........................43
7.3.1 JTAG ................................43
7.3.2 Packet Trace Interface (PTI) ........................43
ARTIK 030 Mesh Networking Module Data Sheet
Table of Contents iii
8. Pin Definitions ..............................44
8.1 Pin Definitions ..............................44
8.1.1 GPIO Overview.............................53
8.2 Alternate Functionality Pinout ........................54
8.3 Analog Port (APORT) ...........................60
9. Package Specifications ..........................68
9.1 ARTIK 030 Dimensions...........................68
9.2 ARTIK 030 Module Footprint .........................68
9.3 ARTIK 030 Recommended PCB Land Pattern ...................69
9.4 ARTIK 030 Package Marking.........................70
10. Tape and Reel Specifications ........................72
10.1 Tape and Reel Packaging .........................72
10.2 Reel Material and Dimensions ........................72
10.3 Module Orientation and Tape Feed ......................73
10.4 Tape and Reel Box Dimensions .......................74
10.5 Moisture Sensitivity Level .........................74
11. Certifications ..............................75
12. Revision History............................. 76
12.1 Revision 0.5 ..............................76
ARTIK 030 Mesh Networking Module Data Sheet
Table of Contents iv
1. Feature List
MCU Features
•ARM Cortex®-M4 + Floating Point Unit
•Up to 40 MHz Clock Speed
• Low Active Mode Current: 63 μA/MHz
• 256 kB flash, 32 kB SRAM
• Advanced hardware cryptographic engine with support for
AES-128/-256, ECC, SHA-1, SHA-256, and a Random Num-
ber Generator
• 8 Channel DMA Controller
Digital Peripherals
•2 x USART (UART, SPI, IrDA, I2S)
•Low Energy UART (LEUART™)
•I2C peripheral interface (address recognition down to EM3)
• Timers: RTCC, Low Energy Timer, Pulse Counter
• 12-channel Peripheral Reflex System (PRS)
• Up to 25 GPIO with interrupts
Analog Peripherals
• ADC (12-bit, 1 Msps, 326 µA)
• Current-mode Digital to Analog Converter (IDAC)
• 2 x Analog Comparator (ACMP)
Energy Efficient Low Power Modes
• Energy Mode 2 (Deep Sleep) Current: 2.5 µA
(Full RAM retention and RTCC running from LXFO)
• Ultra-fast wake up: 3 µS down to EM3
• Wide Supply Voltage range of 1.85 to 3.8 V
Environmental & Regulatory
• Operating Temperature: -40 to +85°C
• FCC, IC, CE, Aus/NZ, Korea certifications (pending)
Dimensions
• W x L x H: 12.9 x 15.0 x 2.2 mm
Radio Features
•2.4 GHz with integrated balun
• Support for wireless mesh networking (ZigBee/Thread)
• Integrated PA (up to +10 dBm TX power)
• Packet Trace Interface (PTI) for non-intrusive packet trace with
Simplicity Studio development tools
• Antenna interface: integrated high-performance chip antenna
or u.FL variant for external antenna
ZigBee and Thread Features
• IEEE 802.15.4
• Data Rate / Modulation: 250 kbps DSSS-OQPSK
• +10 dBm Programmable TX Power
• -99 dBm RX Sensitivity
• 9.8 mA RX current
• 8.2 mA TX current (at +0 dBm)
• Support for SoC and Network Co-Processor (NCP) architec-
tures with SPI/UART host support
• Serial and Over-The-Air (OTA) bootloaders
ARTIK 030 Mesh Networking Module Data Sheet
Feature List
Samsung ARTIK™ Modules | artik.io Preliminary Rev. 0.5 | 1
2. Ordering Information
Ordering Code Description Max TX
Power
Antenna Packaging Production Status
ARTIK-030-AV1 ARTIK 030 Mesh Networking
Module
+10 dBm Integrated
chip antenna
Cut Reel
(100 pcs)
Initial Production / Engineering
Samples (non-certified)
ARTIK-030-AV1R ARTIK 030 Mesh Networking
Module
+10 dBm Integrated
chip antenna
Reel
(1000 pcs)
Initial Production / Engineering
Samples (non-certified)
ARTIK-030-EV1 ARTIK 030 Mesh Networking
Module
+10 dBm External (U.FL) Cut Reel
(100 pcs)
Initial Production / Engineering
Samples (non-certified) 1
ARTIK-030-EV1R ARTIK 030 Mesh Networking
Module
+10 dBm External (U.FL) Reel
(1000 pcs)
Initial Production / Engineering
Samples (non-certified) 1
ARTIK-030-AV2 ARTIK 030 Mesh Networking
Module
+10 dBm Integrated
chip antenna
Cut Reel
(100 pcs)
Full Production (certified) 1
ARTIK-030-AV2R ARTIK 030 Mesh Networking
Module
+10 dBm Integrated
chip antenna
Reel
(1000 pcs)
Full Production (certified) 1
ARTIK-030-EV2 ARTIK 030 Mesh Networking
Module
+10 dBm External (U.FL) Cut Reel
(100 pcs)
Full Production (certified) 1
ARTIK-030-EV2R ARTIK 030 Mesh Networking
Module
+10 dBm External (U.FL) Reel
(1000 pcs)
Full Production (certified) 1
SIP-KITSZG001 ARTIK 030 Mesh Networking
Kit (includes 3 x ARTIK-030-A
development boards)
— — Development Kit —
Note:
1. Contact sales@artik.io for availability and certification timelines.
2. ARTIK 030 development kit and IAR license required for ZigBee® and Thread software development.
ARTIK 030 Mesh Networking Module Data Sheet
Ordering Information
Samsung ARTIK™ Modules | artik.io Preliminary Rev. 0.5 | 2
3. System Overview
3.1 Introduction
This section provides a brief overview of the ARTIK 030 module architecture including both MCU and RF sub-systems. A detailed func-
tional description of the Silicon Lab's EFR32MG1 SoC used inside the module is available in the EFR32MG1 Mighty Gecko Datasheet
and EFR32xG1 Wireless Gecko Reference Manual and a block diagram of the EFR32MG1 SoC is shown in the figure below.
Analog Peripherals
Clock Management
LFXTAL_P / N LFXO
IDAC
ARM Cortex-M4 Core
Up to 256 KB ISP Flash
Program Memory
Up to 32 KB RAM
A
H
B
Watchdog
Timer
Reset
Management
Unit
Brown Out /
Power-On
Reset
RESETn
Digital Peripherals
Input MUX
Port
Mapper
Port I/O Configuration
I2C
Analog Comparator
12-bit ADC
Temp
Sensor
VREFVDD
VDD
Internal
Reference
TIMER
CRYOTIMER
PCNT
USART
Port A
Drivers
Port B
Drivers
PAn
Port C
Drivers PCn
PBn
Port D
Drivers PDn
LETIMER
RTC / RTCC
IOVDD
AUXHFRCO
HFRCO
ULFRCO
HFXO
Port F
Drivers PFn
Memory Protection Unit
LFRCO
A
P
B
LEUART
CRYPTO
CRC
DMA Controller
+
-
APORT
Floating Point Unit
Energy Management
DC-DC
Converter
DVDD
VREGVDD
VSS
VREGSW
bypass
AVDD
PAVDD
RFVDD
Voltage
Regulator
DECOUPLE
IOVDD
Voltage
Monitor
VREGVSS
RFVSS
PAVSS
Serial Wire Debug /
Programming
Radio Transciever
2G4RF_IOP
2G4RF_ION
RF Frontend
PA
I
Q
LNA
BALUN
RFSENSE
Frequency
Synthesizer
DEMOD
AGC
IFADC
CRC
BUFC
MOD
FRC
RAC
PGA
HFXTAL_P
HFXTAL_N
Figure 3.1. Detailed EFR32MG1 Block Diagram
3.2 Radio
The ARTIK 030 features a flexible, multi-protocol radio that supports wireless mesh networking (ZigBee® / Thread) protocols.
3.2.1 Antenna Interface
The ARTIK 030 module family includes options for either a high-performance, integrated chip-antenna (ARTIK-030-A) or external an-
tenna (ARTIK-030-E) via a U.FL connector. The table below includes performance specifications for the integrated chip antenna.
Table 3.1. Antenna Efficiency and Peak Gain (ARTIK-030-A)
Parameter With optimal layout Note
Efficiency -2 dB to -3 dB Antenna efficiency, gain and radiation pattern are highly depend-
ent on the application PCB layout and mechanical design. Refer
to Chapter 6. Layout Guidelines for PCB layout and antenna inte-
gration guidelines for optimal performance.
Peak gain 1.0 dBi
ARTIK 030 Mesh Networking Module Data Sheet
System Overview
Samsung ARTIK™ Modules | artik.io Preliminary Rev. 0.5 | 3
3.2.2 Packet and State Trace
The ARTIK 030 Frame Controller has a packet and state trace unit that provides valuable information during the development phase. It
features:
• Non-intrusive trace of transmit data, receive data and state information
• Data observability on a single-pin UART data output, or on a two-pin SPI data output
• Configurable data output bitrate / baudrate
• Multiplexed transmitted data, received data and state / meta information in a single serial data stream
3.2.3 Random Number Generator
The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.
The data is suitable for use in cryptographic applications.
Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num-
ber generator algorithms such as Fortuna.
ARTIK 030 Mesh Networking Module Data Sheet
System Overview
Samsung ARTIK™ Modules | artik.io Preliminary Rev. 0.5 | 4
3.3 Power
The ARTIK 030 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only a
single external supply voltage is required, from which all internal voltages are created. An integrated DC-DC buck regulator is utilized to
further reduce the current consumption.
Figure 3.2. ARTIK 030 Power Block
3.3.1 Energy Management Unit (EMU)
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM
blocks, and it contains control registers for the dc-dc regulator and the Voltage Monitor (VMON). The VMON is used to monitor multiple
supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has fallen
below a chosen threshold.
3.3.2 DC-DC Converter
The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2
and EM3. Patented RF noise mitigation allows operation of the DC-DC converter without degrading sensitivity of radio components.
Protection features include programmable current limiting, short-circuit protection, and dead-time protection. The DC-DC converter may
also enter bypass mode when the input voltage is too low for efficient operation. In bypass mode, the DC-DC input supply is internally
connected directly to its output through a low resistance switch. Bypass mode also supports in-rush current limiting to prevent input
supply voltage droops due to excessive output current transients.
ARTIK 030 Mesh Networking Module Data Sheet
System Overview
Samsung ARTIK™ Modules | artik.io Preliminary Rev. 0.5 | 5
3.4 General Purpose Input/Output (GPIO)
ARTIK 030 has up to 25 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or input.
More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO pin.
The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to sev-
eral GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripherals.
The GPIO subsystem supports asynchronous external pin interrupts.
3.5 Clocking
3.5.1 Clock Management Unit (CMU)
The Clock Management Unit controls oscillators and clocks in the ARTIK 030. Individual enabling and disabling of clocks to all peripher-
al modules is perfomed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility
allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and
oscillators.
3.5.2 Internal Oscillators
The ARTIK 030 fully integrates two crystal oscillators and four RC oscillators, listed below.
• A 38.4MHz high frequency crystal oscillator (HFXO) provides a precise timing reference for the MCU and radio.
• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.
• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial
Wire debug port with a wide frequency range.
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-
tal accuracy is not required.
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-
sumption in low energy modes.
3.6 Counters/Timers and PWM
3.6.1 Timer/Counter (TIMER)
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one
of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output
reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width
modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional
dead-time insertion available in timer unit TIMER_0 only.
3.6.2 Real Time Counter and Calendar (RTCC)
The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a
Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla-
tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving
frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy
and convenient data storage in all energy modes.
3.6.3 Low Energy Timer (LETIMER)
The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-
forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be con-
figured to start counting on compare matches from the RTCC.
ARTIK 030 Mesh Networking Module Data Sheet
System Overview
Samsung ARTIK™ Modules | artik.io Preliminary Rev. 0.5 | 6
3.6.4 Ultra Low Power Wake-up Timer (CRYOTIMER)
The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal
oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events
and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter-
rupt periods, facilitating flexible ultra-low energy operation.
3.6.5 Pulse Counter (PCNT)
The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The
clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from
among any of the internal oscillators, except the AUXHFRCO. The module may operate in energy mode EM0 Active, EM1 Sleep, EM2
Deep Sleep, and EM3 Stop.
3.6.6 Watchdog Timer (WDOG)
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by PRS.
3.7 Communications and Other Digital Peripherals
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-
porting:
• ISO7816 SmartCards
• IrDA
•I2S
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow
UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication
possible with a minimum of software intervention and energy consumption.
3.7.3 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and
supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10
kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The
interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated trans-
fers. Automatic recognition of slave addresses is provided in active and low energy modes.
3.7.4 Peripheral Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.
Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-
erals which in turn perform actions in response. Edge triggers and other functionality can be applied by the PRS. The PRS allows pe-
ripherals to act autonomously without waking the MCU core, saving power.
3.8 Security Features
3.8.1 GPCRC (General Purpose Cyclic Redundancy Check)
The GPCRC module implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The sup-
ported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the
needs of the application.
ARTIK 030 Mesh Networking Module Data Sheet
System Overview
Samsung ARTIK™ Modules | artik.io Preliminary Rev. 0.5 | 7
3.8.2 Crypto Accelerator (CRYPTO)
The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. It supports AES en-
cryption and decryption with 128- or 256-bit keys and ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and SHA-256).
Supported modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, CBC-MAC, GMAC and CCM.
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
The CRYPTO is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on data
buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger sig-
nals for DMA read and write operations.
3.9 Analog
3.9.1 Analog Port (APORT)
The Analog Port (APORT) is an analog interconnect matrix allowing access to analog modules ADC, ACMP, and IDAC on a flexible
selection of pins. Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differen-
tially, buses are grouped by X/Y pairs.
3.9.2 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-
er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the
programmable threshold.
3.9.3 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 MSamples/s. The
output sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple
samples. The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide
range of sources, including pins configurable as either single-ended or differential.
3.9.4 Digital to Analog Current Converter (IDAC)
The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin
or routed to the selected ADC input pin for capacitive sensing. The current is programmable between 0.05 µA and 64 µA with several
ranges with various step sizes.
3.10 Reset Management Unit (RMU)
The RMU is responsible for handling reset of the ARTIK 030. A wide range of reset sources are available, including several power sup-
ply monitors, pin reset, software controlled reset, core lockup reset and watchdog reset.
3.11 Core and Memory
3.11.1 Processor Core
The ARM Cortex-M4F processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M4F RISC processor achieving 1.25 Dhrystone MIPS/MHz
• Memory Protection Unit (MPU) supporting up to 8 memory segments
• 256 KB flash program memory
• 32 KB RAM data memory
• Configuration and event handling of all modules
• 2-pin Serial-Wire debug interface
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3.11.2 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code
is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a
read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-
ergy modes EM0 Active and EM1 Sleep.
3.11.3 Linked Direct Memory Access Controller (LDMA)
The Linked Direct Memory Access (LDMA) controller features 8 channels capable of performing memory operations independently of
software. This reduces both energy consumption and software workload. The LDMA allows operations to be linked together and stag-
ed, enabling sophisticated operations to be implemented.
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3.12 Memory Map
The ARTIK 030 memory map is shown in the figures below.
Figure 3.3. ARTIK 030 Memory Map — Core Peripherals and Code Space
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Figure 3.4. ARTIK 030 Memory Map — Peripherals
3.13 Configuration Summary
The features of the ARTIK 030 are a subset of the feature set described in the EFR32xG1 Wireless Gecko Reference Manual. The Pin
Definitions section describes device specific implementation of the features.
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4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-
er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation and operating temperature.
Refer to Table 4.2 General Operating Conditions on page 13 for more details about operational supply and temperature limits.
4.1.1 Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability.
Table 4.1. Absolute Maximum Ratings
Parameter Symbol Test Condition Min Typ Max Unit
Storage temperature range TSTG -40 — +85 °C
External main supply voltage VDDMAX 0 — 3.8 V
External main supply voltage
ramp rate
VDDRAMPMAX — — 1 V / μs
Voltage on any 5V tolerant
GPIO pin1
VDIGPIN -0.3 — Min of 5.25
and VDD+2
V
Voltage on non-5V tolerant
GPIO pins
-0.3 — VDD+0.3 V
Input RF level PRFMAX2G4 — — 10 dBm
Current per I/O pin (sink) IIOMAX — — 50 mA
Current per I/O pin (source) — — 50 mA
Current for all I/O pins (sink) IIOALLMAX — — 200 mA
Current for all I/O pins
(source)
— — 200 mA
Note:
1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = VDD.
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4.1.2 General Operating Conditions
Table 4.2. General Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Operating temperature range TOP Ambient Temperature -40 25 85 °C
VDD supply voltage1VVDD DCDC in regulation 2.4 3.3 3.8 V
DCDC in bypass, 50mA load 1.85 3.3 3.8 V
VDD Current IVDD DCDC in bypass — — 200 mA
HFCLK frequency fCORE 0 wait-states (MODE = WS0) 2— — 26 MHz
1 wait-states (MODE = WS1) 2— 38.4 40 MHz
Note:
1. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for
other loads can be calculated as VVDD_min+ILOAD * RBYP_max
2. in MSC_READCTRL register
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4.1.3 DC-DC Converter
Test conditions: VDCDC_I=3.3 V, VDCDC_O=1.8 V, IDCDC_LOAD=50 mA, Heavy Drive configuration, FDCDC_LN=7 MHz, unless otherwise
indicated.
Table 4.3. DC-DC Converter
Parameter Symbol Test Condition Min Typ Max Unit
Input voltage range VDCDC_I Bypass mode, IDCDC_LOAD = 50
mA
1.85 — VVDD_MAX V
Low noise (LN) mode, 1.8 V out-
put, IDCDC_LOAD = 100 mA, or
Low power (LP) mode, 1.8 V out-
put, IDCDC_LOAD = 10 mA
2.4 — VVDD_MAX V
Low noise (LN) mode, 1.8 V out-
put, IDCDC_LOAD = 200 mA
2.6 — VVDD_MAX V
Output voltage programma-
ble range 1
VDCDC_O 1.8 — VVREGVDD V
Max load current ILOAD_MAX Low noise (LN) mode, Heavy
Drive 3
— — 200 mA
Low noise (LN) mode, Medium
Drive 3
— — 100 mA
Low noise (LN) mode, Light Drive
3
— — 50 mA
Low power (LP) mode,
LPCMPBIAS 2 = 0
— — 75 μA
Low power (LP) mode,
LPCMPBIAS 2 = 3
— — 10 mA
Note:
1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVDD
2. In EMU_DCDCMISCCTRL register
3. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi-
um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.
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4.1.4 Current Consumption
4.1.4.1 Current Consumption 3.3 V using DC-DC Converter
Unless otherwise indicated, typical conditions are: VDD = 3.3 V, DC-DC enabled. TOP = 25 °C. Minimum and maximum values in this
table represent the worst conditions across supply voltage and process variation at TOP = 25 °C.
Table 4.4. Current Consumption 3.3V with DC-DC
Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in EM0
Active mode with all periph-
erals disabled, DCDC in Low
Noise DCM mode1.
IACTIVE 38.4 MHz crystal, CPU running
while loop from flash2
— 88 — μA/MHz
38 MHz HFRCO, CPU running
Prime from flash
— 63 — μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
— 71 — μA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
— 78 — μA/MHz
26 MHz HFRCO, CPU running
while loop from flash
— 76 — μA/MHz
Current consumption in EM0
Active mode with all periph-
erals disabled, DCDC in Low
Noise CCM mode3.
38.4 MHz crystal, CPU running
while loop from flash2
— 98 — μA/MHz
38 MHz HFRCO, CPU running
Prime from flash
— 75 — μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
— 81 — μA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
— 88 — μA/MHz
26 MHz HFRCO, CPU running
while loop from flash
— 94 — μA/MHz
Current consumption in EM1
Sleep mode with all peripher-
als disabled, DCDC in Low
Noise DCM mode1.
IEM1 38.4 MHz crystal2— 49 — μA/MHz
38 MHz HFRCO — 32 — μA/MHz
26 MHz HFRCO — 38 — μA/MHz
Current consumption in EM1
Sleep mode with all peripher-
als disabled, DCDC in Low
Noise CCM mode3.
38.4 MHz crystal2— 61 — μA/MHz
38 MHz HFRCO — 45 — μA/MHz
26 MHz HFRCO — 58 — μA/MHz
Current consumption in EM2
Deep Sleep mode. DCDC in
Low Power mode4.
IEM2 Full RAM retention and RTCC
running from LFXO
— 2.5 — μA
4 kB RAM retention and RTCC
running from LFRCO
— 2.2 — μA
Current consumption in EM3
Stop mode
IEM3 Full RAM retention and CRYO-
TIMER running from ULFRCO
— 2.1 — μA
Current consumption in
EM4H Hibernate mode
IEM4 128 byte RAM retention, RTCC
running from LFXO
— 0.86 — μA
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
— 0.58 — μA
128 byte RAM retention, no RTCC — 0.58 — μA
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Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in
EM4S Shutoff mode
IEM4S no RAM retention, no RTCC — 0.04 — μA
Note:
1. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DCDC voltage.
2. CMU_HFXOCTRL_LOWPOWER=0
3. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DCDC voltage.
4. DCDC Low Power Mode = Medium Drive (PFETCNT=NFETCNT=7), LPOSCDIV=1, LPBIAS=3, LPCILIMSEL=1, ANASW=DCDC
voltage.
4.1.4.2 Current Consumption Using Radio
Unless otherwise indicated, typical conditions are: VDD = 3.3 V. TOP = 25 °C. Minimum and maximum values in this table represent the
worst conditions across supply voltage and process variation at TOP = 25 °C.
Table 4.5. Current Consumption 3.3 V with DC-DC
Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in re-
ceive mode, active packet
reception (MCU in EM1 @
38.4 MHz, peripheral clocks
disabled)
IRX 1 Mbit/s, 2GFSK, F = 2.4 GHz,
Radio clock prescaled by 4
— 8.7 — mA
802.15.4 receiving frame, F = 2.4
GHz, Radio clock prescaled by 3
— 9.8 — mA
Current consumption in
transmit mode (MCU in EM1
@ 38.4 MHz, peripheral
clocks disabled)
ITX F = 2.4 GHz, CW, 0 dBm, Radio
clock prescaled by 3
— 8.2 — mA
F = 2.4 GHz, CW, 10.5 dBm — 32.7 — mA
4.1.5 Wake up times
Table 4.6. Wake up times
Parameter Symbol Test Condition Min Typ Max Unit
Wake up from EM2 Deep
Sleep
tEM2_WU Code execution from flash — 10.7 — μs
Code execution from RAM — 3 — μs
Wakeup time from EM1
Sleep
tEM1_WU Executing from flash — 3 — AHB
Clocks
Executing from RAM — 3 — AHB
Clocks
Wake up from EM3 Stop tEM3_WU Executing from flash — 10.7 — μs
Executing from RAM — 3 — μs
Wake up from EM4H Hiber-
nate1
tEM4H_WU Executing from flash — 60 — μs
Wake up from EM4S Shut-
off1
tEM4S_WU — 290 — μs
Note:
1. Time from wakeup request until first instruction is executed. Wakeup results in device reset.
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4.1.6 Brown Out Detector
For the table below, see Figure 3.2 ARTIK 030 Power Block on page 5 to see the internal connection and relation between DVDD and
AVDD. The module itself has only one external power supply input (VDD).
Table 4.7. Brown Out Detector
Parameter Symbol Test Condition Min Typ Max Unit
AVDD BOD threshold VAVDDBOD AVDD rising — — 1.85 V
AVDD falling 1.62 — — V
AVDD BOD hysteresis VAVDDBOD_HYST — 21 — mV
AVDD response time tAVDDBOD_DELAY Supply drops at 0.1V/μs rate — 2.4 — μs
EM4 BOD threshold VEM4DBOD AVDD rising — — 1.7 V
AVDD falling 1.45 — — V
EM4 BOD hysteresis VEM4BOD_HYST — 46 — mV
EM4 response time tEM4BOD_DELAY Supply drops at 0.1V/μs rate — 300 — μs
4.1.7 Frequency Synthesizer Characteristics
Table 4.8. Frequency Synthesizer Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
RF Synthesizer Frequency
range
FRANGE_2400 2.4 GHz frequency range 2400 — 2483.5 MHz
LO tuning frequency resolu-
tion
FRES_2400 2400 - 2483.5 MHz — — 73 Hz
Maximum frequency devia-
tion
ΔFMAX_2400 — — 1677 kHz
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4.1.8 2.4 GHz RF Transceiver Characteristics
4.1.8.1 RF Transmitter General Characteristics for the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: TOP = 25 °C, VDD = 3.3 V. RF center frequency 2.45 GHz. Measurements are con-
ducted from the antenna feed point.
Table 4.9. RF Transmitter General Characteristics for 2.4 GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Maximum TX power POUTMAX — 10 — dBm
Minimum active TX Power POUTMIN CW -30 — dBm
Output power step size POUTSTEP -5 dBm < Output power < 0 dBm — 1 — dB
0 dBm < output power <
POUTMAX
— 0.5 — dB
Output power variation vs
supply at POUTMAX
POUTVAR_V 1.85 V < VVDD < 3.3 V using DC-
DC converter
— 2.2 — dB
Output power variation vs
temperature at POUTMAX
POUTVAR_T From -40 to +85 °C, DCDC ena-
bled
— 1.5 — dB
Output power variation vs RF
frequency at POUTMAX
POUTVAR_F Over RF tuning frequency range — 0.4 — dB
RF tuning frequency range FRANGE 2400 — 2483.5 MHz
4.1.8.2 RF Receiver General Characteristics for the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: TOP = 25 °C,VDD = 3.3 V. RF center frequency 2.440 GHz. Measurements are con-
ducted from the antenna feed point.
Table 4.10. RF Receiver General Characteristics for 2.4 GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
RF tuning frequency range FRANGE 2400 — 2483.5 MHz
Receive mode maximum
spurious emission
SPURRX 30 MHz to 1 GHz — -57 — dBm
1 GHz to 12 GHz — -47 — dBm
Max spurious emissions dur-
ing active receive mode, per
FCC Part 15.109(a)
SPURRX_FCC 216 MHz to 960 MHz, Conducted
Measurement
— -55.2 — dBm
Above 960 MHz, Conducted
Measurement
— -47.2 — dBm
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4.1.8.3 RF Receiver Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T=25 °C,VDD = 3.3 V. RF center frequency 2.445 GHz. Meaurements are conducted
from the antenna feed point.
Table 4.11. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Max usable receiver input
level, 1% PER
SAT Signal is reference signal1. Packet
length is 20 octets.
— 10 — dBm
Sensitivity, 1% PER SENS Signal is reference signal. Packet
length is 20 octets. Using DC-DC
converter.
— -99 — dBm
Signal is reference signal. Packet
length is 20 octets. DC-DC con-
verter in bypass mode.
— -99 — dBm
Co-channel interferer rejec-
tion, 1% PER
CCR Desired signal 10 dB above sensi-
tivity limit
— -2.6 — dB
High-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
level2
ACR+1 Interferer is reference signal at +1
channel-spacing.
— 33.75 — dB
Interferer is filtered reference sig-
nal3 at +1 channel-spacing.
— 52.2 — dB
Interferer is CW at +1 channel-
spacing.4
— 58.6 — dB
Low-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
level2
ACR-1 Interferer is reference signal at -1
channel-spacing.
— 35 — dB
Interferer is filtered reference sig-
nal3 at -1 channel-spacing.
— 54.7 — dB
Interferer is CW at -1 channel-
spacing.
— 60.1 — dB
Alternate channel rejection,
1% PER. Desired is refer-
ence signal at 3dB above
reference sensitivity level2
ACR2Interferer is reference signal at ±2
channel-spacing
— 45.9 — dB
Interferer is filtered reference sig-
nal3 at ±2 channel-spacing
— 56.8 — dB
Interferer is CW at ±2 channel-
spacing
— 65.5 — dB
Image rejection , 1% PER,
Desired is reference signal at
3dB above reference sensi-
tivity level2
IR Interferer is CW in image band4— 49.3 — dB
Blocking rejection of all other
channels. 1% PER, Desired
is reference signal at 3dB
above reference sensitivity
level2. Interferer is reference
signal.
BLOCK Interferer frequency < Desired fre-
quency - 3 channel-spacing
— 57.2 — dB
Interferer frequency > Desired fre-
quency + 3 channel-spacing
— 57.9 — dB
Blocking rejection of 802.11g
signal centered at +12MHz
or -13MHz
BLOCK80211G Desired is reference signal at 6dB
above reference sensitivity level2
— 51.6 — dB
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