This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be rev is ed by subsequent versi ons or modificat ions due to changes in technical specif ic ations. Publicati on# 21490 Rev: GAmendment/+2
Issue Date: August 14, 2000
Am29LV800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 3.0 Volt-onl y Boot Sec tor Flash Memory
DISTINCTIVE CHARACTERISTICS
■Single power supply operation
— 2.7 to 3.6 volt read and write operations for
battery-powered applications
■Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29LV800 devi ce
■High performan c e
— Access times as fast as 70 ns
■Ultra low power consumption (typical values at
5MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current
■Flexible sector ar chitectur e
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardw are method of loc king a sector to pre v ent
any program or erase operations within that sector
Sectors can be locked in-system or via
programming equipm ent
Temporary Sector Unprotect f eature allo ws code
changes in prev iously locked sectors
■Unlock Bypass Progr am Co mm and
— Reduces ov erall prog ramming time when issuing
multiple program command sequences
■Top or bottom boot block configurations
available
■Embedded Algorithms
— Embedded Erase algorithm automatically
preprogr ams and erases the entire chip or any
combination of designated sectors
— Embedded Program algor ithm automatically
writes and ver ifies data at specified addresses
■Minimum 1 million write c ycle guarantee
per sector
■20-year d ata retention at 125°C
— Reliable operation for the life of the system
■Package option
— 48-ball FBGA
— 48-pin TSOP
— 44-pin SO
— Known Good Die (KGD)
(see publication number 21536)
■Compatibility with JEDEC standards
— Pinout and software compatible with single-
pow er supply Flash
— Superior inadvertent write protection
■Data# Pollin g and toggle bi ts
— Provides a software method of detecting program
or erase operation completion
■Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■Erase Suspend/Erase Resume
— Suspends an er ase operat ion to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■Hardware reset pin (RESET#)
— Hardware method to res et the device to reading
array data
2 Am29LV800B
GENERAL DESCRIPTION
The Am29LV800B is an 8 Mbit, 3.0 volt-only Flash
memory organized as 1,048,576 bytes or 524,288
words. The device is offered in 48-ball FBGA, 44-pin
SO, and 48-pin TSOP packages. The device is also
available in Known Good Die (KGD) form. For more
information, refer to publication number 21536. The
word-wide data (x16) appears on DQ15–DQ0; the
byte-wide (x8) data appears on DQ7–DQ0. This device
requires only a single, 3.0 volt VCC supply to perform
read, program, and erase operations. A standard
EP R O M program mer c an also be used to program and
erase the device.
This device is manufactured using AMD’s 0.32 µm
process technolog y, and off ers all the f eatures an d ben-
efits of the Am29LV800, which was manuf actured using
0.5 µm process technology. In addition, the
Am29LV800B features unlock bypass programming
and in-system sector protection/unprotection.
The standard de vice offers access times of 70, 90, and
120 ns, allowing high speed microprocessors to
operate wit hout wait st ates. To eliminate bus c ontention
the device has separate chip enable (CE#), write
enable ( WE#) and output enable (OE#) controls.
The de vice requires only a single 3. 0 v o lt po wer sup-
ply for both read and write functions. Inter nally gener-
ated and regulated voltages are provided for the
program and erase operations.
The de vice is entirely command set compatib le with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the er ase and progr amming circ uitry. Write cycles
also internally latch addresses and data neede d f or the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM de vices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
De vice erasure occurs by e xecuting the erase command
sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device auto matically tim es the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the de v ice is ready to read arr ay data
or accept another command.
The sector erase ar chitecture allo ws memo ry se ctors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure . True bac kgro und eras e can thus be achie ved.
The hardware RESET# pin term inates any operation
in progress and resets the internal state machine to
reading arr a y data. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The de vice off ers tw o power-saving f eatures. When ad-
dresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also plac e the de v ice into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a s ect or simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron injec-
tion.
Am29LV800B 3
TABLE OF CONTENTS
Product Selecto r Guide . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Special Handling Instructions for FBGA Package ..7
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8
Standard Products ..................................................8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9
Table 1. Am29LV800B Device Bus Operations ............9
Word/Byte Configuration ........................................9
Requirements for Reading Array D ata ...................9
Writing Commands/Command Sequences ............9
Program and Erase Operation Status ..................10
Standby Mode ......................................................10
Automatic Sleep Mode ................................ .........10
RESET#: Hardware Reset Pin .............................10
Output Disable Mode ............................................11
Table 2. Am29LV800BT Top Boot Block
Sector Addresses ........................................................ 11
Table 3. Am29LV800BB Bottom Boot Block
Sector Addresses ... ......................... ............................ 12
Autoselect Mode ............................. ......................12
Table 4. Am29LV800B Autoselect Codes
(High Voltage Method) ................................................13
Sector Protection/Unprotection ............................13
Temporary Sector Unprotect ................................13
Figure 1. Temporary Sector Unprotect Operation....... 13
Figure 2. In-System Sector Protect/
Sector Unprotect Algorithms ....................................... 14
Hardware Data Protection ....................................15
Command Definitions . . . . . . . . . . . . . . . . . . . . . 15
Reading Array Data ..............................................15
Reset Command ................... ...............................15
Autoselect Command Sequence ............. .............15
Word/Byte Program Command Sequence ......... ..16
Figure 3. Program Operation ...................................... 17
Chip Erase Command Sequence .........................17
Sector Erase Command Sequence ......... .............17
Erase Suspend/Erase Resume Commands .........18
Figure 4. Erase Ope rat ion. ..... ..... ..... ..... ..... ..... ...... ..... . 18
Table 5. Am2 9L V80 0B Comm an d Defin itio ns ...... ..... ..19
Write Operation Status . . . . . . . . . . . . . . . . . . . . 20
DQ 7 : D a ta # Po ll in g ....... .. .. ............. .. .. ............. ... .. .20
Figure 5. Data# Polling Algorithm ............................... 20
RY/BY#: Ready/Busy# ........................... ..............21
DQ6: Toggle Bit I ..................................................21
DQ2: Toggle Bit II .................................................21
Reading Toggle Bits DQ6/DQ2 ....................... .....21
DQ5: Exceeded Timing Limits ....................... .......22
DQ3: Sector Erase Timer .....................................22
Figure 6. Toggle Bit Algorithm..................................... 22
Table 6. Write Oper atio n Stat us ........... ..... ..... ...... ..... ..23
Absolute Maximum Ratings . . . . . . . . . . . . . . . . .24
Operati ng Ranges . . . . . . . . . . . . . . . . . . . . . . . . 24
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .25
CMOS Compatible ...............................................25
Figure 9. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents).......................................... 26
Figure 10. Typical ICC1 vs. Frequency ........................ 26
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. Te st Set up........ ..... ..... ...... ..... ..... ..... ..... ..... . 27
Table 7. Tes t Spec ifica tion s ............. ..... ..... ..... ..... ..... ..27
Key to Switching Waveforms. . . . . . . . . . . . . . . . 27
Figure 12. Input Waveforms and
Measurement Levels................................................... 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Read Operations ........................ ..........................28
Figure 13. Read Operations Timings .......................... 28
Hardware Reset (RESET#) ........ ..........................29
Figure 14. RESET# Timings........................................ 29
Word/Byte Configuration (BYTE#) .....................30
Figure 15. BYTE# Timings for Read Operations......... 30
Figure 16. BYTE# Timings for Write Operations......... 30
Erase/Program Operations ...................................31
Figure 17. Program Operation Timings....................... 32
Figure 18. Chip/Sector Erase Operation Timings........ 33
Figure 19. Data# Polling Timings (During
Embedded Algorithms)................................................ 34
Figure 20. Toggle Bit Timings (During
Embedded Algorithms)................................................ 34
Figure 21. D Q2 vs. DQ 6......... ..... ...... ..... ..... ..... ..... ..... . 35
Temp o ra r y Se ctor U n p ro te c t ... .. .. ............. ... .. .......3 5
Figure 22. Temporary Sector Unprotect
Timing Diagram........................................................... 35
Figure 23. Sector Protect/Unprotect
Timing Diagram........................................................... 36
Alternate CE# Controlled
Erase/Program Operations ...................................37
Figure 24. Alternate CE# Controlled Write
Operation Timings....................................................... 38
Erase and Programming Performance . . . . . . . 39
Latchup C haracterist ics. . . . . . . . . . . . . . . . . . . . 39
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 39
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40
TS 048—48-Pin Standard TSOP ......... ....... ........40
TSR048—48-Pin Reverse TSOP ........................41
FBB 048—48-Ball Fine-Pitch Ball Grid Array
(FBGA) 6 x 9 mm ................................................42
SO 044—44-Pin Small Outline Package .............43
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 44
Revision E (January 1998) .......................... .........44
Revision E+1 (March 1998) .......... ........................44
Revision F (January 1999) ...................................44
Revision F+1 (February 1999) .............................44
Revision F+2 (February 1999) .............................44
Revis ion F+ 3 ( Ju ly 2 , 1 999 ) ...... ......... ......... .........44
Revision F+4 (July 26, 1999) ...............................44
Revision G (November 10, 1999) ....................... ..45
Revision G+1 (July 7, 2000) .................... .............45
Revision G+2 (August 14, 2000) ....... ................. ..45
4 Am29LV800B
PRODUCT SELECTOR GUIDE
Note: See “AC Ch aracte r ist ics ” for full specifications.
BLOCK DIAGRAM
Family Part Number Am29LV800B
Speed Options Full Voltage Range: VCC = 2.7–3.6 V -70 -90 -120
Max access time, ns (tACC)7090120
Max CE# access time, ns (tCE)7090120
Max OE# access time, ns (tOE)303550
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
BYTE#
CE#
OE#
STB
STB
DQ0
–
DQ15 (A-1)
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A0–A18
Am29LV800B 5
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 for
more information.
A1
A15
A18
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A1
A15
A18
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
21490G-2
Reverse TSOP
Standard TSOP
6 Am29LV800B
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 for
more information.
A1 B1 C1 D1 E1 F1 G1 H1
A2 B2 C2 D2 E2 F2 G2 H2
A3 B3 C3 D3 E3 F3 G3 H3
A4 B4 C4 D4 E4 F4 G4 H4
A5 B5 C5 D5 E5 F5 G5 H5
A6 B6 C6 D6 E6 F6 G6 H6
DQ15/A-1 VSS
BYTE#A16A15A14A12A13
DQ13 DQ6DQ14DQ7A11A10A8A9
VCC DQ4DQ12DQ5NCNCRESET#WE#
DQ11 DQ3DQ10DQ2NCA18NCRY/BY#
DQ9 DQ1DQ8DQ0A5A6A17A7
OE# VSS
CE#A0A1A2A4A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
SO
FBGA
Top View, Balls Facing Down
Am29LV800B 7
Special Handling Instructions for FBGA
Package
Special handling is required f or Flash Memory products
in FBGA packages.
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be
compromised if the package body is exposed to
temperatures above 150°C for prolonged periods of
time.
PIN CONFIGURATION
A0–A18 = 19 addresses
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1 = DQ15 (data input/outpu t, word mode),
A-1 (LSB address input, byte mode)
BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and vo ltage s upply toler anc es)
VSS = De vice ground
NC = Pin not connected internally
LOGIC SYMBOL
19 16 or 8
DQ0–DQ15
(A-1)
A0–A18
CE#
OE#
WE#
RESET#
BYTE# RY/BY#
8 Am29LV800B
ORDERING INFORMATION
Standard Prod ucts
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in v olume for this device. Consult the local AMD sales
office to confirm av ailability of specific valid combinations and
to check on newly released combinations.
Am29LV800B T -70 E C
TEMPERATURE RANGE
C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 48-Pin Thin S mall Outline Package (TSOP) Standard Pinout (TS 048)
F = 48-Pin Thin S mall Outline Package (TSOP) Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
WB = 48-Ball Fine Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 6 x 9 mm package (FBB048)
This device is also av ailab le in Known Good Die (KGD) form. See publication number
21536 for more information.
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29LV800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
Valid Combinations for TSOP and SO Packages
AM29LV800BT-70,
AM29LV800BB-70 EC, EI, FC, FI, SC, SI
AM29LV800BT-90,
AM29LV800BB-90 EC, EI, EE,
FC, FI, FE,
SC, SI, SE
AM29LV800BT-120,
AM29LV800BB-120
Valid Combinations for FBGA Packages
Order Number Package Marking
AM29LV800BT-70,
AM29LV800BB-70
WBC,
WBI
L800BT70V,
L800BB70V
C, I
AM29LV800BT-90,
AM29LV800BB-90 L800BT90V,
L800BB90V
AM29LV800BT-120,
AM29LV800BB-120 L800BT12V,
L800BB12V
Am29LV800B 9
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The regi st er is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state
machine. The state machine outputs dictate the func-
tion of the device. Table 1 lists the device bus opera-
tions, the inputs and control le v els the y require, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29LV800B Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0
±
0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 oper ate in t he b y te or word c onfigur a-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configurat ion, and only data I/O pins DQ0–DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address funct i on.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates arra y data to the output pins . WE# should
remain at VIH. The BYTE# pin determines whether the
device outputs array data in words or bytes.
The internal state machine is set for reading array
data upon de vic e po wer-up, or after a har dwar e reset.
This ensures that no spur ious alte ration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert v alid addresses on the de vice address in puts pro-
duce v alid data on the de vice data outputs. The de vice
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. ICC1 in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
Operation CE# OE# WE# RESET# Addresses
(Note 1) DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE#
= VIL
Read L L H H AIN DOUT DOUT DQ8–DQ14 = High-Z,
DQ15 = A-1
Write L H L H AIN DIN DIN
Standby VCC ±
0.3 V XXVCC ±
0.3 V X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Reset X X X L X High-Z High-Z High-Z
Sector Protect (Note 2) L H L VID
Sector Ad dre ss,
A6 = L, A1 = H,
A0 = L DIN XX
Sector Unp rot ect (Note 2) L H L VID
Sector Ad dre ss,
A6 = H, A1 = H,
A0 = L DIN XX
Temporary Sector Unprotect X X X VID AIN DIN DIN High-Z
10 Am29LV800B
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
information.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the Un-
lock Bypass mode, only two write cycles are required to
program a word or byte, instead of four. The “W ord/Byte
Program Command Sequence” section has details on
programming data to the device using both standard and
Unlock Bypass command sequences.
An erase oper at ion can er ase one sect or, mult iple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies . A “sector ad-
dress” consists of t he address bits req uired t o un iquely
select a sector. The “Command Definitions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autos elect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections f or more information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or prog ram oper ation, th e system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. St andard read cycle timings and I CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to t he device ,
it can place the device in the standby mode. In this
mode, current co nsumption is g reat ly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the C MOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are he ld at VIH, b ut not within
VCC ± 0.3 V, the de vice will be in the standb y mode, b ut
the standby current will be greater . The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics table, ICC3 and ICC4 repre-
sents the standby curren t specif icat ion.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The dev ice automatically enables
this mode when addresses remain stable for t ACC + 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. St andard address
access timings provide new data w hen addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC4 in the DC
Characteristics table represents the automatic sleep
mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin p rovides a hard ware method of reset-
ting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the de vice is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
dra ws CMOS standby current (ICC4). If RESET# is held
at VIL b ut not within VSS±0.3 V, the standb y current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset oper at ion is complete . If RESET# i s
asserted when a program or er ase operation is not e x-
ecuting (RY/BY# pin is “1”), the reset operation is
completed wi thin a time of tREADY (not during Embed-
ded Algorithms). The system can read data tRH after
the RESET # pi n r e tu rns to VIH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
Am29LV800B 11
Output Disable Mode
When the OE# input is at VIH, outpu t from the de vice is
disabled. The output pins are placed in the high imped-
ance state.
Table 2. Am29LV800BT Top Boot Block Sector Addresses
Sector A18 A17 A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
Address Ran g e (in hexade cim al )
(x8)
Address Ran g e (x16)
Address Range
SA00000XXX 64/32 00000h–0FFFFh 00000h–07FFFh
SA10001XXX 64/32 10000h–1FFFFh08000h–0FFFFh
SA20010XXX 64/32 20000h–2FFFFh10000h–17FFFh
SA30011XXX 64/32 30000h–3FFFFh18000h–1FFFFh
SA40100XXX 64/32 40000h–4FFFFh20000h–27FFFh
SA50101XXX 64/32 50000h–5FFFFh28000h–2FFFFh
SA60110XXX 64/32 60000h–6FFFFh30000h–37FFFh
SA70111XXX 64/32 70000h–7FFFFh38000h–3FFFFh
SA81000XXX 64/32 80000h–8FFFFh40000h–47FFFh
SA91001XXX 64/32 90000h–9FFFFh48000h–4FFFFh
SA101010XXX 64/32 A0000h–AFFFFh50000h–57FFFh
SA111011XXX 64/32 B0000h–BFFFFh58000h–5FFFFh
SA121100XXX 64/32 C0000h–CFFFFh60000h–67FFFh
SA131101XXX 64/32 D0000h–DFFFFh68000h–6FFFFh
SA141110XXX 64/32 E0000h–EFFFFh70000h–77FFFh
SA1511110XX 32/16 F0000h–F7FFFh78000h–7BFFFh
SA161111100 8/4 F8000h–F9FFFh7C000h–7CFFFh
SA171111101 8/4 FA000h–FBFFFh7D000h–7DFFFh
SA18111111X 16/8 FC000h–FFFFFh7E000h–7FFFFh
12 Am29LV800B
Table 3. Am29LV800BB Bottom Boot Block Sector Addresses
Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration”
section.
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended f or programming equipment
to automatically match a de vice to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the c ommand register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin A9.
Address pins A6, A1, and A0 must be as shown in Table
4. In addition, when verifying sector protection, the sec-
tor address must appear on the appropriate highest
order address bits (see Tables 2 and 3). Table 4 shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the program-
ming equipment ma y then read the corresponding iden-
tifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require VID. See “Command Definitions” for
details on using the autos elect mode.
Sector A18 A17 A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
Address Ran g e (in hexade cim al )
(x8)
Address Ran g e (x16)
Address Range
SA0000000X 16/8 00000h–03FFFh 00000h–01FFFh
SA10000010 8/4 04000h–05FFFh02000h–02FFFh
SA20000011 8/4 06000h–07FFFh03000h–03FFFh
SA300001XX 32/16 08000h–0FFFFh04000h–07FFFh
SA40001XXX 64/32 10000h–1FFFFh08000h–0FFFFh
SA50010XXX 64/32 20000h–2FFFFh10000h–17FFFh
SA60011XXX 64/32 30000h–3FFFFh18000h–1FFFFh
SA70100XXX 64/32 40000h–4FFFFh20000h–27FFFh
SA80101XXX 64/32 50000h–5FFFFh28000h–2FFFFh
SA90110XXX 64/32 60000h–6FFFFh30000h–37FFFh
SA100111XXX 64/32 70000h–7FFFFh38000h–3FFFFh
SA111000XXX 64/32 80000h–8FFFFh40000h–47FFFh
SA121001XXX 64/32 90000h–9FFFFh48000h–4FFFFh
SA131010XXX 64/32 A0000h–AFFFFh50000h–57FFFh
SA141011XXX 64/32 B0000h–BFFFFh58000h–5FFFFh
SA151100XXX 64/32 C0000h–CFFFFh60000h–67FFFh
SA161101XXX 64/32 D0000h–DFFFFh68000h–6FFFFh
SA171110XXX 64/32 E0000h–EFFFFh70000h–77FFFh
SA181111XXX 64/32 F0000h–FFFFFh78000h–7FFFFh
Am29LV800B 13
Table 4. Am29LV800B A utosel ect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
progr am and er ase opera tions in an y sect or. The hard-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possib le to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Sector Protection/unprotection can be implemented via
two methods.
The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 2 shows the algo-
rithms and Figure 23 shows the timing diagram. This
method uses standard microprocessor bus cycle tim-
ing. For s ector unprotect, all unprotected sectors must
first be prote cted prior to the firs t sector unprotec t write
cycle.
The alternate method intended only for programming
equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines
written f or earlier 3.0 v olt-only AMD flash de vi ces. Pub-
lication number 20536 contains further details; contact
an AMD representative to request a copy.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sect ors to change data in-system. The
Sector Unprotect mode is activated by setting the R E-
SET# pin to VID. During this mode, former ly protected
sectors can be prog r ammed or er ased b y selec ting the
sector addresses. Once VID is removed from the RE-
SET# pin, all the previously protected sectors are
protected again. Figure 1 shows the algorithm, and
Figure 22 shows the timing diagrams, for this feature.
Figure 1. Temporary Sector Unprotect Operati on
Description Mode CE# OE# WE#
A18
to
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X VID XLXLL X 01h
Device ID:
Am29LV800B
(Top Boot Block)
Word L L H XXV
ID XLXLH22h DAh
Byte L L H X DAh
Device ID:
Am29LV800B
(Bottom Boot Block)
Word L L H XXV
ID XLXLH22h 5Bh
Byte L L H X 5Bh
Sector Protection V erification L L H SA X VID XLXHL X01h
(protected)
X00h
(unprotected)
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
14 Am29LV800B
Figure 2. In-System Sector Protect/
Sector Unprotect Algorithms
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Set up sector
address
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
First Write
Cycle = 60h?
Data = 01h?
Remove VID
from RESET#
Write reset
command
Sector Protect
complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode No
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Set up first sector
address
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
Data = 00h?
Last sector
verified?
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode
No All sectors
protected?
Yes
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
Set up
next sector
address
No
Yes
No
Yes
No
No
Yes
No
Sector Protect
Algorithm Sector Unprotect
Algorithm
First Write
Cycle = 60h?
Protect another
sector?
Reset
PLSCNT = 1
Am29LV800B 15
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC po wer-up and
pow er-down transitions , or from system noise.
Low V CC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
pow er-up and power-do wn. The command register and
all internal program/er ase circuits are disabled, and the
dev ice resets . Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical In hibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or W E# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up , the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates de vice op-
erations. Table 5 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the i mproper sequence resets
the device to reading arra y data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Charac teristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera-
tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.
The system
must
issue the reset command to re-en-
abl e the de vice f or reading arr ay data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” se ctio n , next.
See also “Requirements for Reading Arra y Data” in the
“Device Bus Operations” section fo r more infor mation.
The Read Operations table prov ides the read parame-
ters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command to the device resets t he de-
vice to reading array data. Address bits are don’t care
fo r this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the aut oselect mode , the re set command
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operat ion,
writing the reset command retur ns the device to read-
ing array data (also applies during Erase Sus pend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the man uf acturer and devices codes ,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements. This
method is an alternativ e to that shown in Table 4, which
16 Am29LV800B
is intended for PROM programmers and requires VID
on address bit A9.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect com-
mand. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns t he device code. A
read cycle containing a sector address (SA) and the
address 02h in word mode (or 04h in byte mode) re-
turns 01h if that sector is protected, or 00h if it is unpro-
tected. Refer to Tables 2 and 3 for valid sector
addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is
not
required to provide further controls or t im-
ings. The device automatically provides internally gen-
erated program pulses and verifies the programmed
cell margin. Table 5 shows the address and data re-
quirements for the by te program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in-
formation on these status bits .
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The program command sequence
should be reinit iated once t he de vice has reset to read-
ing array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempti ng to do so ma y halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. Howe ver , a succeeding read will sho w that the
data is still “0”. Only erase operations can conv ert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gra m b yt es or w ords to t he device f as ter t han us ing the
standard progr am command sequenc e. The un lock by-
pass command sequence is initiated b y first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The de-
vice then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the seco nd cycle contains the prog ram
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time . Tab le 5 shows the re quirements for the com-
mand sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don’t care for both cycles. The device then returns to
reading array data.
Figure 3 illustrates the algorithm for the program oper-
ation. See the Eras e/Program Operations table in “AC
Characteristics” for parameters, and to Figure 17 for
timing diagrams.
Am29LV800B 17
Note: See Table 5 for program command sequence.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six b us cy cle oper ation. The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles ar e then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Er ase algo-
rithm automatically preprogr ams a nd v e rifies the entire
memor y for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these oper ations. Tabl e 5 shows
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Not e that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data int eg rity.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these sta-
tus bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.
Figure 4 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 18 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 shows the address and data
requirements f or the sector eras e command sequence.
The device does
not
require the system to preprog ram
the memory prior to er ase. The Embedded Erase algo-
rithm automatically progr ams and verifies the s ector f or
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading t he sector erase buffer
ma y be done in any sequence , and the number of sec-
tors ma y be from one sector to al l sectors. The time be-
tween these additional cy cles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to
ensure all commands are accepted. The inte rrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 t o determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is v alid. All othe r commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has retur ned to
reading array data, to ensure data integrity.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
18 Am29LV800B
When the Embedded Erase algorithm is complete, the
dev ice returns to reading arra y data and addresses are
no longer latched. The system can determine the sta-
tus of the erase opera tion b y using DQ7, DQ6, DQ2, or
RY/BY#. Ref er to “Write Operation Status” for inf orma-
tion on these status bits.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section f or par amet ers , and to
Figure 18 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend c ommand allo ws the s ystem to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only dur ing the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and s uspends t he er ase oper at ion. Ad-
dresses are “don’t-cares” when writing the Erase Sus-
pend command.
When the Erase Suspend command is written during a
sector erase oper ation, the de vice requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected f or eras ure. (The de vice “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determ ine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
After an erase-suspended program operation is com-
plete, t he system can once again read arr ay data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more informa-
tion.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the s ector erase oper ati on. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Notes:
1. See Table 5 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 4. Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
Am29LV800B 19
Table 5. Am29LV800B Command Definitions
Legend:
X = Don’t care
RA = Address of the memory locat ion to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be v erified (in autoselect mode) or
erased. Address bits A18–A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and
command cycles.
5. Address bits A18–A11 are don’t cares for unlock and
command cycles, unless PA or SA required.
6. No unlock or comm and cycles required when reading array
data.
7. The Reset command is required to return to reading array
data when device is in the autos elect mode, or if DQ5 goes
high (while the device is providing status data).
8. The four th cycle of the autoselect com mand sequence is a
read cycle.
9. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
10. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
11. The Unlo ck Bypass Reset comma nd is requ ired to return to
reading array data when the device is in the unlock bypass
mode.
12. The system ma y read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
13. The Erase Resume command is valid only during the Erase
Suspend mode.
Command
Sequence
(Note 1)
Bus Cycles (Notes 2-5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Manufacturer ID Word 4555 AA 2AA 55 555 90 X00 01
Byte AAA 555 AAA
Device ID,
Top Boot Block Word 4555 AA 2AA 55 555 90 X01 22DA
Byte AAA 555 AAA X02 DA
Device ID,
Bottom Boot Block Word 4555 AA 2AA 55 555 90 X01 225B
Byte AAA 555 AAA X02 5B
Sector Pro tect Verify
(Note 9)
Word 4555 AA 2AA 55 555 90
(SA)
X02 XX00
XX01
Byte AAA 555 AAA (SA)
X04 00
01
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Unlock Bypass Word 3555 AA 2AA 55 555 20
Byte AAA 555 AAA
Unlock Bypass Program (Note 10) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 11) 2 XXX 90 XXX 00
Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Sus pend (Note 12) 1 XXX B0
Erase Resume (Note 13) 1 XXX 30
Cycles
Autoselect (Note 8)
20 Am29LV800B
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and R Y/BY# . Table 6 and the f ollo wing subsecti ons de-
scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
DQ7: Data# Polling
The Data# P olling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or com-
pleted, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. Th is DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read va lid status
information on DQ7. If a program address falls within a
protected sector, Data# P olling on DQ7 is acti ve f or ap-
proximately 1 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When t he Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous t o the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
After an er ase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active f or approximately 100 µs , the n the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid dat a at DQ7–
DQ0 on the
following
read cycles . This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted lo w. Figure 19, Data#
Polling Timings (Dur ing Embedded Algorithms), in the
“AC Characteristics” section illustrates this.
Table 6 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm.
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 5. Data# Polling Algorithm
Am29LV800B 21
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the outpu t is low (Busy ), the de vice is activ ely er asing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 shows the outputs for RY/BY#. Figures 13, 14,
17 and 18 sho ws RY/BY# f or read, reset, prog ram, and
erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Er ase algorithm is in prog ress or complete ,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read c ycles.) When the operation is
complete, DQ6 stops toggling.
After an er ase command sequence is written, if all sec-
tors selected f or er asing are protected , DQ6 toggles f or
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the de vice is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the s ystem can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Tab le 6 sho ws the out puts for Toggle Bit I on DQ6. Fig-
ure 6 shows the toggle bit algorithm. Figure 20 in the
“AC Char acteristics” section sho ws the t oggle bit timing
diagrams. Figure 21 shows the differences between
DQ2 and DQ6 in graphical for m. See also the subsec-
tion on “DQ2: Toggle Bit II” .
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is , the Embedded Er ase algo rithm is in progr ess),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode info rmation. Ref er t o Table 6 to compare output s
for DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchart
for m, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggl e Bit I” subsection.
Figure 20 shows the toggle bit timing diagram. Figure
21 shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the follo wing discussion. Whene v er
the system initially begins reading toggle bit status, it
must read DQ7–DQ0 at least twice in a row to determine
whether a toggle bit is toggling. Typically, the system
would note and store the value of the toggle bit after the
first read. After the second read, the system would com-
pare the new value of the toggle bit with the first. If the
toggle bit is not toggling , the device has completed the
program or erase operation. The system can read arra y
data on DQ7–DQ0 on the follo wing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
must write the reset command to return to reading
array data.
22 Am29LV800B
The remaining scenario is that the system initially de-
termines that the toggle bit is togglin g and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successiv e read cycles , de-
termining the stat us as described in the previous par a-
graph. Alternatively, it may choose to perform other
system tasks. In this case , the system must start at the
beginning of the algorithm when it re turns to determine
the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the prog ram or er ase cycle w as
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is pre viously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to deter mine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional
sectors are selected for erasure , the entire time-out also
applies after each additional sector erase command.
When the time-out is complete, DQ3 switches from “0” to
“1.” The system may ignore DQ3 if the system can
guarantee that the time between additional sector
erase commands will always be less than 50 µs. See
also the “Sector Er ase Command Sequence” section.
After the sector erase command sequence is written,
the system should re ad the s tatus on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence , and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands (other th an Er ase Su spend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the s ystem softw are should chec k the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 6 shows the outputs for DQ3.
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle? No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 6. Toggle Bit Algorithm
(Notes
1, 2)
(Note 1)
Am29LV800B 23
Table 6. Write Operation Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
Operation DQ7
(Note 2) DQ6 DQ5
(Note 1) DQ3 DQ2
(Note 2) RY/BY#
Standard
Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Erase
Suspend
Mode
Reading within Erase
Suspended Sector 1 No toggle 0 N/A Toggle 1
Reading within Non-Erase
Suspended Sector Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
24 Am29LV800B
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
Voltage wit h Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE#, and
RESET# (Note 2). . . . . . . . . . . .–0.5 V to +12.5 V
All other pins (Note 1) . . . . . –0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may undershoot VSS
to –2.0 V for periods of up to 20 ns. See Figure 7.
Maximum DC voltage o n input or I/O pin s is V CC +0.5 V.
During voltage transitions, input or I/O pins may overshoot
to VCC +2.0 V for periods up to 20 ns. See Figure 8.
2. Minimum DC input v oltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot VSS to –2.0 V for periods of up
to 20 ns. See Figure 7. Maximum DC input voltage on pin
A9 is +12.5 V w hich may overshoot to 14.0 V for perio ds
up to 20 ns.
3. No more tha n one outpu t may be sh or ted to ground at a
time. Duration of the shor t circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temper ature (TA) . . . . . . . . . . .0°C to +70°C
Industrial (I) De vices
Ambient Temper ature (TA) . . . . . . . . .–40°C to +85°C
Extended (E) Devices
Ambient Temper ature (TA) . . . . . . . .–55°C to +125°C
VCC Supply Voltages
VCC for regulated voltage r ange . . . . +3.0 V to +3.6 V
VCC for full voltage range . . . . . . . . . +2.7 V to +3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed
Figure 7. M aximum Negative Oversho ot
Waveform Figure 8. Maximum Positive Overshoot
Waveform
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
Am29LV800B 25
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
5. Not 100% tested.
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC,
VCC = VCC max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC,
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current
(Notes 1, 2)
CE# = VIL, OE# = VIH,
Byte Mode 5 MHz 7 12
mA
1 MHz 2 4
CE# = VIL, OE# = VIH,
Word Mode 5 MHz 7 12
1 MHz 2 4
ICC2 VCC Active Write Current
(Notes 2, 3, 5) CE# = VIL, OE# = VIH 15 30 mA
ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC±0.3 V 0.2 5 µA
ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 0.2 5 µA
ICC5 Automatic Sleep Mode
(Notes 2, 4) VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V 0.2 5 µA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC VCC + 0.3 V
VID Voltage for Autoselect and
Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 VCC V
VOH2 IOH = –100 µA, VCC = VCC min V
CC–0.4
VLKO Low VCC Lock-Out Voltage
(Note 4) 2.3 2.5 V
26 Am29LV800B
DC CHARACTERISTICS (Continued)
Zero Power Flash
20
15
10
5
00 500 1000 1500 2000 2500 3000 3500 4000
Supply Current in mA
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
8
2
0
12345
Frequency in MHz
Supply Current in mA
Note: T = 25
°
C
Figure 10. Typical ICC1 vs. Frequency
2.7 V
3.6 V
4
6
Am29LV800B 27
TEST CONDITIONS
Table 7. Test Specifications
KEY TO SWITCHING WAVEFORMS
2.7 kΩ
CL6.2 kΩ
3.3 V
Device
Under
Test
Figure 11. Test Setup
Note: Diodes are IN3064 or equivalent
Test Condition -70 -90,
-120 Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig cap aci tan ce) 30 100 pF
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V
Input timing measurement
reference levels 1.5 V
Output timing measurement
reference levels 1.5 V
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changi ng from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
3.0 V
0.0 V 1.5 V 1.5 V OutputMeasurement LevelInput
Figure 12. Input Waveforms and
Measurement Levels
28 Am29LV800B
AC CHARACTERISTICS
Read Operations
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 7 for test specifications.
Parameter
Description
Speed Opt ion s
JEDEC Std Test Setup -70 -90 -120 Unit
tAVAV tRC Read Cycle Time (Note 1) Min 70 90 120 ns
tAVQV tACC Address to Output Delay CE# = VIL
OE# = VIL Max 70 90 120 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 90 120 ns
tGLQV tOE Output Enable to Output Delay Max 30 35 50 ns
tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 25 30 30 ns
tGHQZ tDF Output Enable to Output High Z (Note 1) Max 25 30 30 ns
tOEH Output Enable
Hold Time (Note 1)
Read Min 0 ns
Toggle and
Data# Polling Min 10 ns
tAXQX tOH Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1) Min 0 ns
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output V alid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tOE
0 V
RY/BY#
RESET#
tDF
tOH
Figure 13. Read Operations Timings
Am29LV800B 29
AC CHARACTERISTICS
Hardware Reset (RESET#)
Note: Not 100% tested.
Parameter
Description All Speed OptionsJEDEC Std Test Setup Unit
tREADY RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note) Max 20 µs
tREADY RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH RESET# High Time Before Read (See Note) Min 50 ns
tRPD RESET# Low to Standby Mode Min 20 µs
tRB RY/BY# Recovery Time Min 0 ns
RESET#
RY/BY#
RY/BY#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE#, OE#
tRH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
tRB
Figure 14. RESET# Timings
30 Am29LV800B
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter Speed Option s
JEDEC Std Descriptio n -70 -90 -120 Unit
tELFL/tELFH CE# to BYTE# Switching Low or High Max 5 ns
tFLQZ BYTE# Switching Low to Output HIGH Z Max 25 30 30 ns
tFHQV BYTE# Switching High to Output Active Min 70 90 120 ns
DQ15
Output
Data Output
(DQ0–DQ7)
CE#
OE#
BYTE#
tELFL
DQ0–DQ14 Data Output
(DQ0–DQ14)
DQ15/A-1 Address
Input
tFLQZ
BYTE#
Switching
from word
to byte
mode
DQ15
Output
Data Output
(DQ0–DQ7)
BYTE#
tELFH
DQ0–DQ14 Data Outpu t
(DQ0–DQ14)
DQ15/A-1 Address
Input
tFHQV
BYTE#
Switching
from byte
to word
mode
Figure 15. BYTE# Timings for Read Operations
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 16. BYTE# Timings for Write Operations
CE#
WE#
BYTE#
The falling edge of the last WE# signal
tHOLD (tAH)
tSET
(tAS)
Am29LV800B 31
AC CHARACTERISTICS
Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter Speed Options
JEDEC Std Descript ion -70 -90 -12 0 U nit
tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tWLAX tAH Address Hold Time Min 45 45 50 ns
tDVWH tDS Data Setup Tim e Min 35 45 50 ns
tWHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHWL tGHWL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 35 35 50 ns
tWHWL tWPH Wr ite Pulse Wid th Hig h Min 30 ns
tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 9 µs
Word Typ 11
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec
tVCS VCC Setup Time (Note 1) Min 50 µs
tRB Recovery Time from RY/BY# Min 0 ns
tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns
32 Am29LV800B
AC CHARACTERISTICS
OE#
WE#
CE#
V
CC
Data
Addresses
t
DS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h PA PA
Read Status Data (last two cycles)
A0h
t
CS
Status D
OUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
t
BUSY
t
CH
PA
Notes:
1. PA = program addre ss, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 17. Program Operation Timings
Am29LV800B 33
AC CHARACTERISTICS
OE#
CE#
Addresses
V
CC
WE#
Data
2AAh SA
t
AH
t
WP
t
WC
t
AS
t
WPH
555h for chip erase
10 for Chip Erase
30h
t
DS
t
VCS
t
CS
t
DH
55h
t
CH
In
Progress Complete
t
WHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
RY/BY#
t
RB
t
BUSY
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Wr ite Op eratio n Statu s”).
2. Illustration shows device in word mode.
Figure 18. Ch ip/Sector Erase Operation Timings
34 Am29LV800B
AC CHARACTERISTICS
WE#
CE#
OE#
High
Z
tOE
High
Z
DQ7
DQ0–DQ6
RY/BY#
tBUSY
Complement True
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
tACC
tRC
Note: VA = Valid address. Illus tration shows first statu s cycle after com mand sequenc e, last sta tus read cycle, and array dat
a
read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
WE#
CE#
OE#
High Z
t
OE
DQ6/DQ2
RY/BY#
t
BUSY
Addresses VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA VA
t
ACC
t
RC
Valid DataValid StatusValid Status
(first read) (second read) (stops toggling)
Valid Status
VA
Note: V A = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status rea
d
cycle, and array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
Am29LV800B 35
AC CHARACTERISTICS
Temporary Sector Unprotect
Note: Not 100% tested.
Parameter
All Speed OptionsJEDEC Std Description Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tRSP RESET# Setup Time for Temporary Sector
Unprotect Min 4 µs
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within a
n
erase-suspended sector.
Figure 21. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Pro gra m
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
RESET#
tVIDR
12 V
0 or 3 V
CE#
WE#
RY/BY#
tVIDR
tRSP
Program or Erase Command Sequence
0 or 3 V
Figure 22. Temporary Sector Unprotect
Timing Diagram
36 Am29LV800B
AC CHARACTERISTICS
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
RESET#
SA, A6,
A1, A0
Data
CE#
WE#
OE#
60h 60h 40h
Valid* Valid* Valid*
Status
Sector Protect/Unprotect Verify
V
ID
V
IH
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23 . S ec t or Protec t / U n p rot e c t
Timing Diagram
Am29LV800B 37
AC CHARACTERISTICS
Alternate CE# Controlled
Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter Speed Options
JEDEC Std Description -70 -90 -120 Unit
tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns
tAVEL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 45 45 50 ns
tDVEH tDS Data Setup Time Min 35 45 50 ns
tEHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHEL tGHEL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 35 35 50 ns
tEHEL tCPH CE# Pulse Width High Min 30 ns
tWHWH1 tWHWH1 Programming Operation
(Note 2) Byte Typ 9 µs
Word Typ 11
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec
38 Am29LV800B
AC CHARACTERISTICS
tGHEL
tWS
OE#
CE#
WE#
RESET#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7# D
OUT
tWC tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tRH
tWHWH1 or 2
RY/BY#
tWH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase PA for program
SA for sector erase
555 for chip erase
tBUSY
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the
device.
2. Figure indicates the last two bus cycles of command sequence.
3. Word mode address used as an example.
Figure 24. Alternate CE# Controlled Write Operation Timings
Am29LV800B 39
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typic al chip programming time is c onsiderably less than th e maximum chip p rogramming ti me listed , since m ost bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level over head is the tim e required to execute the two- or four-bus-cycle seq uence for the program com mand. See
Table 5 for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 0.7 15 s Excludes 00h programming
prior to erasure
Chip Erase Time 14 s
Byte Programming Time 9 300 µs
Excludes system level
overhead (Note 5)
Word Programming Time 11 360 µs
Chip Programming Time
(Note 3)
Byte Mode 9 27 s
Word Mode 5.8 17 s
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE #, and RESE T#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF
Parameter Test Conditions Min Unit
Minimum Pattern Data Retention Time 150°C 10 Years
125°C 20 Years
40 Am29LV800B
PH YS ICAL DIMENSIONS *
TS 048—48-Pin Standard TSOP
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Dwg rev AA; 10/99
Am29LV800B 41
PH YS ICAL DIMENSIONS
TSR048—48-Pin Reverse TSOP
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Dwg rev AA; 10/99
42 Am29LV800B
PH YS ICAL DIMENSIONS
FBB 048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6x9mm
Dwg rev AF; 10/99
43 Am29LV800B
PH YS ICAL DIMENSIONS
SO 044—44-Pin Small Outline Package
Dwg rev AC; 10/99
Am29LV800B 44
REVISION SUMMARY
Revision E (January 1998)
Distinctive Characteristics
Changed typical read and program/erase current
specifications.
Device now has a guaranteed m inimum endurance of
1,000,000 write cycles.
In-System Sector Protect/Unprotect Algorithm
Figure
Corrected A6 to 0, Changed wait specification to 150 µs
on sector protect and 15 ms on sector unprotect.
DC Characteristics
Changed typical read and program/erase current
specifications.
AC Characteristics
Alternate CE# Controlled Erase/Program Operations:
Changed tCP to 35 ns f or 70R, 80, and 90 speed options.
Erase and Programming Performance
Device now has a guaranteed m inimum endurance of
1,000,000 write cycles.
Physi cal Dimensions
Corrected dimensions for package length and width in
FBGA illustration (standalone data sheet version).
Revision E+1 (March 1998)
In-System Sector Protect/Unprotect Algorithms
Figure
In the sector protect algorithm, added a “Reset
PLSCNT=1” box in the pa th from “Pr otect ano ther sec-
tor?” back to setting up the next sector address.
DC Characteristics
Changed Note 1 to indicate that OE# is at VIH for the
listed current.
AC Characteristics
Erase/Program Operations; Alternate CE# Controlled
Erase/Program Operations:
Corrected the notes
reference for tWHWH1 and tWHWH2. These parameters
are 100% test ed. Corrected the note ref erence f or t VCS.
This parameter is not 100% tested.
Temporary Sector Unprotect Table
Added note reference for tVIDR. This parameter is not
100% tested.
Figure 23, Sector Protect/Unprotect Timing
Diagram
A valid address is not required for the first write cycle;
only the data 60h.
Erase and Programming Performance
In Note 2, the worst case endurance is now 1 million cycles.
Revision F (January 1999)
Global
Changed references for process technology to “0.32
µm.”
Replaced the 70R ns regulated voltage speed option
with 70 ns full voltage speed option.
Distinctive Characteri stics
Added 20-year dat a retent ion bullet.
Connection Diagrams
Reverse TSOP :
Modified markings.
FBGA
: Replaced Bump side (bottom) view with top
view.
Ordering Info rmation
Valid Combinations for FBGA Packages
: New Table.
DC Characteristics—CMOS Compatible
ICC1, ICC2, I CC3, I CC4, ICC5
: Added Note 2 “Maximum
ICC specifications are tested with VCC = VCCmax”.
ICC3, ICC4
: Deleted VCC = VCCmax.
Physi cal Dimensions
Changed pack age drawing to FBB048.
Revision F+1 (February 1999)
Physi cal Dimensions
Corrected ball grid layout on FBB048 drawing. Added
“048” to drawing title.
Revision F+2 (February 1999)
Distinctive Characteri stics, Operating Ranges
Corrected to indicate that the VCC voltage range for all
devices is 2.7–3.6 V.
Revision F+3 (July 2, 1999)
Global
Added references to availability of device in Known
Good Die (KGD) form.
Revision F+4 (July 26, 1999)
Global
Added the 70R speed option, which is available in the
extended temperature range.
Ordering Info rmation
Deleted the extended temperature range from the
FBGA valid combinations.
45 Am29LV800B
Revision G (November 10, 1999)
Ordering Information
Deleted commercial and industrial temper ature r anges
from the 70R speed option.
AC Characteristics—Figure 17. Program
Operations Timing and Figure 18. Ch ip/Sector
Erase Operations
Deleted tGHWL and changed OE# waveform to star t at
high.
Physi cal Dimensions
Replaced figures with more detailed illustrati ons.
Revision G+1 (July 7, 2000)
Ordering Info rmation
Inserted dashes into ordering part numbers. Deleted
burn-in option.
Revision G+2 (August 14, 2000)
Global
Deleted 70R and 80 ns speed options and burn-in
option.
Trademarks
Copyright © 2000 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
