ADS1293
SNAS602C –FEBRUARY 2013–REVISED DECEMBER 2014
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–CH2ERR: See above, but for channel 2.
–CH1ERR: See above, but for channel 1.
–LEADOFF: This error flag is raised when one of the OUT_LOD bits in the ERROR_LOD register is a
logic 1.
–BATLOW: This error flag is raised when the supply voltage of the ADS1293 drops below 2.7 V. This can
be used as a warning sign to the microcontroller that the state of charge of a supply battery is almost
below levels of operation. The ADS1293 is designed to function within specification for supplies larger
than 2.7 V but communication the digital communication interface will work down to 2.4 V so that this
alarm condition can still be communicated to the microcontroller. A low battery error propagates to the
ALARMB pin unless the MASK_BATLOW bit in the MASK_ERR register is set to 1. System alarms are
filtered by the digital circuitry (see Error Filtering), and for this reason, the master clock must be active in
order to capture an alarm. There is also a battery voltage monitoring feature that can be used to monitor
the state of charge of the battery during normal operation described in Battery Monitoring.
–RLDRAIL: This error flag is raised when the output voltage of the right-leg drive amplifier is approaching
the supply rails. The flag goes high when the output voltage of the common-mode detector is 200 mV
away from either supply rail. This condition would occur if the common-mode on the patient’s body is far
away from the target value and as a result the right-leg drive amplifier needs to deliver a lot of charge to
the patient’s body to restore the common-mode voltage. In this scenario, the common-mode may still be
inside the range of the instrumentation amplifier and the ECG signal may still be accurately acquired.
–CMOR: The CMOR error flag is raised when the output voltage of the common-mode detector is 750 mV
away from either supply rail. In this case, the common-mode voltage detected on the patient’s body is
outside of the input CMVR where the instrumentation amplifier can process the full differential input signal
(see Instrumentation Amplifier (INA)). When this flag is raised, the ECG signal accuracy may be lost.
3. ERROR_RANGE1, ERROR_RANGE2, ERROR_RANGE3: These registers contain the out-of-range error
signals of the AFEs in the three channels. The flags in these registers are described in Instrumentation
Amplifier Fault Detection and in Sigma-Delta Modulator Fault Detection.
4. ERROR_SYNC: This register contains flags that indicate certain synchronization errors have been detected.
These errors have been described in Synchronization Errors.
5. ERROR_MISC: This register contains status flags for common-mode out-of-range, right-leg drive near rail
and low battery errors.
8.3.25 Error Filtering
The alarms that are generated by the analog circuitry inside the ADS1293 are filtered by digital logic. Alarms will
only be accepted if they are active for a number of consecutive digital clock cycles, which toggle on the falling
edge of the 409.6-kHz oscillator clock. The number of digital clock cycles that an alarm will have to be active
before it is accepted is programmable between 1 and 16 counts using the ALARM_FILTER register. This register
contains two separate filter parameters. The 4 LSBs in this register program the filtering of the lead-off detect
error bits. The 4 MSBs program the filtering of the instrumentation amplifier signal out-of-range errors, the sigma-
delta input over range errors, and the CMOR, RLDRAIL and BATLOW errors.
8.3.26 ALARMB Pin and Error Masking
The ADS1293 has an ALARMB output pin. This open-drain output will go low when a new alarm condition occurs
in the ERROR_STATUS register. The ALARMB pin can be used as an interrupt signal to a microcontroller to
warn about error conditions that can potentially corrupt the data that is being collected so that the microcontroller
can take appropriate preventive action. The functionality of the ALARMB pin is flexible and programmable using
the MASK_ERR register. This register allows masking some of the errors in the ERROR_STATUS register so
that certain alarm events will not trigger a high to low transition on the ALARMB pin.
8.3.27 Error Register Automatic Clearing Description
All error bits in the registers 0x18 through 0x1E are latched in a high state when an error occurs and will only
return to zero after being read. The error bits will remember an error until the user reads the error. The sign bits
in the CH1ERR, CH2ERR and CHR3ERR registers are latched on low to high transition of the DIF_HIGH
transitions in the corresponding registers. In this way, when the differential signal goes out-of-range, the sign of
the signal can also be detected when the alarm register is read. Upon read, the error bits will be cleared. If the
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