July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Am41DL16x4D
Data Sheet
Publication Number 25562 Revision AAmendment 0 Issue Date October 24, 2001
PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The information
is int ended to help y ou evaluate thi s product. AMD r eserves the r ight to chan ge or discontin ue work on this pro posed
produ ct without notice.
Publication# 25562 Rev: AAmendment/0
Is su e Date: October 24, 2001
Refer to AMD’s Website (www.amd.com) for the latest informa tion.
Am41DL16x4D
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous
Operati on Flash Memory and 4 Mbit (512 K x 8-Bit/ 256 K x 16-Bit) Stat ic RAM
DISTINCTI VE CHARACTERISTICS
MCP Features
■Powe r su pply voltage of 2.7 to 3.3 volt
■High performance
— Access time as fast as 70 ns
■Package
— 69-Ball FBG A
■Oper at in g Te mpe ra tu r e
— –40°C to +85°C
Flash Memory Features
ARCHITECTURAL ADVANTAGES
■Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between re ad and write operat ions
■Secured Silicon (SecSi) Sector: Extra 64 KB yte sector
—Factory locked and identifiab le: 16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect functio n.
—Customer lockable: Can be read, programmed, or erased
just like other sectors. Once locked, data cannot be changed
■Zero Power Operation
— Sophisticat ed power man ageme nt circuits redu ce power
consumed during inacti ve periods to nearly zero
■Top or bott om boot block
■Manufactured on 0.23 µm process technology
■Compatible with JEDEC standards
—Pinout and software compatible with single-power-supply
flash standard
PERFORMANCE CHARACTERISTICS
■High performance
—70 ns access time
—Program time: 4 µs/word typical utilizing Accelerate function
■Ultra low power consumption (typical values)
—2 mA active read current at 1 MHz
—10 mA active read current at 5 MHz
—200 nA in standby or automatic sleep mode
■Minimum 1 million write cycles guaranteed per sector
■20 Year dat a re te nt io n at 12 5 °C
—Reliable operat ion for the life of the system
SOFTWARE FEATU R ES
■Da ta Ma na geme n t Softw ar e (D M S)
—AMD-supplied software manages data programming and
erasing, enabling EEPROM emulation
—Eases sector erase limitations
■Sup ports Common Flash Me mory Interf ace (CFI)
■Erase Suspend/Erase Resume
—Suspends erase operations to allow programming in same
bank
■Data# Polling and Toggle Bits
—Provides a software method of detecti ng the status of
program or erase cycles
■Unlock Bypass Program command
—Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
■Any combination of sectors can be erased
■Re ad y/Bu s y# ou tp u t (RY/BY #)
—Hardware method for detecting program or erase cycle
completion
■Hardware reset pin (RESET#)
—Hardware method of resetting the internal state machine to
reading array data
■WP#/ACC input pin
—Write pro tec t (WP# ) func ti on all ows p rot ecti on of two o ute rmost
boot sect or s, reg ard less of s ec tor pr ote ct st atu s
—Acceleration (ACC) function accelerates program timing
■Sector protection
—Hardware method of locking a sector, either in-system or
using programm ing equi pme nt, to prevent any program or
erase operat ion within that sector
—Temporary Sector Unprotect allows changing data in
protected sectors in-system
SRAM Features
■Power dissipation
—Operating: 22 mA maximum
—Stand by: 10 µA maximum
■CE1# s an d C E2s Ch ip Sele ct
■Power down features using CE1#s and CE2s
■Data retention supply voltage: 1.5 to 3.3 volt
■Byte data control: LB#s (DQ0–DQ7), UB#s (DQ8–DQ15)
2 Am41DL16x4D
PRELIMINARY
GENERAL DESCRI PTION
Am29 DL16x D Feat ur es
Th e Am 29DL16xD family is a 16 megabit, 3 .0 volt-only
flash memory device, organized as 1,048,576 words of
16 bi ts or 2, 097, 152 by tes of 8 bi ts e ac h. Wo rd mo de
data appears on DQ15–DQ0; byte mode data ap-
pears on DQ7–DQ0. The device is designed to be
programmed in-system with the standard 3.0 volt VCC
supply, and can also be programmed in standard
EP RO M prog ra mm ers .
The device is available with access times of 70 ns or
85 ns. The device is offered in a 69-ball FBGA pack-
age. Standard control pins—chip enab le (CE #f), writ e
enable (WE#), and output enable (OE#)—cont rol nor-
mal read and write operations, and avoid bus
con ten ti on iss ues.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally
gene r ate d a nd regu la ted vo lt age s ar e p rov id ed for th e
pro gram and er ase ope r ati ons.
Simultaneous Read/W rite Operations with
Zero Latency
The Simulta neous Rea d/Write archit ecture provides
simultaneous operation by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and
si multa neo us ly re ad from the oth er b an k, with ze r o la-
tency. This releases the system from waiting for the
completion of program or erase operations.
The Am29DL16xD devices uses multiple bank archi-
tectures to provide flexibility for diffe rent applications.
Four devices are available with the following bank
sizes:
The S ecured Silicon ( SecS i) Sector i s an extra 64
Kb it sector cap able of b eing pe rmanently lock ed by
AMD or cu stomers. The SecSi Secto r Indicator Bit
(DQ7) is perma nently set to a 1 if the part is factory
locked, and set to a 0 if customer lockable. This
way, customer lockable parts can neve r be used to re-
place a factory locked part.
Factory lo cked parts provide several options . The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number). Customer Lockable
parts may utilize the SecSi Sector as bonus space,
reading and writing like any other flash sector, or may
permanently lock their own code there.
DMS (D ata Managemen t Software) allows systems
to eas ily tak e adva ntage of the ad van ced ar chitec ture
of the simultaneous read/write product line by allowing
removal of EEPR OM devices. DMS will also allow the
system softwar e to be simplified , as it will perform al l
functions nece ssary to modify data in file structur es,
as opposed to single-byte modifications. To write or
update a particular piece of data ( a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
wher e the up date d data is lo cate d in the sys tem . This
is an advantage compared to systems where
user-written s oftwar e must keep track of the old data
location, statu s, logical to ph ysical tr anslati on of the
data on to the Flas h memory device (or mem ory de-
vices), an d m ore. Using DMS, user-written software
does not need to interface with the F las h memory di-
rectly. Instead, the us er's s oftw are ac c ess es the Flash
memor y by c alli ng one of o nl y si x f uncti on s. AM D pro -
vides this software to simplify system design and
software integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device sta-
tus bits: RY/BY# pin, DQ7 (Data# Polling) and
DQ6/ DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to reading array data.
The se ctor er ase archit ecture allows memory sec-
tors to be er ased and reprog ram med withou t affecti ng
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures inclu de a low
VCC detector th at autom atically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via
programming equipment.
The device offers two p ower-saving features. When
addr esses hav e been sta ble for a sp ecifie d amou nt of
time, the d evice enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly re-
duced in both modes.
Devi ce Bank 1 Bank 2
DL161 0.5 Mb 15.5 Mb
DL162 2 Mb 14 Mb
DL163 4 Mb 12 Mb
DL164 8 M b 8 M b
Am41DL16x4D 3
PRELIMINARY
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions for FBGA Package ....................7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Tabl e 1. De vi ce Bus O perations— Fl ash Wo rd Mod e, C I O f = V IH;
SRAM Word Mode, CIOs = VCC ..................................................... 11
Tabl e 2. De vi ce Bus O perations— Fl ash Wo rd Mod e, C I O f = V IH;
SRAM Byte Mode, CIOs = VSS ......................................................12
Tabl e 3. De vi ce Bus O peratio ns—Fl ash Byt e M ode, CI O f = V SS;
SRA M W or d M ode, CIO s = VCC .....................................................13
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = VIL; SRAM
Byte Mod e , CIOs = VSS ..................................................................14
Word/Byte Configuration ....................................................... 15
Requirements for Reading Array Data ...................................15
Writing Commands/Command Sequences ............................15
Accelerated Program Operation ..........................................15
Autoselect Functions ...........................................................15
Simultaneous Read/Write Operations with Zero L atency .......15
Standby Mode ........................................................................ 16
Automatic Sleep Mode ........... ...... ....................... ...................16
RESET#: Hardware Reset Pin ...............................................16
Output Disable Mode ..............................................................16
Table 5. Device Bank Division ........................................................16
Table 6. Sector Addresses for Top Boot Sector Devices ............... 17
Table 7. SecSi Sector Addresses for Top Boot Devices ................17
Table 8. Sector Addresses for Bottom Boot Sector Devices ...........18
Tabl e 9. SecSi Addresses fo r Bottom Boot Devices ..................18
Autoselect Mode .....................................................................19
Tabl e 10. Top Boot Sector/Sector Bl ock Addr esses fo r Pro t ection/ U n-
protection ........................................................................................19
Tabl e 11. B ottom Bo ot Sector/Se ct or Block Ad dresse s
for Protection/Unprotection .............................................................19
Write Protect (WP#) ................................................................19
Temporary Sector/Sector Block Unprotect .............................20
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figu re 2. In-System Sector/ S ector Bl ock Pro te ct and Unprotec t Alg o-
rithms .............................................................................................. 21
SecSi (Secured Silicon) Sector Flash Memory Region ..........22
Factory Locked: SecSi Sector Programmed and Protected At
the Factory ..........................................................................22
Customer Lockable: SecSi Sector NOT Programmed or Pro-
tected At the Factory ...........................................................22
Hardware Data Protection ......................................................22
Low V CC Write Inhibit ...........................................................22
Write Pulse “Glitch” Protection ............................................23
Logical Inhibit ......................................................................23
Power-Up Write Inhibit .........................................................23
Common Flash Memory Interface (CFI) . . . . . . .23
Table 12. CFI Query Id entification String........................................ 23
System Interface String................................................................... 24
Table 14. Device Geometry Definition............................................ 24
Table 15. Primary Vendor-Specific Extended Query...................... 25
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 26
Reading Array Data ................................................................26
Reset Command .....................................................................26
Autoselect Command Sequence ............................................26
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..27
Byte/Word Program Command Sequence .............................27
Unlock Bypass Command Sequence ..................................27
Figure 3. Program Operation ......................................................... 28
Chip Erase Command Sequence ...........................................28
Sector Erase Command Sequence ........................................28
Erase Suspend/Erase Resume Commands ...........................29
Figure 4. Erase Operation.............................................................. 29
Table 16. Command Definitions (Flash Word Mode)...................... 30
Table 17. Autoselect Device IDs (Wo rd Mode) .............................. 3 0
Table 18. Command Definitions (Flash Byte Mode)....................... 31
Table 19. Autoselect Device IDs (Byte Mode) ...............................31
Write Operation Status . . . . . . . . . . . . . . . . . . . . 32
DQ7: Data# Polling .......... ........................................ ...............3 2
Figure 5. Data# Polling Algorithm .................................................. 32
RY/BY#: Ready/Busy# ............................................................33
DQ6: Toggle Bit I ....................................................................33
Figure 6. Toggle Bit Algorithm........................................................ 33
DQ2: Toggle Bit II ...................................................................34
Reading Toggle Bits DQ6/DQ2 ...............................................34
DQ5: Exceeded Timing Limits ................................................34
DQ3: Sector Erase Timer .......................................................34
Table 20. Write Operation Status ................................................... 3 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 36
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 36
Industrial (I) Devices ............................................................36
VCCf/VCCs Supply Voltage ...................................................36
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
CMOS Comp ati ble ................................................... ...............3 7
SRAM DC and Operating Characteristics . . . . . 38
Zero-Power Flash .................................................................39
Fi gu r e 9. ICC1 Curr ent v s. Time (S howi ng Activ e and Auto mati c Sle ep
Currents)........................................................................................ 39
Figure 10. Typical ICC1 vs. Frequency............................................ 3 9
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 11. Test Setup.................................................................... 40
Table 21. Test Specifications ......................................................... 40
Key To Switching Waveforms . . . . . . . . . . . . . . . 40
Figure 12. Input Waveforms and Measurement Levels................. 40
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
SRAM CE#s Timing ................................................................41
Figure 13. Timing Diagram for Alternating Between
SRAM to Flash............................................................................... 41
Flash Read-Only Operations .................................................42
Figure 14. Read Operation Timings............................................... 42
Hardware Reset (RESET#) ....................................................43
Figure 15. Reset Timings..... ................................................. ......... 43
Flash Word/Byte Configuration (CIOf) ....................................44
Figure 16. CIOf Timings for Read Operations................................ 44
Figure 17. CIOf Timings for Write Operations................................ 44
Flash Erase and Program Operations ....................................45
Figure 18. Program Operation Timings.......................................... 4 6
Figure 19. Accelerated Program Timing Diagram.......................... 46
Figure 20. Chip/Sector Erase Operation Timings.......................... 47
Figure 21. Back-to-back Read/Write Cycle Timings...................... 48
4 Am41DL16x4D
PRELIMINARY
Figu re 22. Data# P ol l ing Ti m i ngs (During Embedded Algorithms) .. 48
Figure 23. Toggle Bit Timings (During Embedded Algorith ms )....... 49
Figure 24. DQ2 vs. DQ6.................................................................. 49
Temporary Sector/Sector Block Unprotect .............................50
Figu re 25. Te mpor ar y Secto r/ Sector Bl ock Unprote ct
Timing Diagram..................... ........................... ............................... 50
Figu re 26. Se ctor/Sector Bl ock Protect an d U nprotect
Timing Diagram..................... ........................... ............................... 51
Alternate CE#f Controlled Erase and Program Operations ....52
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op-
eratio n Timing s....... .... .......................................... .......................... . 53
SRAM Read Cycle ..................................................................54
Figu re 28. SR AM R ead Cyc le —Address Controlled....................... 54
Figure 29. SRAM Read Cycle......................................................... 55
SRAM Write Cycle ..................................................................56
Figu re 30. SR AM W rite Cyc le—WE# Cont rol................................ . 56
Figure 31. SRAM Write Cycle—CE1#s Control............................. 57
Figure 32. SRAM Write Cycle—UB#s and LB#s Control............... 58
Flash Erase And Programming Performance . 59
Flash Latchup Characteristics. . . . . . . . . . . . . . . 59
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 59
FLASH Data Retention . . . . . . . . . . . . . . . . . . . . . 59
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 60
Figure 33. CE1#s Controlled Data Retention Mode....................... 6 0
Figure 34. CE2s Controlled Data Retentio n Mode......................... 6 0
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 61
FLA069—69-Ball Fine-Pitch Grid Array 8 x 11 mm ...............61
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 62
Revision A (October 24, 2001) ...............................................62
Am41DL16x4D 5
PRELIMINARY
PRODUCT SEL ECTOR GUIDE
MCP BLOCK DI AGRAM
Part Number Am41DL16x4D
Speed Options Standar d Voltage Range:
VCC = 2.7–3.3 V Flash Memory SRAM
70 85 70 85
Max Access Time (n s) 70 85 70 85
CE# Access (n s) 70 85 70 85
OE# Access (ns) 30 35 35 45
VSS/VSSQ
VCCs/VCCQ
RESET#
WE#
CE#f
OE#
CE1#s
VSS
VCCf
RY/BY#
LB#s
UB#s
CIOf
WP#/ACC
CE2s
SA
CIOs
4 Mbit
Static RAM
16 Mbit
Flash Memory DQ0 to DQ15/A
–
1
DQ0 to DQ15/A
–
1
DQ0 to DQ15/A
–
1
A0 to A19
A0 to A19
A0 to A19
A
–
1
A0 to A17
6 Am41DL16x4D
PRELIMINARY
FLASH MEMORY BL OCK DIAGRAM
VCC
VSS
Upper Bank Address
A19–A0
RESET#
WE#
CE#
CIOf
DQ15–DQ0
WP#/ACC
STATE
CONTROL
&
COMMAND
REGISTER
RY/BY#
Upper Bank
X-Decoder
Y-Decoder
Latches and Control Logic
OE# CIOf
DQ15–DQ0
Lower Bank
Y-Decoder
X-Decoder
Latches and
Control Logic
Lower Bank Address
Status
Control
A19–A0
A19–A0
A19–A0A19–A0
DQ15–DQ0 DQ15–DQ0
Am41DL16x4D 7
PRELIMINARY
CONNECTION DIAGRAM
Special Handling Instructions for FBGA
Package
Spec ial handli ng is requir ed for F lash Memory prod-
ucts in FBGA packages.
Flash mem ory devices in FBGA packages may be
damaged if ex posed to ultrasonic c leaning methods.
The package and/or data integrity may be compro-
mised if the package body is exposed to temperatures
above 150°C for prolong ed per iod s of tim e.
A7
A3
A2
NC
NC
NC
NC
NC
DQ8 DQ14
CE1#s
LB#s WP#/ACC WE# A8 A11
B3B1 B4 B5 B6 B7 B8
A6 UB#s RESET# CE2s A19 A12 A15
C2 C3 C4 C5 C6 C7 C8 C9
A5 A18 RY/BY# NC A9 A13 NC
D2 D3 D4 D5 D6 D7 D8 D9
A1 A4 A17 A10 A14 NC
E1 E10
E2 E3 E4 E7 E8 E9
VSS DQ1A0 DQ6 SA A16
F1 F10F3 F4F2 F7 F8 F9
CE#f
DQ0
OE# DQ9 DQ3 DQ4 DQ13 DQ15/A
-
1 CIOf
G2 G3 G4 G5 G6 G7 G8 G9
DQ10 VCCfVCCsDQ12 DQ7 VSS
H2 H3 H4 H5 H6 H7 H8 H9
DQ2 DQ11 CIOs DQ5
J3 J8
J4 J5 J6 J7
NC NC NC
A1 A5 A6
NC
A10
NC NC NC
K1 K5 K6
NC
K10
SRAM only
Shared
Flash only
69-Ball FBGA
Top Vie w
8 Am41DL16x4D
PRELIMINARY
PIN DESCRIPTION
A17–A0 = 18 Address Inputs (Common)
A–1, A19–A18 = 3 Addr es s Input s (Fl as h)
SA = Highest Order Address Input
(SRAM) Byte mode
DQ15–DQ0 = 16 Data Inp uts /Out put s (C om mon )
CE#f = Chip Enable (Flash)
CE #s = Chip Enable (SRAM)
OE# = Output Enable (Common)
WE# = Write Enable (Common)
RY/BY# = Ready/Busy Output
UB #s = Upper Byte Co ntrol (SRAM)
LB#s = Lower Byte Control (SRAM)
CIO f = I/O Con figur at io n (Flas h)
CIOf = VIH = Word mode (x16),
CIOf = VIL = Byte mode (x8)
CIO s = I/O Con fig urat io n (SRA M)
CIOs = VIH = Word mode (x16),
CIOs = VIL = Byte mode (x8)
RESET# = Hardware Reset Pin, Active Low
WP#/ACC = Hardware Write Protect/
Acceleration Pin (Flash)
VCCf = Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
VCCs = SRAM Power Supply
VSS = Device Ground (Common)
NC = Pin Not Connected Internally
LOGIC SYMBOL
18
16 or 8
DQ15–DQ0
A0–A17
CE#f
OE#
WE#
RESET#
UB#s
RY/BY#
WP#/ACC
SA
A–1, A18–A19
LB#s
CIOf
CIOs
CE1#s
CE2s
Am41DL16x4D 9
PRELIMINARY
ORDERING INFORMATION
The order number (Valid Combination) is formed by the follow ing:
Val id Co mb inations
V alid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific val id combinat ions and to ch eck on newly re-
leased combinations.
Am41DL16x 4 D T 70 I T
TAPE AND REEL
T = 7 inch es
S=13 inches
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
FLASH SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T=Top Sector
B = Bottom Sector
FLASH PROCESS TECHNOLOGY
D= CS49S
SRAM DEVICE DENSITY
4= 4 Mbits
AMD DEV ICE NUMBER/DESCRIPTION
Am41DL16x4D
Stacked Multi-Chip Packag e (MCP) Flash Memory and SRAM
Am29DL16xD 16 Megabit (1 M x 16-Bit) CMOS 3.0 Volt-only, Simultan eous Operati on F lash
Memory and 4 Mbit (512 K x 8-Bit/ 256 K x 16-Bit) Static RAM
Valid Combinations
Order Number Package Marking
Am41DL1614DT70I
Am41DL1614DB70I
T, S
M410000000
M410000001
Am41DL1614DT85I
Am41DL1614DB85I M410000002
M410000003
Am41DL1624DT70I
Am41DL1624DB70I M410000004
M410000005
Am41DL1624DT85I
Am41DL1624DB85I M410000006
M410000007
Am41DL1634DT70I
Am41DL1634DB70I M410000008
M410000009
Am41DL1634DT85I
Am41DL1634DB85I M41000000A
M41000000B
Am41DL1644DT70I
Am41DL1644DB70I M41000000C
M41000000D
Am41DL1644DT85I
Am41DL1644DB85I M41000000E
M41000000F
10 Am41DL16x4D
PRELIMINARY
DEVICE BUS OPERAT I ONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the
commands, along with the address and data informa-
tion nee de d to ex ecu t e the comm an d. T he contents of
the r egister serve as inputs to the in ternal s tate ma-
chine. The state machine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs and control levels they require, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Am41DL16x4D 11
PRELIMINARY
Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH; SRAM Word Mode, CIOs = VCC
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5– 12.5 V, VHH = 9.0 ± 0.5 V, X = D on’t Care , SA = SRAM Add ress
Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column ar e inhibited.
2. Do not apply CE#f = VIL, CE1 #s = VIL and CE2s = V IH at the same time.
3. Don’t ca re or open LB#s or UB #s.
4. If WP#/A CC = VIL , the boot sector s w ill be protected. I f WP#/ ACC = VIH the boot sectors p rotec tion will be re mov ed.
If WP#/ACC = VACC (9V ), the pr ogr am time wi ll be reduced by 40%.
5. The sector pr otect and s ector un protect f unctio ns may als o be impl emented vi a programmi ng equipment . See the “The au tosel ect
mode pr ovides m anufac t ure r and devi ce i dentif i cati on, and s ector pr otec t ion v eri fic ation, thr ough identifier codes output on
DQ7–DQ0. T he autos elec t co des can be ac cesse d in- sy stem thro ugh t he c ommand reg ister. Refer to t he Autos ele ct Com mand
Sequenc e se ctio n f or more infor mation.Sector/S ector B lock Prot ec tion and Unprotection” sect ion .
6. If WP#/A CC = VIL, the two out er most b oot sec tor s remai n pr otected. If W P#/A CC = VIH, the two out er most boot se ctor pr otection
depends on whet her they were l ast p rotec t ed or unpr otec t ed using t he me thod des cr ibed in “The aut ose lect mode prov ides
manufac t urer and d evi ce i dent ification, and sector prot ecti on v eri f ic ation, thr ough i dent i fi er codes out put on DQ7– DQ0. The
aut oselect codes can be acces sed in- system through t he c ommand regis ter . Refer t o the Autoselec t C ommand Sequenc e secti on
for more information.Secto r/S ector Bl ock Prot ecti on and Un protection”. If WP#/A CC = VHH, all s ector s will be unpr ot ec ted.
Operation
(Not es 1, 2) CE#f CE1#s CE2s OE# WE# SA Addr. LB#s UB#s RESET# WP#/ACC
(Note 4) DQ7–
DQ0 DQ15–
DQ8
Read from Flash L HX
LH X A
IN XX H L/H D
OUT DOUT
XL
W r ite t o Flash L HX
HL X A
IN XX H(Note 4)D
IN DIN
XL
Standby VCC ±
0.3 V HX
XX X X X XVCC ±
0.3 V H High-Z High-Z
XL
Output Disable L L H HHXXLXH L/H High-Z High-Z
HH X X X L
Flash Hardware
Reset XHX
X X X X X X L L/H High-Z High-Z
XL
Sector Prote ct
(Note 5) L
HX
HL X
SADD,
A6 = L,
A1 = H ,
A0 = L
XX V
ID L/H DIN X
XL
Sector Unprotect
(Note 5) L
HX
HL X
SADD,
A6 = H ,
A1 = H ,
A0 = L
XX V
ID (Note 6) DIN X
XL
Temporary Sector
Unprotect XHX
XX X X X X V
ID (Note 6) DIN High-Z
XL
Read from SRAM H L H L H X AIN
LL
HX
DOUT DOUT
H L High-Z DOUT
LH D
OUT High-Z
Wr ite to SRAM H L H X L X AIN
LL
HX
DIN DIN
H L High-Z DIN
LH D
IN High-Z
12 Am41DL16x4D
PRELIMINARY
Table 2. Device Bus Operations—Flash Word Mode, CIOf = VIH; SRAM Byte Mode, CIOs = VSS
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5 – 12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address
Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out, DNU = Do Not Use
Notes:
1. Other operations except for those indicated in this column ar e inhibited.
2. Do not apply CE#f = VIL, CE1 #s = VIL and CE2s = V IH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/A CC = VIL , the boot sector s w ill be protected. I f WP#/ ACC = VIH the boot sectors p rotec tion will be re mov ed.
If WP#/ACC = VACC (9V ), the pr ogr am time wi ll be reduced by 40%.
5. The sector pr otect and s ector un protect f unctio ns may als o be impl emented vi a programmi ng equipment . See the “The au toselect
mode pr ovides m anufac t ure r and devi ce i dentif i cati on, and s ector pr otec t ion v erif ic ation, thr ough identifier code s output on
DQ7–DQ0. The aut os elec t co des c an be ac cesse d in- system t hro ugh the c omman d reg iste r. Refer to the Autoselect Com mand
Sequenc e se ctio n f or more infor mation.Sector/S ector Bloc k Prot ec tion and Unprotection” sect ion.
6. If WP#/A CC = VIL, the two out er most b oot sec tor s remai n pr otected. If W P#/A CC = VIH, the two out er most boot se ctor pr otection
depends on whet her they were l ast p rotec t ed or unpr otec t ed using t he me thod des cr ibed in “Th e autose lec t mode pr ov ides
manufac t urer and d evi ce i dent ificati on, and s ector pr otection verificat ion, t hr ough i dent i fi er codes output o n DQ7–DQ0. The
aut oselect codes can be acc essed in- system through t he c ommand regis ter . Refer to t he Autos elect C ommand Sequenc e secti on
for mor e i nform ation. S ecto r/S ector Bl ock Prot ecti on and Unprote ction”. If WP#/ACC = VHH, al l s ector s will be unpr ot ec ted.
Operation
(Not es 1, 2) CE#f CE1#s CE2s OE# WE# SA Addr. LB#s
(Not e 3) UB#s
(Note 3) RESET# WP#/ACC
(Not e 4) DQ7–
DQ0 DQ15–
DQ8
Read from Flash L HX
LHX A
IN XXHL/HD
OUT DOUT
XL
Write to Flash L HX
HLX A
IN X X H (Note 3) DIN DIN
XL
Standby VCC ±
0.3 V HX
XXX X X X VCC ±
0.3 V H High-Z High-Z
XL
Output Disable L L H H H SA X DNU DNU H L/H High-Z High-Z
Flash Hardware
Reset XHX
XXX X X X L L/H High-ZHigh-Z
XL
Sector Protect
(Note 5) L
HX
HLX
SADD,
A6 = L,
A1 = H,
A0 = L
XXV
ID L/H DIN X
XL
Se c tor Unprotect
(Note 5) L
HX
HLX
SADD,
A6 = H,
A1 = H,
A0 = L
XXV
ID (Note 6) DIN X
XL
Temporary Sector
Unprotect XHX
XXX A
IN XXV
ID (Note 6) DIN High-Z
XL
Read from SRAM H L H L H SA AIN XXH XD
OUT High-Z
Write to SRAM H L H X L SA AIN XXH XD
IN High-Z
Am41DL16x4D 13
PRELIMINARY
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = VSS; SRAM Word Mode, CIO s = VCC
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5 –12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address
Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In (for Flash Byte Mode, DQ15 = A-1), DIN = Data In, DOUT =
Data Out
Notes:
1. Other operations except for those indicated in this column ar e inhibited.
2. Do not apply CE#f = VIL, CE1 #s = VIL and CE2s = V IH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/A CC = VIL , the boot sector s w ill be protected. I f WP#/ ACC = VIH the boot sectors p rotec tion will be re mov ed.
If WP#/ACC = VACC (9V ), the pr ogr am time wi ll be reduced by 40%.
5. The sector pr otect and s ector un protect f unctio ns may als o be impl emented vi a programmi ng equipment . See the “The au toselect
mode pr ovides m anufac t ure r and devi ce i dentif i cati on, and s ector pr otec t ion v erif ic ation, thr ough identifier code s output on
DQ7–DQ0. The aut os elec t co des c an be ac cesse d in- system t hro ugh the c omman d reg iste r. Refer to the Autoselect Com mand
Sequenc e se ctio n f or more infor mation.Sector/S ector Bloc k Prot ec tion and Unprotection” sectio n.
6. If WP#/A CC = VIL, the two out er most b oot sec tor s remai n pr otected. If W P#/A CC = VIH, the two out er most boot se ctor pr otection
depends on whet her they were l ast p rotec t ed or unpr otec t ed using t he me thod des cr ibed in “Th e autose lec t mode pr ov ides
manufac t urer and d evi ce i dent ificati on, and s ector pr otection verificat ion, t hr ough i dent i fi er codes output o n DQ7–DQ0. The
aut oselect codes can be acc essed in- system through t he c ommand regis ter . Refer to t he Autos elect C ommand Sequenc e secti on
for mor e i nform ation. S ecto r/S ector Bl ock Prot ecti on and Unprote ction”. If WP#/ACC = VHH, al l s ector s will be unpr ot ec ted.
Operation
( Notes 1, 2) CE#f CE1#s CE2s OE#
WE# SA Addr. LB#s
(Note 3 ) UB#s
(No t e 3) RESET# WP#/ACC
(Note 4)
DQ7–
DQ0 DQ15–
DQ8
Read from Flash L HX
LHX A
IN XXHL/HD
OUT High-Z
XL
Write to Flash L HX
HLX A
IN XXH
(Note 3)
DIN High-Z
XL
Standby VCC ±
0.3 V HX
XXX X X X VCC ±
0.3 V H High-Z High-Z
XL
Output Dis able L L H H H X X LXH L/H High-Z High-Z
XL
Flash Hardware
Reset XHX
X X X X X X L L/H High-Z High-Z
XL
Sector Protect
(Note 5) L
HX
HLX
SADD,
A6 = L,
A1 = H,
A0 = L
XXV
ID L/H DIN X
XL
Sector
Unprotec t
(Note 5) L
HX
HLX
SADD,
A6 = L,
A1 = H,
A0 = L
XXV
ID (Note 6) DIN X
XL
Tem porary
Sector
Unprotect XHx
XXX A
IN XXV
ID (Note 6) DIN High-Z
XL
Read from
SRAM HLHLHXA
IN
LL
HX
DOUT DOUT
HL High-ZD
OUT
LH D
OUT High-Z
Write t o SRAM H L H X L X AIN
LL
HX
DIN DIN
HL High-ZD
IN
LH D
IN High-Z
14 Am41DL16x4D
PRELIMINARY
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = VIL; SRAM Byte Mode, CIOs = VSS
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5 –12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address
Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In (for Flash Byte Mode, DQ15 = A-1), DIN = Data In, DOUT =
Data Out, DNU = Do Not Use
Notes:
1. Other operations except for those indicated in this column ar e inhibited.
2. Do not apply CE#f = VIL, CE1 #s = VIL and CE2s = V IH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/A CC = VIL , the boot sector s w ill be protected. I f WP#/ ACC = VIH the boot sectors p rotec tion will be re mov ed.
If WP#/ACC = VACC (9V ), the pr ogr am time wi ll be reduced by 40%.
5. The sector pr otect and s ector un protect f unctio ns may als o be impl emented vi a programmi ng equipment . See the “The au toselect
mode pr ovides m anufac t ure r and devi ce i dentif i cati on, and s ector pr otec t ion v erif ic ation, thr ough identifier code s output on
DQ7–DQ0. The aut os elec t co des c an be ac cesse d in- system t hro ugh the c omman d reg iste r. Refer to the Autoselect Com mand
Sequenc e se ctio n f or more infor mation.Sector/S ector Bloc k Prot ec tion and Unprotection”.
6. If WP#/ACC = VIL, the tw o outer most b oot sec tor s remai n pr ot ected . If WP#/A CC = VIH, the t wo outer mos t boot se ctor prot ecti on
depends on whet her they were l ast p rotec t ed or unpr otec t ed using t he me thod des cr ibed in “Th e autose lec t mode pr ov ides
manufac t urer and d evi ce i dent ificati on, and s ector pr otection verificat ion, t hr ough i dent i fi er codes output o n DQ7–DQ0. The
aut oselect codes can be acc essed in- system through t he c ommand regis ter . Refer to t he Autos elect C ommand Sequenc e secti on
for mor e i nform ation. S ecto r/S ector Bl ock Prot ecti on and Unprote ction”. If WP#/ACC = VHH, all sectors will be unprotected.
Operation
( Notes 1, 2) CE#f CE1#s CE2s OE#
WE# SA Addr. LB#s
(N ot e 3) UB#s
(Note 3) RESET# WP#/ACC
(N ot e 4)
DQ7–
DQ0 DQ15–
DQ8
Read from Flash L HX
LH X A
IN XXHL/HD
OUT High-Z
XL
Write to Flash L HX
HL X A
IN XXH
(Note 3)
DIN High-Z
XL
Standby VCC ±
0.3 V HX
XX X X X X VCC ±
0.3 V H High-Z High-Z
XL
Output Dis able H L H H H SA X DNU DNU H L/H High- Z Hi gh- Z
Flash Hardware
Reset XHX
X X X X X X L L/H High-Z High-Z
XL
Sector Protect
(Note 5) L
HX
HL X
SADD,
A6 = L,
A1 = H,
A0 = L
XXV
ID L/H DIN X
XL
Sector Unprotect
(Note 5) L
HX
HL X
SADD,
A6 = L,
A1 = H,
A0 = L
XXV
ID (Note 6) DIN X
XL
Tem porary
Sector Unprotect XHX
XX X A
IN XXV
ID (Note 6) DIN High-Z
XL
Read from SRAM H L H L H SA AIN XXH XD
OUT High-Z
Write t o SRAM H L H X L SA AIN XXH XD
IN High-Z
Am41DL16x4D 15
PRELIMINARY
Word/Byte Configuration
The CIOf pin controls whether the device data I/O pins
operate in the byte or word configura tion. If the CIOf
pin is set at logic ‘1’, the device is in word configura-
tion, DQ0–DQ15 are active and controlled by CE# and
OE#.
If the CIOf pin is set at logic ‘0’, the device is in byte
co nfig uratio n, a nd o nly data I/O pin s D Q0–DQ7 are
active and controlled by CE# and OE #. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ 15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outpu ts, the system must
driv e t he CE# f a nd OE# pins to VIL. CE#f i s the po wer
co ntro l an d se le cts t he d ev ice . O E # is th e ou tpu t c on-
trol and gates array data to the output pins. WE#
should remain at VIH. The CIOf pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
conte nt occurs during th e power tr ansition . No com-
mand is necessary in this mode to obtain array data.
Sta ndar d micropr oce ssor re ad cycl es that as sert va lid
addr e sse s o n t he dev ice ad dr ess i npu ts prod uc e va lid
data on the dev ice data outputs. Each bank remains
ena bled for read access until the comman d register
contents are altered.
See “Requirements for Reading Array Data ” for more
information. Refer to the AC Flash Read-Only Opera-
tions table for timing specifications and to Figure 14 for
the timing diagram. ICC1 in the DC Characteristics
table represents the active current specific ation for
readin g array data.
Writing Commands/Command Sequences
To wr ite a com m and or comm an d se qu enc e (whi c h in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE#f to VIL, and OE# to VIH.
For program operations, the CIOf pin determines
whether the device accepts program data i n bytes or
words. R efer to “Wor d/Byte Co nfiguration” for more
information.
Th e de vic e fea ture s an Unlock Bypa ss m od e to fa cil-
itate faster programming. Once a bank enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word/Byt e Conf igurati on” section has details on pro-
gramming data to the device using both standard and
Unlock Bypass command seque nces.
An erase operation can erase one sector , multiple sec-
tors, or the entire device. Tables 6–7 indicate the
address space that each sector occupies. The device
addr ess spa ce is divi ded i nto two ba nks: Ban k 1 con -
tains the boo t/p aram ete r sectors , and Ban k 2 conta in s
the larger, code secto rs of uniform size. A “bank ad-
dress” is the add res s bits requ ire d to un iq uel y select a
bank. Similarly, a “sector address” is the address bits
required to uniquely select a sector.
ICC2 in the DC Char ac te ristic s ta bl e repr es en ts th e ac -
tive current specification for the write mod e. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
throu gh the A CC fun ct ion. T hi s is on e of two f uncti on s
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
If the system asserts VHH on this pi n, the de vice a uto-
matically en ters the af orementione d Unlock Bypas s
mode, tempor arily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would us e a two-cycle program command s equence
as requ ired by the Unlock Bypa ss mode. Re moving
VHH from the WP#/ACC pin returns the device to no r-
mal ope ration. Note that the WP#/ACC pin mu st not
be at V HH for operations other than accelerate d p ro-
gramming, or device damage may result. In addition,
the WP#/ACC pin must not be left floating or un con-
nected; inconsistent behavior of the device may result.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mo de. The
system c an the n rea d au tos e le ct co des fro m th e i nte r -
nal register (which is separate from the memory array)
on D Q7–DQ0. Standard read cycle timings apply in
this m ode . Refe r to th e Au tos elec t Mode and A uto se-
lect Command Sequence sections for more
information.
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be sus-
pende d to read from or program to anoth er location
within the same bank (except the sector being
erased). Figure 21 shows how read and write cycles
may be initiated for simultaneous operation with zero
latency. ICC6 and ICC7 in the DC Characteristics table
represent the current specifications for read-while-pro-
gram a nd read-while-e rase, respectively.
16 Am41DL16x4D
PRELIMINARY
Standby Mode
When the syste m is not r eading or writing to the de-
vice, it c an place the de vice in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
Th e d evi ce en ters t he CM O S st and by m od e w hen th e
CE#f and RESET# pins are both held at VCC ± 0. 3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE#f and RESET# are held at VIH, but not
within VCC ± 0.3 V, the dev ice wi ll be in th e stan dby
mod e, but the s tandby cu rrent wi ll be gr eater. T he de-
vice requires standard access time (tCE) for read
access when the device is in either of these standby
modes, before it is ready to read data.
If the de vice is dese lected during er asur e or prog ram-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for tACC +
30 ns. The automatic sleep mode is independent of
the C E# f, WE#, an d OE# co nt ro l si gn al s . S tan da r d ad-
dress access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
ICC4 in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESE T# pin provides a hardware m ethod of re-
setting the device to reading array data. When the
RESET# pin is dr iven low for at least a p eriod of tRP,
the device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the R ESET#
pulse. The device also r esets th e inte rnal state ma -
chine to read ing array data . The operation that was
interrupted should be reinitiated once the device is
ready to acc ept an other c ommand seq uence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESE T# is h eld at VSS ± 0.3 V, the de-
vice draws CMOS standby current (ICC4). If RESET# is
held at VIL but not within VSS ± 0.3 V, the standby cur-
rent will be grea ter.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whethe r the res e t op erat io n i s c om pl ete . I f RE SET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset o peration is
completed within a time of tREADY (not during Embed-
ded Algorithm s). The system can rea d data tRH after
the RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 15 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
Table 5. Device Bank Division
Device
Part Number
Bank 1 Bank 2
Megabits Sector Sizes Megabits Sector Sizes
Am29DL161D 0.5 Mbit Eight 8 Kbyte/4 Kword 15.5 Mbit Thirty-one
64 Kbyte/32 Kword
Am29DL162D 2 Mbit Eight 8 Kbyte/4 K word,
three 64 Kbyte/32 Kword 14 Mbit Twenty-eight
64 Kbyte/32 Kword
Am29DL163D 4 Mbit Eight 8 Kbyte/4 K word,
seven 64 Kbyte/32 Kword 12 Mbit Twenty-four
64 Kbyte/32 Kword
Am29DL164D 8 Mbit Eight 8 Kbyte/4 K word,
fifteen 64 Kbyte/32 Kword 8 Mbit Sixteen
64 Kbyte/32 Kword
Am41DL16x4D 17
PRELIMINARY
Table 6. Sector Addresses for Top Boot Sector Devices
Note: The add ress range is A19 :A-1 in byte m ode (CIOf =VIL) or A19:A0 i n word mode (CIOf=V IH). The bank a ddres s bit s are A19–15 for
Am29DL161DT, A19–A1 7 for Am29DL162DT, A19 and A18 for Am 29DL163DT, and A19 for Am29DL 164DT.
Table 7. SecSi Sector Addresses for Top Boot Devices
Am29DL164DT
Am29DL163DT
Am29DL162DT
Am29DL161DT
Sector Sector Address
A19–A12 Sector Size
(Kbytes/Kwords) (x8)
Ad dress Range (x16)
Ad dress Range
Bank 2
Bank 2
Bank 2
Bank 2
SA0 00000xxx 64/32 000000h-00FFFFh 00000h–07FFFh
SA1 00001xxx 64/32 010000h-01FFFFh 08000h–0FFFFh
SA2 00010xxx 64/32 020000h-02FFFFh 10000h–17FFFh
SA3 00011xxx 64/32 030000h-03FFFFh 18000h–1FFFFh
SA4 00100xxx 64/32 040000h-04FFFFh 20000h–27FFFh
SA5 00101xxx 64/32 050000h-05FFFFh 28000h–2FFFFh
SA6 00110xxx 64/32 060000h-06FFFFh 30000h–37FFFh
SA7 00111xxx 64/32 070000h-07FFFFh 38000h–3FFFFh
SA8 01000xxx 64/32 080000h-08FFFFh 40000h–47FFFh
SA9 01001xxx 64/32 090000h-09FFFFh 48000h–4FFFFh
SA10 01010xxx 64/32 0A0000h-0AFFFFh 50000h–57FFFh
SA11 01011xxx 64/32 0B0000h-0BFFFFh 58000h–5FFFFh
SA12 01100xxx 64/32 0C0000h-0CFFFFh 60000h–67FFFh
SA13 01101xxx 64/32 0D0000h-0DFFFFh 68000h–6FFFFh
SA14 01110xxx 64/32 0E0000h-0EFFFFh 70000h–77FFFh
SA15 01111xxx 64/32 0F0000h-0FFFFFh 78000h–7FFFFh
Bank 1
SA16 10000xxx 64/32 100000h-10FFFFh 80000h–87FFFh
SA17 10001xxx 64/32 110000h-11FFFFh 88000h–8FFFFh
SA18 10010xxx 64/32 120000h-12FFFFh 90000h–97FFFh
SA19 10011xxx 64/32 130000h-13FFFFh 98000h–9FFFFh
SA20 10100xxx 64/32 140000h-14FFFFh A0000h–A7FFFh
SA21 10101xxx 64/32 150000h-15FFFFh A8000h–AFFFFh
SA22 10110xxx 64/32 160000h-16FFFFh B0000h–B7FFFh
SA23 10111xxx 64/32 170000h-17FFFFh B8000h–BFFFFh
Bank 1
SA24 11000xxx 64/32 180000h-18FFFFh C0000h–C7FFFh
SA25 11001xxx 64/32 190000h-19FFFFh C8000h–CFFFFh
SA26 11010xxx 64/32 1A0000h-1AFFFFh D0000h–D7FFFh
SA27 11011xxx 64/32 1B0000h-1BFFFFh D8000h–DFFFFh
Bank 1
SA28 11100xxx 64/32 1C0000h-1CFFFFh E0000h–E7FFFh
SA29 11101xxx 64/32 1D0000h-1DFFFFh E8000h–EFFFFh
SA30 11110xxx 64/32 1E0000h-1EFFFFh F0000h–F7FFFh
Bank 1
SA31 11111000 8/4 1F0000h-1F1FFFh F8000h–F8FFFh
SA32 11111001 8/4 1F2000h-1F3FFFh F9000h–F9FFFh
SA33 11111010 8/4 1F4000h-1F5FFFh FA000h–FAFFFh
SA34 11111011 8/4 1F6000h-1F7FFFh FB000h–FBFFFh
SA35 11111100 8/4 1F8000h-1F9FFFh FC000h–FCFFFh
SA36 11111101 8/4 1FA000h-1FBFFFh FD000h–FDFFFh
SA37 11111110 8/4 1FC000h-1FDFFFh FE000h–FEFFFh
SA38 11111111 8/4 1FE000h-1FFFFFh FF000h–FFFFFh
Device Sec tor Address
A19–A12 Sector
Size (x8)
Address Range (x16)
Address Range
Am29DL16xDT 11111XXX 64/32 1F0000h-1FFFFFh F8000h–FFFFFh
18 Am41DL16x4D
PRELIMINARY
Table 8. Sector Addresses for Bottom Boot Sector Devices
Note: The add ress rang e is A19 :A-1 in byte m ode (BYTE#=VIL) or A19:A0 in word mode (BYTE#=VIH). The bank addres s bit s are A1 9–A15 fo r
Am29DL161 DB, A1 9–A17 for Am29 DL162DB, A19 and A18 for Am 29DL163DB, and A19 for Am29DL164DB.
Table 9. SecSi Addresses for Bottom Boot Devices
Am29DL164DB
Am29DL163DB
Am29DL162DB
Am29DL161DB
Sector Sector Address
A19–A12 Sector Size
(Kbytes/Kwords) (x8)
Ad dress Range (x16)
Ad dr es s R ang e
Bank 1
Bank 1
Bank 1
Bank 1
SA0 00000000 8/4 000000h-001FFFh 00000h-00FFFh
SA1 00000001 8/4 002000h-003FFFh 01000h-01FFFh
SA2 00000010 8/4 004000h-005FFFh 02000h-02FFFh
SA3 00000011 8/4 006000h-007FFFh 03000h-03FFFh
SA4 00000100 8/4 008000h-009FFFh 04000h-04FFFh
SA5 00000101 8/4 00A000h-00BFFFh 05000h-05FFFh
SA6 00000110 8/4 00C000h-00DFFFh 06000h-06FFFh
SA7 00000111 8/4 00E000h-00FFFFh 07000h-07FFFh
Bank 2
SA8 00001XXX 64/32 010000h-01FFFFh 08000h-0FFFFh
SA9 00010XXX 64/32 020000h-02FFFFh 10000h-17FFFh
SA10 00011XXX 64/32 030000h-03FFFFh 18000h-1FFFFh
Bank 2
SA11 00100XXX 64/32 040000h-04FFFFh 20000h-27FFFh
SA12 00101XXX 64/32 050000h-05FFFFh 28000h-2FFFFh
SA13 00110XXX 64/32 060000h-06FFFFh 30000h-37FFFh
SA14 00111XXX 64/32 070000h-07FFFFh 38000h-3FFFFh
Bank 2
SA15 01000XXX 64/32 080000h-08FFFFh 40000h-47FFFh
SA16 01001XXX 64/32 090000h-09FFFFh 48000h-4FFFFh
SA17 01010XXX 64/32 0A0000h-0AFFFFh 50000h-57FFFh
SA18 01011XXX 64/32 0B0000h-0BFFFFh 58000h-5FFFFh
SA19 01100XXX 64/32 0C0000h-0CFFFFh 60000h-67FFFh
SA20 01101XXX 64/32 0D0000h-0DFFFFh 68000h-6FFFFh
SA21 01110XXX 64/32 0E0000h-0EFFFFh 70000h-77FFFh
SA22 01111XXX 64/32 0F0000h-0FFFFFh 78000h-7FFFFh
Bank 2
SA23 10000XXX 64/32 100000h-10FFFFh 80000h-87FFFh
SA24 10001XXX 64/32 110000h-11FFFFh 88000h-8FFFFh
SA25 10010XXX 64/32 120000h-12FFFFh 90000h-97FFFh
SA26 10011XXX 64/32 130000h-13FFFFh 98000h-9FFFFh
SA27 10100XXX 64/32 140000h-14FFFFh A0000h-A7FFFh
SA28 10101XXX 64/32 150000h-15FFFFh A8000h-AFFFFh
SA29 10110XXX 64/32 160000h-16FFFFh B0000h-B7FFFh
SA30 10111XXX 64/32 170000h-17FFFFh B8000h-BFFFFh
SA31 11000XXX 64/32 180000h-18FFFFh C0000h-C7FFFh
SA32 11001XXX 64/32 190000h-19FFFFh C8000h-CFFFFh
SA33 11010XXX 64/32 1A0000h-1AFFFFh D0000h-D7FFFh
SA34 11011XXX 64/32 1B0000h-1BFFFFh D8000h-DFFFFh
SA35 11100XXX 64/32 1C0000h-1CFFFFh E0000h-E7FFFh
SA36 11101XXX 64/32 1D0000h-1DFFFFh E8000h-EFFFFh
SA37 11110XXX 64/32 1E0000h-1EFFFFh F0000h-F7FFFh
SA38 11111XXX 64/32 1F0000h-1FFFFFh F8000h-FFFFFh
Device Sector Add ress
A19–A12 Sector
Size (x8)
Ad dres s Ra nge (x16)
Address Ra nge
Am29DL16xDB 00000XXX 64/32 000000h-00FFFFh 00000h-07FFFh
Am41DL16x4D 19
PRELIMINARY
Autose lect Mod e
The autoselect mode provides manufacturer and de-
vice identifica tion, and s ector pr otection verification,
thr ough iden tifier c odes outpu t on DQ7 –DQ0. T h e au-
toselect codes can be accessed in-system through the
command register. Refer to the Autoselect Command
Sequence section for more information.Sector/Sector
Bl ock Protection and Unprotection
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
bl ock consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Tables
10 and 11).
Ta ble 10. Top Boot Sector/Sector Block
Addresses for Protection/Unprote ction
Table 11. Bottom Boot Sector/Sector Block
Addresses for Protection/Unprotection
The hardwar e sector protection feature disables both
program and erase operations in any sector . The hard-
ware sector unprotection feature re-enables both
pro gram an d er ase ope ratio ns i n prev iousl y prot ect ed
sectors. Sector protection and unprotection can be im-
plemented as follows .
Sector protection/unprotection requires VID on th e RE -
SET# pin only, and can be implemented either
in-system or via programming equipment. Figure 2
shows the algorithms and Figure 26 shows the timing
diagram. This method uses standard microprocessor
bus cyc le timi ng. For sector unprot ect, al l unpro tected
sectors must first be protected prior to the first sector
unprotect write cycle. Note that the sector unprotect
algorithm unprotects all sectors in parallel. Al l previ-
ously protected sectors must be individually
re-protected. To change data in protected sectors effi-
ciently, the temporary sector un protect function is
available. See “Temporary Sector/Sector Block
Unprotect”.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is pro-
tected or unprotected. See the Autoselect Mode
section for details.
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting certain boot sectors without
using VID. This function is one of two provided by the
WP#/ACC pin.
Sector / Sector
Block A19–A12 Sector / Sector Block Size
SA0 00000XXX 64 Kbytes
SA1-SA3 00001XXX,
00010XXX,
00011XXX 19 2 ( 3x 64 ) Kbyt e s
SA4-SA7 001XXXXX 256 (4x64) Kbytes
SA8-SA11 010XXXXX 25 6 (4x64) Kbytes
SA12-SA15 011 XXXXX 25 6 (4x64) Kbytes
SA16-SA19 100XXXXX 256 (4x64 ) Kbytes
SA20-SA23 101XXXXX 256 (4x64 ) Kbytes
SA24-SA27 110XXXXX 256 (4x64) Kbytes
SA28-SA30 11100XXX,
11101XXX,
11110XXX 192 ( 3x 64 ) Kbyt e s
SA31 11111000 8 Kbytes
SA32 11111001 8 Kbytes
SA33 11111010 8 Kbytes
SA34 11111011 8 Kbytes
SA35 11111100 8 Kbytes
SA36 11111101 8 Kbytes
SA37 11111110 8 Kbytes
SA38 11111111 8 Kbytes
Sector / Sector
Block A19–A12 Sector / Sector Block Size
SA38 11111XXX 64 Kbytes
SA37-SA35 11110XXX,
11101XXX,
11100XXX 192 (3x64) Kbytes
SA34-SA31 110XXXXX 256 (4x64) Kbytes
SA 30-SA27 101XXXXX 256 (4x64) K bytes
SA 26-SA23 100XXXXX 256 (4x64) K bytes
SA22-SA19 011XXXXX 256 (4x64) Kbytes
SA 18-SA15 010XXXXX 256 (4x64) K bytes
SA14-SA11 001XXXXX 256 (4x64) Kbytes
SA10-SA8 00001XXX,
00010XXX,
00011XXX 192 (3x64) Kby tes
SA7 00000111 8 Kbytes
SA6 00000110 8 Kbytes
SA5 000 00101 8 Kbytes
SA4 000 00100 8 Kbytes
SA3 00000011 8 Kbytes
SA2 000 00010 8 Kbytes
SA1 000 00001 8 Kbytes
SA0 000 00000 8 Kbytes
20 Am41DL16x4D
PRELIMINARY
If the system asserts VIL o n the WP #/ AC C pi n, the de-
vice disables program and er ase functions in the two
“outermost” 8 Kby te boot sectors independently of
whether those sector s were protected or unprotected
using the method described in “The autoselect mode
provides m anufacturer and device identification, and
sector protection verification, through identifier codes
output on DQ7–DQ0 . T h e au t os el ec t c o des ca n b e ac -
cessed in-system through the command register.
Refer to the Autoselect Command Sequence section
for more info rma tion.Sec tor/Sec tor B loc k Pr otectio n
and Unprotection”. The two outermost 8 Kbyte b oot
sectors are the two sector s containing the lowes t ad-
dresses in a top-boot-configured device, or the two
sectors containing the highest addresses in a
top-boot-configured device.
If the system asserts VIH on the WP# /A CC pi n, th e de-
vice reverts to whether the two outermost 8 Kbyte boot
sectors were last set to be protected or unprotected.
That is, sector protect io n or unprotectio n for these two
sectors depends on whether they were last protected
or unprotected using the method described in “The au-
toselect mode provides manufacturer and device
identification, and sector protection verification,
thr ough iden tifier c odes outpu t on DQ7 –DQ0. T h e au-
toselect codes can be accessed in-system through the
command register. Refer to the Autoselect Command
Sequence section for mor e information.Sector/Sector
Bl ock Protection and Unprotection”.
Note that the WP#/ACC pin must not be left floating or
unc onne cted; incon siste nt beha vior of th e device may
result.
Temporary Sector/Sector Block Unprotect
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
bl ock consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Tables
10 and 11).
This feature allows temporary unprot ection of previ-
ously protected sectors to change data in-system. The
Sect or Un pr ot ec t m od e is a ctiv ate d by sett in g t he RE -
SET# pin to VID (8.5 V – 12.5 V). D uri ng t his m ode,
formerly protected sectors can be programmed or
erased by selecting the sector addresses. Once VID is
removed from the RESET# pin, all the previously pro-
tected sectors are protected again. Figure 1 shows the
algorithm, and Figure 25 shows the timing diagrams,
for this feature.
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unpr ot e ct Comp leted
(Note 2)
RE S ET # = V ID
(Note 1)
Notes:
1. All protected sectors unprotected (If WP#/ACC = VIL,
outermost boot sectors will remain protected).
2. All previous ly protected sectors are protec ted once
again.
Figure 1. Te mporary Sector Unprotect Operation
Am41DL16x4D 21
PRELIMINARY
Note: The term “sector” in the figure applies to both sectors and sector blocks.
Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Set up sector
address
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
First Write
Cycle = 60h?
Data = 01h?
Remove VID
from RESET#
Write reset
command
Sector Protect
complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode No
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Set up first sector
address
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
Data = 00h?
Last sector
verified?
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode
No All sectors
protected?
Yes
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
Set up
next sector
address
No
Yes
No
Yes
No
No
Yes
No
Sector Protect
Algorithm Sector Unprotect
Algorithm
First Write
Cycle = 60h?
Protect another
sector?
Reset
PLSCNT = 1
22 Am41DL16x4D
PRELIMINARY
SecSi (Secured Silicon) Sector Flash
Memory Region
The SecSi (Secured Silicon) Sector feature provides a
Flash mem ory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The S ecSi Sector is 64 Kbytes in length, and
uses a SecSi Sector Indicator Bit to indicate whether
or not the SecSi Sector is locked when shipped fr om
the fac tory. This bit is permanentl y set at the factory
and cannot b e changed, which prevents cloning of a
factory locked part. This ensures the security of the
ESN once the product is shipped to the field. Current
version of this device has 64 Kbytes; future ver-
sions will have only 256 bytes. This should be
considered during system design.
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the factor y, and ha s the Sec Si Secto r Indicator
Bit perm anently set to a “1.” The customer-lockable
version is shipped with the unprotected, allowing cus-
tomers to utilize the that sector in any manner they
choose. The customer-lockable version has the SecSi
Sector Indicator Bit permanently set to a “0.” Thus, the
Sec Si Sec tor Indicat or Bit pre vent s custom er-loc kable
devices from being used to replace devices that are
factory locked.
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi S ector/Exit
SecSi Sector Command Sequence”). Af ter the system
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the
addresses normally occupied by the boot sectors. This
mode of operation c ontinues un til the sys tem issues
the Exit SecSi Sector command sequence, or until
powe r is removed from the device. On power-up, or
following a hardware reset, the device reverts to send-
ing commands to the boot sectors.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
In a factory locked device, the SecSi Sector is pro-
tected when the device is shipped from the factory.
The SecSi Sector cannot be modified in any way. The
device is available preprogrammed with a random, se-
cure ESN only
In de vices that ha ve an ES N, the Top Boot de vice wi ll
have the 16-byte ESN, with the starting address of the
ESN will be at the bottom of the lowe st 8 Kbyte boot
sector a t addre sses F8 000h–F8007h in word mode (or
1F0000h–1F000Fh in byte mode).
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
If the s ec uri ty f eat ur e is no t r e qui red , the SecSi Sector
can be trea ted as an add iti ona l F lash me m or y sp a ce ,
ex p an d i ng t h e s iz e of the av ailabl e Flas h arra y by 64
Kby tes. Current version of this device has 64
Kbytes; future vers ions will have on ly 256 bytes.
This shoul d be cons idered durin g system de sign.
The SecSi Sector can be read, programmed, and erased
as often as required. Note that the accelerated program-
ming (ACC) and unlock bypass functions are not
available when programming the SecSi Sector.
The SecSi Sector area can be protected using one of the
fo llowin g p roc ed ur es:
■Write the three-cycle Enter SecSi Sector Region
com ma nd sequ en ce , and then fo llow the in- sy st em
sector protect algorithm as shown in Figure 2, ex-
cept tha t RE S ET# ma y be at e ither VIH or VID. This
allows in-system protection of the without raising
any device pin to a high voltage. Note that this
method is only applicable to the SecSi Sector.
■Write the three-cycle Enter SecSi Sector Region
command sequence, and then use the alternate
method of sector protection described in the “The
autoselect mode provides manufacturer and device
identification, and sector protection verification, through
iden tifier codes output on DQ7–DQ 0. The autos elect
codes can be accessed in-system through the com-
mand r egister. Refer to th e A utoselect Comm and Se-
quence section for more information.Sector/Sector Block
Protection and Unprotection”.
Once the SecSi Sector is locked and verified, the sys-
tem must write the Exit SecSi Sector Region
command sequenc e to return to reading a nd writing
the rema inder of the ar ray.
The SecSi Sector protection must be used with cau-
tion since, once protected, there is no procedure
available for unprotecting the SecSi Sector area and
none of the bi ts in the SecS i Sect or memory space
can be modified in any way.
Hardware Data Protection
The comm an d se qu enc e requi re me nt of un lock cyc les
for program ming or erasi ng provides da ta protection
against inadvertent writes (refer to Table 16 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any w rite c ycles. T his pro tects data during VCC
power-up and power-down. The command register
Am41DL16x4D 23
PRELIMINARY
and all internal program/erase circuits are disabled,
and the d evi ce res ets to rea ding array data. Subs e-
quent writes are ignored until VCC is greater than VLKO.
The system must provide the proper signals to the
control pins to prevent unintentional writes when VCC
is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on O E#, CE#f
or WE# do not initiat e a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE #f = VIH or WE# = VIH. To initiate a write cycle,
CE#f and W E# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE#f = VIL and OE# = VIH during power up,
the device does not acc ept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
softw are algorithms to be used for ent ire families of
devices. Soft ware support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The sys-
tem can read CFI information at the addresses given
in Tables 12–15. To terminate readi ng CFI data, the
system must write the reset command. The CFI Query
mode is not accessible when the device is executing
an Embedded Program or embedded erase algorithm.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI dat a at the address es give n in Table s 12–15. The
s yst e m m us t w r i t e t h e r ese t c o mman d to r e t urn t he d e-
vice to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/prod-
ucts/nvd/overview/cfi.html. Alternatively, contact an
AMD representative for copies of these documents.
Table 12. CFI Query Ident if ica tio n Stri ng
Addresses
(Word Mode ) Data Description
10h
11h
12h
0051h
0052h
0059h Query Unique A SCII string “QRY”
13h
14h 0002h
0000h Primary OEM Command Set
15h
16h 0040h
0000h Address for Primary Extended Table
17h
18h 0000h
0000h Alternate OEM Command Set (00h = none exists)
19h
1Ah 0000h
0000h Address for Alternate OEM Extended Table (00h = none exists)
24 Am41DL16x4D
PRELIMINARY
Table 13. System Interface String
Table 14. Device Geometry Definition
Addresses
(Word Mode ) Data Description
1Bh 0027h VCC Min. (w rite/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch 0036h VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh 0000h VPP Min. voltage (00h = no VPP pin present)
1Eh 0000h VPP Max. v oltage (00h = no VPP pin present)
1Fh 0004h Typical timeout per single byte/wor d write 2N µs
20h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 000Ah Typical timeout per individual block erase 2N ms
22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 0005h Max. timeout for byte/word write 2N times typical
24h 0000h Max. timeout for buffer write 2N times typical
25h 0004h Max. timeout per individual block erase 2N times typical
26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)
Addresses
(Word Mode ) Data Description
27h 0016h Device Size = 2N byte
28h
29h 0002h
0000h Flash Devic e Interface description (refer to CFI publication 100)
2Ah
2Bh 0000h
0000h Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch 0002h Number of Erase Block Regions within devic e
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
003Eh
0000h
0000h
0001h
Erase Block Region 2 Information
35h
36h
37h
38h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
Am41DL16x4D 25
PRELIMINARY
Table 15. Primary Vendor-Specific Extended Query
Note:
The number of sectors in Bank 2 is device dependent.
Am29DL161 = 1Fh
Am29DL162 = 1Ch
Am29DL163 = 18h
Am29DL164 = 10h
Addresses
(Word Mode ) Data Description
40h
41h
42h
0050h
0052h
0049h Query-unique ASCII string “PRI”
43h 0031h Major version number, ASCII
44h 0033h Minor version number, ASCII
45h 0001h Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Silicon Revision Number (Bits 7-2)
46h 0002h Erase S usp end
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 0001h Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h 0001h Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h 0004h Sector Protect/Unprotect scheme
04 = 29LV800 mode
4Ah 00XXh
(See Note) Simultaneous Operation
00 = Not Supported, X= Number of Sectors in B ank 2 (Uniform Bank)
4Bh 0000h Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch 0000h Page Mod e Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh 0085h ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Eh 0095h ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Fh 000Xh Top/Bottom Boot Sector Flag
02h = Bottom Boot Device, 03h = Top Boot Device
26 Am41DL16x4D
PRELIMINARY
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device
operations. Table 16 defines the valid register com-
mand sequences. Writing incorrect address and
data values or writing them in the improper se-
quence resets the device to reading array data.
All addresses are latched on the falling edge of WE#
or CE#f, whichever happens later. All data is latched
on the rising edge of WE# or CE#f, whichever hap-
pens first. Refer to the AC Char acteristics section for
timing diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrie ve data. E ach bank is ready t o read ar ray da ta
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read
data from any non-erase-suspended sector within the
same bank. After completing a programming operation
in the Erase Suspend mode, the system may once
again read array data with the same exception. See
the Erase Suspend/Erase Resum e Commands sec-
tion for more information.
The system must issu e the re set co mm an d to r et urn a
bank to the read (or erase-suspend-read) mode if DQ5
goes hig h duri ng an activ e progr am o r era se op era-
tion, or if the bank is in the autoselect mode. See the
next section, Reset Command, for more information.
Se e also Re qui remen ts fo r Rea ding Ar ray Data i n the
Device Bus Operations section for more information.
Th e Flash R ead -Only O peratio ns ta ble pro vides the
read para meters, a nd Figure 14 shows the timing
diagram.
Reset Command
Writing the reset command resets the banks to the
read or era se-suspend -read mo de. Add ress bi ts are
don’t cares for this command.
The res et command may be written between the se-
quence cycles in an erase command sequence before
era sin g b egi ns. This r e sets th e b ank t o w hi ch th e s y s-
tem was writing to readin g array data. Onc e erasure
begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the bank to
which the system was writing to reading array data. If
the program command sequence is written to a bank
that is in the Erase Suspend mo de, writing the reset
command returns that bank to the erase-sus-
pend-read mode. Once programming begins,
howev er, the de vic e i gn ores res et c om man ds u ntil t he
oper ation is compl ete .
The reset comman d may be written between the se-
quence cycles in an autoselect command s equence.
Once in the autoselect mode, the reset command
must be written to return to reading array data. If a
bank entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns
that bank to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to read-
ing array data (or erase-suspend-read mode if that
bank was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and de termine wh ether or not a sector is protected.
Table 16 shows the address an d data r equirements.
The autoselect command sequence may be written to
an address within a bank that is either in the read or
erase-suspend-read mode. The autoselect command
may not be written while the device is actively pro-
gramming or erasing in the other bank.
The au toselec t comma nd sequ ence is ini tiated by fi rst
wri ting tw o un lock cy cles . Th is is follo we d by a t hird
write cycle that contains the bank address and the au-
toselect command. The bank then enters the
autoselect mode. The system may read at any ad-
dress within the same bank any number of times
without initiating another autoselect command
sequence:
■A read cycle at address (BA)XX00h (where BA is
the bank address) returns the manufacturer code.
■A read cycle at address (BA)XX01h in word mode
(or (BA)XX02h in byte mode) returns the device
code.
■A read cycle to an address containing a sector ad-
dress (SA) within the sam e bank, an d the addres s
02h on A7–A0 in word mode (or the address 04h on
A6–A-1 in byte mode) returns 01h if the sector is
protected, or 00h if it is unprotected. (Refer to Ta-
bles 6–7 for valid sector addresses).
The system must writ e the r eset co mm an d to retur n to
rea ding array data (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
Am41DL16x4D 27
PRELIMINARY
Enter SecSi Sector/Exit SecSi Sector
Command Sequenc e
Th e sys te m c an acc es s t he Sec S i Se ct or r egion b y is-
suing the three-cycle Enter SecSi Sector command
sequence. The device continues to access the SecSi
Sector region until the system issues the four-cycle
Exit SecSi Se cto r c om mand se quen ce. The Exit SecSi
Sector command sequence returns the device to nor-
mal o peration. The SecSi Sector is not acces sible
when the device is executing an Embedded Program
or Embe d ded Er ase al go r i th m. Tabl e 16 s h ows t he ad -
dress and data requirements for both command
sequences. See also “SecSi (Secured Silicon) Sector
Fla sh Memory Region” for further information. Note
that a hardware reset (RESET#=VIL) will reset the de-
vice to reading array data.
Byte/Word Program Command Sequence
The system may program the device by word or byte,
depending on the state of the CIOf pin. Programming
is a four-bus-cycle opera tion. The progr am command
sequence is ini tiated by writing tw o unlock write cy-
cles, fol lowed by the program s et-up command . The
program ad dress and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not req uired to provid e further contro ls or
timings. T he device automatically p rovides internally
generated program pulses and verifies the pro-
grammed cell margin. Table 16 shows the address
and da ta r equ irem en ts for the by tewo rd pr og ram co m-
mand sequence.
When the Embedded Program algorithm is complete,
that ban k then retur ns to read ing array data and ad-
dresses are no longer latched. The system can
determine the status of the program operation by
using DQ7, DQ6, or RY/BY#. Refer to the Write Oper-
ation Status section for information on these status
bits.
Any command s written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
oper ation . The p rogram com mand seque nce sh ould
be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundarie s. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and
DQ6 status bits to indicate the operat ion was succe ss-
ful. However, a succeeding read will show that the
data is still “0.” Only er ase opera tions can convert a
“0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature a llows the system to pro-
gram bytes or wo rds to a bank faster than using the
standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
That bank then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all th at is r eq uire d to progr a m in thi s mod e. Th e fi rst
cycle in this sequence contains the unlock bypass pro-
gram comman d, A 0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Table 16 shows the require-
ments for the command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock B ypass Reset co mmands
are val id. To ex it the unlo ck byp ass mod e, the s ystem
must issue the two-cycle unlock bypass r eset com-
mand sequence. The first cycle must contain the bank
address and the data 90h. The second cycle need
only contain the data 00h. The bank then returns to
the read ing arra y dat a.
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
VHH on th e WP #/ AC C pi n, th e d ev ic e au t om at ic al l y en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/A CC pin to a ccelera te the o peration. Note that
the W P#/ACC pin mus t not be a t VHH any operation
other than accelerated programming, or device dam-
age may result. In addition, the WP#/ACC pin must not
be left floating or unconnected; inconsistent behavior
of the device may result .
Figure 3 illustrates the algorithm for the program oper-
ation. Refer to the Flash Erase and Program
Operations table in the AC Characteristics section for
parameters, and Figure 18 for timing diagrams.
28 Am41DL16x4D
PRELIMINARY
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycl es, follo wed by a set- up c om ma nd. Tw o ad ditio na l
unlock write cycles are then followed by the chip erase
com m and , whi ch in tur n inv ok es th e Embedd ed E r ase
algorithm. T he device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rit h m a ut o ma ti ca lly prep r o gra ms an d v e ri f i es th e en t ire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any co n-
trols o r timi ngs during these op erations. Table 16
sho ws the ad dres s an d da ta requ ir em en ts for th e c hip
erase command sequence.
When the Embedded Erase algorithm is complete,
that ban k re tur n s to rea din g a r ray dat a an d a ddre ss es
are no longer latched. The system can determine the
status of the e rase operation by using DQ7, DQ6,
DQ2, or RY/BY#. Refer to the Write Operation Status
section for information on these status bits.
Any commands written dur ing the chip erase operation
are ignored. However, note that a hard wa re re set im-
mediately terminates the erase operation. If that
occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 4 illustra tes the algorithm f or the erase o pera-
tion. Refer to the Flash Erase and Program
Operations tables in the AC Characte ristics section for
parameters, and Figure 20 section for timing
diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command seque nce is initiated by writing two
unlock cycles, followed by a set-up command. T wo ad-
ditional unlock cycles are written, and are then
followed by the address of the sector to be erased,
and the s ector er ase com mand. Table 16 s hows the
address and data requirement s for the sector erase
command sequence.
The device does not require the system to preprogram
prior to erase. The Embedded E rase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buf fer
may be done in any sequence, and the number of sec-
tors may be from one s ector to a ll secto rs. The ti me
between thes e additional cycles must be less than
50 µ s, oth er wi se er as ure may be gi n. Any se ct or er ase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mended that processor interrupts be dis abled during
this time to e nsure all commands are accepte d. The
interrupts can be re-enabled after the last Sector
Erase command is wr itten. Any command other than
Sector Erase or Erase Suspend during the
time-out p eriod resets that b ank to read ing array
data. The system must rewrite the command se-
quence and any additional addresses and commands.
The system can monitor DQ3 to determ ine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
bank retur ns to re adi ng arr ay data and ad dre sses are
no longer latched. Note that while the Embedded
Erase o perati on is in progre ss, the s ystem c an read
data from the non-erasing bank. The system can de-
termine the s tatus o f the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note: See Table 16 for program command sequence.
Am41DL16x4D 29
PRELIMINARY
Refer to the Write Operation Status section for infor-
mation on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
man ds a re ig nored. How ever, note that a hardware
reset immediately termina tes the erase o peration . If
that occurs, the sector erase command sequence
sho uld be r einitiate d onc e that bank has return ed to
reading array data, to ensure data integrity.
Figure 4 illustrates the algo rithm for the era se opera-
tion. Refer to the Flash Erase and Program
Operations tables in the AC Characteristics section for
parameters, and Figure 20 section for timing
diagrams.
Erase Suspend/Erase Resume
Commands
The Erase S uspend command , B0h, allows th e sys-
tem to interrupt a sector erase operation and then read
data fr om , or pr o gram dat a to , an y s ecto r n ot se lec te d
for erasure. The bank address is required when writing
this command. This command is valid only during the
sector erase operation, including the 50 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur-
ing the chip erase operation or Embedded Program
algorithm.
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation.
However, when the Eras e Suspend command is writ-
ten during the sector erase time-out, the device
imme diately termina tes the ti me-out period and sus-
pends the erase operation.
After the erase operation has been suspended, the
bank enters the erase-suspend-read mode. The sys-
tem c an read data fr om o r pr o gram data to an y s ector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Read ing at
any address within erase-suspended sectors pro-
duc es stat us infor mati on on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a s ector is actively eras ing or is erase-suspe nded.
Refer to the Write Operation Status section for infor-
mation on these status bits.
After an erase-suspended program operation is com-
plete, the bank returns to the erase-suspend-read
mode. The system c an determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard Byte Program operation.
Refer to the Write Operation Status section for more
information.
In the er ase- s usp end - read mod e, th e s yste m c an also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
To resume the sector erase operation, the system
must write the Erase Resume command. The bank
address of the erase-suspended bank is required
when writing this command. Further writes of the Re-
sume command are ignored. Another Erase Suspend
command can b e written afte r the chip has resu med
erasing.
Figur e 4. Erase Operation
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
Notes:
1. See Table 16 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
30 Am41DL16x4D
PRELIMINARY
Table 16. Command Definitions (Flash Word Mode)
Legend:
X = Don’t care
RA = Address of the m e mory lo c at ion to be re ad.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE#f pulse, whichever happens
later.
PD = Data to be programmed at location PA. Dat a latches on the rising
edge of WE# or CE#f pulse, whichever happens first.
SADD = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A12 uniquely select any sector.
BA = Address of the bank that is being switched to autoselect mode, is
in bypass mode, or is being erased.
Notes:
1. See Table 1 for description of bus operations.
2. All values ar e in hex adecimal .
3. Except for t he read cycle and the fourth cyc le of the au toselect
command seq uence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 ar e don’t care in command sequences,
except for RD and PD.
5. Unles s othe rwise no ted, address bi ts A19–A11 are don’t ca res.
6. No unlock or command cycles required wh en bank is in read
mode.
7. The Reset command is req uired to r eturn to read ing array data
(or to the erase-suspend -re ad m ode if previou sly in Er ase
Suspend) when a ba nk is in the autoselect mode, or if DQ5 goes
high (w hile the bank is providing sta tus information).
8. The fourth cyc le of the autoselect command sequenc e is a re ad
cycle. The system m ust pro vide the bank ad dres s to obtain the
ma nufacturer ID, devic e ID, or SecSi Sector factory pro tect
information. See the Autoselect Command Sequence section for
mo re infor m ation.
9. The data is 80h for factory locked and 00h for not factory locked.
10. The data is 00h for a n unprotec ted se ctor/se ctor bloc k and 01h
for a protect ed sector/sector block.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
12. The Unlock Bypass Reset command is required to return to
reading array data when the ban k is in the un loc k bypass mode.
13. The sys tem ma y read and pro g ram i n no n-er as i n g secto rs , or
enter the autoselect mode, when in the Erase Suspend mode.
The Eras e Suspend command is val id only during a sector erase
operation, and r equires the bank address.
14. The Erase Resume command is valid only during the Erase
Suspen d mode, and re qu i re s the ba nk addre ss .
15. Command is valid when device is ready to read array data or when
device is in autoselect mode.
Table 17. Aut oselect Device IDs (Word Mode)
T = Top Boot Sector, B = Bottom Boot Sector
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Autoselect (Note 8)
Manufactu rer ID 4 555 AA 2AA 55 (BA)555 90 (BA)X00 0001
Device ID 4 555 AA 2AA 55 (BA)555 90 (BA)X01 s ee Table 17
SecSi Sector Factory
Protect (Note 9) 4 555 AA 2AA 55 (BA)555 90 (BA)X03 0081/0001
Sector Protect Verify
(Note 10) 4 555 AA 2AA 55 (BA)555 90 (SA)X02 0000/0001
Enter SecSi Sector Region 3 555 AA 2AA 55 555 88
Exit SecSi Sector Region 4 555 AA 2AA 55 555 90 XXX 00
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Pr ogram
(Note 1 1) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 12) 2 BA 90 XXX 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SADD 30
Erase Suspend (Note 13) 1 BA B0
Erase Resume (Note 14) 1 BA 30
CFI Query (Note 15) 1 55 98
Device Autoselect Device ID
Am 29DL161D 2236 h (T) , 2239 h (B)
Am 29DL162D 222Dh (T), 222Eh (B)
Am 29DL163D 2228h (T), 222Bh (B)
Am 29DL164D 2233 h (T) , 2235 h (B)
Am41DL16x4D 31
PRELIMINARY
Table 18. Command Definitions (Flash Byte Mode)
Legend:
X = Don’t care
RA = Address of the m e mory lo c at ion to be re ad.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE#f pulse, whichever happens
later.
PD = Data to be programmed at location PA. Dat a latches on the rising
edge of WE# or CE#f pulse, whichever happens first.
SADD = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A12 uniquely select any sector.
BA = Address of the bank that is being switched to autoselect mode, is
in bypass mode, or is being erased.
Notes:
1. See Table 1 for description of bus operations.
2. All values ar e in hex adecimal .
3. Except for t he read cycle and the fourth cyc le of the au toselect
command seq uence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 ar e don’t care in command sequences,
except for RD and PD.
5. Unles s othe rwise no ted, address bi ts A19–A11 are don’t ca res.
6. No unlock or command cycles required wh en bank is in read
mode.
7. The Reset command is req uired to r eturn to read ing array data
(or to the erase-suspend -re ad m ode if previou sly in Er ase
Suspend) when a ba nk is in the autoselect mode, or if DQ5 goes
high (w hile the bank is providing sta tus information).
8. The fourth cyc le of the autoselect command sequenc e is a re ad
cycle. The system m ust pro vide the bank ad dres s to obtain the
ma nufacturer ID, devic e ID, or SecSi Sector factory pro tect
information. Data bits DQ15–DQ8 are don’t care. See the
Autoselect Command Sequence section for more information.
9. The data is 80h for factory locked and 00h for not factory locked.
10. The data is 00h for a n unprotec ted se ctor/se ctor bloc k and 01h
for a protect ed sector/sector block.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Progr am com m and.
12. The Unl ock Bypass Rese t command is require d to return to
reading array data w hen the ba nk is in the unl ock bypass mode.
13. The system may rea d and program in non-era sin g sectors, or
enter the autose lect mode, when in the Eras e Suspend mode.
The Eras e Suspend command is val id only during a sector erase
operation, and r equires the bank address.
14. The Erase Resume command is valid only during the Erase
Suspen d mode, and re qu i re s the ba nk addre ss .
15. Command is valid when device is ready to read array data or when
device is in autoselect mode.
Table 19. Autoselect Device IDs (Byte Mode)
T = Top Boot Sector, B = Bottom Boot Sector
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XX X F0
Autoselect (Note 8)
Manufacturer ID 4 AAA AA 555 55 AAA 90 00 01
Device ID 6 AAA AA 555 55 AA A 90 02 see Table 19
SecSi Sector Factory
Protect (Note 9) 4 AAA AA 555 55 (BA)
AAA 90 (BA)
X06 81/01
Sector Pr otect Verify
(Note 10) 4 AAA AA 555 55 AAA 90 (SA)
X04 00
01
Enter SecSi Sector Region 3 AAA AA 555 55 AAA 88
Exit SecSi Sector Region 4 AAA AA 555 55 AAA 90 XXX 00
Program 4 AAA AA 555 55 AAA A0 PA PD
Unlock Bypass 3 AAA AA 555 55 AA A 20
Unlock Bypass Program (Note 11) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 12) 2 XXX 90 XXX 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Sector Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SADD 30
Erase Suspend (Note 13) 1 BA B0
Erase Resume (Note 14) 1 BA 30
CFI Query (Note 15) 1 55 98
Device Autoselect Device ID
Am 29DL161D 36h (T), 39h (B)
Am 29DL162D 2D h (T), 2Eh (B)
Am 29DL163D 28h (T) , 2Bh (B)
Am 29DL164D 33h (T), 35h (B)
32 Am41DL16x4D
PRELIMINARY
WRITE OPERATION STATUS
Th e devic e provide s sever al bits to det ermine the sta-
tus of a p r ogra m o r eras e op erati on : D Q2 , D Q 3, D Q 5,
DQ6, and DQ7. Table 20 and the following subsec-
tions describe the function of these bits. DQ7 and DQ6
each offer a method for determining whether a pro-
gram or erase operation is complete or in progress.
The device also provides a hardware-based output
signal, RY/BY#, to determine whether an Embedded
Program or Erase operation is in progress or has been
completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Program or Erase
algorithm is in progress or completed, or whether a
bank is in Erase Suspend. Data# Polling is valid after
the r ising ed ge of the final WE# pulse in the command
sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also appl ies to
pro gramming during Eras e Suspen d. Whe n the E m-
bedded Program algorithm is complete, the device
outputs the da tum pr ogrammed to DQ7. The s ystem
mus t prov i de the pro gr am add res s to read v al id sta tus
information on DQ7. If a program address falls within a
pr otected sec tor, D ata # Po lling on DQ7 is activ e for
approximately 1 µs, then that bank returns to reading
arra y dat a.
During the Embedded Erase algorithm, Data# Polling
produ ces a “0” o n DQ7. When the Embedde d Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
Th e syst e m mu st pr ovid e an a ddr e ss wi thin an y of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
After an erase command sequence is written, if all
sect o rs sel ec te d for er a sing ar e prot ec ted , Dat a# P ol l-
ing on D Q7 is ac tive fo r ap proxima tely 100 µs, the n
the bank returns to reading array data. If not all se-
lected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected. However, if the
system reads DQ7 at a n address within a protected
sector, the status may not be valid.
Jus t prior to th e comp leti on of an Em bedd ed Progr am
or E ras e op erat io n, DQ 7 m ay ch an ge as y nch ro no us ly
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the statu s or valid data. Even if the device has c om-
pleted the program or erase o peration and DQ7 has
va lid data , the da ta out puts on DQ 0–D Q6 may be sti ll
in vali d. Vali d dat a o n DQ0 –DQ7 will ap pear on suc-
cessive read cycles.
Tabl e 2 0 sho w s th e o utp uts fo r Da ta# P olli ng on DQ 7.
Figur e 5 shows th e D ata # P ol ling alg or ithm . F igur e 22
in the AC Characteristics section shows the Data#
Polling timing diagram.
Figure 5. Data# Polling Algorithm
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for progr amming. During a sector
erase operation, a valid address is any sector address
within th e sector being erased . During ch ip er ase , a
valid address is any non-protected sector address.
2. DQ7 should be rechec ked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Am41DL16x4D 33
PRELIMINARY
RY/ BY#: Ready/Busy #
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the r ising ed ge of the final WE# pulse in the command
sequ en c e. Sin c e R Y / BY# is an op en -d r ai n out pu t , sev -
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If th e outp ut is low (B usy ), the de vi ce is a ctiv ely era s-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Re ady), the device is re ading array data, the stan dby
mode, or one of the banks is in the erase-sus-
pend-read mode.
Table 20 shows the outputs for RY/B Y#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bi t I ma y be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
Dur i ng a n Em be dd ed P r og ram or E ras e a lg or ithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE#f to control the read cycles. When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ 6 tog-
gle s for app roxi mate ly 100 µs , then re turns to read ing
array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
era se- s uspen de d. W he n th e de v ice i s a ctiv el y er asin g
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Sus-
pend mo de, D Q6 s top s to ggli ng. Howe ve r, th e syste m
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data#
Polling).
If a program address falls within a protected sector,
DQ 6 togg les for appro xim atel y 1 µs after th e pro gram
com m and s equ en ce is w ritte n, the n r et urns to read in g
arra y dat a.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 20 show s the o utputs for Toggle Bi t I on D Q6.
Figure 6 shows the toggle bit algorithm. Figure 23 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 24 shows the differences be-
tween DQ2 and DQ6 in graphical form. See als o the
subsec ti on on DQ2: To ggle Bit II.
Figure 6. Toggle Bit Algorithm
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle? No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Note: The system should re che ck the toggl e bit even if DQ5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more inf or mati on.
34 Am41DL16x4D
PRELIMINARY
DQ2: Toggle Bit II
The “Toggle Bi t II” on DQ2, w hen us ed wit h DQ6, ind i-
cates wheth er a particu lar sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE#f to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by c omparison , indicates whethe r the
dev ice is activ ely eras ing , or is in E rase S usp end, b ut
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 20 to compare out-
puts for DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchart
for m, and the secti on “DQ2: To ggle Bi t II” expl ai ns th e
algorithm. See also the DQ6: Toggle Bit I subsection.
Fig ure 23 show s the togg le bi t timi ng di agram . Fi gure
24 shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit
status , it must read DQ7–DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the firs t read. After the second read, the
syst em wo uld com pa re th e n ew valu e o f th e t ogg le bit
with the fir st. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see th e section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vi ce di d no t c omp leted the oper ati on succ e ssfu lly, an d
the system must write the reset command to return to
readin g array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ 5 has
not gone high . The sy stem m ay co ntinu e to moni tor
the to ggle bit and DQ5 through successive read cy-
cles, determining the status as described in the
previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, the system
must s tart at the be gi nni ng of the algor ithm when it re -
turns to determine the status of the operation (top of
Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time
has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1,” indicating
that the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries
to prog ram a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the ope ration, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Under both thes e conditio ns, the syste m must write
the reset command to return to reading array data (or
to the erase-suspend-read mode if a bank was previ-
ousl y in the erase -su sp end - prog ra m mo de).
DQ3: Sector Erase Timer
After writing a sector erase command seq uence, the
system may read DQ 3 to determine whether or not
erasure has begun. ( The s ector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase comman ds from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also t he Se ctor Erase Co mmand
Sequence section.
After the sector erase command is written, the system
shou ld r e ad th e s tat us o f DQ7 (D a ta# Po ll ing) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the E mbe dd ed E ras e al gori thm ha s b eg un; al l fur -
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following e ach subseq uent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
Tabl e 2 0 s ho ws the statu s of D Q 3 rel at ive t o th e o t he r
status bits.
Am41DL16x4D 35
PRELIMINARY
Table 20. Write Ope ratio n St a tus
Notes:
1. DQ5 switches to ‘1’ when an Embedded P rogram or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. When rea ding wr ite oper atio n status bits, t he system mu st alway s provi de the ban k address wher e the Embedded Alg orith m
is in progress. The device outputs array data if the system addresses a non-busy bank.
Status DQ7
(Note 2) DQ6 DQ5
(Note 1) DQ3 DQ2
(Note 2) RY/BY#
Standard
Mode Embedded Progr am Algo ri t hm DQ7# Toggl e 0 N/ A No toggle 0
Embed ded Eras e Alg or ithm 0 Toggle 0 1 Toggle 0
Erase
Suspend
Mode
Erase-Suspend-
Read
Erase
Suspended Sector 1 No toggle 0 N/A Toggle 1
Non-Erase
Suspended Sector Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
36 Am41DL16x4D
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage Temper ature
Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C
Amb ie nt Te mp erat ur e
with Power Applied . . . . . . . . . . . . . . –40°C to +85°C
Voltage wit h Respect to Ground
VCCf/VCCs (Note 1) . . . . . . . . . . . .–0.3 V to +4.0 V
OE# and RESET#
(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to + 10.5 V
All other pins (Note 1). . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figur e 7. During voltage t ra ns itions, input or I /O pi ns
may ov ers hoot t o VCC +2.0 V for peri ods u p t o 20 ns. Se e
Figure 8.
2. Minimum DC input voltage on pins OE#, RESET#, and
WP#/ACC is –0.5 V. During voltage transitions, OE#,
WP#/ACC, and RESET# may overshoot VSS to –2.0 V
for periods of up to 20 ns. See Figure 7. Maximum DC
input voltage on pin RESET# is +12.5 V which may
overshoot to +14.0 V for periods up to 20 ns. Maximum
DC input voltage on WP#/ACC is +9.5 V which may
overshoot to +12.0 V for periods up to 20 ns .
3. No more than one output may be shorted to ground at a
time. Durat ion of the short circuit sh ould not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress r ating only; functional o peration of t he d evice at
the se or any othe r condition s abov e those indic ated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Device s
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
VCCf/VCCs Supply Voltage
VCCf/VCCs for standard voltage range. . 2.7 V to 3.3 V
Op erati ng ran ges def ine t hose limi ts betwe en w hich the f unc-
tionality of the device is guaranteed.
Figure 7. Maximum Negative
Overshoot Waveform Figure 8. Maximum Posi tive
Overshoot Waveform
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
Am41DL16x4D 37
PRELIMINARY
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol Parameter Description Test Conditions M in Typ Max Unit
ILI Input Load Current VIN = VSS to VCC,
VCC = VCC max ±1.0 µA
ILIT RESET# Input Load Current VCC = VCC max; RESET# = 12.5 V 35 µA
ILO Output Leakage Cur rent VOUT = VSS to VCC,
VCC = VCC max ±1.0 µA
ILIA ACC Input Leakage Current VCC = VCC max,
WP#/ACC = VACC ma x 35 µA
ICC1fFlash V CC Active Read Current
(N otes 1, 2) CE#f = VIL, OE# = VIH,
Word Mode 5 MHz 10 16 mA
1 MHz 2 4
ICC2fFlash V CC Active Write Current
(N otes 2, 3) CE#f = VIL, OE # = VIH, WE# = VIL 15 30 mA
ICC3fFlash V
CC Standby Current (Note 2) VCCf = VCC max, CE#f, RESET#,
WP#/ACC = VCCf ± 0.3 V 0.2 5 µA
ICC4fFlash V
CC Reset Current (Note 2) VCCf = VCC max, RESET# = VSS ±
0.3 V, W P #/AC C = VCCf ± 0.3 V 0.2 5 µA
ICC5fFlash V CC Current Automatic Sleep
Mode (Notes 2, 4) VCCf = VCC max , VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V 0.2 5 µA
ICC6fFlash V CC Active
Read-While-Program Current (Notes
1, 2) CE#f = VIL, OE# = VIH 21 45 mA
ICC7fFlash V CC Act ive Read-While-E rase
Current (Notes 1, 2) CE#f = VIL, OE# = VIH 21 45 mA
ICC8fFlash V CC Active
Program-While-Erase-Suspended
Current (Notes 2, 5) CE#f = VIL, OE#f = VIH 17 35 mA
IACC ACC Accelerated Program Current CE#f = VIL, OE# = VIH ACC pin 5 10 mA
VCC pin 15 30 mA
ICC4sSRAM V
CC Standby Current CE1#s ≥ VCCs – 0.2 V, CE2s ≥
VCCs – 0.2V 10 µA
ICC5sSRAM V
CC Standby Current CE2s ≤ 0.2 V 10 µA
VIL Input Low Voltage –0.2 0.8 V
VIH Input High Voltage 2.4 VCC + 0. 2 V
VHH
Voltage for WP#/ ACC Progr am
Acceleration and Sector
Protection/Unprotection 8.5 9.5 V
VID
Voltage for Sector Protection,
Autoselect and Temporary Sector
Unprotect 8.5 12.5 V
VOL Output Low Vol tage IOL = 4.0 mA, VCCf = VCCs =
VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.0 mA, VCCf = VCCs =
VCC min 0.85 x
VCC V
VOH2 IOH = –100 µA, V CC = VCC min VCC–0.4
38 Am41DL16x4D
PRELIMINARY
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC spec ific at ion s are t es ted wit h VCC = VCCmax.
3. ICC act iv e whil e Embedded E ras e or Embedded P rogr am i s i n progre ss .
4. Automati c sleep mode enable s the low pow er mode whe n addresses remain stabl e for tACC + 30 ns . Typical sleep m ode current is
200 nA.
5. Not 100% tested.
VLKO Flash Low VCC Lock-Out Voltage
(Note 5) 2.3 2.5 V
SRAM DC AND OPERATING CHARACTERISTI CS
Parameter
Symbol Parameter Description Test Conditions Min Typ Ma x Unit
ILI Input Leakage Current VIN = VSS to VCC –1.0 1.0 µA
ILO Output Leakage Cur rent CE1#s = V IH, CE2s = VIL or O E# =
VIH or WE# = V IL, VIO= VSS to VCC –1.0 1.0 µA
ICC1s Average Operating Current
Cycle time = 1 µs, 100% duty,
IIO = 0 mA, CE1#s ≤ 0.2 V,
CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
3mA
ICC2s Average Operating Current Cycle time = Min., IIO = 0 mA,
100% duty, CE1# s = VIL, CE2 s =
VIH, VIN = VIL = o r VIH
22 mA
VOL Output Low Vol tage IOL = 2.1 mA 0.4 V
VOH Output High Voltage IOH = –1.0 mA 2.4 V
ISB1 Standby Current (CMOS)
CE1#s ≥ VCC – 0.2 V, CE2 ≥ VCC –
0.2 V (CE1#s controlled) or 0 V ≤
CE2 ≤ 0.2 V (CE2s controlled),
CIOs = VSS or V CC, Other in put = 0
~ VCC
10 µA
DC CHARACTERISTICS (Con tinued)
CMOS Compatible
Parameter
Symbol Parameter Description Test Conditions M in Typ Max Unit
Am41DL16x4D 39
PRELIMINARY
DC CHARACTERISTICS
Zero-Power Flash
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
25
20
15
10
5
00 500 1000 1500 2000 2500 3000 3500 4000
Supply Cur rent in mA
Time in ns
10
8
2
0
12345
Frequency in MHz
Supply Current in mA
Note: T = 25 °C
Figure 10. Typical ICC1 vs. Frequency
2.7 V
3.3 V
4
6
12
40 Am41DL16x4D
PRELIMINARY
TEST CONDITIONS
Table 21. Test Specifications
KEY TO SWITCHING WAVEFORMS
2.7 kΩ
CL6.2 kΩ
3.3 V
Device
Under
Test
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
Test Condition 70, 85 ns Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig capacitance) 30 pF
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V
Input timing measurement reference
levels 1.5 V
Output tim ing measurement
reference levels 1.5 V
KS000010-PAL
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
3.0 V
0.0 V 1.5 V 1.5 V OutputMeasurement LevelInput
Figure 12. Input Waveforms and Measurement Levels
Am41DL16x4D 41
PRELIMINARY
AC CHARACTERISTICS
SRAM CE#s Timing
Figure 13. Timing Diagram for Alternating Between
SRAM to Flash
Parameter
Description Test Setup All Speed Options Unit
JEDEC Std
—tCCR CE# s Rec ov er Time —Min 0 ns
CE#f
tCCR tCCR
CE1#s
CE2s tCCR tCCR
42 Am41DL16x4D
PRELIMINARY
AC CHARACTERISTICS
Flash Read-Only Operations
Notes:
1. Not 100% tested.
2. See Figur e 11 a nd Table 21 for tes t specif i cations.
Parameter
Description Test Setup Speed Options Unit
JEDEC Std 70 85
tAVAV tRC Read Cycle Time (Note 1) Min 70 85 ns
tAVQV tACC Address to Output Delay CE#f, OE# = VIL Max 70 85 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 85 ns
tGLQV tOE Output Enable to Output Delay Max 30 35 ns
tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns
tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns
tAXQX tOH Output Hold Time Fr om A ddr es s es , CE#f or
OE#, Whichever Occurs First Min 0 ns
tOEH Output Enable Hold
T ime (No t e 1 )
Read Min 0 ns
Toggle and
Data# Polling Min 10 ns
tOH
tCE
Outputs
WE#
Addresses
CE#f
OE#
HIGH Z
Output V alid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tRH
tOE
tRH
0 V
RY/BY#
RESET#
tDF
Figure 14. Read Operation Timings
Am41DL16x4D 43
PRELIMINARY
AC CHARACTERISTICS
Hardware Reset (RESET#)
Note: Not 100% tested.
Parameter Descri pt i on All Spee d Optio ns Unit
JEDEC Std
tReady RESE T# Pin Low (During Embedded Algorithms) to
Read Mode (See Note) Max 20 µs
tReady RES ET# Pin Low (NOT Dur ing Embedded A lgorith ms) to
Read Mode (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH Reset High Time Before Read (See Note) Min 50 ns
tRPD RESET# Low to Standby Mode Min 20 µs
tRB RY/BY# Recovery Time Min 0 ns
RESET#
RY/BY#
RY/BY#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE#f, OE#
tRH
CE#f, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
tRB
Figure 15. Reset Timi ngs
44 Am41DL16x4D
PRELIMINARY
AC CHARACTERISTICS
Flash Word/Byte Configuration (CIOf)
Parameter Speed Options
JEDEC Std Description 70 85 Unit
tELFL/tELFH CE#f to CIOf Switching Low or High Max 5 ns
tFLQZ CIOf Switching Low to Output HIGH Z Max 25 30 ns
tFHQV C IOf Switching High to Output Active Min 7 0 85 ns
DQ15
Output
Data Output
(DQ7–DQ0)
CE#f
OE#
CIOf
tELFL
DQ14–DQ0 Data Output
(DQ14–DQ0)
DQ15/A-1 Address
Input
tFLQZ
CIOf
Switching
from word
to byte
mode
DQ15
Output
Data Output
(DQ7–DQ0)
CIOf
tELFH
DQ14–DQ0 Data Output
(DQ14–DQ0)
DQ15/A-1 Address
Input
tFHQV
CIOf
Switching
from byte
to word
mode
Figure 16. CIOf Timings for Read Operations
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 17. CIOf Timings for Write Operations
CE#f
WE#
CIOf
The falling edge of the last WE# signal
tHOLD (tAH)
tSET
(tAS)
Am41DL16x4D 45
PRELIMINARY
AC CHARACTERISTICS
Flash Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming P erformance” secti on f or more inf ormati on .
Parameter Speed Optio ns Unit
JEDEC Std Description Min 70 85
tAVAV tWC Write Cycle Time (Note 1) Min 70 85 ns
tAVWL tAS Address Setup Time (WE# to Address) Min 0 ns
tASO Address Setup Time to OE# or CE#f low during toggle bit
polling Min 15 ns
tWLAX tAH Address Hold Time (WE# to Address) Min 45 ns
tAHT Addres s Hold Time From CE#f or OE# high during toggle bit
polling Min 0 ns
tDVWH tDS Data Setup Time Min 3 5 ns
tWHDX tDH Data Hold Time M in 0 ns
tOEH OE# Hold Time Read Min 0 ns
Toggle and Data# Polling Min 10 ns
tOEPH Output Enable High dur ing toggle bit polling Min 20 ns
tGHEL tGHEL Read Recovery Time Before Write (OE# High to CE#f Low) M in 0 ns
tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns
tWLEL tWS WE# Setup Time (CE#f to WE#) Min 0 ns
tELWL tCS CE#f Setup Time (WE# to CE#f) Min 0 ns
tEHWH tWH WE# Hold Time (CE#f to WE#) Min 0 ns
tWHEH tCH CE#f Hold Time (CE#f to WE#) Min 0 ns
tWLWH tWP Writ e Pul s e Width M in 30 35 ns
tELEH tCP CE#f Pulse Width Min 30 35 ns
tWHDL tWPH Write Pulse Width High Min 0 ns
tSR/W Latency Between Read and Write Operations Min 0 ns
tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 7 µs
tWHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ 4 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec
tVCS VCCf Setu p Time ( Note 1) M in 50 µs
tRB Write Recov ery Time from RY/BY# M in 0 ns
tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns
46 Am41DL16x4D
PRELIMINARY
AC CHARACTERISTICS
Figure 19. Accelerated Program Timing Diagram
OE#
WE#
CE#f
V
CC
f
Data
Addresses
t
DS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h PA PA
Read Status Data (last two cycles)
A0h
t
GHWL
t
CS
Status D
OUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
t
BUSY
t
CH
PA
N
otes:
1
. PA = program address, PD = program data, DOUT is the true data at the program address.
2
. Illus tration shows device in word mode.
Figure 18. Program Operati on Timings
WP#/ACC tVHH
VHH
VIL or VIH VIL or VIH
tVHH
Am41DL16x4D 47
PRELIMINARY
AC CHARACTERISTICS
OE#
CE#f
Addresses
V
CC
f
WE#
Data
2AAh SADD
t
GHWL
t
AH
t
WP
t
WC
t
AS
t
WPH
555h for chip erase
10 for Chip Erase
30h
t
DS
t
VCS
t
CS
t
DH
55h
t
CH
In
Progress Complete
t
WHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
RY/BY#
t
RB
t
BUSY
Notes:
1. SADD = sector ad dres s (f or Sec tor Er ase), VA = V ali d Addr es s for r eading status dat a (see “Writ e Oper at i on Stat u s”).
2. These wavefor ms are f or the wo rd m ode.
Figure 20. Chip/Sector Erase Operation Timings
48 Am41DL16x4D
PRELIMINARY
AC CHARACTERISTICS
OE#
WE#
Addresses
t
OH
Data
Valid
In Valid
In
Valid PA Valid RA
t
WC
t
WPH
t
AH
t
WP
t
DS
t
DH
t
RC
t
CE
Valid
Out
t
OE
t
ACC
t
OEH
t
GHWL
t
DF
Valid
In
CE#f Controlled Write CyclesWE# Controlled Write Cycle
Valid PA Valid PA
t
CP
t
CPH
t
WC
t
WC
Read Cycle
t
SR/W
CE#f
Figure 21. Back-to-back Read/Write Cycle Timings
WE#
CE#f
OE#
High Z
tOE
High Z
DQ7
DQ6–DQ0
RY/BY#
tBUSY
Complement True
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
tACC
tRC
Note: VA = Valid address. Illustration shows first status cycle after command sequence, las t status read cycle, and array data
read cycle.
Figure 22. Data# Polling Timings (During Embedded Algorithms)
Am41DL16x4D 49
PRELIMINARY
AC CHARACTERISTICS
OE#
WE#
Addresses
tOEH
tDH
tAHT
tASO
tOEPH
tOE
Valid Data
(first read) (second read) (stops toggling)
tCEPH
tAHT
tAS
DQ6/DQ2 Valid Data
Valid
Status Valid
Status Valid
Status
RY/BY#
CE#f
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequenc e, last status
read cycle, and array data read c ycle
Figure 23. Toggle Bit Timings (During Embedded Algorithms)
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to
toggle DQ2 and DQ6.
Figure 24. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
50 Am41DL16x4D
PRELIMINARY
AC CHARACTERISTICS
Temporary Sector/Sector Block Unprotect
Note: Not 100% tested.
Parameter All Speed Options Unit
JEDEC Std Description
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tVHH VHH Rise and Fall Tim e (See Note) Min 250 ns
tRSP RESET# Setup Time for Temporary
Sector/Sector Block Unprotect Min 4 µs
tRRB RESET# Hold Time from RY/BY# High for
Temporary Sector/Sector Block Unprotect Min 4 µs
RESET#
tVIDR
VID
VSS, VIL,
or VIH
VID
VSS, VIL,
or VIH
CE#f
WE#
RY/BY#
tVIDR
tRSP
Program or Erase Command Sequence
tRRB
Figure 25. Temporary Sector/Sector Block Unprotect
Timing Diagram
Am41DL16x4D 51
PRELIMINARY
AC CHARACTERISTICS
Sector/Sector Block Protect: 150 µs,
Sector/Sector Block Unprotect: 15 ms
1 µs
RESET#
SADD, A6,
A1, A0
Data
CE#f
WE#
OE#
60h 60h 40h
Valid* Valid* Valid*
Status
Sector/Sector Block Protect or Unprotect Verify
V
ID
V
IH
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A 1 = 1, A0 = 0. SADD = S ector Address
Figure 26. Sector/Sector Block Protect and Unprotect
Timing Diagram
52 Am41DL16x4D
PRELIMINARY
AC CHARACTERISTICS
Alternat e CE#f Con t rolled Era se and Pro gram Ope rat ions
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming P erformance” secti on f or more inf ormati on .
Parameter Speed Options
JEDEC Std Description 70 85 Unit
tAVAV tWC Write Cycle Time (Note 1) Min 70 85 ns
tAVWL tAS Address Setup Time (WE# to Address) Min 0 ns
tASO Address Setup Time to CE#f Low During Toggle
Bit Polling Min 15 ns
tELAX tAH Address Hold Time Min 45 ns
tAHT Addres s Hol d time from C E#f or O E # Hi gh During
Toggle Bi t Poll ing Min 0 ns
tDVEH tDS Data Setup Time Min 35 ns
tEHDX tDH Data Hold Time Min 0 ns
tGHEL tGHEL Read R ecovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time M in 0 ns
tELEH tCP CE#f Pulse Width Min 30 35 ns
tEHEL tCPH CE #f Pulse Widt h High Min 30 35 ns
tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 7 µs
tWHWH1 tWHWH1 Accelerated P rogramming Operation (Note 2) Typ 4 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec
Am41DL16x4D 53
PRELIMINARY
AC CHARACTERISTICS
tGHEL
tWS
OE#
CE#f
WE#
RESET#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7# D
OUT
tWC tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tRH
tWHWH1 or 2
RY/BY#
tWH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase PA for program
SADD for sector erase
555 for chip erase
tBUSY
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = progr am addres s, S ADD = sector addr ess, PD = progr am data .
3. DQ7# i s the c omplement of the data written to t he d evi ce. DOUT is the data wr itt en t o the dev ice .
4. Waveforms are for the word mode.
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings
54 Am41DL16x4D
PRELIMINARY
AC CHARACTERISTICS
SRAM Read Cycle
Note: CE1#s = OE# = VIL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL
Figure 28. SRAM Read Cycle—Address Controlled
Parameter
Symbol Description Speed Options Unit
70 85
tRC Read Cycle Time Min 70 85 ns
tAA Address Access Time Max 70 85 ns
tCO1, tCO2 Chip Enable to Output Max 70 85 ns
tOE Output Enable Access Time Max 35 45 ns
tBA LB#s, UB#s to Valid Output M ax 70 85 ns
tLZ1, tLZ2 Chip Enable (CE1#s Low and CE2s High) to Low-Z
Output Min 10 ns
tBLZ UB#, LB# Enable to Low-Z Output Min 10 ns
tOLZ Output Enable to Low-Z Output Min 5 ns
tHZ1, tHZ2 Chip disable to High-Z Output Min 0 ns
Max 25
tBHZ UB#s, LB#s Disable to High-Z Output Min 0 ns
Max 25
tOHZ Output Disable to High-Z Output Min 0 ns
Max 25
tOH Output Data Hold from Address Change Min 10 15 ns
Address
Data Out Previous Data Valid Data Valid
tAA
tRC
tOH
Am41DL16x4D 55
PRELIMINARY
AC CHARACTERISTICS
Figure 29. SRAM Read Cycle
Notes:
1. WE# = VIH, if CIOs is low, ignore UB#s/LB#s timing.
1. tHZ and t OHZ are defined a s the time at which the output s ac hie ve t he open circu it co nditions an d are not ref erenc ed to outp ut
voltage levels.
2. At any giv en temperatur e and voltage condit ion, tHZ (Max.) is less than tLZ (Min.) both for a gi ven device and f rom device to devic e
interconnection.
Data Valid
High-Z
tRC
CS#1
Address
UB#, LB#
OE#
Data Out
tOH
tAA
tCO1
tBA
tOE
tOLZ
tBLZ
tLZ
tOHZ
tBHZ
tHZ
CS2 tCO2
56 Am41DL16x4D
PRELIMINARY
AC CHARACTERISTICS
SRAM Write Cycle
Notes:
1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.
2. tCW is measure d from CE1#s going low to the end of wri te.
3. tWR is measured from t he end of wr it e to th e addr ess cha nge. t WR applie d in c ase a writ e ends a s CE1 #s or WE# goi ng high.
4. tAS is measured f rom the addr ess val id to t h e beginning of write.
5. A wr ite occurs du ri ng the overlap (tWP) of low CE#1 and low WE#. A write begins when CE 1#s goes low and WE# goes low when
asse rti ng UB#s or LB#s for a sing le by t e oper ation or s imu ltaneous ly asser t ing UB #s an d LB#s f or a double byte operation. A
write ends at the earliest tra nsi t ion when CE1#s goes high and WE# goes h igh. T he tWP is measured f r om the beg inni ng of wr ite
to th e end of wr ite. Figur e 30. SRAM Write Cycle—WE# Control
Parameter
Symbol Description Speed Options Unit
70 85
tWC Write Cycle Time Min 70 85 ns
tCw Chip Enable to End of Write Min 60 70 ns
tAS Address Setup Time Min 0 ns
tAW Address Valid to End of Write Min 60 70 ns
tBW UB#s, LB#s to End of Write Min 60 70 ns
tWP Write Pulse Time Min 50 60 ns
tWR Write Recovery Time Min 0 ns
tWHZ Write to Output High-Z Min 0 ns
Max 20 25
tDW Data to Write Time Overlap Min 30 35 ns
tDH Data Hold from Write Time M in 0 ns
tOW End Wr ite to Output Low-Z Min 5 ns
Address
CS1#s
Data Undefined
UB#s, LB#s
WE#
Data In
Data Out
tWC
tCW
(See Note 2)
tAW
High-Z High-Z
Data Valid
CS2s tCW
(See Note 2)
tBW
tWP
(See Note 5)
tAS
(See Note 4)
tWR (See Note 3)
tBW
tDW tDH
tOW
Am41DL16x4D 57
PRELIMINARY
AC CHARACTERISTICS
Notes:
1. CE1#s controlled, if CIO s is low, ignore UB#s and LB#s timing.
2. tCW is measure d from CE1#s going low to the end of wri te.
3. tWR is measured from t he end of wr it e to th e addr ess cha nge. t WR applie d in c ase a writ e ends a s CE1 #s or WE# goi ng high.
4. tAS is measured f rom the addr ess val id to t h e beginning of write.
5. A wr ite occurs du ri ng the overlap (tWP) of low CE#1 and low WE#. A write begins when CE 1#s goes low and WE# goes low when
asse rti ng UB#s or LB#s for a sing le by t e oper ation or s imu ltaneous ly asser t ing UB #s an d LB#s f or a double byte operation. A
write ends at the earliest tra nsi t ion when CE1#s goes high and WE# goes h igh. T he tWP is measured f r om the beg inni ng of wr ite
to th e end of wr ite. Figure 31. SRAM Write Cycle—CE1#s Control
Address
Data Valid
UB#s, LB#s
WE#
Data In
Data Out High-Z High-Z
tWC
CE1#s
CE2s
tAW
tAS (See Note 2 )
tBW
tCW
(See Note 3) tWR (See Note 4)
tWP
(See Note 5)
tDW tDH
58 Am41DL16x4D
PRELIMINARY
AC CHARACTERISTICS
Notes:
1. UB#s and LB#s controlled, CIOs must be high.
2. tCW is measure d from CE1#s going low to the end of wri te.
3. tWR is measured from t he end of wr it e to th e addr ess cha nge. t WR applie d in c ase a writ e ends a s CE1 #s or WE# goi ng high.
4. tAS is measured f rom the addr ess val id to t h e beginning of write.
5. A wr ite occurs du ri ng the overlap (tWP) of low CE#1 and low WE#. A write begins when CE 1#s goes low and WE# goes low when
asse rti ng UB#s or LB#s for a sing le by t e oper ation or s imu ltaneous ly asser t ing UB #s an d LB#s f or a double byte operation. A
write ends at the earliest tra nsi t ion when CE1#s goes high and WE# goes h igh. T he tWP is measured f r om the beg inni ng of wr ite
to th e end of wr ite. Figure 32. SRAM Write Cycle—UB#s and LB#s Control
Address
Data Valid
UB#s, LB#s
WE#
Data In
Data Out High-Z High-Z
tWC
CE1#s
CE2s
tAW
tBW
tDW tDH
tWR (See Note 3)
tAS
(See Note 4)
tCW
(See Note 2)
tCW (See Note 2)
tWP
(See Note 5)
Am41DL16x4D 59
PRELIMINARY
FLASH ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assum e the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles . Additionally,
programming typicals assume checkerboard pattern.
2. Under wor s t cas e con ditions of 90°C, VCC = 2.7 V, 1,0 00, 000 c ycles .
3. The ty pic al c hip p rogramm ing time is co nsi derab ly les s than t he maxi mum chi p pro gram ming time l is ted, si nce most by t eswords
progr am fast er than t he m axi mum program times l is ted.
4. In th e pre- progr ammi ng s tep of the Em bedded E ra se algor it hm, al l bytewor ds ar e pr ogramme d to 00h bef or e er as ure.
5. Syst em-lev el o ver head is t he tim e r equir ed t o exe cute t h e t wo- or f our-bus-cycle sequence f or the pr ogr am c ommand. Se e Table
16 f or fur ther infor mation on command defin itions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
FLASH LATCHUP CHARACTERISTICS
Note: Includes all pins except V CC. Test conditions: VCC = 3.0 V, one pin at a time.
PACKAGE PIN CAPACITANCE
Note: 7.Test conditions TA = 25°C, f = 1.0 MHz.
FLASH DATA RETE NTION
Pa ramete r Typ (Note 1) Max (Note 2) Un it Comments
Sector Erase Time 0.7 15 sec Excl udes 00h pr ogr ammi ng
prior to erasure (Note 4)
Chip Er as e Time 27 sec
Byte Program Time 5 150 µs
Word Program Time 7 210 µs
Excludes s yst em level
overhead (Note 5)
Accelerated Byte/Word Program Time 4 120 µs
Byte Mode 9 27
Chip Pr ogr am T ime
(Note 3) Word Mode 6 18 sec
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
(including OE# and RESET#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Parameter
Symbol Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 1114pF
COUT O utput C apacitance VOUT = 0 1216pF
CIN2 Control Pin Capaci tance V IN = 0 1416pF
CIN3 WP#/ACC Pin Capacit a nce VIN = 0 1720pF
Parameter Description Test Conditions Min Unit
Minimum Pattern Data Retention Time 150°C 10 Years
125°C 20 Years
Am41DL16x4D 60
PRELIMINARY
SRAM DATA RETE NTION
Notes:
1. CE1#s ≥ VCC – 0.2 V, CE2s ≥ VCC – 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled), CIOs = VSS or VCC.
2. Typical values are not 100% tested.
Figure 33. CE1#s Controlled Data Retention Mode
Figure 34. CE2s Controlled Data Retention Mode
Parameter
Symbol Para met er Desc ri pt i on Test Setup Min Typ Max Unit
VDR VCC for Data Retention CS1#s ≥ VCC – 0.2 V (Note 1) 1.5 3.3 V
IDR Data Retention Current VCC = 3.0 V, CE1#s ≥ VCC – 0.2 V
(Note 1) 1.0
(Note 2) 10 µA
tSDR Data Retention Set-Up Time See data retention waveforms 0ns
tRDR Recovery Time tRC ns
VDR
VCC
2.7V
2.2V
CE1#s
GND
Data Retention Mode
CE1#s ≥ VCC
-
0.2 V, CE2s ≥ VCC
-
0.2 V
tSDR tRDR
VCC
2.7 V
0.4 V
VDR
CE2s
GND
Data Retention Mode
tSDR tRDR
CE2s £ 0.2 V
61 Am41DL16x4D
PRELIMINARY
PHYSICAL DIM E NSI ONS
FLA069—69-Ball Fine-Pitch Grid Array 8 x 11 mm
8.00 BSC
1.40 (max)
0.20 (min)
1
2
3
4
5
6
7
8
9
10
ABCDEFGHJK
0.80
7.20 BSC
0.80
7.20 BSC
(69x)
Pin A1
Corner Index Mark
11.00 BSC
0.08
0.15 MB
MC
CA
0.40
DATUM A
DATUM B
B
A
0.08
0.97
1.07
C
0.20 C
0.15 C
(2x)
0.15 C
(2x)
C
0.40
0.25
0.35
Am41DL16x4D 62
PRELIMINARY
REVISION SUMM ARY
Revision A (October 24, 2001)
Initial release.
Trademarks
Copyright © 2001 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for ident ificat ion purposes only and may be trademarks of their respective companies.
