9.3 GHz Latched Comparator with RSPECL Output Stage HMC674LC3C/HMC674LP3E Data Sheet FUNCTIONAL BLOCK DIAGRAM HYS 13 VEE RTN 14 16 VCCI 15 HMC674LC3C/HMC674LP3E VTP 1 12 VCCO INP 2 50 11 Q INN 3 50 10 Q 6 7 8 LE LE NIC 9 VCCO PACKAGE BASE VEE APPLICATIONS Automatic test equipment (ATE) applications High speed instrumentation Digital receiver systems Pulse spectroscopy High speed trigger circuits Clock and data restoration 14861-001 VTN 4 5 Equivalent input bandwidth: 9.3 GHz typical Propagation delay: 85 ps typical Overdrive and slew rate dispersion: 10 ps typical Input signal minimum pulse width: 60 ps typical Resistor programmable hysteresis Differential latch control Power dissipation: 140 mW typical 16-terminal, 3 mm x 3 mm, ceramic leadless chip carrier (LCC) 16-lead lead frame chip scale package (LFCSP) VCCI FEATURES Figure 1. HMC674LC3C/HMC674LP3E Functional Block Diagram GENERAL DESCRIPTION The HMC674LC3C/HMC674LP3E are silicon germanium (SiGe), monolithic, ultrafast comparators that feature reduced swing positive emitter-coupled logic (RSPECL) output drivers and latch inputs. These comparators support 10 Gbps operation and provide 85 ps propagation delay and an input signal minimum pulse width of 60 ps with 0.2 ps rms of random jitter (RJ). Overdrive and slew rate dispersion is typically 10 ps, making the HMC674LC3C/HMC674LP3E ideal for a wide range of Rev. K applications from ATE to broadband communications. The RSPECL output stages directly drive 400 mV into a 50 resistor terminated to VTT = (VCCO - 2.0 V), where VTT is the PECL termination voltage (see Figure 16). The HMC674LC3C/ HMC674LP3E feature a high speed latch and programmable hysteresis. These devices can operate in either latch mode or as a tracking comparator. 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Technical Support www.analog.com HMC674LC3C/HMC674LP3E Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Pin Configurations and Function Descriptions ............................7 Functional Block Diagram .............................................................. 1 Interface Schematics .....................................................................8 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................9 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 10 Specifications..................................................................................... 3 Power Sequencing ...................................................................... 10 Latch Enable (LE/LE) Specifications ......................................... 3 Applications Information .............................................................. 11 DC Output Specifications ........................................................... 3 Evaluation Printed Circuit Board (PCB)................................. 11 AC Specifications.......................................................................... 4 Application Circuits ................................................................... 12 Power Supply Specifications........................................................ 4 Outline Dimensions ....................................................................... 13 Timing Descriptions .................................................................... 5 Ordering Guide .......................................................................... 13 Absolute Maximum Ratings ............................................................ 6 REVISION HISTORY Two Hittite Mircrowave product data sheets have been reformatted to the styles and standards of Analog Devices, Inc., and combined into one data sheet. 12/2016--v12.0616 (HMC674LC3C and HMC674LP3E) to Rev. K Updated Format .................................................................. Universal Changes to Title, Features Section, and General Description Section ................................................................................................ 1 Changes to Table 7 ............................................................................ 6 Changes to Table 8 ............................................................................ 7 Changes to Figure 10 ........................................................................ 9 Changed Operational Description Section to Theory of Operation Section ........................................................................... 10 Changes to Figure 15 and Table 9 ................................................. 12 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 13 Rev. K | Page 2 of 14 Data Sheet HMC674LC3C/HMC674LP3E SPECIFICATIONS TA = 25C, VCCI = 3.3 V, VCCO = 2.0 V, VEE = -3 V, VTT = 0 V, unless otherwise noted. Table 1. Parameter INPUT Voltage Range Differential Voltage Offset Voltage (VOS) Temperature Coefficient Bias Current Temperature Coefficient Offset Current Impedance Common-Mode Differential Active Gain Common-Mode Rejection Ratio (CMRR) Hysteresis, RHYS = Infinity Min Typ -2 -1.75 Max Unit +2 +1.75 V V mV V/C A nA/C A k k dB dB mV 5 15 15 50 4 50 350 15 48 80 1 LATCH ENABLE (LE/LE) SPECIFICATIONS Table 2. Parameter LATCH ENABLE (LE/LE) Input Impedance To Output Delay Minimum Pulse Width Input Range LATCH ENABLE (LE/LE) TIME Setup Hold Symbol Min Typ Max Unit Test Conditions/Comments 2.4 k ps ps V Each pin Input overdrive voltage (VOD) = 200 mV VOD = 200 mV VOD = 200 mV ps ps VOD = 200 mV 8 85 20 tPLOL, tPLOH tPL 1.6 tS tH 45 -42 DC OUTPUT SPECIFICATIONS VCCO = 2.00 V, VTT = 0 V, unless otherwise noted. Table 3. Parameter OUTPUT VOLTAGE High Level Low Level Differential Swing Symbol Min Typ Max Unit VOH VOL 1.03 0.65 440 1.09 0.71 760 1.14 0.81 980 V V mV p-p Rev. K | Page 3 of 14 HMC674LC3C/HMC674LP3E Data Sheet AC SPECIFICATIONS Table 4. Parameter PROPAGATION DELAY (tPDL, tPD, tPDH) Temperature Coefficient Skew (Rising to Falling Transition) VOD 1 DISPERSION PROPAGATION DELAY (tPD) vs. INPUT COMMON-MODE VOLTAGE (VCM) DISPERSION NOISE (RETURN TO INPUT, RTI) EQUIVALENT INPUT BANDWIDTH (BWEQ) 2 JITTER Deterministic Random INPUT SIGNAL MINIMUM PULSE WIDTH Q/Q TIME Rise Fall 1 2 Min 80 8.6 Typ 85 0.45 10 10 8 5.9 9.3 Max 110 12 Unit ps ps/C ps ps ps Test Conditions/Comments VOD = 500 mV VOD = 500 mV 50 mV < VOD < 1 V VOD = 500 mV, -1.75 V < VCM < +1.75 V nV/Hz GHz 10 Gbps with 100 mV overdrive 2 0.2 60 ps p-p ps rms ps 24 15 ps ps VCM = 0 V, 100 mV overdrive From 20% to 80% VOD is the input overdrive voltage, for example, (VINP - VINN - VOS), where VOS is the input offset voltage. Equivalent input bandwidth is calculated by BWEQ = 0.22/ (TRCOMP 2 - TRIN 2 ) where: TRIN is the 20%/80% transition time of a quasi Gaussian signal applied to the comparator input. TRCOMP is the effective transition time digitized by the comparator. POWER SUPPLY SPECIFICATIONS Table 5. Parameter VOLTAGE Power Supply Voltage Input Stage Power Supply Voltage Output Stage Negative Power Supply (-3 V) CURRENT Supply Input Supply Output VEE POWER DISSIPATION POWER SUPPLY REJECTION RATIO VCCI VEE Symbol Min Typ Max Unit VCCI VCCO VEE 3.135 1.8 -3.15 3.3 3.3 -3.0 3.465 3.465 -2.85 V V V ICCI ICCO IEE PD PSRR Rev. K | Page 4 of 14 9 45 19 140 mA mA mA mW 38 38 dB dB Data Sheet HMC674LC3C/HMC674LP3E TIMING DESCRIPTIONS Table 6. Parameter Input to Output High Delay Symbol tPDH Input to Output Low Delay tPDL Latch Enable (LE/LE) to Output High Delay tPLOH Latch Enable (LE/LE) to Output Low Delay tPLOL Minimum Hold Time tH Minimum Latch Enable (LE/LE) Pulse Width tPL Minimum Setup Time tS Output Rise Time tR Output Fall Time tF Input Overdrive Voltage VOD Description The propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output low to high transition. The propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output high to low transition. The propagation delay measured from the 50% point of the latch enable (LE/LE) signal high to low transition to the 50% point of an output low to high transition. The propagation delay measured from the 50% point of the latch enable (LE/LE) signal high to low transition to the 50% point of an output high to low transition. The minimum time after the positive transition of the latch enable (LE/LE) signal that the input signal must remain unchanged to be acquired and held at the outputs. The minimum time that the latch enable (LE/LE) signal must be low to acquire an input signal change. The minimum time before the positive transition of the latch enable (LE/LE) signal that an input signal change must be present to be acquired and held at the outputs. The amount of time required to transition from a low to a high output as measured at the 20% and 80% points. The amount of time required to transition from a high to a low output as measured at the 20% and 80% points. The difference between the input voltages (VINP and VINN). Timing Diagram LATCH TRACK LATCH TRACK LATCH LATCH ENABLE (LE) 50% LATCH ENABLE (LE) tPL tS tH DIFFERENTIAL INPUT VOLTAGE Q OUTPUT VIN VCM VOS VOD tPDL tPLOH 50% tF tPDH tR Figure 2. Timing Diagram Rev. K | Page 5 of 14 tPLOL 14861-002 50% Q OUTPUT HMC674LC3C/HMC674LP3E Data Sheet ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Supply Voltage Input (VCCI to GND) Output (VCCO to GND) Positive Differential (VCCI to VCCO) VEE Supply to GND Input Voltage Differential Latch Enable (LE/LE) Applied Voltage (HYS) Current Maximum Input Output Continuous Power Dissipation (PDISS), TA = 85C Derate 43.5 mW/C Above 85C (HMC674LP3E) Derate 20.4 mW/C Above 85C (HMC674LC3C) Junction Temperature Maximum Peak Reflow Temperature1 MSL1 and MSL3 Thermal Resistance (JC) HMC674LP3E HMC674LC3C Storage Temperature Range Operating Temperature Range ESD Sensitivity, Human Body Model (HBM) 1 Rating -0.5 V to +4 V -0.5 V to +4 V -0.5 V to +3.3 V -3.3 V to +0.5 V -2 V to +2 V -2 V to +2 V -0.5 V to VCCI + 0.5 V VEE to GND Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 20 mA 40 mA 1.74 W 0.816 W 125C 260C 23C/W 49C/W -65C to +150C -40C to +85C Class 1A See the Ordering Guide section. Rev. K | Page 6 of 14 Data Sheet HMC674LC3C/HMC674LP3E 12 VCCO 13 VEE 14 HYS VTP 1 12 VCCO INP 2 HMC674LC3C 11 Q INP 2 HMC674LP3E 11 Q INN 3 TOP VIEW (Not to Scale) 10 Q INN 3 TOP VIEW (Not to Scale) 10 Q 9 VTN 4 VEE LE 7 VCCO PACKAGE BASE VEE NOTES 1. NIC = NOT INTERNALLY CONNECTED. CONNECT THIS PIN TO GROUND FOR IMPROVED NOISE. 2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO VEE. 14861-003 NOTES 1. NIC = NOT INTERNALLY CONNECTED. CONNECT THIS PIN TO GROUND FOR IMPROVED NOISE. 2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO VEE. NIC 8 PACKAGE BASE 9 LE 6 VCCO VCCI 5 LE 7 NIC 8 LE 6 VCCI 5 VTN 4 Figure 3. HMC674LC3C Pin Configuration 14861-004 VTP 1 15 RTN 16 VCCI 13 VEE 14 HYS 15 RTN 16 VCCI PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. HMC674LP3E Pin Configuration Table 8. HMC674LC3C/HMC674LP3E Pin Function Descriptions Pin No. 1 2 3 4 5, 16 6 Mnemonic VTP INP INN VTN VCCI LE 7 LE 8 9, 12 10 NIC VCCO Q 11 Q 13 14 VEE HYS 15 RTN EPAD Description Termination Resistor Return Pin for VP Input. See Figure 5 for the interface schematic. Noninverting Analog Input. See Figure 5 for the interface schematic. Inverting Analog Input. See Figure 5 for the interface schematic. Termination Resistor Return Pin for VN Input. See Figure 5 for the interface schematic. Positive Supply Voltage Input Stage. See Figure 6 for the interface schematic. Latch Enable Input Pin, Inverting Side. See the Theory of Operation section for additional information. See Figure 6 for the interface schematic. Latch Enable Input Pin, Noninverting Side. See the Theory of Operation section for additional information. See Figure 6 for the interface schematic. Not Internally Connected. Connect this pin to ground for improved noise. Positive Supply Voltage for the Output Stage. See Figure 7 for the interface schematic. Inverting Output. Q is at logic low if the analog voltage at the noninverting input, INP, is greater than the analog voltage at the inverting input, INN, provided that the comparator is in track mode. See the Theory of Operation section for additional information. See Figure 7 for the interface schematic. Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, INP, is greater than the analog voltage at the inverting input, INN, provided that the comparator is in track mode. See the Theory of Operation section for additional information. See Figure 7 for the interface schematic. Negative Power Supply, -3 V. See Figure 6 for the interface schematic. Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect this pin to VEE with a resistor to add the desired amount of hysteresis. See Figure 12 to determine the correct size of the RHYS hysteresis control resistor. See Figure 8 for the interface schematic. Return for ESD Protection. Exposed Pad. The exposed pad must be connected to VEE. Rev. K | Page 7 of 14 HMC674LC3C/HMC674LP3E Data Sheet INTERFACE SCHEMATICS VTP, VTN VCCO Q, Q Figure 5. VTP, VTN and INP, INN Interface Schematic 14861-007 14861-005 50 INP, INN Figure 7. Q, Q Interface Schematic VCCI HYS 14861-008 VEE 14861-006 LE, LE Figure 8. HYS Interface Schematic Figure 6. LE, LE Interface Schematic Rev. K | Page 8 of 14 Data Sheet HMC674LC3C/HMC674LP3E TYPICAL PERFORMANCE CHARACTERISTICS 11 15.0 RISING EDGE FALLING EDGE RISING EDGE FALLING EDGE 12.5 9 NORMALIZED tPD (ps) DISPERSION (ps) 10.0 7 5 3 7.5 5.0 2.5 0 1 0 10 20 30 40 50 60 70 80 90 100 OVERDRIVE VOLTAGE (mV) -5.0 -2.0 14861-009 -1 Figure 9. Dispersion vs. Overdrive Voltage -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 COMMON-MODE VOLTAGE (V) 14861-011 -2.5 Figure 11. Normalized Propagation Delay (tPD) vs. Common-Mode Voltage 2.8 15 VOH VOL HYSTERESIS (mV) 2.4 2.2 10 5 1.8 -45 -32 -19 -6 7 20 33 46 59 TEMPERATURE (C) 72 85 Figure 10. Output Voltage vs. Temperature 0 100 1k 10k RESISTANCE () Figure 12. Comparator Hysteresis vs. RHYS Control Resistance Rev. K | Page 9 of 14 14861-012 2.0 14861-010 OUTPUT VOLTAGE (V) 2.6 HMC674LC3C/HMC674LP3E Data Sheet THEORY OF OPERATION The HMC674LC3C/HMC674LP3E are latched comparators with a 9.3 GHz equivalent input bandwidth. These devices are comprised of three blocks: an input amplifier, a latch, and an output buffer. The latching circuit is level sensitive and consists of a single, high speed latch. The HMC674LC3C/HMC674LP3E comparators support 10 Gbps operation. The input signal minimum pulse width is 60 ps. The HMC674LC3C/HMC674LP3E operate in either track (transparent) mode, where the output follows the logical value of the input, or latch (hold) mode, where the output value is held to the logical value of the comparison result of the input just prior to (LE - LE) going high. Select track mode operation by either setting (LE - LE) low or by floating the LE and LE inputs. Select latch mode by setting (LE - LE) high. The input impedance of the LE and LE inputs is 8 k; however, these inputs can be terminated with 50 external resistors, if desired. POWER SEQUENCING As long as the input signal is not near the -2 V extreme, either VCC or VEE can be powered on first. However, if the input voltage is more negative than -1.8 V, use the following power-up sequence: 1. 2. 3. VEE VCCI and VCCO (if VCCO = VCCI) VCCO (if different than ground) Note that the power-down sequence is the reverse of this sequence. It is recommended to power up the HMC674LC3C or the HMC674LP3E before applying the input signal and to remove the input signal prior to powering either down. These recommendations are important if any of the inputs are more negative than -1.8 V. When the clock inputs are dc-coupled, they operate at an input common-mode voltage of 2 V. In this case, any termination resistors ideally return to 2 V. If the clock inputs are ac-coupled to the HMC674LC3C/HMC674LP3E, return the input termination resistors to ground. Rev. K | Page 10 of 14 Data Sheet HMC674LC3C/HMC674LP3E APPLICATIONS INFORMATION EVALUATION PRINTED CIRCUIT BOARD (PCB) Figure 13 shows the front side of the evaluation PCB, and Figure 14 shows the back side of the evaluation PCB. 14861-013 The evaluation PCB used in the application must use RF circuit design techniques. Signal lines must have 50 impedance, and the package ground leads must be connected directly to the ground plane similar to that shown in Figure 15. Use a sufficient number of via holes to connect the top and bottom ground planes to provide good RF grounding to 10 GHz. The evaluation PCB shown in Figure 13 is available from Analog Devices, Inc., upon request. 14861-014 Figure 13. Front Side of the Evaluation PCB Figure 14. Back Side of the Evaluation PCB Rev. K | Page 11 of 14 HMC674LC3C/HMC674LP3E Data Sheet APPLICATION CIRCUITS See Figure 15 for the typical application circuit, Table 9 for the bill of materials, and Figure 16 for the output interfacing application circuit. TP3 HYS TP4 C8 100pF C1 100pF J1 VCCI 50 11 3 50 10 4 C3 100pF 8 7 C9 100pF J4 Q J5 Q 9 6 JP2 C2 100pF 2 5 TP2 VTN J1 VEE C12 4.7F 12 1 J2 INP J3 INN C4 330pF 13 JP1 C5 100pF 14 C7 330pF 16 TP1 VTP C13 4.7F 15 J1 VCCI C6 100pF PACKAGE BASE C11 330pF VEE C10 100pF C14 4.7F J1 VCCO J8 GND J6 LE J7 LE 14861-015 VEE Figure 15. Typical Application Circuit Table 9. Bill of Materials for the Evaluation PCB (125929-3) Item J1 J2 to J7 J8 JP1, JP2 C1 to C3, C5, C6, C8 to C10 C4, C7, C11 C12 to C14 TP1 to TP4 U1 PCB Reference this number when ordering complete evaluation PCB. VCCO = +2.0V OSCILLOSCOPE INPUT Q 50 CH1 50 VCM_OUT ~0.9V Q 50 CH2 GND (VTT) 50 GND (VTT) VEE = -3.0V Figure 16. Output Interfacing Application Circuit, Output to Oscilloscope Rev. K | Page 12 of 14 14861-016 1 Description Eight position vertical header 2.92 mm, 40 GHz jacks Terminal strip, single row, 3-pin surface mount (SMT) Two position vertical header 100 pF capacitors, 0402 package 330 pF capacitors, 0402 package 4.7 F tantalum capacitors DC pin, swage mount test points HMC674LC3C/HMC674LP3E comparator 125929-31 evaluation PCB, circuit board material is Rogers 4350 or Arlon 25FR Data Sheet HMC674LC3C/HMC674LP3E OUTLINE DIMENSIONS PIN 1 INDICATOR 3.03 2.90 SQ 2.77 0.36 0.30 0.24 13 PIN 1 (0.32 x 0.32) 16 1 12 0.50 BSC 1.60 1.50 SQ 1.40 EXPOSED PAD 9 4 5 8 BOTTOM VIEW TOP VIEW 1.50 REF 2.10 BSC SIDE VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. PKG-000000 SEATING PLANE 04-25-2016-A 0.92 MAX Figure 17. 16-Terminal Ceramic Leadless Chip Carrier [LCC] (E-16-1) Dimensions shown in millimeters 0.30 0.25 0.18 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 EXPOSED PAD 1.950 1.725 SQ 1.500 9 TOP VIEW 1.00 0.90 0.80 4 5 8 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PKG-000000 0.45 0.40 0.35 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT WITH JEDEC STANDARDS MO-220-VEED-4. 02-13-2015-A PIN 1 INDICATOR 3.10 3.00 SQ 2.90 Figure 18. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body and 0.90 mm Package Height (HCP-16-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 HMC674LC3C Temperature Range -40C to +85C Package Body Material Alumina, White Lead Finish Gold over Nickel MSL Rating 2 MSL3 Package Description 16-Terminal LCC Package Option E-16-1 HMC674LC3CTR -40C to +85C Alumina, White Gold over Nickel MSL3 16-Terminal LCC E-16-1 HMC674LC3CTR-R5 -40C to +85C Alumina, White Gold over Nickel MSL3 16-Terminal LCC E-16-1 Rev. K | Page 13 of 14 Branding H674 XXXX H674 XXXX H674 XXXX HMC674LC3C/HMC674LP3E Model 1 HMC674LP3E Temperature Range -40C to +85C HMC674LP3ETR -40C to +85C Data Sheet Package Body Material Low Stress, Injection Molded Plastic Low Stress, Injection Molded Plastic Lead Finish 100% Matte Sn MSL Rating 2 MSL1 Package Description 16-Lead LFCSP Package Option HCP-16-1 100% Matte Sn MSL1 16-Lead LFCSP HCP-16-1 125932-HMC674LC3C HMC674LC3C Evaluation Board HMC674LP3E Evaluation Board 125932-HMC674LP3E 1 2 The HMC674LC3C, the HMC674LC3CTR, the HMC674LC3CTR-R5, the HMC674LP3E, and the HMC674LP3ETR are RoHS Compliant Parts. See the Absolute Maximum Ratings section. (c)2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14861-0-12/16(K) Rev. K | Page 14 of 14 Branding H674 XXXX H674 XXXX