9.3 GHz Latched Comparator
with RSPECL Output Stage
Data Sheet
HMC674LC3C/HMC674LP3E
Rev. K Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Equivalent input bandwidth: 9.3 GHz typical
Propagation delay: 85 ps typical
Overdrive and slew rate dispersion: 10 ps typical
Input signal minimum pulse width: 60 ps typical
Resistor programmable hysteresis
Differential latch control
Power dissipation: 140 mW typical
16-terminal, 3 mm × 3 mm, ceramic leadless chip carrier (LCC)
16-lead lead frame chip scale package (LFCSP)
APPLICATIONS
Automatic test equipment (ATE) applications
High speed instrumentation
Digital receiver systems
Pulse spectroscopy
High speed trigger circuits
Clock and data restoration
FUNCTIONAL BLOCK DIAGRAM
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
VTP
50Ω
50Ω
INP
INN
VTN
V
CCO
V
EE
HYS
RTN
V
CCI
Q
Q
V
CCO
V
CCI
LE
LE
NIC
V
EE
PACKAGE
BASE
HMC674LC3C/HMC674LP3E
14861-001
Figure 1. HMC674LC3C/HMC674LP3E Functional Block Diagram
GENERAL DESCRIPTION
The HMC674LC3C/HMC674LP3E are silicon germanium
(SiGe), monolithic, ultrafast comparators that feature reduced
swing positive emitter-coupled logic (RSPECL) output drivers
and latch inputs. These comparators support 10 Gbps operation
and provide 85 ps propagation delay and an input signal
minimum pulse width of 60 ps with 0.2 ps rms of random jitter
(RJ). Overdrive and slew rate dispersion is typically 10 ps, making
the HMC674LC3C/HMC674LP3E ideal for a wide range of
applications from ATE to broadband communications. The
RSPECL output stages directly drive 400 mV into a 50 Ω resistor
terminated to VTT = (VCCO − 2.0 V), where VTT is the PECL
termination voltage (see Figure 16). The HMC674LC3C/
HMC674LP3E feature a high speed latch and programmable
hysteresis. These devices can operate in either latch mode or as
a tracking comparator.
HMC674LC3C/HMC674LP3E Data Sheet
Rev. K | Page 2 of 14
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Latch Enable (LE/LE) Specifications ......................................... 3
DC Output Specifications ........................................................... 3
AC Specifications .......................................................................... 4
Power Supply Specifications........................................................ 4
Timing Descriptions .................................................................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution...................................................................................6
Pin Configurations and Function Descriptions ............................7
Interface Schematics .....................................................................8
Typical Performance Characteristics ..............................................9
Theory of Operation ...................................................................... 10
Power Sequencing ...................................................................... 10
Applications Information .............................................................. 11
Evaluation Printed Circuit Board (PCB)................................. 11
Application Circuits ................................................................... 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 13
REVISION HISTORY
Two Hittite Mircrowave product data sheets have been
reformatted to the styles and standards of Analog Devices, Inc.,
and combined into one data sheet.
12/2016—v12.0616 (HMC674LC3C and HMC674LP3E) to
Rev. K
Updated Format .................................................................. Universal
Changes to Title, Features Section, and General Description
Section ................................................................................................ 1
Changes to Table 7 ............................................................................ 6
Changes to Table 8 ............................................................................ 7
Changes to Figure 10 ........................................................................ 9
Changed Operational Description Section to Theory of
Operation Section ........................................................................... 10
Changes to Figure 15 and Table 9 ................................................. 12
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 13
Data Sheet HMC674LC3C/HMC674LP3E
Rev. K | Page 3 of 14
SPECIFICATIONS
TA = 25°C, VCCI = 3.3 V, VCCO = 2.0 V, VEE = −3 V, V TT = 0 V, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit
INPUT
Voltage Range −2 +2 V
Differential Voltage −1.75 +1.75 V
Offset Voltage (VOS) ±5 mV
Temperature Coefficient 15 µV/°C
Bias Current 15 µA
Temperature Coefficient
50
nA/°C
Offset Current 4 µA
Impedance 50 Ω
Common-Mode 350 kΩ
Differential 15 kΩ
Active Gain 48 dB
Common-Mode Rejection Ratio (CMRR) 80 dB
Hysteresis, RHYS = Infinity ±1 mV
LATCH ENABLE (LE/LE) SPECIFICATIONS
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
LATCH ENABLE (LE/LE)
Input Impedance 8 kΩ Each pin
To Output Delay tPLOL, tPLOH 85 ps Input overdrive voltage (VOD) = 200 mV
Minimum Pulse Width tPL 20 ps VOD = 200 mV
Input Range 1.6 2.4 V VOD = 200 mV
LATCH ENABLE (LE/LE) TIME
Setup tS 45 ps VOD = 200 mV
Hold tH −42 ps
DC OUTPUT SPECIFICATIONS
VCCO = 2.00 V, VTT = 0 V, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
OUTPUT VOLTAGE
High Level VOH 1.03 1.09 1.14 V
Low Level VOL 0.65 0.71 0.81 V
Differential Swing 440 760 980 mV p-p
HMC674LC3C/HMC674LP3E Data Sheet
Rev. K | Page 4 of 14
AC SPECIFICATIONS
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
PROPAGATION DELAY (t
PDL,
t
PD
, t
PDH
)
80
85
110
ps
V
OD
= 500 mV
Temperature Coefficient 0.45 ps/°C
Skew (Rising to Falling Transition) 10 ps VOD = 500 mV
V
OD 1
DISPERSION
10
ps
50 mV < V
OD
< 1 V
PROPAGATION DELAY (tPD) vs. INPUT COMMON-MODE VOLTAGE (VCM)
DISPERSION
8 ps VOD = 500 mV,
−1.75 V < VCM < +1.75 V
NOISE (RETURN TO INPUT, RTI) 5.9 nV/√Hz
EQUIVALENT INPUT BANDWIDTH (BWEQ)2 8.6 9.3 12 GHz
JITTER 10 Gbps with ±100 mV overdrive
Deterministic 2 ps p-p
Random 0.2 ps rms
INPUT SIGNAL MINIMUM PULSE WIDTH
60
ps
V
CM
= 0 V, ±100 mV overdrive
Q/Q TIME From 20% to 80%
Rise 24 ps
Fall 15 ps
1 VOD is the input overdrive voltage, for example, (VINP − VINN − VOS), where VOS is the input offset voltage.
2 Equivalent input bandwidth is calculated by
)(
22
EQ
TRINTRCOMP
BW −0.22/
=
where:
TRIN is the 20%/80% transition time of a quasi Gaussian signal applied to the comparator input.
TRCOMP is the effective transition time digitized by the comparator.
POWER SUPPLY SPECIFICATIONS
Table 5.
Parameter Symbol Min Typ Max Unit
VOLTAGE
Power Supply Voltage Input Stage VCCI 3.135 3.3 3.465 V
Power Supply Voltage Output Stage VCCO 1.8 3.3 3.465 V
Negative Power Supply (−3 V) VEE −3.15 −3.0 −2.85 V
CURRENT
Supply Input ICCI 9 mA
Supply Output ICCO 45 mA
VEE IEE 19 mA
POWER DISSIPATION PD 140 mW
POWER SUPPLY REJECTION RATIO PSRR
V
CCI
38
dB
VEE 38 dB
Data Sheet HMC674LC3C/HMC674LP3E
Rev. K | Page 5 of 14
TIMING DESCRIPTIONS
Table 6.
Parameter Symbol Description
Input to Output High Delay
t
PDH
The propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output low to high transition.
Input to Output Low Delay tPDL The propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output high to low transition.
Latch Enable (LE/LE) to Output High Delay tPLOH The propagation delay measured from the 50% point of the latch enable (LE/LE)
signal high to low transition to the 50% point of an output low to high transition.
Latch Enable (LE/LE) to Output Low Delay tPLOL The propagation delay measured from the 50% point of the latch enable (LE/LE)
signal high to low transition to the 50% point of an output high to low transition.
Minimum Hold Time tH The minimum time after the positive transition of the latch enable (LE/LE) signal
that the input signal must remain unchanged to be acquired and held at the outputs.
Minimum Latch Enable (LE/LE) Pulse Width tPL The minimum time that the latch enable (LE/LE) signal must be low to acquire an
input signal change.
Minimum Setup Time tS The minimum time before the positive transition of the latch enable (LE/LE) signal
that an input signal change must be present to be acquired and held at the outputs.
Output Rise Time tR The amount of time required to transition from a low to a high output as measured
at the 20% and 80% points.
Output Fall Time tF The amount of time required to transition from a high to a low output as measured
at the 20% and 80% points.
Input Overdrive Voltage VOD The difference between the input voltages (VINP and VINN).
Timing Diagram
LATCH ENABLE ( LE)
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE ( LE)
Q OUTPUT
Q OUTPUT
LATCH TRACK LATCH LATCH
50%
50%
50%
V
CM
± V
OS
TRACK
tH
V
IN
V
OD
tF
tStPL
tPDL
tPDH
tPLOH
tPLOL
tR
14861-002
Figure 2. Timing Diagram
HMC674LC3C/HMC674LP3E Data Sheet
Rev. K | Page 6 of 14
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
Supply Voltage
Input (VCCI to GND) −0.5 V to +4 V
Output (VCCO to GND) −0.5 V to +4 V
Positive Differential (VCCI to VCCO) −0.5 V to +3.3 V
VEE Supply to GND −3.3 V to +0.5 V
Input Voltage −2 V to +2 V
Differential −2 V to +2 V
Latch Enable (LE/
LE
)
−0.5 V to V
CCI
+ 0.5 V
Applied Voltage (HYS) VEE to GND
Current
Maximum Input ±20 mA
Output 40 mA
Continuous Power Dissipation (PDISS), TA = 85°C
Derate 43.5 mW/°C Above 85°C
(HMC674LP3E)
1.74 W
Derate 20.4 mW/°C Above 85°C
(HMC674LC3C)
0.816 W
Junction Temperature 125°C
Maximum Peak Reflow Temperature1
MSL1 and MSL3 260°C
Thermal Resistance (θJC)
HMC674LP3E 23°C/W
HMC674LC3C 49°C/W
Storage Temperature Range −65°C to +150°C
Operating Temperature Range
−40°C to +85°C
ESD Sensitivity, Human Body Model (HBM) Class 1A
1 See the Ordering Guide section.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Data Sheet HMC674LC3C/HMC674LP3E
Rev. K | Page 7 of 14
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
12
11
10
1
3
4 9
2
6
5
7
8
16
15
14
13
VTP
INP
INN
VTN
VCCO
VEE
HYS
RTN
VCCI
Q
Q
VCCO
VCCI
LE
LE
NIC
VEE
PACKAGE
BASE
NOTES
1. NI C = NOT INT E RNALL Y CONNECTED. CO NNE CT
THIS PIN TO GROUND FOR IMPROVED NOISE.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO V EE.
HMC674LC3C
TOP VIEW
(No t t o Scale)
14861-003
Figure 3. HMC674LC3C Pin Configuration
12
11
10
1
3
4 9
2
6
5
7
8
16
15
14
13
VTP
INP
INN
VTN
VCCO
VEE
HYS
RTN
VCCI
Q
Q
VCCO
VCCI
LE
LE
NIC
HMC674LP3E
TOP VIEW
(No t t o Scale)
VEE
PACKAGE
BASE
NOTES
1. NI C = NOT INT E RNALL Y CONNECTED. CO NNE CT
THIS PIN TO GROUND FOR IMPROVED NOISE.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTE D TO VEE.
14861-004
Figure 4. HMC674LP3E Pin Configuration
Table 8. HMC674LC3C/HMC674LP3E Pin Function Descriptions
Pin No. Mnemonic Description
1 VTP Termination Resistor Return Pin for VP Input. See Figure 5 for the interface schematic.
2 INP Noninverting Analog Input. See Figure 5 for the interface schematic.
3 INN Inverting Analog Input. See Figure 5 for the interface schematic.
4
VTN
Termination Resistor Return Pin for V
N
Input. See Figure 5 for the interface schematic.
5, 16
V
CCI
Positive Supply Voltage Input Stage. See Figure 6 for the interface schematic.
6 LE Latch Enable Input Pin, Inverting Side. See the Theory of Operation section for additional information. See
Figure 6 for the interface schematic.
7 LE Latch Enable Input Pin, Noninverting Side. See the Theory of Operation section for additional information. See
Figure 6 for the interface schematic.
8 NIC Not Internally Connected. Connect this pin to ground for improved noise.
9, 12 VCCO Positive Supply Voltage for the Output Stage. See Figure 7 for the interface schematic.
10 Q Inverting Output. Q is at logic low if the analog voltage at the noninverting input, INP, is greater than the
analog voltage at the inverting input, INN, provided that the comparator is in track mode. See the Theory of
Operation section for additional information. See Figure 7 for the interface schematic.
11 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, INP, is greater than the
analog voltage at the inverting input, INN, provided that the comparator is in track mode. See the Theory of
Operation section for additional information. See Figure 7 for the interface schematic.
13 VEE Negative Power Supply, −3 V. See Figure 6 for the interface schematic.
14 HYS Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect this pin to VEE with a resistor to add
the desired amount of hysteresis. See Figure 12 to determine the correct size of the RHYS hysteresis control resistor.
See Figure 8 for the interface schematic.
15 RTN Return for ESD Protection.
EPAD Exposed Pad. The exposed pad must be connected to VEE.
HMC674LC3C/HMC674LP3E Data Sheet
Rev. K | Page 8 of 14
INTERFACE SCHEMATICS
INP,
INN
VTP,
VTN
50Ω
14861-005
Figure 5. VTP, VTN and INP, INN Interface Schematic
VEE
VCCI
LE, LE
14861-006
Figure 6. LE, LE Interface Schematic
Q,
Q
VCCO
14861-007
Figure 7. Q, Q Interface Schematic
HYS
14861-008
Figure 8. HYS Interface Schematic
Data Sheet HMC674LC3C/HMC674LP3E
Rev. K | Page 9 of 14
TYPICAL PERFORMANCE CHARACTERISTICS
11
–1
1
3
5
7
9
010 3020 40 50 60 70 80 90 100
DISPERSION (ps)
OVERDRIVE VOLTAGE (mV)
RISING EDGE
FALLING EDGE
14861-009
Figure 9. Dispersion vs. Overdrive Voltage
2.8
1.8
2.0
2.2
2.4
2.6
–45 –32 –6–19 720 33 46 59 72 85
OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
VOH
VOL
14861-010
Figure 10. Output Voltage vs. Temperature
15.0
–5.0
–2.5
0
5.0
10.0
2.5
7.5
12.5
–2.0 –1.5 –0.5–1.0 00.5 1.0 1.5 2.0
NORMALIZED
tPD
(p s)
COMMON-MODE VOLT AGE (V)
RISING EDGE
FALLING EDGE
14861-011
Figure 11. Normalized Propagation Delay (tPD) vs. Common-Mode Voltage
15
0
5
10
100 1k 10k
HYSTERESIS (mV)
RESISTANCE (Ω)
14861-012
Figure 12. Comparator Hysteresis vs. RHYS Control Resistance
HMC674LC3C/HMC674LP3E Data Sheet
Rev. K | Page 10 of 14
THEORY OF OPERATION
The HMC674LC3C/HMC674LP3E are latched comparators
with a 9.3 GHz equivalent input bandwidth. These devices are
comprised of three blocks: an input amplifier, a latch, and an
output buffer. The latching circuit is level sensitive and consists
of a single, high speed latch. The HMC674LC3C/HMC674LP3E
comparators support 10 Gbps operation. The input signal
minimum pulse width is 60 ps.
The HMC674LC3C/HMC674LP3E operate in either track
(transparent) mode, where the output follows the logical value
of the input, or latch (hold) mode, where the output value is held
to the logical value of the comparison result of the input just
prior to (LE − LE) going high. Select track mode operation by
either setting (LE − LE) low or by floating the LE and LE inputs.
Select latch mode by setting (LE − LE) high. The input impedance
of the LE and LE inputs is 8 kΩ; however, these inputs can be
terminated with 50 Ω external resistors, if desired.
When the clock inputs are dc-coupled, they operate at an input
common-mode voltage of 2 V. In this case, any termination
resistors ideally return to 2 V. If the clock inputs are ac-coupled
to the HMC674LC3C/HMC674LP3E, return the input
termination resistors to ground.
POWER SEQUENCING
As long as the input signal is not near the −2 V extreme, either
VCC or VEE can be powered on first. However, if the input voltage is
more negative than −1.8 V, use the following power-up sequence:
1. VEE
2. VCCI and VCCO (if VCCO = VCCI)
3. VCCO (if different than ground)
Note that the power-down sequence is the reverse of this
sequence.
It is recommended to power up the HMC674LC3C or the
HMC674LP3E before applying the input signal and to remove the
input signal prior to powering either down. These recommendations
are important if any of the inputs are more negative than −1.8 V.
Data Sheet HMC674LC3C/HMC674LP3E
Rev. K | Page 11 of 14
APPLICATIONS INFORMATION
EVALUATION PRINTED CIRCUIT BOARD (PCB)
Figure 13 shows the front side of the evaluation PCB, and
Figure 14 shows the back side of the evaluation PCB.
The evaluation PCB used in the application must use RF circuit
design techniques. Signal lines must have 50 Ω impedance, and
the package ground leads must be connected directly to the ground
plane similar to that shown in Figure 15. Use a sufficient number
of via holes to connect the top and bottom ground planes to
provide good RF grounding to 10 GHz. The evaluation PCB shown
in Figure 13 is available from Analog Devices, Inc., upon request.
14861-013
Figure 13. Front Side of the Evaluation PCB
14861-014
Figure 14. Back Side of the Evaluation PCB
HMC674LC3C/HMC674LP3E Data Sheet
Rev. K | Page 12 of 14
APPLICATION CIRCUITS
See Figure 15 for the typical application circuit, Table 9 for the bill of materials, and Figure 16 for the output interfacing application circuit.
J8 GND
VEE
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
50Ω
50Ω
VEE
PACKAGE
BASE
C6
100pF
TP4
C5
100pF
C7
330pF
C8
100pF
JP1
C13
4.7µF
J1
VCCI
J1
VCCI
C12
4.7µF
C2
100pF
C3
100pF
C4
330pF
C14
4.7µF
C11
330pF
C1
100pF
J1
VEE
TP3
HYS
TP1
VTP
J2
INP
J6
LE
J3
INN
J4
Q
C9
100pF
C10
100pF
JP2
TP2
VTN
J7
LE
J5
Q
J1
VCCO
14861-015
Figure 15. Typical Application Circuit
Table 9. Bill of Materials for the Evaluation PCB (125929-3)
Item Description
J1 Eight position vertical header
J2 to J7 2.92 mm, 40 GHz jacks
J8 Terminal strip, single row, 3-pin surface mount (SMT)
JP1, JP2 Two position vertical header
C1 to C3, C5, C6, C8 to C10 100 pF capacitors, 0402 package
C4, C7, C11 330 pF capacitors, 0402 package
C12 to C14 4.7 µF tantalum capacitors
TP1 to TP4 DC pin, swage mount test points
U1 HMC674LC3C/HMC674LP3E comparator
PCB 125929-31 evaluation PCB, circuit board material is Rogers 4350 or Arlon 25FR
1 Reference this number when ordering complete evaluation PCB.
50Ω
50ΩCH1
50Ω
GND ( V TT)
GND ( V TT)
CH2
Q
Q
VCM_OUT
~0.9V
VEE = –3.0V
OSCILLOSCOPE INPUT
VCCO = +2.0V
50Ω
14861-016
Figure 16. Output Interfacing Application Circuit, Output to Oscilloscope
Data Sheet HMC674LC3C/HMC674LP3E
Rev. K | Page 13 of 14
OUTLINE DIMENSIONS
TOP VIEW
SIDE VIEW
SEATING
PLANE
0.92 M AX
04-25-2016-A
PKG-000000
PIN 1
INDICATOR
3.03
2.90 SQ
2.77
PIN 1
(0.32 × 0.32)
EXPOSED
PAD
0.36
0.30
0.24
1.60
1.50 SQ
1.40
1
0.50
BSC
BOTTOM VIEW
16
5
8
9
12
13
4
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTI ON DESCRIPTI ONS
SECTION OF THIS DATA SHEET.
1.50
REF
2.10 BSC
Figure 17. 16-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-16-1)
Dimensions shown in millimeters
3.10
3.00 SQ
2.90
0.30
0.25
0.18
1.950
1.725 SQ
1.500
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
1213
4
EXPOSED
PAD
PIN 1
INDICATOR
0.45
0.40
0.35
SEATING
PLANE
0.05 M AX
0.02 NO M
0.20 REF
0.20 M IN
COPLANARITY
0.08
PIN 1
INDICATOR
1.00
0.90
0.80
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTI O N DE S CRIPTI ONS
SECTION OF THIS DATA SHEET.
02-13-2015-A
PKG-000000
COM P LIANT WI TH JEDE C STANDARDS MO - 220- V E ED-4.
Figure 18. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.90 mm Package Height
(HCP-16-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
Temperature
Range
Package Body
Material Lead Finish
MSL
Rating2
Package
Description
Package
Option Branding
HMC674LC3C −40°C to +85°C Alumina, White Gold over Nickel MSL3 16-Terminal LCC E-16-1 H674
XXXX
HMC674LC3CTR −40°C to +85°C Alumina, White Gold over Nickel MSL3 16-Terminal LCC E-16-1 H674
XXXX
HMC674LC3CTR-R5 −40°C to +85°C Alumina, White Gold over Nickel MSL3 16-Terminal LCC E-16-1 H674
XXXX
HMC674LC3C/HMC674LP3E Data Sheet
Rev. K | Page 14 of 14
Model 1
Temperature
Range
Package Body
Material Lead Finish
MSL
Rating2
Package
Description
Package
Option Branding
HMC674LP3E −40°C to +85°C Low Stress,
Injection
Molded Plastic
100% Matte Sn MSL1 16-Lead LFCSP HCP-16-1 H674
XXXX
HMC674LP3ETR −40°C to +85°C Low Stress,
Injection
Molded Plastic
100% Matte Sn MSL1 16-Lead LFCSP HCP-16-1 H674
XXXX
125932-HMC674LC3C HMC674LC3C
Evaluation Board
125932-HMC674LP3E HMC674LP3E
Evaluation Board
1 The HMC674LC3C, the HMC674LC3CTR, the HMC674LC3CTR-R5, the HMC674LP3E, and the HMC674LP3ETR are RoHS Compliant Parts.
2 See the Absolute Maximum Ratings section.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14861-0-12/16(K)
