3 V/5 V, Rail-to-Rail
Quad, 8-Bit DAC
AD7304/AD7305
Rev. C
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
Four 8-bit DACs in one package
+3 V, +5 V, and ±5 V operation
Rail-to-rail REF input to voltage output swing
2.6 MHz reference multiplying bandwidth
Internal power-on reset
SPI serial interface-compatible—AD7304
Fast parallel interface—AD7305
40 µA power shutdown
APPLICATIONS
Automotive output span voltage
Instrumentation, digitally controlled calibration
Pin-compatible AD7226 replacement when VDD < 5.5 V
GENERAL DESCRIPTION
The AD7304/AD73051 are quad, 8-bit DACs that operate from
a single +3 V to +5 V supply, or ±5 V supplies. The AD7304 has
a serial interface, while the AD7305 has a parallel interface.
Internal precision buffers swing rail-to-rail. The reference input
range includes both supply rails, allowing for positive or negative
full-scale output voltages. Operation is guaranteed over the
supply voltage range of 2.7 V to 5.5 V, consuming less than
9 mW from a 3 V supply.
The full-scale voltage output is determined by the external
reference input voltage applied. The rail-to-rail VREF input to
DAC VOUT allows for a full-scale voltage set equal to the positive
supply, VDD, the negative supply, VSS, or any value in between.
The AD7304’s doubled-buffered serial data interface offers high
speed, 3-wire, SPI®-, and microcontroller-compatible inputs
using data in (SDI), clock (CLK), and chip select (CS) pins.
Additionally, an internal power-on reset sets the output to zero
scale.
The parallel input AD7305 uses a standard address decode
along with the WR control line to load data into the input
registers.
The double-buffered architecture allows all four input registers
to be preloaded with new values, followed by an LDAC control
strobe that copies all the new data into the DAC registers,
thereby updating the analog output values.
_____________________________________________________
1 Protected under Patent No. 5684481.
FUNCTIONAL BLOCK DIAGRAMS
CS
PWR-ON
RESET
V
SS
AD7304
V
OUT
A
INPUT
REG A DAC A
LDAC
SDI/SHDN
GND
CLK
8 8
8 8
DAC A
REG
DAC B
8
8 8
8 8 DAC D
DAC C
SERIAL
REG
V
REF
BV
REF
A
CLR V
REF
CV
REF
D
V
DD
V
OUT
B
V
OUT
C
V
OUT
D
INPUT
REG B DAC B
REG
INPUT
REG C DAC C
REG
INPUT
REG D DAC D
REG
01114-001
Figure 1.
PWR-ON
RESET
AD7305
VOUTA
INPUT
REG A DAC A
LDAC
8 8
8 8
DAC A
REG
DAC B
8
8 8
8 8 DAC D
DAC C
DECODE
VREF
VSS GND
VDD
VOUTB
VOUTC
VOUTD
INPUT
REG B DAC B
REG
INPUT
REG C DAC C
REG
INPUT
REG D DAC D
REG
01114-002
DB0
DB1
DB2
DB3
DB4
DB5
DB6 8
WR
A
0/SHDN
A1
Figure 2.
When operating from less than 5.5 V, the AD7305 is
pin-compatible with the popular industry-standard AD7226.
An internal power-on reset places both parts in the zero-scale
state at turn-on. A 40 µA power shutdown (SHDN) feature is
activated on both parts by three-stating the SDI/SHDN pin on
the AD7304 and three-stating the A0/SHDN address pin on the
AD7305.
The AD7304/AD7305 are specified over the extended industrial
−40°C to +85°C and the automotive −40°C to +125°C
temperature ranges. AD7304s are available in a wide-body
16-lead SOIC (R-16) package. The parallel input AD7305 is
available in the wide-body 20-lead SOIC (R-20) surface-mount
package. For ultracompact applications, the thin 1.1 mm,
16-lead TSSOP (RU-16) package is available for the AD7304,
while the 20-lead TSSOP (RU-20) houses the AD7305.
AD7304/AD7305
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 10
Circuit Operation ........................................................................... 14
DAC Section................................................................................ 14
AD7304 Serial Data Interface ....................................................... 15
AD7304 Hardware Shutdown SHDN...................................... 15
AD7304/AD7305 Power-On Reset.......................................... 15
Power up sequence ..................................................................... 15
AD7305 Parallel Data Interface.................................................... 16
AD7226 Pin Compatibility ....................................................... 16
AD7305 Hardware Shutdown SHDN...................................... 16
ESD Protection Circuits ............................................................ 16
Applications..................................................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 19
Revision History
11/04—Data Sheet Changed from Rev. B to Rev. C
Update Format ....................................................................Universal
Update Features ................................................................................ 1
Changes to Figure 35...................................................................... 15
Add Power-Up Sequence............................................................... 15
Changes to Figure 36...................................................................... 16
Change to Figure 37 ....................................................................... 16
Updated Outline Dimensions....................................................... 18
2/04—Data Sheet Changed from Rev. A to Rev. B
Renumber TPCs and Figures............................................Universal
Deleted N-16 and N-20 packages.....................................Universal
Changes to Absolute Maximum Ratings....................................... 3
Changes to Ordering Guide ............................................................ 4
Updated Outline Dimensions....................................................... 14
3/98—Changed from Rev. 0 to Rev. A
2/98—Revision 0: Initial Version
AD7304/AD7305
Rev. C | Page 3 of 20
SPECIFICATIONS
@ VDD = 3 V or 5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, VSS ≤ VREF ≤ VDD, −40°C < TA < +85°C/+125°C, unless otherwise noted.
Table 1.
Parameter Symbol Condition 3 V ± 10% 5 V ± 10% ±5 V ± 10% Unit
STATIC PERFORMANCE
Resolution1N 8 8 8 Bits
Integral Nonlinearity2 INL ±1 ±1 ±1 LSB max
Differential Nonlinearity DNL Monotonic, all codes 0 to 0xFF ±1 ±1 ±1 LSB max
Zero-Scale Error VZSE Data = 0x00 15 15 ±15 mV max
Full-Scale Voltage Error VFSE Data = 0xFF ±4 ±4 ±4 LSB max
Full-Scale Temperature
Coefficient3
TCVFS 5 5 5 ppm/°C typ4
REFERENCE INPUT
VREFIN Range VREFIN VSS/VDD VSS/VDD VSS/VDD V min/max
Input Resistance (AD7304) RREFIN Code = 0x55 28 28 28 kΩ typ
Input Resistance (AD7305) RREFIN All DACs at code = 0x55 7.5 7.5 7.5 kΩ typ
Input Capacitance3CREFIN 5 5 5 pF typ
ANALOG OUTPUTS
Output Voltage Range VOUT VSS/VDD VSS/VDD VSS/VDD V min/max
Output Current Drive IOUT Code = 0x80, ∆VOUT < 1 LSB ±3 ±3 ±3 mA typ
Shutdown Resistance ROUT DAC outputs placed in shutdown
state
120 120 120 kΩ typ
Capacitive Load3CL No oscillation 200 200 200 pF typ
LOGIC INPUTS
Logic Input Low Voltage VIL 0.6 0.8 0.8 V min
Logic Input High Voltage VIH 2.1 2.4 2.4 V max
Input Leakage Current5 IIL ±10 ±10 ±10 µA max
Input Capacitance3CIL 8 8 8 pF max
AC CHARACTERISTICS3
Output Slew Rate SR Code = 0x00 to 0xFF to 0x00 1/2.7 1/3.6 1.0/3.6 V/µs min/typ
Reference Multiplying BW Small signal, VSS = –5 V
2.6 MHz typ
Total Harmonic Distortion THD VREF = 4 V p-p, VSS = –5 V, f = 1 kHz
0.025 %
Settling Time6 tS To ±0.1% of full scale 1.1/2 1.0/2 1.0/2 µs typ/max
Shutdown Recovery Time tSDR To ±0.1% of full scale 2 2 2 µs max
Time to Shutdown tSDN 15 15 15 µs typ
DAC Glitch Q 15 15 15 nVs typ
Digital Feedthrough Q 2 2 2 nVs typ
Feedthrough VOUT/VREF Code = 0x00, VREF = 1 V p-p, f = 100 kHz
−65 dB
SUPPLY CHARACTERISTICS
Positive Supply Current IDD VLOGIC = 0 V or VDD, no load 6 6 6 mA max
Negative Supply Current ISS VSS = –5 V
6 mA max
Power Dissipation PDISS VLOGIC = 0 V or VDD, no load 15 30 60 mW max
Power Down IDD_SD SDI/SHDN = floating 40 40 40 µA typ
Power Supply Sensitivity PSS ∆VDD = ±10% 0.004 0.004 0.004 %/%
1 One LSB = VREF/256.
2 The first three codes (0x00, 0x01, 0x10) are excluded from the integral nonlinearity error measurement in single-supply operation 3 V or 5 V.
3 These parameters are guaranteed by design and not subject to production testing.
4 Typical specifications represent average readings measured at 25°C.
5 The SDI/SHDN and A0/SHDN pins have a 30 µA maximum IIL input leakage current.
6 The settling time specification does not apply for negative going transitions within the last three LSBs of ground in single-supply operation.
AD7304/AD7305
Rev. C | Page 4 of 20
V
OUT
= 10V p-p
+5V
0V
–5V
+5V
0V
–5V
(IN)
V
REF
= 10V p-p
f = 20kHz
01114-003
(OUT)
Figure 3. Rail-to-Rail Reference Input to Output at 20 kHz
TIMING SPECIFICATIONS
@ VDD = 3 V or 5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, VSS ≤ VREF ≤ VDD, –40°C < TA < +85°C/+125°C, unless otherwise noted.
Table 2.
Parameter Symbol 3 V ± 10% 5 V ± 10% ±5 V ± 10% Unit
INTERFACE TIMING SPECIFICATIONS1, 2
AD7304 Only
Clock Width High tCH 70 55 55 ns min
Clock Width Low tCL 70 55 55 ns min
Data Setup tDS 50 40 40 ns min
Data Hold tDH 30 20 20 ns min
Load Pulse Width tLDW 70 60 60 ns min
Load Setup tLD1 40 30 30 ns min
Load Hold tLD2 40 30 30 ns min
Clear Pulse Width tCLWR 60 60 60 ns min
Select tCSS 30 20 20 ns min
Deselect tCSH 60 40 40 ns min
AD7305 Only
Data Setup tDS 60 40 40 ns min
Data Hold tDH 30 20 20 ns min
Address Setup tAS 60 40 40 ns min
Address Hold tAH 30 20 20 ns min
Write Width tWR 60 50 50 ns min
Load Pulse Width tLDW 60 50 50 ns min
Load Setup tLS 60 40 40 ns min
Load Hold tLH 30 20 20 ns min
1 These parameters are guaranteed by design and not subject to production testing.
2 All input control signals are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
AD7304/AD7305
Rev. C | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VDD to GND −0.3 V, +8 V
VSS to GND +0.3 V, −8 V
VREFX to GND VSS, VDD
Logic Inputs to GND −0.3 V, VDD + 0.3 V
VOUTX to GND −0.3 V, VDD + 0.3 V
IOUT Short-Circuit to GND 50 mA
Package Power Dissipation (TJ MAX – TA)/θJA
Thermal Resistance θJA
16-Lead SOIC Package (R-16) 73°C/W
16-Lead TSSOP Package (RU-16) 180°C/W
20-Lead SOIC Package (R-20) 74°C/W
20-Lead TSSOP Package (RU-20) 155°C/W
Maximum Junction Temperature (TJ MAX) 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature
R-16, R-20, RU-16, RU-20 (Vapor Phase, 60 sec) 235°C
R-16, R-20, RU-16, RU-20 (Infrared, 15 sec) 220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD7304/AD7305
Rev. C | Page 6 of 20
SDI
CLK
CS
LDAC
SA SI A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
t
CSH
t
LD2
t
CSS
t
LD1
SDI
CLK
CLR
LDAC
FS
ZS
V
OUT
t
DS
t
DH
t
CL
t
CH
t
LDW
t
S
t
CLRW
t
S
±1 LSB
ERROR BAND
01114-004
Figure 4. AD7304 General Timing Diagram
t
SDR
SDI/SHDN
I
DD
t
SDN
01114-005
Figure 5. AD7304 Timing Diagram Zoom In
Table 4. AD7304 Control Logic Truth Table
CS 1CLK1 LDAC CLR1 Serial Shift Register Function Input REG Function DAC Register Function
H X H H No effect No effect No effect
L ↑+ H H Data advanced 1 bit No effect No effect
↑+ L H H No effect Updated with SR contents2 No effect
H X L H No effect Latched with SR contents2 All input register contents transferred3
H X H ↓– No effect Loaded with 0x00 Loaded with 0x00
H X H ↑+ No effect Latched with 0x00 Latched with 0x00
1 ↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.
2 One input register receives the data bits D7–D0 decoded from the SR address bits (A1, A0), where REG A = (0, 0), B = (0, 1), C = (1, 0), and D = (1, 1).
3 LDAC is a level-sensitive input.
Table 5. AD7304 Serial Input Register Data Format, Data is Loaded in MSB-First Format
MSB
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
LSB
B0
AD7304 SAC SDC A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
If B11 (SAC), Shutdown All Channels, is set to logic low, all DACs are placed in a power shutdown mode, and all output voltages become
high resistance. If B10 (SDC), Shutdown Decoded Channel, is set to logic low, only the DAC decoded by Address Bits A1 and A0 is placed
in shutdown mode.
AD7304/AD7305
Rev. C | Page 7 of 20
Table 6. AD7305 Control Logic Truth Table
WR 1 A1 A0 LDAC2Input Register Function DAC Register Function
L L L H Register A loaded with DB0 to DB7 Latched with previous contents, no change
↑+ L L H Register A latched with DB0 to DB7 Latched with previous contents, no change
L L H H Register B loaded with DB0 to DB7 Latched with previous contents, no change
↑+ L H H Register B latched with DB0 to DB7 Latched with previous contents, no change
L H L H Register C loaded with DB0 to DB7 Latched with previous contents, no change
↑+ H L H Register C latched with DB0 to DB7 Latched with previous contents, no change
L H H H Register D loaded with DB0 to DB7 Latched with previous contents, no change
↑+ H H H Register D latched with DB0 to DB7 Latched with previous contents, no change
H X X L No effect All input register contents loaded, register transparent
L X X L Input register x transparent to DB0 to DB7 Register transparent
H X X ↑+ No effect All input register contents latched
H X X H No effect, device not selected No effect, device not selected
1 ↑+ positive logic transition; ↓– negative logic transition; X don’t care.
2 LDAC is a level-sensitive input.
t
AH
t
DH
t
LH
t
LDW
t
WR
t
AS
t
DS
t
LS
t
S
±1 LSB
ERROR BAND
A0, A1
WR
D0–D7
LDAC
V
OUT
01114-006
Figure 6. AD7305 General Timing Diagram
tSDR
A0/SHDN
I
DD
tSDN
01114-007
Figure 7. AD7305 Timing Diagram Zoom In
AD7304/AD7305
Rev. C | Page 8 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
OUT
B
1
V
OUT
A
2
V
SS 3
V
REF
A
4
V
OUT
C
16
V
OUT
D
15
V
DD
14
V
REF
C
13
V
REF
B
5
V
REF
D
12
GND
6
SDI/SHDN
11
LDAC
7
CLK
10
CLR
8
CS
9
AD7304
TOP VIEW
(Not to Scale)
01114-008
Figure 8. AD7304 Pin Configuration
Table 7. AD7304 Pin Function Descriptions
Pin No. Mnemonic Description
1 VOUTB Channel B Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFB pin.
Output is open circuit when SHDN is enabled.
2 VOUTA Channel A Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFA pin.
Output is open circuit when SHDN is enabled.
3 VSS Negative Power Supply Input. Specified range of operation is 0 V to −5.5 V.
4 VREFA Channel A Reference Input. Establishes VOUTA full-scale voltage. Specified range of operation is VSS < VREFA < VDD.
5 VREFB Channel B Reference Input. Establishes VOUTB full-scale voltage. Specified range of operation is VSS < VREFB < VDD.
6 GND Common Analog and Digital Ground.
7 LDAC Load DAC Register Strobe, Active Low. Simultaneously transfers data from all four input registers into the
corresponding DAC registers. Asynchronous active low input. DAC register is transparent when LDAC = 0. See
Table 4 for operation.
8 CLR Clears All Input and DAC Registers to the Zero Condition. Asynchronous active low input. The serial register is
not effected.
9 CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial input register data to
the decoded input register when CS returns high. Does not effect LDAC operation.
10 CLK Clock Input, Positive Edge Clocks Data into Shift Register. Disabled by chip select CS.
11 SDI/SHDN Serial Data Input Loads Directly into the Shift Register, MSB First. Hardware shutdown (SHDN) control input,
active when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as
power is present on VDD.
12 VREFD Channel D Reference Input. Establishes VOUTD full-scale voltage. Specified range of operation is VSS < VREFD < VDD.
13 VREFC Channel C Reference Input. Establishes VOUTC full-scale voltage. Specified range of operation is VSS VREFC < VDD.
14 VDD Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V.
15 VOUTD Channel D Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFD pin.
Output is open circuit when SHDN is enabled.
16 VOUTC Channel C Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFC pin.
Output is open circuit when SHDN is enabled.
AD7304/AD7305
Rev. C | Page 9 of 20
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
OUT
A
V
SS
V
REF
DB7
LDAC
GND
V
OUT
B
V
OUT
D
V
DD
A0/SHDN
DB0
WR
A1
DB4
DB5
DB6
DB3
DB2
DB1
V
OUT
C
AD7305
TOP VIEW
(Not to Scale)
01114-009
Figure 9. AD7305 Pin Configuration
Table 8. AD7305 Pin Function Description
Pin No. Mnemonic Description
1 VOUTB Channel B Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFB pin. Output is
open circuit when SHDN is enabled.
2 VOUTA Channel A Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFA pin. Output is
open circuit when SHDN is enabled.
3 VSS Negative Power Supply Input. Specified range of operation is 0 V to –5.5 V.
4 VREF Channel B Reference Input. Establishes VOUT full-scale voltage. Specified range of operation is VSS < VREF < VDD.
5 GND Common Analog and Digital Ground.
6 LDAC Load DAC Register Strobe, Active Low. Simultaneously transfers data from all four input registers into the
corresponding DAC registers. Asynchronous active low input. DAC register is transparent when LDAC = 0. See Table 6
for operation.
7 DB7 MSB Digital Input Data Bit.
8 DB6 Data Bit 6.
9 DB5 Data Bit 5.
10 DB4 Data Bit 4.
11 DB3 Data Bit 3.
12 DB2 Data Bit 2.
13 DB1 Data Bit 1.
14 DB0 LSB Digital Input Data Bit.
15 WR Write Data into Input Register Control Line, Active Low. See Table 6 for operation.
16 A1 Address Bit 1.
17 A0/SHDN Address Bit 0/Hardware Shutdown (SHDN) Control Input, Active When Pin Is Left Floating by a Three-State Logic
Driver. Does not effect DAC register contents as long as power is present on VDD.
18 VDD Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V.
19 VOUTD Channel D Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFD pin. Output is
open circuit when SHDN is enabled.
20 VOUTC Channel C Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFC pin. Output is
open circuit when SHDN is enabled.
AD7304/AD7305
Rev. C | Page 10 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
V
OUT
(mV)
144
120
0015
REFERENCE INPUT VOLTAGE (V)
1.0
0.6
–1.0
–5.0 5.0–3.0
INL (LSB)
–1.0 1.0 3.0
0.2
–0.2
–0.6
V
DD
= +5V
V
SS
= –5V
DATA = 0x80
T
A
= +25°C
DAC A
DAC B DAC C
DAC D
01114-013
3
I
OUT
SINK CURRENT (mA)
6912
96
72
48
24
V
DD
= +5V
V
SS
= –5V
V
REF
= V
DD
DATA = 0x00
01114-010
Figure 10. IOUT Sink vs. VOUT Rail-to-Rail Performance
V
OUT
OUTPUT VOLTAGE (V)
–35
–28
0
4.0 5.04.2
I
OUT
SOURCE CURRENT (mA)
4.4 4.6 4.8
–21
–14
–7
V
DD
= +5V
V
SS
= –5V
V
REF
= V
DD
DATA = 0xFF
01114-011
Figure 11. IOUT SOURCE vs. VOUT Rail-to-Rail Performance
CODE (Decimal)
+1
0
0 25632
INL (LSB)
64 96 128 160 192 224
0
0
+1
–1
+1
–1
+1
–1
0
–1
DAC A
DAC B
DAC C
DAC D
V
DD
= +5V
V
SS
= –5V
V
REF
= +2.5V
T
A
= +25°C
01114-012
Figure 12. INL vs. Code, All DAC Channels
Figure 13. INL vs. Reference Input Voltage
CODE (Decimal)
0.500
–0.500 0 25632
DNL (LSB)
64 96 128 160 192 224
0.375
0
–0.125
–0.250
–0.375
0.250
0.125
V
DD
= +5V
V
SS
= –5V
V
REF
= +2.5V
01114-014
Figure 14. DNL vs. Code
TEMPERATURE (°C)
4.0
3.6
2.0
–55 125–35
ZERO-SCALE VOLTAGE (mV)
–15 5 25 45 65 85 105
3.2
2.8
2.4
V
DD
= 5.5V
V
SS
= 0V
V
REF
= 5.45V
01114-015
Figure 15. Zero-Scale Voltage vs. Temperature
AD7304/AD7305
Rev. C | Page 11 of 20
CS 5V
0V
0V
V
OUT
01114-016
V
DD
= 5V
V
REF
= 4V
DATA = 0x00 0xFF
2µs/DIV
Figure 16. Large-Signal Settling Time
V
OUT
A
–5V
0V
+5V
–5V
0V
+5V
V
REFIN
(±5V @
50kHz)
DATA = 0xFF
01114-017
2µs/DIV
Figure 17. Multiplying Mode Step Response and Output Slew Rate
FREQUENCY (Hz)
6
–8
10k 10M
GAIN (dB)
4
1M100k
0
–4
–6
V
DD
= +5V
V
SS
= –5V
DATA = 0xFF
V
REF
= 100mV rms
f
–3dB
= 2.6MHz
01114-018
Figure 18. Multiplying Mode Gain vs. Frequency
V
OUT
CS
R
L
= 10kΩ
R
L
= 70kΩ
NO LOAD V
DD
= 5V
C
L
= 150pF
01114-019
5µs/DIV
Figure 19. Time to Shutdown
CS
V
OUT
I
DD
1mA/V
V
DD
= 5V
01114-020
Figure 20. Shutdown Recovery Time (Wakeup)
V
REF
AMPLITUDE (V p-p)
10
1
0.001
10m 101
THD (%)
23456789
0.1
0.01
V
DD
= +5V
V
SS
= –5V
01114-021
Figure 21. THD vs. Reference Input Amplitude
AD7304/AD7305
Rev. C | Page 12 of 20
FREQUENCY (Hz)
1
0.1
0.00120 100k100
THD (%)
1k 10k
0.01
V
DD
= +5V
V
SS
= –5V
01114-022
Figure 22. THD vs. Frequency
3.0
2.4
01 100k10
NOISE DENSITY (
µ
V/ Hz)
100 1k 10k
1.8
1.2
0.6
V
DD
= +5V
V
SS
= –5V
V
REF
= +4V
DATA = 0xFF
FREQUENCY (Hz)
01114-023
Figure 23. Output Noise Voltage Density vs. Frequency
50ns/DIV
CLK
V
DD
= +5V
V
SS
= –5V
V
REF
= +2.5V
DAC A = 0xFF
DAC B = 0x00
F = 2MHz
V
OUT
B
01114-024
50ns/DIV
Figure 24. Digital Feedthrough
CS
V
DD
= +5V
V
SS
= –5V
V
REF
= +2.5V
F = 1MHz
DATA = 0x80 0x7F
V
OUT
01114-025
Figure 25. Midscale Transition Glitch
FREQUENCY (Hz)
40
20
–160
100 10M1k
CROSS TALK (dB)
10k 1M
0
–20
–40
V
DD
= +5V
V
SS
= –5V
V
REF
= 50mV rms
DAC A DATA = 0xFF
DAC B, DAC C, DAC D DATA = 0x00
–60
–80
–100
–120
–140
V
OUT
B
V
REF
CT = 20 LOG
100k
01114-026
Figure 26. Crosstalk vs. Frequency
FREQUENCY (Hz)
60
010 100
PSRR (dB)
1k 100k
50
40
30
20
10
10k
DATA = 0x80
T
A
= +25°C
+PSRR, V
DD
= +5V ±∆10%
–PSRR, V
SS
= –5V ±∆10%
+PSRR, V
DD
= +3V ±∆10%
–PSRR, V
SS
= –3V ±∆10%
01114-027
Figure 27. Power-Supply Rejection vs. Frequency
AD7304/AD7305
Rev. C | Page 13 of 20
DIGITAL INPUT VOLTAGE (V)
12
10
0051
SUPPLY CURRENT (mA)
234
8
6
4
2
V
DD
= +5V
V
SS
= –5V
V
REF
= +2.5V
A0 = +5V
ALL OTHER DIGITAL
PINS VARYING
I
DD
I
SS
01114-028
Figure 28. Supply Current vs. Digital Input Voltage
DIGITAL INPUT VOLTAGE (V)
10
1
0.0001 051
SUPPLY CURRENT (mA)
234
0.1
0.01
0.001
V
DD
= +5V
V
SS
= –5V
V
REF
= +2.5V
ALL DIGITAL PINS VARY,
EXCEPT A0 = +5V
I
DD
I
SS
01114-029
Figure 29. Shutdown Supply Current vs. Digital Input Voltage (A0 Only)
TEMPERATURE (
°
C)
5.0
4.4
2.0–55 125–35
SUPPLY CURRENT (mA)
–15 5 25 45 65 85 105
3.8
3.2
2.6
V
DD
= +5V
V
SS
= –5V
V
REF
= +2.5V
I
DD
AND I
SS
01114-030
Figure 30. Supply Current vs. Temperature
80
20
–55 125–35
SHUTDOWN SUPPLY (µA)
–15 5 25 45 65 85 105
70
60
50
40
30
V
DD
= +5.5V
V
SS
= –5.5V
V
REF
= +2.5V
PIN A0 FLOATING
TEMPERATURE (
°
C)
01114-031
Figure 31. Shutdown Supply Current vs. Temperature
TEMPERATURE (
°
C)
0.08
–0.04
084
NORMALIZED TOTAL UNADJUSTED
ERROR DRIFT (LSB)
168 252 336 420 504
0.04
0
–0.08
READING MADE AT T
A
= +25
°
C
SAMPLE SIZE = 924 UNITS
V
DD
= +2.7V
V
DD
= +5.5V
01114-032
Figure 32. Normalized TUE Drift Accelerated by Burn-In Hours
of Operation @ 150°C
AD7304/AD7305
Rev. C | Page 14 of 20
CIRCUIT OPERATION
The AD7304/AD7305 are 4-channel, 8-bit, voltage output
DACs, differing primarily in digital logic interface and number
of reference inputs. Both parts share the same internal DAC
design and true rail-to-rail output buffers. The AD7304 contains
four independent multiplying reference inputs, while the
AD7305 has one common reference input. The AD7304 uses a
3-wire SPI-compatible serial data interface, while the AD7305
offers an 8-bit parallel data interface.
DAC SECTION
Each part contains four voltage-switched R-2R ladder DACs.
Figure 33 shows a typical equivalent DAC. These DACs are
designed to operate both single-supply or dual-supply,
depending on whether the user supplies a negative voltage on
the VSS pin. In a single-supply application, the VSS is tied to
ground. In either mode, the DAC output voltage is determined
by the VREF input voltage and the digital data (D) loaded into
the corresponding DAC register according to Equation 1.
VOUT = VREF D/256 (1)
Note that the output full-scale polarity is the same as the VREF
polarity for dc reference voltages.
V
REF
DB7 2R
V
DD
V
SS
V
OUT
R
2R
DB6 2R
DB0 2R
01114-033
Figure 33. Typical Equivalent DAC Channel
These DACs are also designed to accommodate ac reference
input signals. As long as the ac signals are maintained between
VSS < VREF < VDD, the user can expect 50 kHz of full power,
multiplying bandwidth performance. In order to use negative
input reference voltages, the VSS pin must be biased with a
negative voltage of equal or greater magnitude than the
reference voltage.
The reference inputs are code dependent, exhibiting worst-case
minimum resistance values specified in the parametric specifi-
cation table. The DAC outputs VOUTA, VOUTB, VOUTC, and VOUTD
are each capable of driving 2 kΩ loads in parallel with up to 500 pF
loads. Output sink current and source current are shown in
Figure 10 and Figure 11, respectively. The output slew rate is
nominally 3.6 V/µs while operating from ±5 V supplies. The
low output impedance of the buffers minimizes crosstalk
between analog input channels. At 100 kHz, 65 dB of channel-
to-channel isolation exists (Figure 26). Output voltage noise is
plotted in Figure 23. In order to maintain good analog perform-
ance, power supply bypassing of 0.01 µF in parallel with 1 µF is
recommended. The true rail-to-rail capability of the AD7304/AD7305
allows the user to connect the reference inputs directly to the
same supply as the VDD or VSS pin (Figure 34). Under these
conditions, clean power supply voltages (low ripple, avoid
switching supplies) appropriate for the application should be
used.
V
DD
V
SS
V
OUT
X
120kΩ
Q1
Q2
01114-034
Figure 34. Equivalent DAC Amplifier Output Circuit
AD7304/AD7305
Rev. C | Page 15 of 20
AD7304 SERIAL DATA INTERFACE
The AD7304 uses a 3-wire (CS, SDI, CLK) SPI-compatible
serial data interface. New serial data is clocked into the serial
input register in a 12-bit data-word format. MSB bits are loaded
first.
Table 5 defines the 12 data-word bits. Data is placed on the
SDI/SHDN pin and clocked into the register on the positive
clock edge of CLK subject to the data setup and data hold time
requirements specified in the Timing Specifications section.
Data can only be clocked in while the CS chip select pin is
active low. Only the last 12-bits clocked into the serial register
are interrogated when the CS pin returns to the logic high state,
extra data bits are ignored. Since most microcontrollers output
serial data in 8-bit bytes, two right-justified data bytes can be
written to the AD7304. Keeping the CS line low between the
first and second byte transfer results in a successful serial
register update.
Once the data is properly aligned in the shift register, the
positive edge of the CS initiates either the transfer of new data
to the target DAC register, determined by the decoding of
Address Bits A1 and A0, or the shutdown features is activated
based on the SAC or SDC bits. When either SAC or SDC pins
are set (Logic 0), the loading of new data determined by Bits B9
to B0 are still loaded, but the results do not appear on the buffer
outputs until the device is brought out of the shutdown state.
The selected DAC output voltages become high impedance with
a nominal resistance of 120 kΩ to ground, see Figure 34. If
both the SAC and SDC pins are set, all channels are still placed
in shutdown mode. When the AD7304 has been programmed
into the power shutdown state, the present DAC register data is
maintained as long as VDD remains greater than 2.7 V. The
remaining characteristics of the software serial interface are
defined by Table 4, Table 5, and Figure 5.
Two additional pins, CLR and LDAC, on the AD7304 provide
hardware control over the clear function and the DAC register
loading. If these functions are not needed, the CLR pin can be
tied to logic high, and the LDAC pin can be tied to logic low.
The asynchronous input CLR pin forces all input and DAC
registers to the zero-code state. The asynchronous LDAC pin
can be strobed to active low when all DAC registers need to be
updated simultaneously from their respective input registers.
The LDAC pin places the DAC register in a transparent mode
while in the logic low state.
AD7304
DAC A
DAC A
B
C
D
2:4
DECODE
A0
A1
SDC
SAC
D0
D1
D2
D3
D4
D5
D6
D7
8
EN
320kΩ
280kΩ
80kΩ
640kΩ680kΩ
V
DD
LDAC V
SS
V
OUT
C
CS
SDI
V
OUT
B
V
OUT
A
V
DD
DQ
INPUT
REGISTER R
POWER-
ON
RESET
V
REF
AV
REF
BV
REF
CV
REF
D
V
OUT
D
CLR
GND
CLK
INPUT
REGISTER R
R
R
DQ
DQ
DQ
OE
DAC A
REGISTER
DAC B
OE
DAC B
REGISTER
DAC C
OE
DAC C
REGISTER
DAC D
OE
DAC D
REGISTER
01114-035
INPUT
REGISTER
INPUT
REGISTER
R
R
R
R
Figure 35. AD7304 Equivalent Logic Interface
AD7304 HARDWARE SHUTDOWN SHDN
If a three-state driver is used on the SDI/SHDN pin, the
AD7304 can be placed into a power shutdown mode when the
SDI/ SHDN pin is placed in a high impedance state. For proper
operation, no other termination voltages should be present on
this pin. An internal window comparator detects when the logic
voltage on the SHDN pin is between 28% and 36% of VDD. A
high impedance internal bias generator provides this voltage on
the SHDN pin. The four DAC output voltages become high
impedance with a nominal resistance of 120 kΩ to ground (see
Figure 34 for an equivalent circuit).
AD7304/AD7305 POWER-ON RESET
When the VDD power supply is turned on, an internal reset
strobe forces all the input and DAC registers to the zero-code
state. The VDD power supply should have a monotonically
increasing ramp in order to have consistent results, especially in
the region of VDD = 1.5 V to 2.3 V. The VSS supply has no effect
on the power-on reset performance. The DAC register data
stays at zero until a valid serial register software load takes
place. In the case of the double-buffered AD7305, the output
DAC register can only be changed once the LDAC strobe is
initiated.
POWER-UP SEQUENCE
It is recommended to power VDD/VSS first before applying any
voltage to the reference terminals to avoid potential latch up.
The ideal power-up sequence is in the following order: GND,
VDD, VSS, Digital Inputs, and VREFx. The order of powering
digital inputs and reference inputs is not important as long as
they are powered after VDD/VSS.
AD7304/AD7305
Rev. C | Page 16 of 20
AD7305 PARALLEL DATA INTERFACE
The AD7305 has an 8-bit parallel interface DB7 = MSB, DB0 =
LSB. Two address bits, A1 and A0, are decoded when an active
low write strobe is placed on the WR pin, see Table 6. The WR
is a level-sensitive input pin, therefore, the data setup and data
hold times defined in the Timing Specifications section need to
be adhered to.
AD7305
8
320k
Ω
280k
Ω
80kΩ
640k
Ω
680k
Ω
V
DD
LDAC V
SS
WR
V
DD
V
REF
GND
DATA
DB0–DB7
A1
A0/SHDN
R
R
R
R
POWER-
ON
RESET
DAC A
OE
DAC A
REGISTER
DAC B
OE
DAC B
REGISTER
DAC C
OE
DAC C
REGISTER
DAC D
OE
DAC D
REGISTER
DAC A
B
C
D
2:4
DECODE
V
OUT
C
V
OUT
B
V
OUT
A
V
OUT
D
01114-036
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
R
R
R
R
Figure 36. AD7305 Equivalent Logic Interface
The LDAC pin provides the capability of simultaneously
updating all DAC registers with new data from the input
registers at the same time. This results in the analog outputs all
changing to their new values at the same time. The LDAC pin is
a level-sensitive input. If the simultaneous update feature is not
required, the LDAC pin can be tied to logic low. When the
LDAC is tied to Logic Low, the DAC registers become
transparent and the input register data determines the DAC
output voltage (see Figure 36 for an equivalent interface logic
diagram).
AD7226 PIN COMPATIBILITY
By tying the LDAC pin to ground, the AD7305 has the same pin
configuration and functionality as the AD7226, with the
exception of a lower power supply operating voltage.
AD7305 HARDWARE SHUTDOWN SHDN
If a three-state driver is used on the A0/SHDN pin, the AD7305
can be placed into a power shutdown mode when the A0/SHDN
pin is placed in a high impedance state. For proper operation,
no other termination voltages should be present on this pin. An
internal window comparator detects when the logic voltage on
the SHDN pin is between 28% and 36% of VDD. A high imped-
ance, internal-bias generator provides this voltage on the SHDN
pin. The four DAC output voltages become high impedance
with a nominal resistance of 120 kΩ to ground.
ESD PROTECTION CIRCUITS
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND). The VREF pins also contain a back-
biased ESD protection Zener connected to VDD (see Figure 37).
GND
DIGITA
L
INPUTS V
DD
V
REF
X
01114-037
Figure 37. Equivalent ESD Protection Circuits
AD7304/AD7305
Rev. C | Page 17 of 20
APPLICATIONS
The AD7304/AD7305 are inherently 2-quadrant multiplying
DACs. That is, they can easily be set up for unipolar output
operation. The full-scale output polarity is the same as the
reference input voltage polarity.
In some applications, it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing.
This is easily accomplished using an external true rail-to-rail op
amp, such as the OP295. Connecting the external amplifier with
two equal value resistors, as shown in Figure 38, results in a full
4-quadrant multiplying circuit. In this circuit, the amplifier
provides a gain of two, which increases the output span
magnitude to 10 V. The transfer equation of this circuit shows
that both negative and positive output voltages are created as
the input data (D) is incremented from code zero (VOUT = –5 V)
to midscale (VOUT = 0 V) to full scale (VOUT = +5 V).
REFOUT V
D
V×
−
=1128
(2)
+5V 10kΩ10kΩ
AD7304
REF
–5V < V
OUT
< +5V
01114-038
2.2pF
Figure 38. 4-Quadrant Multiplying Application Circuit
AD7304/AD7305
Rev. C | Page 18 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AA
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
2.65 (0.1043)
2.35 (0.0925)
1.27 (0.0500)
BSC
16 9
8
1
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
10.50 (0.4134)
10.10 (0.3976)
8°
0°
0.75 (0.0295)
0.25 (0.0098) × 45°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COPLANARITY
0.10
Figure 39. 16-Lead Standard Small Outline Package [SOIC]
Wide Body (R-16)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AC
0.75 (0.0295)
0.25 (0.0098)
20 11
10
1
8°
0°
× 45°
1.27 (0.0500)
0.40 (0.0157)
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
2.65 (0.1043)
2.35 (0.0925)
0.33 (0.0130)
0.20 (0.0079)
1.27
(0.0500)
BSC
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
13.00 (0.5118)
12.60 (0.4961)
COPLANARITY
0.10
Figure 40. 20-Lead Standard Small Outline Package [SOIC]
Wide Body (R-20)
Dimensions shown in millimeters and (inches)
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX 0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
20
1
11
10
6.40 BSC
4.50
4.40
4.30
PIN 1
6.60
6.50
6.40
SEATING
PLANE
0.15
0.05
0.30
0.19
0.65
BSC 1.20 MAX 0.20
0.09 0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153AC
COPLANARITY
0.10
Figure 42. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
AD7304/AD7305
Rev. C | Page 19 of 20
ORDERING GUIDE
Model Temperature Range Package Description Package Options
AD7304BR –40°C to +85°C 16-Lead SOIC R-16
AD7304BR-REEL –40°C to +85°C 16-Lead SOIC R-16
AD7304BRZ1–40°C to +85°C 16-Lead SOIC R-16
AD7304BRZ-REEL1 –40°C to +85°C 16-Lead SOIC R-16
AD7304YR –40°C to +125°C 16-Lead SOIC R-16
AD7304YRZ1 –40°C to +125°C 16-Lead SOIC R-16
AD7304BRU –40°C to +85°C 16-Lead TSSOP RU-16
AD7304BRU-REEL7 –40°C to +85°C 16-Lead TSSOP RU-16
AD7305BR –40°C to +85°C 20-Lead SOIC R-20
AD7305BR-REEL –40°C to +85°C 20-Lead SOIC R-20
AD7305YR –40°C to +125°C 20-Lead SOIC R-20
AD7305YR-REEL –40°C to +125°C 20-Lead SOIC R-20
AD7305BRU –40°C to +85°C 20-Lead TSSOP RU-20
AD7305BRU-REEL7 –40°C to +85°C 20-Lead TSSOP RU-20
AD7305BRUZ1 –40°C to +85°C 20-Lead TSSOP RU-20
AD7305BRUZ-REEL71 –40°C to +85°C 20-Lead TSSOP RU-20
1 Z = Pb-free part.
AD7304/AD7305
Rev. C | Page 20 of 20
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A. C01114-0-11/04(C)
