Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. K
06/06/05
IS61LV256 ISSI®
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying
on any published information and before placing orders for products.
FEATURES
• High-speed access times:
-- 8, 10, 12, 15 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
-- 345 mW (max.) operating
-- 7 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three-state outputs
• Lead-free Available
DESCRIPTION
The ISSI IS61LV256 is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using
ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 8 ns maximum.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation is reduced to
50 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Enable (CE). The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS61LV256 is available in the JEDEC standard 28-pin,
300-mil SOJ and the 450-mil TSOP (Type I) packages.
32K x 8 LOW VOLTAGE
CMOS STATIC RAM June 2005
FUNCTIONAL BLOCK DIAGRAM
A0-A14
CE
OE
WE
32K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
IS61LV256 ISSI
®
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. K
06/06/05
PIN CONFIGURATION
28-Pin SOJ
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
A11
A9
A8
A13
WE
VDD
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VDD
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
28-Pin TSOP (Type I)
PIN DESCRIPTIONS
A0-A14 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
VDD Power
GND Ground
TRUTH TABLE
Mode WEWE
WEWE
WE CECE
CECE
CE OEOE
OEOE
OE I/O Operation VDD Current
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC
Read H L L DOUT ICC
Write L L X DIN ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VDD Power Supply Voltage Relative to GND –0.5 to +4.6 V
VTERM Terminal Voltage with Respect to GND –0.5 to +4.6 V
TSTG Storage Temperature –65 to +150 ° C
PDPower Dissipation 1 W
IOUT DC Output Current ±20 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
IS61LV256 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. K
06/06/05
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –2.0 mA 2.4 — V
VOL Output LOW Voltage VDD = Min., IOL = 4.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VDD + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND ≤ VIN ≤ VDD Com. –1 1 µA
Ind. –5 5
ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled Com. –1 1 µA
Ind. –5 5
Notes:
1. VIL (min.) = –0.3V (DC); VIL (min.) = –2.0V (pulse width ≤ 2.0 ns).
VIH (max.) = VDD + 0.5V (DC); VIH (max.) = VDD + 2.0V (pulse width ≤ 2.0 ns).
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 5 p F
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
OPERATING RANGE
Range Ambient Temperature Speed (ns) VDD
Commercial 0°C to +70°C 8,10,12 3.3V, +10%, –5%
15 3.3V ± 10%
Industrial –40°C to +85°C 10,12 3.3V + 10%, –5%
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns -10 ns -12 ns -15 ns
Sym. Parameter Test Conditions
Min.Max. Min.Max. Min.Max. Min.Max. Unit
ICC VDD Dynamic Operating VDD = Max., CE = VIL Com. — 120 — 110 — 100 — 90 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — — — 120 — 110 — 100
ISB1TTL Standby Current VDD = Max., C o m. — 1 5 — 1 0 — 1 0 — 1 0 mA
(TTL Inputs) VIN = VIH or VIL Ind. — — — 20 — 20 — 20
CE ≥ VIH, f = 0
ISB2CMOS Standby VDD = Max., C o m . — 2 — 2 — 2 — 2 mA
Current (CMOS Inputs) CE
≤
VDD – 0.2V, Ind. — — — 5 — 5 — 5
VIN ≥ VDD – 0.2V, or
VIN
≤
0.2V, f = 0
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS61LV256 ISSI
®
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. K
06/06/05
AC TEST LOADS
Figure 1. Figure 2.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1 and 2
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 ns -10 ns -12 ns -15 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 8 — 10 — 12 — 15 — ns
tAA Address Access Time — 8 — 10 — 12 — 15 ns
tOHA Output Hold Time 2 — 2 — 2 — 2 — n s
tACE CE Access Time — 8 — 10 — 12 — 15 ns
tDOE OE Access Time — 4 — 5 — 6 — 7 ns
tLZOE
(2)
OE to Low-Z Output 0 — 0 — 0 — 0 — ns
tHZOE
(2)
OE to High-Z Output — 4 — 5 — 5 — 6 n s
tLZCE
(2)
CE to Low-Z Output 3 — 3 — 3 — 3 — n s
tHZCE
(2)
CE to High-Z Output — 4 — 5 — 6 — 7 n s
tPU
(3)
CE to Power-Up 0 — 0 — 0 — 0 — ns
tPD
(3)
CE to Power-Down — 8 — 10 — 12 — 15 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100%
tested.
3. Not 100% tested.
319 Ω
30 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
IS61LV256 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. K
06/06/05
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
D
OUT
t
HZCE
READ CYCLE NO. 2(1,3)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
IS61LV256 ISSI
®
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. K
06/06/05
AC WAVEFORMS
WRITE CYCLE NO. 1
(CE Controlled, OE is HIGH or LOW)
(1 )
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
DIN DATA
IN
VALID
t
LZWE
t
SD
CE_WR1.eps
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-8 ns -10 ns -12 ns -15 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 8 — 10 — 12 — 15 — n s
tSCE CE to Write End 6.5 — 8 — 8 — 10 — ns
tAW Address Setup Time 6.5 — 8 — 8 — 10 — ns
to Write End
tHA Address Hold 0 — 0 — 0 — 0 — ns
from Write End
tSA Address Setup Time 0 — 0 — 0 — 0 — ns
tPWE1WE Pulse Width (OE HIGH) 6.5 — 7 — 8 — 10 — n s
tPWE2WE Pulse Width (OE LOW) 8 — 1 0 — 1 2 — 15 — n s
tSD Data Setup to Write End 5 — 5 — 6 — 7 — ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — n s
tHZWE
(3)
WE LOW to High-Z Output — 3.5 — 4 — 6 — 7 n s
tLZWE
(3)
WE HIGH to Low-Z Output 0 — 0 — 0 — 0 — n s
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing
are referenced to the rising or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
IS61LV256 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. K
06/06/05
DATA UNDEFINED
LOW
t WC
VALID ADDRESS
t PWE1
t AW
t HA
HIGH-Z
t HD
t SA t HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t LZWE
t SD
CE_WR2.eps
WRITE CYCLE NO. 2
(WE Controlled, OE is HIGH During Write Cycle)
(1,2)
WRITE CYCLE NO. 3
(WE Controlled, OE is LOW During Write Cycle)
(1)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIH.
IS61LV256 ISSI
®
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. K
06/06/05
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
8 IS61LV256-8T TSOP - Type I
IS61LV256-8J 300-mil Plastic SOJ
IS61LV256-8JL 300-mil Plastic SOJ, Lead-free
10 IS61LV256-10T TSOP - Type I
IS61LV256-10TL TSOP - Type I, Lead-free
IS61LV256-10J 300-mil Plastic SOJ
12 IS61LV256-12T TSOP - Type I
IS61LV256-12J 300-mil Plastic SOJ
IS61LV256-12JL 300-mil Plastic SOJ, Lead free
15 IS61LV256-15T TSOP - Type I
IS61LV256-15TL TSOP - Type I, Lead free
IS61LV256-15J 300-mil Plastic SOJ
IS61LV256-15JL 300-mil Plastic SOJ, Lead free
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
10 IS61LV256-10TI TSOP - Type I
IS61LV256-10JI 300-mil Plastic SOJ
12 IS61LV256-12TI TSOP - Type I
IS61LV256-12TLI TSOP - Type I, Lead-free
IS61LV256-12JI 300-mil Plastic SOJ
IS61LV256-12JLI 300-mil Plastic SOJ, Lead-free
PACKAGING INFORMATION ISSI®
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
02/25/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
300-mil Plastic SOJ
Package Code: J
Notes:
1. Controlling dimension: inches, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash
protrusions and
should be measured from the bottom of
the package
.
4. Formed leads shall be planar with respect to one
another within 0.004 inches at the seating plane.
MILLIMETERS INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
N0.
Leads 24/26
A — — 3.56 — — 0.140
A1 0.64 — — 0.025 — —
A2 2.41 — 2.67 0.095 — 0.105
b 0.41 — 0.51 0.016 — 0.020
B 0.66 — 0.81 0.026 — 0.032
C 0.20 — 0.25 0.008 — 0.010
D 17.02 — 17.27 0.670 — 0.680
E 8.26 — 8.76 0.325 — 0.345
E1 7.49 — 7.75 0.295 — 0.305
E2 6.27 — 7.29 0.247 — 0.287
e 1.27 BSC 0.050 BSC
SEATING PLANE
1
N
E1
D
E2
E
b
eA1
A
BC
A2
PACKAGING INFORMATION ISSI®
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
02/25/03
MILLIMETERS INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
N0.
Leads 28
A — — 3.56 — — 0.140
A1 0.64 — — 0.025 — —
A2 2.41 — 2.67 0.095 — 0.105
b 0.41 — 0.51 0.016 — 0.020
B 0.66 — 0.81 0.026 — 0.032
C 0.20 — 0.25 0.008 — 0.010
D 18.29 — 18.54 0.720 — 0.730
E 8.26 — 8.76 0.325 — 0.345
E1 7.49 — 7.75 0.295 — 0.305
E2 6.27 — 7.29 0.247 — 0.287
e 1.27 BSC 0.050 BSC
MILLIMETERS INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
N0.
Leads 32
A — — 3.56 — — 0.140
A1 0.64 — — 0.025 — —
A2 2.41 — 2.67 0.095 — 0.105
b 0.41 — 0.51 0.016 — 0.020
B 0.66 — 0.81 0.026 — 0.032
C 0.20 — 0.25 0.008 — 0.010
D 20.83 — 21.08 0.820 — 0.830
E 8.26 — 8.76 0.325 — 0.345
E1 7.49 — 7.75 0.295 — 0.305
E2 6.27 — 7.29 0.247 — 0.287
e 1.27 BSC 0.050 BSC
300-mil Plastic SOJ
Package Code: J
Integrated Silicon Solution, Inc.
1
ISSI
®
PACKAGING INFORMATION
D
SEATING PLANE
B
eC
1
E
A1
A
S
H
Lα
N
Plastic TSOP - 28-pins
Package Code: T (Type I)
Plastic TSOP (T—Type I)
Millimeters Inches
Symbol Min Max Min Max
Ref. Std.
No. Leads 28
A 1.00 1.20 0.037 0.047
A1 0.05 0.20 0.002 0.008
B 0.16 0.27 0.006 0.011
C 0.10 0.20 0.004 0.008
D 7.90 8.10 0.308 0.316
E 11.70 11.90 0.456 0.465
H 13.20 13.60 0.515 0.531
e 0.55 BSC 0.022 BSC
L 0.30 0.70 0.011 0.027
α0°5°0°5°
Notes:
1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and
should be measured from the bottom of the package
.
4. Formed leads shall be planar with respect to one another within
0.004 inches at the seating plane.
PK13197T28 Rev. B 01/31/97
