June 2011 Rev 8 1/47
1
M45PE10
1 Mbit, page-erasab l e serial Flash memory
with byte-alterability and 75 MHz SPI bus interface
Features
SPI bus comp atible serial interface
75 MHz clock rate (maximum)
2.7 V to 3.6 V single supply voltage
1 Mbit of page-erasable Flash memory
Page size : 25 6 bytes
– Page w rite in 11 ms (typical)
– Page program in 0 . 8 ms (typi c al)
– Page e rase in 10 ms (typ ic al)
Sector erase (512 Kbits)
Hardw are writ e protec tion of th e bottom se ctor
(64 Kbytes)
Electronic signature
– JEDEC standard two-byte signature
(4011h)
– Unique ID code (UID) with 16 bytes read-
only, available upon customer request only
in the T9HX pro ce ss
Deep power-down m ode 1 µA (typical)
More than 100 000 write cycles
More than 20 years data retention
Packages
– RoHS compliant
SO8N (MN)
150 mil width
VFQPN8 (MP)
(MLP8)
Contents M45PE10
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Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.7 V
CC
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8 V
SS
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 An easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 13
4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6 Active power, standby power and deep power-down modes . . . . . . . . . . 13
4.7 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Read identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 Read status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
M45PE10 Contents
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6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Read data bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.6 Read data bytes at higher speed (FAST_READ) . . . . . . . . . . . . . . . . . . . 23
6.7 Page write (PW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.8 Page program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.9 Page erase (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.10 Sector erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.11 Deep power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.12 Release from deep power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
List of tables M45PE10
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List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Pow er-up timing and VWI threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 8. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 9. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5
Table 10. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 11. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 12. AC characteristics (25 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 13. AC characteristics (33 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 14. AC characteristics (50 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. AC characteristics (75 MHz operation, T9HX (0.11 µm ) process) . . . . . . . . . . . . . . . . . . . 40
Table 16. SO8N – 8 lead plas t ic small outline, 15 0 m ils body widt h, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 17. MLP8, 8-lead very thin dual flat package no lead, 6 × 5 mm, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 18. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
M45PE10 List of figures
5/47
List of figures
Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. SO and VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. SPI modes supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Read identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 20
Figure 9. Read status register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . . 21
Figure 10. Read data bytes (READ) instruct ion sequ ence and data-out sequence . . . . . . . . . . . . . . 22
Figure 11. Read data bytes at higher speed (FAST_READ) instruction sequence
and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Page write (PW) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. Page program (PP) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. Page erase (PE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15. Sector erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16. Deep power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. Release from deep power-down (RDP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 19. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 20. Serial input timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 21. Write Protect setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 22. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 23. Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 24. SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 43
Figure 25. MLP8, 8-lead very thin dual flat package no lead, 6 × 5 mm, package outline. . . . . . . . . . 44
Description M45PE10
6/47
1 Description
The M45PE10 is a 1 M bit (128 Kb x 8 bit) serial paged Fla sh memory accessed by a high
speed SPI-compatible bus.
The memor y can be wr itte n o r prog ramm ed 1 to 256 b ytes at a ti me, usin g t he p a ge w rit e or
page pr ogram instru ction. The page write instru ction con s ists of an in t egrated page erase
cycle followed by a page program cycle.
The memory is organized as 2 sectors, each containing 256 pages. Each page is 256 bytes
wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131,072 bytes.
The memory can be erased a page at a time, using the page erase instruction, or a sector at
a time, using the sector erase instruction.
Important note
This datasheet details the functionality of the M45PE10 devices, based on the previous T7X
process or based on the current T9HX process (available since August 2007). Delivery of
parts oper at ing with a maxim um cloc k rat e of 75 M Hz starts from week 8 of 2008.
Figure 1. Logic diagr am
Figure 2. SO and VDFPN connections
1. There is an exposed central pad on the underside of the VFQFP N package. This is pulled, internal ly, to
V
SS
, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Package mechanical secti on for package dimensions, and how to identif y pin-1.
Reset
AI07403
S
VCC
M45PE10
VSS
W
Q
C
D
1
AI07404
2
3
4
8
7
6
5WS VCC
VSS
C
DQ
Reset
M45PE10
M45PE10 Description
7/47
Table 1. Signal names
Signal name Function Direction
C Serial Clock Input
D Serial Data input Input
Q Serial Data output Output
S Chip Select Input
W Write Protect Input
Reset Reset Input
V
CC
Supply voltage
V
SS
Ground
Signal description M45PE10
8/47
2 Signal description
2.1 Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2 Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
2.3 Serial Clock (C)
This input s ignal pro v ides th e t im ing of the serial interf ace. Instructions, addre sses, or data
present at serial data input (D) are latched on the rising edge of Serial Clock (C). Data on
serial data output (Q) changes after the falling edge of Serial Cloc k (C).
2.4 Chip Select (S)
When this in put signal is Hi gh, the devi c e is de s elected an d s er ial data output (Q) is at hi gh
impedance. Unless an internal read, program, erase or write cycle is in progress, the device
will be in the standby power mode (this is not the deep power-down mode). Driving Chip
Select (S) Low selects the device, placing it in the active power mode.
After power-up, a fa lling edge on C hip Sele ct (S) is required prior to the start of an y
instruction.
2.5 Reset (Reset)
The Re set (Reset) input provides a hardware reset for the memory. In this mode, the
outputs are hi gh impe dance.
When Reset (Reset) is driven High, the memory is in t he norm al operating mode . When
Reset ( Res et) is driven Low , the memory will enter the reset mode, provided that no internal
operation is currently in progress. Driving Reset (Reset) Low while an internal operation is in
progre ss has no effect on that internal op eration (a write cycle, prog ram cycle, or era se
cycle).
2.6 Write Protect (W)
This input signal puts the device in the hardwa re protec ted mo de, whe n writ e protect (W ) is
connected to V
SS
, causin g the fir st 256 p ages of m emory to becom e read-o nly by pr otecti ng
them from write, progr am and erase op er ations. When write protect (W) is connecte d t o
V
CC
, the first 256 pages of memory behave like the other pages of memory.
M45PE10 Signal description
9/47
2.7 V
CC
supply voltage
V
CC
is the supply voltage.
2.8 V
SS
ground
V
SS
is the reference for the V
CC
suppl y v oltag e.
SPI modes M45PE10
10/47
3 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
CPOL =0, CP HA=0
CPOL =1, CP HA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
outp ut data is av ailable from t he fall ing edge of Se rial Clock (C ).
The difference between the two modes, as shown in Figure 4, is th e cl ock p ol arity w hen th e
bus master is in standby mode and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 3. Bus master and memory devices on the SPI bus
1. The Write Protect (W) signal should be driven, High or Low as appropriate.
Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only
one device is selected at a time, so only one device drives the serial data output (Q) line at
a tim e, the other devices are high impedan c e.
The pull-up resistor R (represented in Figure 3) ensures that no device is selected if the bus
master leaves the S line in the high impedance state.
In applications where the bus master might enter a state where all inputs/outputs SPI li nes
are in high impedance at the same t ime (for example, if the bus master is re set durin g the
transmission of an instructio n), the Clo ck line (C) must be connected to an external pul l-
down resistor so that, if all inputs/outputs become high impedance, the C line is pulled Low
(while the S line is pulled High). This ensures that S and C do not be com e Hig h at the sa me
tim e, and so, th at the t
SHCH
requirement is met.
AI12836c
SPI bus master
SPI memory
device
SDO
SDI
SCK
CQD
S
SPI memory
device
CQD
S
SPI memory
device
CQD
S
CS3 CS2 CS1
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
WReset WWReset
RR R
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
R
Reset
M45PE10 SPI modes
11/47
The typical value of R is 100 kΩ, assuming that the time constant R*C
p
(C
p
= parasitic
capacitance of the bus line) is short enough, as the S and C lines must reach the correct
state (S = High and C = Low) while the SPI bus is in high impedance.
Example: C
p
= 50 pF, that is R*C
p
= 5 µs <=> the applicat ion must ensure that the bus
master never leaves the SPI bus in the high impedance state for a time period shorter than
5µs.
Figure 4. SPI modes supported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
Operating features M45PE10
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4 Operating features
4.1 Sharing the overhead of modifying data
To write or program one (or more) data bytes, two instructions are required: Write Enable
(WREN), which is one byte, and a page write (PW) or page program (PP) sequence, which
consis ts of fou r by tes pl us da t a. Thi s i s fol lowed b y the inter nal cycl e (o f durati on t
PW
or t
PP
).
To share t his overhead, t he page write (P W) or page program (PP) instruc tion allows up to
256 bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1)
at a time, provided that they lie in consecutive addresses on the same page of memory.
4.2 An easy way to modify data
The page write (PW) instruction provides a convenient way of modifying data (up to 256
contiguous bytes at a time), and simply requires the start address, and the new data in the
instruction sequence.
The page write (PW) instruction is en tered by driving Chip S elect (S) Low, and then
transmitti ng the i nstruction byte, three address bytes (A23-A0 ) and at least one data byte ,
and then driving Chip Se lect (S) High. While Chip Select (S) is being held Low, the data
bytes are written to the data buffer, starting at the address given in the third address byte
(A7-A0). When Chip Select (S) is driven High, the write cycle starts. The remaining,
unchanged, bytes of the data buffer are automatically loaded with the values of the
corresponding bytes of t he addre ssed mem ory page. The addressed memory page th en
automatic al ly pu t into an erase cycle. Fina lly, the addressed memory page is programmed
wit h the c ontents of the data bu ffer.
All of this buffer management is handled internally, and is transparent to the user. The user
is given the facility of being able to alter the contents of the memory on a byte-by-byte basis.
For optimized timings, it is recommended to use the page write (PW) instruction to write all
consecutive targeted bytes in a single sequence versus using several page write (PW)
sequences wi th each containing only a few by tes (see Section 6.7: Page write (PW),
Table 14: AC charac ter istics ( 50 MHz ope r ati on), and Table 15: AC characteristics (75 MHz
operation, T9HX (0.11 µm) process)).
M45PE10 Operating features
13/47
4.3 A fast way to modify data
The Pa ge Prog ram (PP) in st ruct ion provides a f ast way of modif y ing data (u p t o 256
conti guous byt es at a time), pro v ided th at it only involves resetting bits to 0 that had
previ o us ly been set to ‘1 ’.
This might be:
when the designer is programmi ng the device for the first time
when the designer knows that the page has al ready been erased by an earlier page
eras e ( P E) or s ec tor erase ( S E) instructio n. This is useful, for examp le , whe n s t or i ng a
fast stream of data, having first pe rformed the e r ase cycle wh en time was availa ble
when the desi gner knows tha t th e only changes in volve rese tting bits t o 0 t hat are s ti ll
set to ‘1’. Whe n t his method is possibl e, it has the addit ional ad vantage of mini m izing
the num ber of un necessary erase operat ions, and t he extra stress incurred by e ach
page.
For optimized timings, it is recommended to use the page program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several page
program (PP) sequences with each containing only a few bytes (see Section 6.8: Page
program (PP), Tabl e 14: AC characteristics (50 MHz operation), an d Table 15: AC
characteristics (75 MHz operatio n, T9HX (0.11 µm ) proc ess) ).
4.4 Polling during a write, program or erase cycle
A furt her imp roveme nt in the writ e, pr ogram o r era se time can be achie ved by not wa itin g for
the worst case delay (t
PW
, t
PP
, t
PE
, or t
SE
). The wri te in progr e s s (WIP) bit is provided in the
status registe r so that the a pplicat ion program ca n m onit or its value, polling it to esta blish
when the previous cycle is complete.
4.5 Reset
An internal power on reset circuit helps protect against inadvertent data writes. Addition
protection is provided by driving Reset (R eset) Low du ring the power-on process, and only
driving it High when V
CC
has reached the correct vol tag e level, V
CC
(min).
4.6 Active power, standby power and deep power-down modes
When Chip Select (S ) is Low, the device is selected, and in the active power mode.
When Chip Select (S) is Hi gh, the d evic e is dese lected , but coul d rema in in th e active po wer
mode until all internal cycles have completed (program, erase, write). The device then goes
in to the standby power mode. The device consumption drops to I
CC1
.
The deep power-down mode is entered when the specific instruction (the deep power-down
(DP) instruction) is executed. The device consumption drops further to I
CC2
. The device
remains in this mode until another specific instruction (the release from deep power-down
and read electronic signature (RES) instruction) is executed.
All other instructions are ignored while the device is in the deep power-down mode. This can
be use d as an ext ra sof twa re prot ecti on mecha nis m, w hen th e dev ic e is not i n ac tive u se, to
protec t the dev ice from inadv er te nt wr ite, pro gram or erase ins t ruc t i on s .
Operating features M45PE10
14/47
4.7 Status register
The status register contains two status bits that can be read by the read status register
(RDSR) instruction. See Section 6 .4 : Read s tatus register ( RD S R) fo r a det ai l ed desc rip tion
of the status register bits .
4.8 Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can o pe rate correctly in the presen ce of excessive noise. To help comb at this, the
M45PE1 0 features the following dat a pr otection mechan is ms :
Power on reset and an internal timer (t
PUW
) can pr o v id e pr otection again s t ina dv ertent
changes while the power supply is outside the operating specification.
Program, erase and write instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution.
All instructions that modify data must be preceded by a write enable (WREN)
instruction to set the write enable latch (WEL) bit. This bit is returned to its reset state
by the f ollowing events:
– Power-up
– Res et (RESET) driven Low
– Write disable (WRDI) instruction completion
– Pag e write (PW ) instruc ti on completion
– Pag e program (PP ) instruction completion
– Pag e erase ( PE) instruction completi on
– Sector erase (SE) instruction completion
The har dware pr otect ed mode is entered when wri te prot ect (W) is driven Low, causing
the first 256 pages of memory to become read-onl y. When write protect (W) is drive n
High, th e f irst 256 pages of memory beha ve like the other pages of memo ry
The Rese t (R eset ) signal can be driven Low to protect the contents of the memory
during any critical time, not ju st during power-up and power-down
In addi tion to the low power consum ption feature , the deep power-down mode offers
extra software p r ot ecti on from inadverten t write, program and erase instructi ons while
the device is not in act iv e use .
M45PE10 Memory organization
15/47
5 Memory organization
The memory is organized as:
512 pages (256 bytes eac h)
131, 07 2 by tes (8 bits each)
2 sectors (512 Kbits, 65536 byt es each)
Each page can be in dividua lly:
programmed (bits are programmed from 1 to 0)
erased (bits are erased from 0 to 1)
written (bits are changed to either 0 or 1)
The device is page or s ector er asable (bits are erase d from 0 to 1).
Ta ble 2. Memory organization
Sector Address range
1 10000h 1FFFFh
0 00000h 0FFFFh
Memory organization M45PE10
16/47
Figure 5. Block diagra m
AI07405
S
WControl logic High voltage
generator
I/O shift register
Address register
and counter 256-byte
data buffer
256 bytes (page size)
X decoder
Ydecoder
C
D
Q
Status
register
00000h
1FFFFh
000FFh
R
eset
10000h
First 256 pages ca
n
be made read-onl
y
M45PE10 Instructions
17/47
6 Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial d ata input (D) is sam pled o n t he fi rst rising edge of Serial Cloc k (C) after Chip Select
(S) is driven Low. Then, the one-b y te instr uc tion co de must be s h ifted in to the devi c e, m os t
significant bit first, on serial data input (D), each bit being latched on the rising edges of
Serial Clock (C).
The in struction s et is listed in Table 3.
Every i nst ruction sequence starts with a one-byte instruction code . Depe nding on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a read data by tes ( READ), read data bytes at higher spe ed (FAST_R E A D) or
read status register (RDSR) instruction, the shifted-in instruction sequence is followed by a
data-out sequence. Chip Select (S) can be driven High after any bit of the data-out
sequence is being shifted out.
In the case of a page write (PW), pag e program (PP), page erase (PE), secto r erase (SE),
write enable (WREN), write disable (WRDI), deep power-down (DP) or release from deep
power- down (RDP) instruction, Chip Select (S) must be driven High exactly at a byte
bounda r y, otherw is e the instructi on is r ejecte d, a nd is not execut ed. That is , Chip S el ec t (S)
must driven High when the number of clock pulses after Chip Select (S) being dri ven Low is
an exact multiple of eight.
All attempts to access the memory array during a write cycle, program cycle or erase cycle
are ignored, and the internal write cycle, program cycle or erase cycle continues unaffected.
Table 3. Instru cti on se t
Instruction Description One-byte instruction
code Address
bytes Dummy
bytes Data
bytes
WREN Write enable 0000 0110 06h 0 0 0
WRDI Write disable 0000 0100 04h 0 0 0
RDID Read identification 1001 1111 9Fh 0 0 1 to 3
RDSR Read status register 0000 0101 05h 0 0 1 to ∞
READ Read data bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read data bytes at higher
speed 0000 1011 0Bh 3 1 1 to ∞
PW Page write 0000 1010 0Ah 3 0 1 to 256
PP Page program 0000 0010 02h 3 0 1 to 256
PE Page erase 1101 1011 DBh 3 0 0
SE Sector erase 1101 1000 D8h 3 0 0
DP Deep power-down 1011 1001 B9h 0 0 0
RDP Release from deep
power-down 1010 1011 ABh 0 0 0
Instructions M45PE10
18/47
6.1 Write enable (WREN)
The write enable (W RE N) inst ruct ion (Figure 6) sets the write enable latch (WEL) bit.
The write enable latch (WEL) bit must be set prior to every page write (PW), page program
(PP), page e rase (PE), and sector erase (SE) instru ction.
The write enab le (WREN ) instructi on i s entered by dri v ing Chip Sel ec t ( S ) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 6. Write ena ble (WREN) instruction sequence
6.2 Write disable (WRDI)
The write disable (W RDI) instruction ( Figure 7) resets the write enable latch (WEL) bit.
The write disable (W RDI) instruction is entered by driving Chi p Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The write en able latch (WEL) bit is reset under the following co nditio ns:
Power-up
Write disable (WRDI) instruction completion
Page write (PW) instruction completion
Page program (PP) instruction completion
Page erase (PE) instruction completion
Sector erase (SE) in struction completion
Figure 7. Write disable (WRD I) instruction sequence
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
M45PE10 Instructions
19/47
6.3 Read identification (RDID)
The read identification (RDID) instruction allows to read the de vi c e identif ic a tion dat a:
Manufacturer identification (1 byte)
Device identification (2 bytes)
A unique ID code (UID) (17 bytes, of which 16 available upon customer request)
(a)
.
The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx.
The dev ic e identification i s as s ig ned by th e device m a nufacturer, an d i ndicates the m em o ry
type in the first byte (40h), and the memory capacity of the device in the second byte (11h).
The UID contains the length of the following data in the first byte (set to 10h), and 16 bytes
of the optional custo m ized factory data (CFD) cont ent. Th e CFD bytes are rea d-only an d
can be programmed with customers data upon their demand. If the customers do not make
requests, the de vices are shipped with all the CFD byte s programmed to zero (00h).
Any read identification (RDID) instruction whil e an erase or program cycle is in progress, is
not de coded, and has n o eff ect on th e cycle th at is in progre ss.
The de vice is first selected by driving Chip Se lect (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. After this, the 24-bit device identification, stored in the
memory, the 8-bit CFD length followed by 16 bytes of CFD content will be shifted out on
serial data output (Q). Each bit is shifted out during the falling edge of Serial Clock (C).
The instructi on sequence is sh own in Figure 8.
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S ) is driven High, the device is put in the standby power mode. Once in
the st and by power mod e, the devi ce wait s to be sel ecte d, so that it can rec eive, decode an d
exec ut e instruct ions.
a. The 17 bytes of unique ID code are available only in the T9HX process (see Important note on
page 6).
Table 4. Read identification (RDID) data-out sequence
Manufacturer
Identification
Device Identification UID
(1)
Memory type Memory capacity CFD length CFD content
20h 40h 11h 10h 16 bytes
1. The unique ID code is available only in the T9HX process (see Important note on page 6).
Instructions M45PE10
20/47
Figure 8. Read identi f ication (RDI D) i nstruction sequence and data-out sequence
1. The unique ID code is available only in the T9HX process (see Important note on page 6).
6.4 Read status register (RDSR)
The read status register (RDSR) instruction allows the status register to be read. The status
register may be read at any time, even while a program, erase or write cycle is in progress.
When one of these cycles is in pro gre ss, it is reco mmended to ch eck the write in progre ss
(WIP) bit before sending a new instruction to the device. It is also possible to read the status
regist er contin uously, as shown in Figure 9.
The stat us bits of the status regist er ar e as follows:
6.4.1 WIP bit
The write in progress (W I P ) bit ind icates wh ether the m emory is busy with a write, program
or erase cycle. When set to ‘1’, such a cycle is in progress, when reset to ‘0’ no such cycle is
in progress.
6.4.2 WEL bit
The write enable latch (WEL) bit indicates the status of the internal write enable latch. When
set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write enable latch is
reset and no write, program or erase instruction is accepted.
C
D
S
213456789101112131415
Instruction
0
AI06809c
Q
Manufacturer identification
High Impedance
MSB
Device identification
MSB
15 14 13 3 2 1 0
16 17 18 28 29 30 31
MSB
UID
Table 5. Status register format
b7 b0
0 0 0 0 0 0 WEL
(1)
1. WEL and WIP are volati le read-only bits (WEL is set and reset by specific instructions; WIP is
automati cally set and reset by the internal logic of the device).
WIP
(1)
M45PE10 Instructions
21/47
Figure 9. Read status r egister (RDSR) instruction sequence a nd dat a-ou t se quence
6.5 Read data bytes (READ)
The device is first selected by driving Chip Select (S) Low . T he instruction code for the read
data bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on serial data output (Q), each bit being shifted ou t, at a maximum
frequency f
R
, during the fa lling edge of Seri al Clock (C).
The instructi on sequence is sh own in Figure 10.
The first byt e addre ssed can be at any location. The address is a ut omatically incre mented
to the next hi gher add r ess after each byte of data is shift ed out. The wh ole mem ory can,
therefore, be read with a single read data bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be conti nued indefinitely.
The read data bytes (READ) instruction is terminated by driving Chip Select (S) High. Ch ip
select (S) can be driven High at any time during data output. Any read data bytes (READ)
instruction, while an era s e, pro gram or write cycle is in progress, is rejected without havi ng
any effects on the cycle that is in progress.
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
Instructions M45PE10
22/47
Figure 10. Read data bytes (READ) ins t ruc t ion se quence and dat a-out sequenc e
1. Address bits A23 to A17 are don’t care.
C
D
AI03748D
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 1 7
0
High Impedance Data out 1
Instruction 24-bit address
0
MSB
MSB
2
39
Data out 2
M45PE10 Instructions
23/47
6.6 Read data bytes at higher speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low . T he instruction code for the read
data byt es at highe r speed (FAS T_READ) instruct ion is follo wed by a 3-b y t e address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on serial data output (Q), each bit
being shifted out, at a maximum frequency f
C
, durin g the fa lling ed ge of Seria l Clock (C).
The instructi on sequence is sh own in Figure 11.
The first byt e addre ssed can be at any location. The address is a ut omatically incre mented
to the next hi gher add r ess after each byte of data is shift ed out. The wh ole mem ory can,
therefore, be read with a single read data bytes at higher speed (FAST_READ) instruction.
When the highest address is reached, the address counter rolls over to 000000h, allowing
the read sequence to be continued indefinitely.
The r ead d at a byte s a t hi ghe r sp eed (FAST_R EAD ) i nst ruc ti on i s te rmin ate d by dr iv ing Chip
Select (S) High. Ch ip se lec t (S) ca n be dr ive n Hig h at any ti me d uri ng data output. Any re ad
data byt es at highe r speed (FAST_R EAD) instruct ion, while an erase, pr ogram or write
cycle is in prog ress, is rejected without having any effects on the cycle that is in progress.
Figure 11. Read data bytes at higher speed (FAST_READ) instruc t ion sequence
and dat a -out s equence
1. Address bits A23 to A17 are don’t care.
C
D
AI04006
S
Q
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24-bit address
0
C
D
S
Q
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy byte
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
Instructions M45PE10
24/47
6.7 Page write (PW)
The page write (PW) instruction allows bytes to be written in the memory. Before it can be
accep ted, a wri te enabl e (WREN ) instru cti on must pre vious ly have bee n execut ed. Af ter th e
write enable (WREN) instruction has been decoded, the device sets the write enable latch
(WEL).
The page write (PW) instruction is entere d by driving Chip Sel ect (S) Low, followed by the
instruction code, three address bytes and at least one data byte on serial data input (D). The
rest of the page remains u nchange d if no power failu r e occurs during th is write cy cle.
The page write (PW) instruction perfo rms a page erase cycle even if o nl y one byte is
updated.
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding
the ad dressed page bou ndary wrap round, and are written f r om the start address o f t he
same p age (th e one whos e 8 least signifi cant add ress bits (A7-A0 ) are al l zero). Chip Se lect
(S) must be driven Low for the entire duration of the sequence.
The instructi on sequence is sh own in Figure 12.
If more tha n 256 byte s ar e sent t o th e dev ice , pre vious ly latc hed da t a are di scar ded an d t he
last 2 56 data bytes a r e guaran tee d to be written c orr ec tly with in the same page. If le ss than
256 data bytes are sent to device, they are correctly written at the requested addresses
without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the page write (PW) instruction to write all
consecutive targeted bytes in a single sequence versus using several page write (PW)
sequences wi th each containi ng only a few by tes (see Table AC ch aracteristics (50 MHz
operation) and Table 75 MHz operation).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, ot herwise the pag e write (PW) in structi on is not execute d.
As soon as Chip Select (S) is driven High, the self-timed page write cycle (whose duration is
t
PW
) is initiated. While the page write cycle is in progress, the status register may be read to
check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during
the self-timed page write cycle, and is 0 wh en it is comple ted. At some uns pecified time
before the cycle is complete, the write enable latch (W EL) bit is reset.
A page wr it e (PW) inst ruction applied to a page t hat is hardw are prot ect ed is not executed.
Any page write (PW ) instruction, while an erase , pro gra m or write cycle is in progress, is
rejected with ou t having any effects on the cycle tha t is in progress.
M45PE10 Instructions
25/47
Figure 12. P age write (PW) instruction sequence
1. Address bits A23 to A17 are don’t care.
2. 1 ≤ n ≤ 256.
C
D
AI04045
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-bit address
0
765432 0
1
Data byte 1
39
51
765432 0
1
Data byte 2
765432 0
1
Data byte 3 Data byte n
765432 0
1
MSB MSB
MSB MSB MSB
Instructions M45PE10
26/47
6.8 Page program (PP)
The page program (PP) instruction allo ws bytes to b e pro grammed in the memory
(changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the write enable (WREN) instructio n
has been decoded, the device sets the write enable latch (WEL).
The page program (PP) instruct ion is entered by dri ving Chi p Select (S) Low, followed by
the inst r ucti on co de, thr ee ad dres s byte s and at leas t one da t a by te on s er ial d at a input (D) .
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding
the ad dressed page bou ndary wrap round , and are pro gramme d from th e start add r ess of
the same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip
Select (S) must be driven Low for the entire duration of the sequence.
The instructi on sequence is sh own in Figure 13.
If more tha n 256 byte s ar e sent t o th e dev ice , pre vious ly latc hed da t a are di scar ded an d t he
last 256 data byte s are guara nteed to be progra mmed corre ctly with in the same pag e. If less
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the page program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several page
program (PP) sequences with each containing only a few bytes (see Table 14: AC
characteristics (50 MHz operation) and Ta ble 15 : AC charact eri st ics (75 MHz operation,
T9HX (0.11 µm) proces s)).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the page program (PP) instruction is not executed.
As soon as Chip Select (S) is driven Hi gh, the self-timed page program cycle (w hose
duration is t
PP
) is initia ted. While th e page program cycle is in progress, t he statu s register
may be read to check the value of the write in progress (WIP) bit. The write in progress
(WIP) b it is 1 during th e self-timed page pro gram cyc le, and is 0 when it is complet ed. At
some unspecified time before the cycle is complete, the write enable latch (WEL) bit is
reset.
A page program (PP) instruction applied to a page that is hardware protected is not
executed.
Any p a ge progra m (PP ) ins truction, whi le an er as e, progr am or write cycl e is in progre s s, is
rejected with out having an y effects on the cycle tha t is in progress.
M45PE10 Instructions
27/47
Figure 13. P age program (PP) instruction sequence
1. Address bits A23 to A17 are don’t care.
2. 1 ≤ n ≤ 256.
C
D
AI04044
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-bit address
0
765432 0
1
Data byte 1
39
51
765432 0
1
Data byte 2
765432 0
1
Data byte 3 Data byte n
765432 0
1
MSB MSB
MSB MSB MSB
Instructions M45PE10
28/47
6.9 Page erase (PE)
The page erase (P E) instruct ion sets to ‘1’ (FF h) all bits inside th e chosen page. Before it
can be accepted, a write enable (WREN) instruction must previously have been executed.
After the write enable (WREN) instruction has been decoded, the device sets the write
enable latch (WEL).
The page erase (PE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on serial data input (D). Any address inside the
page is a valid address fo r the page erase (PE) instruction. Chip Select (S) must be driven
Low for the enti re duration of the sequence.
The instructi on sequence is sh own in Figure 14.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the page erase (PE) instruction is not executed. As soon as Chip
Select (S) is driv en Hig h, the se lf-t imed p age era se cyc le ( whose dura ti on is t
PE
) is initiated.
While the page erase cycle is in progress, the status register may be read to check the value
of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed
page erase cycle, and is 0 when it is completed. At some unspec ifie d time before the cycl e
is complete, the write enable latch (WEL) bit is reset.
A page erase (PE) instruction applied to a page that is hardware protected is not executed.
Any page erase (PE) instr uctio n, while a n era s e, program or write cycl e is in prog ress, is
rejected with out having an y effects on the cycle tha t is in progress.
Figure 14. Page erase (PE) instruction sequence
1. Address bits A23 to A17 are don’t care.
24-bit address
C
D
AI04046
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
M45PE10 Instructions
29/47
6.10 Sector erase (SE)
The sec tor e r as e (S E ) i nstruction sets to ‘1 ’ (F Fh) al l bits inside the c hosen sector. Before it
can be accepted, a write enable (WREN) instruction must previously have been executed.
After the write enable (WREN) instruction has been decoded, the device sets the write
enable latch (WEL).
The sector erase (SE) instruction is entered by driving Chip Select (S) Low, followed by t he
instruction code, and three address by te s on serial data input (D). Any address inside the
sector (see Table 2) is a valid address for the sector erase (SE) instruction. Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instructi on sequence is sh own in Figure 15.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the sector erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven Hi gh, the self-timed sector erase cycle (whose dura tion is t
SE
) is
initi at ed. While the sector erase cycle is in progress, the status register may b e read to
check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during
the self-timed sector erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is complete, the write en ab le latch (WEL) bit is reset.
A sector erase (SE) instruction applied to a sector that contains a page that is Hardware
Protecte d is not executed.
Any sector era se (SE) instruction , w hi le a n e rase, program or write cycl e is in progress, is
rejected with out having an y effects on the cycle tha t is in progress.
Figure 15. Sector erase (SE) instruction sequence
1. Address bits A23 to A17 are don’t care.
24-bit address
C
D
AI03751D
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
Instructions M45PE10
30/47
6.11 Deep power-down (DP)
Executing the deep power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the deep power-down mode). It can also be used as an extra
software protection mechanism, while the device is not in active use, since in this mode, the
device ign ores all write, program an d erase instruct ions.
Driving Chip Select (S) High deselects the device, and puts the device in the standby power
mode (if ther e is no internal cycle currently in progress). But this mode is not the deep
power -down mo de. The deep p ower -down mo de ca n only be enter ed by execut ing t he deep
power-down (DP) instruction, to reduce the standby current (from I
CC1
to I
CC2
, as specified
in Table 11).
Once the device has entered the deep power-down mode, all instructions are ignored
except th e release from deep power-do wn (RDP) instruction. Th is releases the de vice from
this mode.
The deep po wer-down mode auto m atically stops at p ower-down, and t he device always
powers-up in the standby power mode.
The de ep power-dow n (DP) instruction is enter ed by drivi ng Chip Se lect (S ) Low, foll owed
by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the
entire durat ion of the sequence .
The instructi on sequence is sh own in Figure 16.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the deep power-down (DP) instruction is not executed. As soon as
Chip Sel ec t (S ) is dri ven High , it requ ire s a de lay of t
DP
befor e the su pply curr ent i s redu ced
to I
CC2
and th e deep po wer-down mode is entered.
Any deep power-d own (DP) in stru ction, while an erase , p rogram or write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 16. Deep power-down (DP) instruc tion sequence
C
D
AI03753D
S
21 345670t
DP
Deep power-down mode
Standby mode
Instruction
M45PE10 Instructions
31/47
6.12 Release from deep power-down (RDP)
Once the device has entered the deep power-down mode, all instructions are ignored
except the rele ase from d eep pow er-d own (RDP) instruct ion. Exec ut ing this instruction
takes the device out o f the deep power-down m ode.
The re lease fro m deep po wer-down (RDP) instruction is entered by driving Ch ip Select (S)
Low, followed by the instruction code on Serial Data input (D). Chip Select (S) must be
driven Low for the entire duration of the sequence.
The instructi on sequence is sh own in Figure 17.
The release from deep power-down (RDP) instruction is terminated by driving Chip Select
(S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is drive n
Low, cause the instruction to be rejected, and not executed.
After Chip Select (S) has bee n driv en High, followe d by a dela y, t
RDP
, the device is put in the
S t andby Pow er mode. Chip S elect (S) must remain Hi gh at least un til this peri od is over . The
device waits to be selected, so that it can receiv e, decode and execute inst ruct ions.
Any release from deep power-down (RDP) instruction, while an erase, program or write
cycle is in prog ress, is rejected without having any effects on the cycle that is in progress.
Figure 17. Release fro m deep power-down (RDP) instruction sequ enc e
C
D
AI06807
S
21 345670tRDP
Standby mode
Deep power-down mode
QHigh Impedance
Instruction
Power-up and power-down M45PE10
32/47
7 Power-up and power-down
At pow er- up and power- dow n, th e devi ce mus t not be s elec ted ( that is Chip Sele ct (S) must
follow the voltage applied on V
CC
) until V
CC
reaches the co rrect va lue:
V
CC
(min) at power-up, and then for a further delay of t
VSL
V
SS
at power- d own
A safe co nf iguration is provided in Section 3: SPI mode s.
To avo id dat a corr uption and inad verte nt write operat ions du ring po wer up, a power o n reset
(POR) circuit is included. The logic inside the device is held reset while V
CC
is less than the
power on reset (POR) threshold value, V
WI
– all operations are disabled, and the device
does not respond to any instruction.
Moreover, the device ignores all write enable (WREN), page write (PW), page program
(PP), page erase (PE) and sector erase (SE) instructions until a time delay of t
PUW
has
elapsed after the moment that V
CC
rise s above the V
WI
threshold. However, the correct
operation of the device is not guaranteed if, by this time, V
CC
is still below V
CC
(min). No
write, program or era s e instruct ions should be se nt until th e later of:
t
PUW
after V
CC
passed th e V
WI
threshold
t
VSL
after wr ap round V
CC
passed the V
CC
(min) level
These values are specified in Table 6.
If the delay, t
VSL
, has el apsed, after V
CC
has risen above V
CC
(min), the device can be
selected for read instructions even if the t
PUW
delay is not y et ful ly elapsed.
As an extra pr otec tion , the Rese t (R eset) signal can b e dr iven Low fo r th e whole dur ati on of
the power-up and power-down phases.
At power-up, the device is in the following state:
The device is in the standby power mode (not the deep power-down mode)
The wri t e ena ble latch (WEL) bit is re s et
The wri t e in progre ss (WIP) bit is reset
Normal precautions must be taken for supply rail de c oupling, to stab ilize the V
CC
supply.
Each device in a system should have the V
CC
line decoupled by a suitable capacitor close
to the package pins (generally, this capacitor is of th e order of 100 nF).
At power-d own, wh en V
CC
drops from the opera ting vol tage, to below t he power on rese t
(POR) threshold value, V
WI
, all operations are di sabled and the device does not respond to
any instruction (the designer needs to be aware that if a power-down occurs while a write,
program or erase cycle is in progress, some data corruption can result).
M45PE10 Power-up and power-down
33/47
Figure 18. Power-up timing
Ta ble 6. Power-up timing and V
WI
threshold
Symbol Parameter Min. Max. Unit
t
VSL(1)
1. These parameters are charac terized only, over the temperature range –40 °C to +85 °C.
V
CC
(min) to S low 30 µs
t
PUW(1)
Time delay before the first write, program or erase instruction 1 10 ms
V
WI(1)
Write inhibit voltage 1.5 2.5 V
VCC
AI04009C
VCC(min)
VWI
Reset state
of the
device
Chip selection not allowed
Program, erase and write commands are rejected by the device
tVSL
tPUW
time
Read access allowed Device fully
accessible
VCC(max)
Initial deli very state M45PE10
34/47
8 Initial delivery state
The device is delive red with the memory array erased: al l bits are set to ‘1’ ( each by te
contains FFh). All usa ble st atus register bits are 0.
9 Maximum rating
Stressing the device o utside th e rat ings listed in Table 7: Abso lute max imum ratings may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these, or any other conditions outside those indica ted in th e operatin g sections of
this specification, is not implied. Exposure to absolute maximum rating conditions for
extended period s may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.
Table 7. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
T
STG
Stor age temper ature –65 1 50 °C
T
LEAD
Lead temperature during soldering See note
(1)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx 7191395
specification, and the European directive on Restr ictions on Hazardous Substances (RoHS) 2002/95/EU.
°C
V
IO
Input and output voltage (with respect to ground) –0.6 V
CC
+ 0.6 V
V
CC
Supply voltage –0.6 4.0 V
V
ESD
Electrostatic discharge voltage (human body model)
(2)
2. JEDEC Std JESD22-A114A (C1 =100 pF, R1=1500 Ω, R2=500 Ω).
–2000 2000 V
M45PE10 DC and AC parameters
35/47
10 DC and AC parameters
This section summari z es the operat ing and m easur em ent co nditio ns, and th e DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
1. Output Hi-Z is defined as the point where dat a out is no longer driven.
Figure 19. A C measurement I/O waveform
Ta ble 8. Operating conditions
Symbol Parameter Min. Max. Unit
V
CC
Supply voltage 2.7 3.6 V
T
A
Ambient operating temperature –40 85 °C
Table 9. AC measurement conditions
Symbol Parameter Min. Max. Unit
C
L
Load capacitance 30 pF
Input rise and fall times 5 ns
Input pulse voltages 0.2V
CC
to 0.8V
CC
V
Input and output timing reference voltages 0.3V
CC
to 0.7V
CC
V
Table 10. Capacitance
(1)
1. Sampled only, not 100% tested, at T
A
=25 °C and a frequency of 33 MHz.
Symbol Parameter Test condition Min. Max. Unit
C
OUT
Output capacitance (Q) V
OUT
= 0 V 8 pF
C
IN
Input capacitance (other pins) V
IN
= 0 V 6 p F
AI00825B
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and output
timing reference levels
Input levels
DC and AC parameters M45PE10
36/47
Table 11. DC characteristics
Symbol Parameter Test condition
(in addition to those in Table 8)Min. Max. Unit
I
LI
Input leakage current ± 2 µA
I
LO
Output leakage current ± 2 µA
I
CC1
Standby current
(standby and r es et
modes) S = V
CC
, V
IN
= V
SS
or
V
CC
50 µA
I
CC2
Deep power-down
current S = V
CC
, V
IN
= V
SS
or
V
CC
10 µA
I
CC3
Operating current
(FAST_READ)
C = 0.1V
CC
/ 0.9.V
CC
at 33 MHz,
Q = open 4mA
C = 0.1V
CC
/ 0.9.V
CC
at 75 MHz,
Q = open 12
I
CC4
Operating current (PW) S = V
CC
15 mA
I
CC5
Operating current (SE) S = V
CC
15 mA
V
IL
Input low voltage – 0.5 0.3V
CC
V
V
IH
Input high voltage 0.7V
CC
V
CC
+0.4 V
V
OL
Output low voltage I
OL
= 1.6 mA 0.4 V
V
OH
Output high voltage I
OH
= –100 µA V
CC
–0.2 V
M45PE10 DC and AC parameters
37/47
Table 12. AC characteristics (25 MHz operation)
Test conditions specified in Table 8 and Table 9
Symbol Alt. Parameter Min. Typ. Max. Unit
f
C
f
C
Clock frequency for the following
instructions: FAST_READ, PW, PP, PE,
SE, DP, RDP, WREN, WRDI, RDSR D.C. 25 MHz
f
R
Clock frequency for Read ins tructions D.C. 20 MHz
t
CH(1)
1. t
CH
+ t
CL
must be greater tha n or equal to 1/ f
C
(max).
t
CLH
Clock High time 18 ns
t
CL(1)
t
CLL
Clock Low time 18 ns
Clock slew rate
(2)
(peak to peak)
2. Value guaranteed by characterization, not 100% tested in production.
0.03 V/ns
t
SLCH
t
CSS
S active setup time (relative to C) 10 ns
t
CHSL
S not active hold time (relative to C) 10 ns
t
DVCH
t
DSU
Data in setup time 5 ns
t
CHDX
t
DH
Data i n hold ti me 5 ns
t
CHSH
S active hold time (relative to C) 10 ns
t
SHCH
S not active setup time (relative to C) 10 ns
t
SHSL
t
CSH
S deselect time 200 ns
t
SHQZ(2)
t
DIS
Output disable time 15 ns
t
CLQV
t
V
Clock Low to Output valid 15 ns
t
CLQX
t
HO
Output hold time 0 ns
t
RLRH(2)
t
RST
Reset pulse width 10 µs
t
RHSL
t
REC
Reset recovery time 3 µs
t
SHRH
Chip should have been deselected
before Reset is de-asserted 10 ns
t
WHSL
Write prot ect setup time 50 ns
t
SHWL
Write pr otect hold time 100 ns
t
DP(2)
S to deep power-down 3 μs
t
RDP(2)
S High to standby power mode 30 μs
t
PW(3)
3. When using PP and PW instructions to updat e consecutive bytes, optimized timings are obtained with one
sequence inc luding all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).
Page write cycle time (256 bytes) 11 25 ms
Page write cycle time (n bytes) 10.2+
n*0.8/256
t
PP(3)
Page program cycle time (256 bytes) 1.2 5ms
Page program cycle time (n bytes) 0.4+
n*0.8/256
t
PE
Page erase cycle time 10 20 ms
t
SE
Sector erase cycle time 1 5 s
DC and AC parameters M45PE10
38/47
Table 13. AC characteristics (33 MHz operation)
33 MHz only available for products marked since week 40 of 2005
(1)
Test conditions specified in Table 8 and Table 9
1. Details of how to find the date of marking are given in application note, AN1995.
Symbol Alt. Parameter Min. Typ. Max. Unit
f
C
f
C
Clock frequency for the following
instructio ns: FAST_READ, PW, PP, PE,
SE, DP, RDP, WREN, WRDI, RDSR D.C. 33 MHz
f
R
Clock frequency for READ instructions D .C. 20 MH z
t
CH(2)
2. t
CH
+ t
CL
must be greater tha n or equal to 1/ f
C
.
t
CLH
Clock High time 13 ns
t
CL(2)
t
CLL
Clock Low time 13 ns
Clock slew rate
(3)
(peak to peak)
3. Value guaranteed by characterization, not 100% tested in production.
0.03 V/ns
t
SLCH
t
CSS
S active setup time (relative to C) 10 n s
t
CHSL
S not active hold time (relative to C) 10 ns
t
DVCH
t
DSU
Data in setup time 3 ns
t
CHDX
t
DH
Data in hold time 5 ns
t
CHSH
S active hold time (relative to C) 5 ns
t
SHCH
S not active setup time (relative to C) 5 ns
t
SHSL
t
CSH
S deselect time 200 ns
t
SHQZ(3)
t
DIS
Output disable time 12 ns
t
CLQV
t
V
Clock Low to Output valid 12 ns
t
CLQX
t
HO
Output hold time 0 ns
t
THSL
Top Sector Lock setup time 50 ns
t
SHTL
Top Sector Lock hold time 100 n s
t
DP(3)
S to deep power-down 3 μs
t
RDP(3)
S High to standby power mode 30 μs
t
PW(4)
4. When using PP and PW instructions to updat e consecutive bytes, optimized timings are obtained with one
sequence inc luding all the by tes versus several sequences of only a few bytes (1 ≤ n ≤ 256).
Page write cycle time (256 bytes) 11 25 ms
Page write cycle time (n bytes) 10.2+
n*0.8/256
t
PP(4)
Page program cycle time (256 bytes) 1.2 5ms
Page program cycle time (n bytes) 0.4+
n*0.8/256
t
PE
Page erase cycle time 10 20 ms
t
SE
Sector erase cycle time 1 5 s
M45PE10 DC and AC parameters
39/47
Table 14. AC characteristics (50 MHz operation)
50 MHz operation for T9HX technology
(1)
Test conditions specified in Table 8 and Table 9
Symbol Alt. Parameter Min. Typ. Max. Unit
f
C
f
C
Clock frequency for the following instructions:
FAST_READ, PW, PP, PE, SE, DP, RDP,
WREN, WRDI, RDSR, RDID D.C. 50 MHz
f
R
Clock frequency for read instructions D.C. 33 MHz
t
CH(2)
t
CLH
Clock High time 9 ns
t
CL(2)
t
CLL
Clock Low time 9 ns
Clock slew rate
(3)
(peak to peak) 0.1 V/ns
t
SLCH
t
CSS
S active setup time (relative to C) 5 ns
t
CHSL
S not active hold time (relative to C) 5 ns
t
DVCH
t
DSU
Data in setup time 2 ns
t
CHDX
t
DH
Data in hold time 5 ns
t
CHSH
S active hold time (relative to C) 5 ns
t
SHCH
S not active setup time (relative to C) 5 ns
t
SHSL
t
CSH
S deselect time 100 ns
t
SHQZ(3)
t
DIS
Output disable time 8 ns
t
CLQV
t
V
Clock Low to Output valid 8 ns
t
CLQX
t
HO
Output hold time 0 ns
t
WHSL
Write protect setup time 50 ns
t
SHWL
Write protect hold time 100 ns
t
DP(3)
S to deep power-down 3 µs
t
RDP(3)
S High to standby mode 30 µs
t
RLRH(3)
t
RST
Reset pul s e width 10 µs
t
RHSL
t
REC
Reset recovery time 3 µs
t
SHRH
Chip should have been deselected before
Reset is de-asserted 10 ns
t
PW(4)
Page write cycle time (256 bytes) 11 23 ms
t
PP(4)
Page program cycle time (256 bytes ) 0.8 3ms
Page program cycle time (n bytes) int(n/8) × 0.025
t
PE
Page erase cycle time 10 20 ms
t
SE
Sector erase cycle time 1.5 5 s
1. Delivery of parts in T9HX process to start from August 2007.
2. t
CH
+ t
CL
must be greater th an or equal to 1/ f
C
.
3. Value guaranteed by characterization, not 100% tested in production.
4. n = number of bytes to program. int(A) corresponds to the upper integer part of A. Examples: int(1/8) = 1, int(16/8) = 2,
int(17/8) = 3.
DC and AC parameters M45PE10
40/47
Table 15. AC characteristics (75 MHz operation, T9HX (0.11 µm) process
(1)
)
(2)
Test conditions specified in Table 8 and Table 9
Symbol Alt. Parameter Min. Typ. Max. Unit
f
C
f
C
Clock frequency for the following instructions:
FAST_READ, PW, PP, PE, SE, DP, RDP,
WREN, WRDI, RDSR, RDID D.C. 75 MHz
f
R
Clock frequency for read instructions D.C. 33 MHz
t
CH(3)
t
CLH
Clock High time 6 ns
t
CL(3)
t
CLL
Clock Low time 6 ns
Clock slew rate
(3)
(peak to peak) 0.1 V/ns
t
SLCH
t
CSS
S active setup time (relative to C) 5 ns
t
CHSL
S not active hold time (relative to C) 5 ns
t
DVCH
t
DSU
Data in setup time 2 ns
t
CHDX
t
DH
Data in hold time 5 ns
t
CHSH
S active hold time (relative to C) 5 ns
t
SHCH
S not active setup time (relative to C) 5 ns
t
SHSL
t
CSH
S deselect time 100 ns
t
SHQZ(4)
t
DIS
Output disable time 8 ns
t
CLQV
t
V
Clock Low to Output valid 8 ns
t
CLQX
t
HO
Output hold time 0 ns
t
WHSL(5)
Write protect setup time 20 ns
t
SHWL(5)
Write protect hold time 1 00 ns
t
DP(3)
S to deep power-down 3 µs
t
RDP(3)
S High to standby mode 30 µs
t
W
Write status register cycle time 3 15 ms
t
PW(6)
Page write cycle time (256 bytes) 11 23 ms
t
PP(6)
Page program cycle time (256 bytes) 0.8 3ms
Page program cycle time (n bytes) int(n/8) × 0.025
(7)
t
PE
Page erase cycle time 10 20 ms
t
SE
Sector erase cycle time 1.5 5 s
t
SSE
Subsector erase cycle time 80 150 ms
t
BE
Bul k era se cycle t ime 4.5 10 s
1. See Important note on page 6.
2. Details of how t o fi nd the technology process in the marking are given in AN1995, see also Section 12: Ordering
information.
3. t
CH
+ t
CL
must be greater th an or equal to 1/ f
C
.
4. Value guaranteed by characterization, not 100% tested in production.
5. Only applic able as a constraint for a WRSR instruction when SRWD is set to ‘1’.
6. When using PP and PW instruc tions to update co nsecutive bytes , optimized timi ngs are obtained with one sequence
including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256).
7. int(A) corresponds to the upper integer part of A. For instance, int(12/8) = 2, int(32/8) = 4 int(15. 3) =16.
M45PE10 DC and AC parameters
41/47
Figure 20. Serial input timing
Figure 21. Write Protect setup and hold timin g
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
C
D
S
Q
High Impedance
W
tWHSL tSHWL
AI07439
DC and AC parameters M45PE10
42/47
Figure 22. O utput timing
Figure 23. Reset AC waveforms
C
Q
AI01449e
S
LSB OUT
DADDR.LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
AI06808
Reset tRLRH
S
tRHSLtSHRH
M45PE10 Package mechanical
43/47
11 Package mechanical
In order to me et environmental requirements, Numonyx offe rs t hese devices in RoHS
packages. RoHS pack ages are le ad-free. The categ ory of second level int erconnect is
marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97 . The ma ximum rati ngs relate d to solder ing cond it ions are also mark ed on th e inne r
box label.
Figure 24. S O8N – 8 lead plastic small outline, 150 mils body width, package outline
1. Drawing is not to scal e.
Ta ble 16. SO8N – 8 lead plastic small outline, 150 mils body width, package
mec hani cal data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.75 0.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.009
ccc 0.10 0.004
D 4.90 4.80 5.00 0.193 0.189 0.197
E 6.00 5.80 6.20 0.236 0.228 0.244
E1 3.90 3.80 4.00 0.154 0.150 0.157
e1.27– –0.050– –
h 0.25 0.50 0.010 0.020
k0°8°0°8°
L 0.40 1.27 0.016 0.050
L1 1.04 0.041
SO-A
E1
8
ccc
be
A
D
c
1E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
Package me chanic al M45PE10
44/47
Figure 25. MLP8, 8-lead very thin dual flat package no lead, 6 × 5 mm, package
outline
1. Drawing is not to scal e.
Table 17. MLP8, 8-lead very thin dual flat package no lead, 6 × 5 mm, package
mec hani cal data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 0.85 0.80 1.00 0.033 0.031 0.039
A1 0.00 0.05 0.000 0.002
A2 0.65 0.026
A3 0.20 0.008
b 0.40 0.35 0.48 0.016 0.014 0.019
D 6.00 0.236
D1 5.75 0.226
D2 3.40 3.20 3.60 0.134 0.126 0.142
E 5.00 0.197
E1 4.75 0.187
E2 4.00 3.80 4.30 0.157 0.150 0.169
e1.27– –0.050– –
R1 0.10 0.00 0.004 0.000
L 0.60 0.50 0.75 0.024 0.020 0.029
Θ12° 12°
aaa 0.15 0.006
bbb 0.10 0.004
ddd 0.05 0.002
D
E
70-M
E
A2
AA3
A1
E1
D1
eE2
D2
L
b
θ
R1
ddd
bbb
C
CAB
aaa CAA
B
aaa CB
M
0.10 CA
0.10 CB
2x
M45PE10 Order ing informatio n
45/47
12 Ordering information
For a list of available options (speed, package, etc.), for further information on any aspect of
this de vice or when ordering parts op erating at 75 MHz (0.11 µm technology, process digit
‘4’), please contact your nearest Numonyx Sales Office.
Table 18. Ordering information scheme
Example: M45PE10 – V MP 6 T G
Device type
M45PE = serial Flash memory for data storage
Device function
10 = 1 Mbit (128 Kb × 8)
Security
(1)
1. Secure options are available upo n cus tomer request.
– = no extra security
S– = CFD programmed with UID and halogen free
Operating voltage
V = V
CC
= 2.7 V to 3.6 V
Package
MN = SO8 (150 mil width)
MP = VDFPN8 6 × 5 mm (MLP8)
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = standard packing
T = tape and reel packing
Plating technology
P or G = RoHS compliant
Revision history M45PE10
46/47
13 Revision history
Ta ble 19. Document revision history
Date Version Changes
29-Apr-2003 1.0 Initial release.
04-Jun-2003 1.1 D escription corrected of entering hardware protected mode (W must be
driven, and cannot be left unconnected).
04-Dec-2003 1.2 V
IO
(min) extended to –0.6 V, t
PW
(typ) and t
PP
(typ) improved. Table of
contents, warning about exposed paddle on MLP8, and lead-free
options added. Change of naming for VDFPN8 package.
25-Jun-2004 1.3 Sol dering temperature information clarified for RoHS compliant devices.
Device grade clarified.
22-Sep-2004 2.0 Document promoted to preliminary data. Minor wording changes
08-Oct-2004 3.0 Document promoted to m at ure datasheet. No other changes
4-Oct-2005 4.0
Added AC characteristics (33 MHz operation) . An easy way to modify
data, A fast way to modify data, Page write (PW) and Page program
(PP) sections updated to explain optimal use of page write and page
program instructions. Updated I
CC3
values in Table 11: DC
characteristics. Updated T able 18: Ordering information scheme. Added
RoHS information.
02-Feb-2007 5
Document reformatted. 50 MHz frequency added (Table 14 added).
VCC supply voltage and VSS ground descriptions added.
Figure 4: SPI modes supported modified and explanatory text added.
V
IO
max modified in Table 7: Absolute maximum ratings .
At power-up, The write in progress (WIP) bit is reset
t
SHQZ
end timing line modified in Figure 22: Output timing.
Blank option removed below Plating technology in Table 18: Ordering
information scheme. Small text changes.
Package specifications updated (see Section 11: Package mechanical).
21-Feb-2008 6
Removed ‘low voltage’ from the title.
Updated the value for the maximum clock fre quency (from 50 to
75 MH z) through the docu men t.
Added: Table 15: AC characteristics (75 M H z operation, T9HX (0.11
µm) process) and RoHS text in Section 11: Package mechanical.
Modified: Table 11: DC characteristics, Figure 3: Bus master and
memory devices on the SPI bus, and Section 6.3: Read identification
(RDID).
Minor text changes.
26-Mar-2008 7 Applied Num onyx br anding.
7-June-2011 8 Addes Security Features to Order Information.
M45PE10
47/47
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