7955 Security Accelerator Data Sheet Hifn Confidential DS-0114-08, (c) 2004, Hi/fn(R), Inc. All rights reserved. 8/08 No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form by any means without the written permission of Hi/fn, Inc. ("Hifn") Licensing and Government Use Any Hifn software ("Licensed Programs") described in this document is furnished under a license and may be used and copied only in accordance with the terms of such license and with the inclusion of this copyright notice. Distribution of this document or any copies thereof and the ability to transfer title or ownership of this document's contents are subject to the terms of such license. Such Licensed Programs and their documentation have been developed at private expense and no part of such Licensed Programs is in the public domain. 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Specific testing of all parameters, with the exception of those mandated by government requirements, of each product is not necessarily performed. Certain applications using Hifn products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). Hifn products are not designed, intended, authorized, or warranted to be suitable for use in life saving, or life support applications, devices or systems or other critical applications. Inclusion of Hifn products in such critical applications is understood to be fully at the risk of the customer. Questions concerning potential risk applications should be directed to Hifn through a local sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals," should be validated for each customer application by the customer's technical experts. Hifn does not warrant that its products are free from infringement of any patents, copyrights or other proprietary rights of third parties. In no event shall Hifn be liable for any special, incidental or consequential damages arising from infringement or alleged infringement of any patents, copyrights or other third party intellectual property rights. The use of this product in stateful compression protocols (for example, PPP or multi-history applications) with certain configurations may require a license from Motorola. In such cases, a license agreement for the right to use Motorola patents may be obtained through Hifn or directly from Motorola. Patents May include one or more of the following United States patents: 4,701,745; 5,003,307; 5,016,009; 5,126,739; 5,146,221; 5,414,425; 5,463,390; 5,506,580; and 5,5532,694. Other patents pending. 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If not, please destroy the document. 750 University Ave. Los Gatos, CA 95032 E:info@hifn.com P:408.399.3500 F: 408.399.3501 Hifn Confidential Contents List of Figures ............................................................................................................................. 5 List of Tables ............................................................................................................................... 6 Preface ......................................................................................................................................... 7 About This Document ............................................................................................ 7 Customer Support ................................................................................................. 7 Web Site.............................................................................................................. 7 1 2 Product Description .............................................................................................................. 8 Features ................................................................................................................................. 9 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3 Performance Summary ....................................................................................................... 11 3.1 3.2 3.3 4 High Performance ......................................................................................... 9 Major Security and Compression Protocol Support ............................................. 9 Multiple Host Bus Interface Modes ................................................................... 9 Low Host Overhead ......................................................................................10 Advanced Cryptographic Engines ....................................................................10 Software Support .........................................................................................10 Other Features ............................................................................................10 Symmetric Key Processing Units.....................................................................11 Protocol Performance....................................................................................12 Public Key ...................................................................................................12 Block Diagram ..................................................................................................................... 14 4.1 Operation ...................................................................................................14 4.2 Security Processing ......................................................................................16 4.2.1 Muting Table ........................................................................................16 4.2.2 Public Key Processing ............................................................................16 5 Configuration Options ........................................................................................................ 17 5.1 Core Clock Configuration ...............................................................................17 5.2 EEPROM and Hardware Configuration ..............................................................17 5.2.1 EEPROM Memory Map ...........................................................................19 5.2.2 Configuration without EEPROM ...............................................................20 5.3 Endianness Configuration ..............................................................................21 5.3.1 Device Endianness Configuration ............................................................21 5.3.2 Device Endianness Configuration Examples ..............................................24 6 Signal Description............................................................................................................... 25 6.1 Signal Overview ...........................................................................................25 6.1.1 PCI Signal Overview..............................................................................25 6.1.2 PowerQuicc II Signal Overview ...............................................................26 6.1.3 PowerQuicc I Signal Overview ................................................................27 6.2 Detailed Signal Description ............................................................................28 6.2.1 PCI Signal Description ...........................................................................28 6.2.2 PowerQuicc II Signal Description.............................................................29 7955 - Data Sheet, DS-0114-08 Hifn Confidential 3 6.2.3 6.2.4 6.2.5 6.2.6 7 Timing Specifications ......................................................................................................... 35 7.1 7.2 7.3 7.4 7.5 7.6 8 AC Operating Conditions ...............................................................................35 Host Bus Interface Clock ...............................................................................35 PCI Timing ..................................................................................................37 PowerQuicc I Timing .....................................................................................38 PowerQuicc II Timing ....................................................................................39 EEPROM .....................................................................................................41 DC Specifications................................................................................................................ 42 8.1 8.2 8.3 8.4 9 PowerQuicc I Signal Description ..............................................................31 EEPROM Signal Description ....................................................................32 Clock and Test Signal Description ...........................................................32 Power and Ground Signal Description ......................................................34 Absolute Maximum Ratings............................................................................42 Power Sequencing ........................................................................................42 Recommended Operating Conditions ...............................................................43 DC Characteristics ........................................................................................43 Thermal Specifications ....................................................................................................... 45 9.1 9.2 Heat Sink Requirements ................................................................................45 Junction Temperature Specifications ...............................................................45 10 Pin List ................................................................................................................................. 46 10.1 10.2 10.3 10.4 10.5 10.6 LQFP LQFP LQFP LQFP LQFP LQFP PCI-Mode Pin List ..............................................................................46 PCI Mode Pinout ................................................................................48 PQI Mode Pin List ..............................................................................49 PQI Mode Pinout................................................................................51 PQII Mode Pin List .............................................................................52 PQII Mode Pinout ..............................................................................54 11 Physical Specifications ...................................................................................................... 55 11.1 LQFP 144-pin Plastic Quad Flatpack .............................................................55 Document Changes/Revisions ................................................................................................ 56 7955 - Data Sheet, DS-0114-08 Hifn Confidential 4 List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Example System Concept, MPC versus PCI Interface Mode ............................... 8 Block Diagram ......................................................................................... 14 Hardware Configuration Options ................................................................. 18 Endianness Transfer Modes ........................................................................ 23 PCI Host Bus Interface Signals ................................................................... 25 PowerQuicc II Host Bus Interface Signals ..................................................... 26 PowerQuicc I Host Bus Interface Signals ...................................................... 27 Input Bus Clock Timing ............................................................................. 35 PQI bus Read/Write Timing ........................................................................ 39 PQII bus Read/Write Timing .................................................................... 40 EEPROM Timing ..................................................................................... 41 Power Sequence Specifications ................................................................ 43 LQFP PCI Mode Pinout Drawing ................................................................ 48 LQFP PQI Mode Pinout Drawing................................................................ 51 LQFP PQII Mode Pinout Drawing .............................................................. 54 144 LQFP Package ................................................................................. 55 7955 - Data Sheet, DS-0114-08 Hifn Confidential 5 List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Ordering Information ................................................................................ Processing Unit Performance ...................................................................... Protocol Processing Performance ................................................................ IKE Performance ...................................................................................... Public Key Performance (133 MHz Operation) ............................................... Description of the functional units ............................................................... EEPROM Memory Map ............................................................................... PowerQuicc I and PowerQuicc II Chip Select Methods .................................... Host Bus Mode Configuration without EEPROM .............................................. Host Bus Endian Configuration without EEPROM ............................................ PCI Register Configuration without EEPROM ................................................. 7955 Endianness Configuration .................................................................. Endianness Mapping of System Data ........................................................... 64-bit Host Data Endianness Control ........................................................... PCI Signals .............................................................................................. PowerQuicc II Signals ............................................................................... PowerQuicc I Signals ................................................................................ EEPROM Signals ....................................................................................... PLL Signals .............................................................................................. Test and JTAG signals ............................................................................... Power and Ground signals ......................................................................... AC Operating Conditions............................................................................ PCI_CLK Timing ....................................................................................... PQI_CLK Timing ....................................................................................... PQII_CLK Timing ...................................................................................... PLL_REF Clock ......................................................................................... PCI Timing Parameters .............................................................................. Read/Write Timing (PQI bus) ..................................................................... Read/Write Timing (PQII bus) .................................................................... EEPROM Timing ....................................................................................... Absolute Maximum Ratings ........................................................................ Recommended Operating Conditions ........................................................... DC Electrical Characteristics ....................................................................... Thermal Specifications .............................................................................. LQFP Thermal Resistance........................................................................... LQFP PCI-Mode Pin List (Numerically) .......................................................... LQFP PCI-Mode Pin List (Alphabetically) ....................................................... LQFP PQI Mode Pin List (Numerically) .......................................................... LQFP PQI Mode Pin List (Alphabetically) ....................................................... LQFP PQII Mode Pin List (Numerically)......................................................... LQFP PQII Mode Pin List (Alphabetically) ...................................................... 7955 - Data Sheet, DS-0114-08 Hifn Confidential 10 11 12 12 13 15 19 20 20 20 20 21 22 24 28 29 31 32 33 33 34 35 35 36 36 36 37 38 39 41 42 43 43 45 45 46 47 49 50 52 53 6 Preface Welcome to the Data Sheet for the Hifn 7955 network security processors family. This document provides feature, performance, and interface information and specifications for the 7955 Security Accelerator. The reader is assumed to have a general knowledge of Hifn 795x architecture. The 7955 is the newest members of the 795x family of algorithm accelerators, which began with the Hifn 7951. For register descriptions, definitions of data structures, and general usage information, refer to the 7954/7955/7956 Hardware Users Guide (UG-0034). About This Document This document assumes you are already familiar with the chip technology and terminology. This document is intended for integrators and application developers responsible for and familiar with software and hardware architecture of a target system. Customer Support For technical support about this product, please contact your local Hifn sales office, representative, or distributor. Web Site For general information about Hifn and Hifn products refer to: www.hifn.com. 7955 - Data Sheet, DS-0114-08 Hifn Confidential 7 1 Product Description High Performance- The Hifn TM 7955 Security Accelerator supports multi-protocol algorithm processing. Optimized for OC3/T3 Applications, 7955 Security Accelerator achieves over 250 Mbps full-duplex sustained performance with simultaneous encryption, compression, and authentication of large packets (1500 Bytes). Highly Integrated- All major security/compression protocols are supported. The 7955 is an ideal security solution for VPN enabled routers, remote access concentrators, VPN gateways, firewalls, and WAN switches. The 7955's integrated high-speed compression engines also make it ideal for wireless applications. IPSec algorithms include AES-128, AES-192, AES-256, DES, 3DES, and ARC4 encryption. The 7955 supports SHA-1 and MD5 authentication, LZS and MPPC compression. AES Support- The 7955 fully supports the new Advanced Encryption Standard, AES, with key lengths of 128, 192 & 256-bits. It also supports AES counter-mode. Integrated Public-Key Processing- The 7955 contains an on-chip public-key subsystem. SSL, TLS, and IKE algorithms include RSA, DSA, and Diffie-Hellman operations. Host Bus Interface- The 7955 is equipped with a configurable PCI-2.2 compliant interface, enabling direct connection to any PCI host system. The 7955 also offers a glueless interface to the MPC860 or MPC8260 bus. Compatibility- The 7955 is software-compatible with the Hifn 79xx family. WAN/LAN Ports System Memory WAN Ports LAN Ports 7955 7955 PCI Host Bus (32/64-bit @ 66 MHz ) MPC CPU (860/8260) PowerQuicc I/II Bus (32-bit @ 66 MHz ) Figure 1 7955 - Data Sheet, DS-0114-08 Hifn Confidential System Memory System Controller CPU Example System Concept, MPC versus PCI Interface Mode 8 2 2.1 Features High Performance Supports IPSec processing at OC3 and higher data rates (for 1500-byte packets) Processes entire packet (compression, encryption, and authentication) in a single pass Supports concurrent Public-Key and Symmetric Key processing Integrated Public Key processor IPSec performance; 75 Diffie-Hellmann quick-mode connections/s (1024-bit) SSL performance; 40 RSA signatures/s (1024-bit) Compression engine runs at over 250 Mbps and increases effective throughput Supports 128 Security Associations (SA) on-chip, and unlimited in host memory. 2.2 Major Security and Compression Protocol Support 128/192/256-bit AES (Advanced Encryption Standard), DES, 3DES, and ARC4 encryption (ARC4 is fully compatible with RSA's RC4TM algorithm) SHA-1 and MD5 hashing and authentication LZS and MPPC compression Public-key support includes RSA, DSA, SSL, IKE, and Diffie-Hellman Supports up to 3072-bit modular arithmetic and exponentiation True Hardware Random Number Generator 2.3 Multiple Host Bus Interface Modes Bus mastering PCI-2.2 Interface at 33 or 66 MHz Efficient scatter/gather DMA engines handle fragmented host memory Programmable bus arbitration/utilization for PCI bandwidth control 64-byte FIFO input and output buffers support high-speed burst transfers Optional external serial EEPROM enables customized PCI configurations Direct MPC860/850 PowerQuicc bus (32-bit GPCM) interface, up to 4 word burst Direct MPC8260 PowerQuicc II bus (32-bit UPM) interface, up to 4 double word burst 7955 - Data Sheet, DS-0114-08 Hifn Confidential 9 2.4 Low Host Overhead Security context (encryption keys and other stateful parameters) may be stored in on-chip memory to reduce host overhead Descriptor Based DMA engine (supports data scatter / gather) in PCI mode On-chip memory used to buffer control data packets 2.5 Advanced Cryptographic Engines Support for ECB, CBC, and CTR block-cipher modes of operation Multi-mode automatic padding Programmable mutable field MAC support for handling AH, IPv4, IPv6, and others 2.6 Software Support Supported by standard 79xx Hifn API API supports the full feature set of Hifn 79xx products API works with a wide variety of host architectures 2.7 Other Features Architecture compatibility with other Hifn 79xx Security Accelerators Supports low-cost implementation with 144-pin LQFP package JTAG support Reference hardware design 1.5V core with 3.3V I/O Typical dissipation = 0.64 W Table 1 Ordering Information Part Number Speed Description 7956PT6/2-G 66 MHz 144-pin LQFP 7955 Network Security Accelerator 7955 - Data Sheet, DS-0114-08 Hifn Confidential 10 Performance Summary 3 The figures in this section summarize the performance of the 7955 Security Accelerator functional units. Performance of the 7955 Security Accelerator when multiple engines are used (for example, the compression, MAC and encryption engines are all engaged) can be approximated by using throughput of the slowest engine. The MAC and encryption engine speeds are accelerated (effectively multiplied) by the actual compression ratio achieved by the compression engine. For example, if the achieved compression ratio is 2:1, then the MAC and encryption engine speeds are effectively doubled and the compression engine would be the slowest engine. This performance data reflects the following conditions: 66 MHz maximum internal core frequency 1500-byte packets. Single session or security association. Encoded text throughput 3.1 Symmetric Key Processing Units Table 2 Processing Unit Performance Protocol Performance @ 66 MHz (Mbps) AES-128, 192, 256 3DES ARC4 SHA-1 MD5 365, 420, 460 340 210 325 360 LZS Compression LZS Decompression MPPC Compression MPPC Decompression Stateless Stateful 510 455 505 420 450 395 460 425 Note: All performance numbers are based on simulation results. Text from the United States Constitution was arbitrarily selected for the compression and decompression simulations. The compression ratio is approximately 2:1. 7955 - Data Sheet, DS-0114-08 Hifn Confidential 11 3.2 Protocol Performance Table 3 Protocol Processing Performance Protocol IPSec (Tunnel; 3DES-CBC, SHA-1 HMAC) IPSec (Tunnel; AES-256, SHA-1 HMAC) IPSec (AH Tunnel; SHA-1 HMAC) 3-DES, SHA-1, Stateless LZS PPTP (RC4, MPPC) Performance @ 66 MHz Throughput Packets/Sec (Mbps) 325 27K 330 27K 320 370 360 27K 31K 30K Note: All performance numbers are based on simulation results. Text from the United States Constitution was arbitrarily selected for the compression and decompression simulations. The compression ratio is approximately 2:1. 3.3 Public Key Table 4 IKE Performance IKE Handshake Connections/Sec @ 133 MHz Two 1024-bit Diffie-Hellman operations (Quick Mode) Two 1024-bit Diffie-Hellman operations, 1 RSA sign, 2 RSA verifies (Main Mode) Four 1024-bit Diffie-Hellman operations, 1 RSA sign, 2 RSA verifies (Main Mode + Quick Mode) 70 24 38 Note: 180-bit exponent. The number of connections/sec is based on simulation results. 7955 - Data Sheet, DS-0114-08 Hifn Confidential 12 Table 5 Public Key Performance (133 MHz Operation) Operation @ 66 MHz RSA private key RSA public key (3-bit exponent) Diffie-Hellman (180-bit exponent) Diffie-Hellman (exponent = key size) DSA sign DSA verify Completion Time (ms) vs. Key Length (bits) 2048 1024 768 82.75 .45 27.13 308 512 11.88 .12 7.25 41.25 4.69 .07 4.81 20.50 1.75 .03 2.06 5.88 12.94 19.41 7.78 11.66 3.75 5.63 Note: Performance numbers assume a uniform distribution of ones and zeros in the exponent. Actual performance varies with the Hamming weight of the exponent. Performance numbers assume that the public key module has unrestricted access to memory. Actual performance varies with the memory usage of other system components. These numbers are only estimates and have not been experimentally verified. 7955 - Data Sheet, DS-0114-08 Hifn Confidential 13 4 4.1 Block Diagram Operation The 7955 Security Accelerator contains several processing units - Public Key encryption, symmetric key encryption, compression, padding, authentication, and Random Number Generator,. The symmetric key encryption, compression, padding, and authentication units are combined into a single functional block called the Packet Engine. The 7955 Security Accelerator also contains two programmable DMA engines with time-multiplex capability to transfer control and traffic data, two source and destination FIFOs, a PCI interface, and a PowerQuicc I/II Host Interface. JTAG PK Engine PK Operand RAM (4KB) RNG EEPROM Optional EEPROM Interface PLL Local RAM (32KB) Encryption Encryption Data Path DMA (PCI) Memory Ctrl Interrupt and Control Registers Pipeline uControl Compression Authentication Post FIFOs Host Bus Interface (PCI, PQI, or PQII) PCI Rev 2.2 64/32-bits 66/33MHz Master MPC PowerQuicc I Slave MPC PowerQuicc II Slave PLL_REF Figure 2 7955 - Data Sheet, DS-0114-08 Hifn Confidential Packet Engine Engines Fetch FIFOs Block Diagram 14 Table 6 Description of the functional units Block Packet Engine Public-Key Processor Local RAM Inbound/Outbound DMA Units PCI Interface PowerQuicc I&II 7955 Security Accelerator Registers EEPROM / Hardware Configuration Interface 7955 - Data Sheet, DS-0114-08 Hifn Confidential Description The packet engine consist of the encryption, compression and authentification processors. The packet engine contains pipelined compression, encryption, padding and authentication units, along with hardware for computing checksums, CRCs, and LCBs. The packet engine is configured by a command message prior to the start of each packet or task. The public-key processor incorporates enhanced features, providing hardware acceleration of public-key or symmetric key calculations on keys of up to 3,072 bits. The public-key processor also contains a hardware true-random number generator. It is accessible from both the PCI or MPC interfaces. The 32KB local memory is used for the storage of information such as descriptor, command, or per-session security context data. It may also contain I/O packet buffers. When the 7955 Security Accelerator is operating in PCI-bus mode, the inbound and outbound DMA units are specialpurpose block-transfer engines controlled by the 7955 Security Accelerator. The inbound DMA unit transfers commands and unprocessed packets from PCI to the 7955 Security Accelerator's security processing core, while the outbound DMA unit transfers processed packets and status information from security core to PCI. Fragmented buffers are supported through scatter/gather features in the DMA hardware. Internal FIFOs provide buffering to allow highspeed burst transfers. When the 7955 Security Accelerator is operating in slave-bus MPC mode, the PCI portion of the inbound/outbound DMA unit is disabled, and the PowerQuicc_I&II logic is enabled. The PCI interface is both an efficient bus master and an efficient bus target. It becomes a bus master for either the inbound DMA unit, or the outbound DMA unit. As a PCI slave, it services requests by the PCI host to access 7955 Security Accelerator registers and private memory. The PowerQuicc I&I interface is an alternate I/O interface supporting direct host interface to MPC860/850 and MPC8260. The MPC interface shares pins with the PCI interface, so both cannot be active in the same design. The 7955 Security Accelerator registers control the operation of the subsystem. They are memory-mapped to both the MPC and PCI. This interface supports an optional serial EEPROM used to configure the device registers at reset. If no EEPROM is used, the interface can be used to select default configuration, including host bus interface mode. 15 4.2 Security Processing The 7955 DMA channels and associated controller are designed to off-load the host from having to move numerous copies of data and associated context for each iteration of security processing. Locally accessible descriptor, command and context further relieve the host from having to move multiple control data packets between the host and target to perform necessary security related processing. 4.2.1 Muting Table An on-board muting table memory provides the mask that controls the input to the MAC processor. The mask nulls specific segments of the data packet prior to being submitted to the MAC processor. The masks are programmable through the host bus & are selected by the MAC descriptor. 4.2.2 Public Key Processing 7955 uses an enhanced Public Key (PK) processor. To further optimize the PK acceleration, 7955 PK processor is equipped with a 16 Opcode FIFO. The PK processor operates on a batch of modular arithmetic instructions (up to 16) and issues an interrupt once the operand FIFO is empty. Since each modular arithmetic instruction (nano instruction) execution is host independent, the host is only expected to setup the PK engine and retrieve the result upon reception of PK interrupt. 7955 - Data Sheet, DS-0114-08 Hifn Confidential 16 Configuration Options 5 The 7955 Security Accelerator supports a five-pin configuration interface that is used during hardware reset to select the host bus mode and to set up critical register values. This configuration information may be contained in a serial EEPROM attached to the interface. Otherwise, a default configuration can be selected by the applying a value to the interface during hardware reset. 5.1 Core Clock Configuration When the 7955 comes out of reset the core logic is directly driven by the host bus interface clock, HBI_CLK (PCI_CLK, PQI_CLK or PQII_CLK depending on the bus mode selected). During register initialization, the on-chip PLL is enabled and programmed appropriately if a multiple of one of the input clocks (host bus interface or PLL_REF) is needed to maximize the 7955's performance. The clock configuration circuit provides maximum flexibility allowing the 7955 to be clocked synchronously or asynchronously to its host bus interface. Refer to the PLL Configuration Register section in the 7954/7955/7956 Hardware Users Guide (UG-0034) for details on configuring the clock circuit. Note The PLL_REF input signal may not be required in some systems to achieve maximum performance (see 6.2.5 for more information on use of this input signal). Care must be exercised in configuring the clock circuit to prevent the core logic from being overclocked. 5.2 EEPROM and Hardware Configuration This section describes how the 5-pin serial EEPROM interface is used to configure the 7955 as it comes out of reset. The 7955 is designed so that the use of an external serial EEPROM is optional. When the 7955 comes out of reset (rising edge of the RST# signal), the EEPROM_EN signal is sampled to determine if an external EEPROM is present or not. If EEPROM_EN is tied high, the 7955 will determine that an EEPROM is present and begin loading configuration register values from it. Aside from internal register logic, the remainder of the 7955, including the host interface, is held in a reset state for 20K clock cycles (the time it takes to load register values from EEPROM). If EEPROM_EN is tied low, the 7955 will determine that there is no external EEPROM present as the device comes out of reset. However, in non-EEPROM configurations, the remaining 4 EEPROM signals are designed to be individually tied high and low (see section 5.2.2) on the PCB to enable additional 7955 configuration options. 7955 - Data Sheet, DS-0114-08 Hifn Confidential 17 7955 EEPROM_EN Security Accelerator EEPROM_CS EEPROM_SK EEPROM_DI EEPROM_DO 7955 EEPROM_EN Security Accelerator EEPROM_CS EEPROM_SK EEPROM EEPROM_DI Local Configuration Memory EEPROM_DO Figure 3 7955 - Data Sheet, DS-0114-08 Hifn Confidential Hardware Configuration Option Flag Hardware Configuration Options 18 5.2.1 EEPROM Memory Map Table 7 EEPROM Memory Map EEPROM Address (H) 0x00 0x00 0x00 0x00 0x00 0x01 0x02 0x03 0x04 0x04 0x05 0x05 0x06 0x06 0x07 0x07 0x08 0x09 0x0A 0x0A 0x0B 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x10 0x10 0x11 0x12 0x1F 0x20 0x2F 0x30 0x3F Default Value (H) Bit Field Name Description 1:0 3:2 4 5 15:6 15:0 15:0 15:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:0 15:0 15:8 7:0 15:8 7:0 15:0 15:0 15:0 15:0 0 1 15:2 15:0 HBI Select RESERVED HBI_SWAP8* HBI_SWAP32* RESERVED PCI Vendor ID PCI Device ID PCI Class Code [23:8] PCI Class Code [7:0] RESERVED PCI Revision ID RESERVED PCI BIST RESERVED PCI Header Type RESERVED PCI Subsystem ID PCI Subsystem Vendor ID PCI Max_Lat PCI Min_Gnt PCI Interrupt Pin RESERVED RESERVED RESERVED RESERVED RESERVED PQ_ADD_DECODE_EN PQII_PIPELINE_EN RESERVED PQ_BASE_ADD Host Bus Interface Select 15:0 RESERVED 0x0000 15:0 RESERVED 0x0000 15:0 RESERVED 0x0000 Endian Byte Swap Endian Double-Word Swap Address decode enable MPC8260 bus pipeline enabled Base address 0x0 0x0 0x0 0x0 0x0 0x13A3 0x0020 0x0B40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0000 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x0 0x0 0x0000 0x0000 Notes: * Refer to Section 5.3 for endianness control. When using the 7955 in the PowerQuick I and PowerQuick II modes, the 7955 device supports two chip select methods. The PQ_ADD_DECODE_EN bit from EEPROM (address 0x010 bit 0) selects which method is used as shown in Table 8. For sake of this discussion, PQ_signalname will represent signals from both PowerQuicc I and PowerQuicc II. 7955 - Data Sheet, DS-0114-08 Hifn Confidential 19 If the PQ_ADD_DECODE_EN bit is zero, the device is selected solely by the PQ_CS# pin, qualified by PQ_TS#. This method is used for configurations without an EEPROM, for configurations with an EEPROM when PQ_ADD_DECODE_EN is zero, and as the default. If the PQ_ADD_DECODE_EN bit is a one, the device is selected using a combination of chip select and address comparison. When PQ_CS# and PQ_TS# are asserted and the 16 most significant bits of the host address PQ_A[0:15] matches the PQ_BASE_ADD field in the EEPROM, address 0x011 bits [15:0], the device is selected. In a typical application of this method the PQ_CS# pin would be tied low. Table 8 PowerQuicc I and PowerQuicc II Chip Select Methods PQ_ADD_DECODE_EN EEPROM 0 Yes 1 0 (default value) No Chip Select Method PQ_TS# and PQ_CS# active PQ_TS# and PQ_CS# active, and PQ_A[0:15] = PQ_BASE_ADD[15:0] PQ_TS# and PQ_CS# active 5.2.2 Configuration without EEPROM If the EEPROM_EN input is tied low, the EEPROM interface signals are used as simple configuration inputs. EEPROM_CS and EEPROM_SK select the Host Bus mode, while EEPROM_DI and EEPROM_DO select the endian settings. Table 9 Host Bus Mode Configuration without EEPROM EEPROM_CS EEPROM_SK Host Bus Mode 0 0 1 1 0 1 0 1 PCI Bus Mode PowerQuicc-II Bus Mode PowerQuicc-I Bus Mode Asynchronous SRAM Bus Mode Table 10 Host Bus Endian Configuration without EEPROM EEPROM_DI EEPROM_DO Host Bus Endian Mode 0 0 1 1 0 1 0 1 SWAP[32,8] SWAP[32,8] SWAP[32,8] SWAP[32,8] = = = = 00 01 10 11 Table 11 PCI Register Configuration without EEPROM PCI Configuration Space Field Default Value (H) Read/Write Access PCI Configuration Address (H) EEPROM Loadable? Device ID 0x0020 or 0x001D (1) 0x13A3 0x0280 0x0000 0x0B4000 Read only 0x02-03 Yes Read only Read only Read/Write Read only 0x00-01 0x06-07 0x04-05 0x09-0B Yes No No Yes Vendor ID Status Command Class Code 7955 - Data Sheet, DS-0114-08 Hifn Confidential 20 Revision ID BIST Header Type Master Lat Timer Cacheline Size BAR0 BAR1 BAR2 Subsystem ID Subsystem Vendor ID Max_Lat Min_Gnt Interrupt Line 0x0000 0x00 0x00 0x00 Read only Read only Read only Read/Write 0x08 0x0F 0x0E 0x0D Yes No Yes No 0x00 (2) 0x00000000 0x00000000 0x00000000 0x0000 0x0000 Read/Write Read/Write Read/Write Read/Write Read only Read only 0x0C 0x10-13 0x14-17 0x18-1B 0x2E-2F 0x2C-2D No No No No Yes Yes 0x00 0x00 0x00 Read only Read only Read/Write 0x3F 0x3E 0x3C Yes Yes No Note (1) The two different Device_IDs are to be used for the 7955 and 7956, respectively. (2) The Cacheline size may be set to 0x08 for better performance. 5.3 Endianness Configuration The internal data endianness format of the 7955 is 64-bit Little-Endian. However, the 7955 is capable of functioning with four different host interface modes; 64-bit PCI-2.2 , 32-bit PowerQuicc I and 32-bit PowerQuicc II. Endianness configuration is controlled for the following data paths: Target access to Registers (EEPROM Memory Map) Target access to Local-RAM (DMA Configuration Register #1) Target access to PKRAM (DMA Configuration Register #2) Initiator access to external descriptors (DMA Configuration Register #1) Initiator access to external data (Descriptor Structures) Initiator access to Local-RAM for internal descriptors and data is always in Little-Endian format. Target access to Local-RAM must be configured appropriately to preserve internal Little-Endian format. 5.3.1Device Endianness Configuration Independent 2-bit fields will determine the endianness of each of these 5 data paths. The 2-bit field comprise of SWAP8 bit, which controls byte transposition of a 32-bit entity, and SWAP32 bit that controls swapping within a 64-bit entity. To the extent possible, these two bits are adjacent and the SWAP32 bit is the significant bit position. Table 12 7955 Endianness Configuration Endianness Configuration HBI_SWAP32 HBI_SWAP8 System Data Format 32-bit 0 Little-Endian 0 7955 - Data Sheet, DS-0114-08 Hifn Confidential 64-bit Little-Endian 21 0 1 1 0 1 1 Big-Endian (Double-Word Swapped) Little-Endian (Double-Word Swapped) Big-Endian Big-Endian RESERVED Table 13 Endianness Mapping of System Data System System Data Format Endianness Mode Byte[7] Byte[6] Byte[5] 32-bit LittleEndian RESERVED 32-bit BigEndian 64-bit LittleByte[7] Byte[6] Byte[5] Endian 64-bit LittleEndian (DW Byte[3] Byte[2] Byte[1] swapped) 64-bit BigByte[0] Byte[1] Byte[2] Endian 64-bit BigEndian (DW Byte[4] Byte[5] Byte[6] swapped) 7955 - Data Sheet, DS-0114-08 Hifn Confidential Byte[4] Byte[3] Byte[2] Byte[1] Byte[0] Byte[3] Byte[2] Byte[1] Byte[0] Byte[0] Byte[1] Byte[2] Byte[3] Byte[4] Byte[3] Byte[2] Byte[1] Byte[0] Byte[0] Byte[7] Byte[6] Byte[5] Byte[4] Byte[3] Byte[4] Byte[5] Byte[6] Byte[7] Byte[7] Byte[0] Byte[1] Byte[2] Byte[3] 22 32-bit Little-Endian 32-bit Big-Endian B3 B2 B1 B0 B0 B1 B2 B3 B3 B2 B1 B0 B3 B2 B1 B0 64-bit Little-Endian 64-bit Big-Endian B7 B6 B5 B4 B3 B2 B1 B0 B0 B1 B2 B3 B4 B5 B6 B7 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B5 B0 64-bit Big-Endian (Double-Word Swapped) 64-bit Little-Endian (Double-Word Swapped) B3 B2 B1 B0 B7 B6 B5 B4 B4 B5 B6 B7 B0 B1 B2 B3 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 Figure 4 7955 - Data Sheet, DS-0114-08 Hifn Confidential Endianness Transfer Modes 23 5.3.2 Device Endianness Configuration Examples Table 14 64-bit Host Data Endianness Control Endianness Configuration HBI_SWAP32 HBI_SWAP8 0 0 0 1 1 0 1 1 System Data Format 32-bit Mode Transferred Data 0 1 6 7 RESERVED 7955 - Data Sheet, DS-0114-08 Hifn Confidential 2 3 4 5 4 5 2 3 64-bit Mode Transferred Data 6 7 0 1 0 1 8 9 E F 6 7 2 3 A B C D 4 5 4 5 C D A B 2 3 6 7 E F 8 9 0 1 8 9 6 7 6 7 E F A B 4 5 4 5 C D C D 2 3 2 3 A B E F 0 1 0 1 8 9 24 Signal Description 6 The 7955 Security Accelerator supports three different Host Bus Interface modes; PCI 2.2, PowerQuicc I and PowerQuicc II. All other signals are used for configuration and testing. 6.1 Signal Overview 6.1.1 PCI Signal Overview 7955 PCI_CLK PCI 2.2 Host Bus Interface PCI_RST# PCI_IDSEL Security Accelerator (PCI mode) AVD AVS PLL_REF Core Clock PLL PCI_GNT# 32 PCI_AD[31:0] 32 PCI_AD[63:32] PCI_PAR PCI_PAR64 8 PCI_CBE#[7:0] PCI_FRAME# PCI_TRDY# EEPROM_CS EEPROM_SK EEPROM_DI EEPROM_DO EEPROM Config Interface EEPROM_EN PCI_IRDY# PCI_DEVSEL# TEST_EN Tied Low PCI_STOP# PCI_PERR# JTDI PCI_SERR# JTDO PCI_ACK64# JTMS PCI_REQ# PCI_REQ64# JTCK JTAG Test Interface JTRST# PCI_INTA# Figure 5 7955 - Data Sheet, DS-0114-08 Hifn Confidential PCI Host Bus Interface Signals 25 6.1.2 PowerQuicc II Signal Overview PQII_CLK PQII_RST# 32 32 AVS PLL_REF PQII_A[0:31] PQII_DBB# PQII_PSDVAL# PQII_TA# PQII_TBST# PQII_TEA# 5 AVD Security PQII_CS# Accelerator PQII_AACK# (PowerQuicc_II Mode) PQII_D[0:31] 4 7955 PQII_TS# EEPROM_CS EEPROM_SK EEPROM_DI EEPROM_DO EEPROM_EN TEST_EN PQII_TSIZ[0:3] PQII_TT[0:4] PQII_INT# JTDI JTDO JTMS JTCK JTRST# Figure 6 7955 - Data Sheet, DS-0114-08 Hifn Confidential PowerQuicc II Host Bus Interface Signals 26 6.1.3 PowerQuicc I Signal Overview 7955 32 32 2 PQI_CLK PQI_RST# PQI_CS# PQI_A[0:31] PQI_BURST# PQI_D[0:31] PQI_RD/WR# PQI_TA# PQI_TEA# PQI_TS# PQI_TSIZ[0:1] PQI_INT# Security Accelerator (PowerQuicc_I mode) AVD AVS PLL_REF EEPROM_CS EEPROM_SK EEPROM_DI EEPROM_DO EEPROM_EN TEST_EN JTDI JTDO JTMS JTCK JTRST# Figure 7 7955 - Data Sheet, DS-0114-08 Hifn Confidential PowerQuicc I Host Bus Interface Signals 27 6.2 Detailed Signal Description 6.2.1 PCI Signal Description The 7955 provides a PCI 2.2 compliant interface mode. The following PCI signals are supported. Table 15 PCI Signals PCI Signals I/O (Buffer type) Description PCI_CLK PCI_RST# PCI_IDSEL PCI_REQ# PCI_GNT# PCI_AD[63:0] PCI_PAR Input (I-PCI) Input (I-PCI) Input (I-PCI) Output (TS-PCI) Input (I-PCI) I/O (I/O-PCI) I/O (I/O-PCI) PCI_PAR64 I/O (I/O-PCI) PCI_CBE#[7:0] PCI_FRAME# PCI_TRDY# PCI_IRDY# PCI_DEVSEL# PCI_STOP# PCI_PERR# PCI_SERR# PCI_ACK64# I/O (I/O-PCI) I/O (I/O-PCI) I/O (I/O-PCI) I/O (I/O-PCI) I/O (I/O-PCI) I/O (I/O-PCI) I/O (I/O-PCI) Output (TS-PCI) I/O (I/O-PCI) PCI_REQ64# I/O (I/O-PCI) PCI_INTA# Output (TS-PCI) PCI clock PCI reset. Master reset for 7955. PCI initialization device select. PCI bus request. PCI bus grant. PCI address/data bus. PCI Parity signal; even parity across PCI_AD[31:0] and PCI_CBE#[3:0] PCI Parity Upper DWORD signal for PCI_AD[63:32] and PCI_CBE#[7:4]. The PCI_PAR64 port is used only when the interface is configured with a 64-bit AD bus. PCI bus command/byte-enable bits. PCI cycle frame. PCI target ready. PCI initiator ready. PCI device select. PCI stop. PCI parity error. PCI system error. PCI Acknowledge 64-Bit Transfer signal. The PCI_ACK64# is used only when the interface is configured with a 64-bit AD bus. PCI Request 64-Bit Transfer signal. The PCI_REQ64# is used only when the interface is configured with a 64-bit AD bus. PCI interrupt request. Notes: Buffer Type: I-PCI=PCI input, I/O-PCI=PCI Bidirectional, TS-PCI=PCI Tri-State output 7955 - Data Sheet, DS-0114-08 Hifn Confidential 28 6.2.2 PowerQuicc II Signal Description The 7955 provides a MPC8260 PowerQuicc II compliant interface mode. The following PowerQuicc II signals are supported. It is important to note that bus transactions have certain restrictions for the transfer type, alignment, and size that must be adhered to for proper operation. Only word, double word and burst type bus accesses are supported by the 7955. Table 16 specifies the supported encodings of PQII_TSIZ[0:3]. All transferred data must be naturally aligned. All word bus transfers must be aligned on a 32-bit word boundary, all double word bus transfers must be aligned on a double word boundary. Local memory, address range 0x8000 - 0xFFFC, can be accessed using word, double word, or burst transfers. The remaining address space, address range 0x0000 - 0x33FC, can only be accessed using word transfers. Should a bus transaction violate the restrictions mentioned above, the device will immediately terminate the transaction with the transfer error acknowledge signal PQII_TEA# asserted. Only the specified transfer types encodings of PQII_TT[0:4] are supported. The device ignores all unsupported transfer types. Table 16 PowerQuicc II Signals PowerQuicc II Signal I/O (Buffer type) PQII_CLK PQII_RST# PQII_CS# PQII_AACK# Input (I-PQ) Input (I-PQ) Input (I-PQ) Tri-state Output (I/O-PQ) Input (I/O-PQ) Input (I/O-PQ) I/O (I/O-PQ) Tri-state Output (I/O-PQ) Tri-state Output (I/O-PQ) Input (I/O-PQ) Tri-state Output (TS-PQ) Input (I-PQ) Input (I/O-PQ) PQII_A[0:31] PQII_DBB# PQII_D[0:31] PQII_TA# PQII_PSDVAL# PQII_TBST# PQII_TEA# PQII_TS# PQII_TSIZ[0:3] 7955 - Data Sheet, DS-0114-08 Hifn Confidential Description Clock input, for the PowerQuicc I&II interface bus clock Chip reset. Master reset for 7955. The device chip select. Active low. PowerQuicc II address acknowledge PowerQuicc II address bus PowerQuicc II data bus busy PowerQuicc II data bus PowerQuicc II transfer acknowledge PowerQuicc II partial data valid indication PowerQuicc II transfer burst PowerQuicc II transfer error acknowledge PowerQuicc II transfer start PowerQuicc II transfer size PQII_TSIZ[0:3] PQII_TBST# 0000 1 0010 0 Transfer Size 8 bytes 32 bytes Access Local Memory only Local Memory 29 PowerQuicc II Signal I/O (Buffer type) Description 0100 PQII_TT[0:4] Input (I/O-PQ) Open-Drain Output (TS-PQ) 4 bytes only All address space PowerQuicc II transfer type PQII_TT[0:4] 01010 01110 11010 11110 01011 00010 00110 10010 PQII_INT# 1 Transfer Type Read - Single Beat Read with intent to write Read atomic Read with intent to modify atomic Read with no intent to cache Write with flush Write with kill Write with flush automatic PowerQuicc II interrupt request Notes: Buffer Type: I-PQ=PQ input, I/O-PQ=PQ Bi-directional, TS-PQ=PQ Tri-State output 7955 - Data Sheet, DS-0114-08 Hifn Confidential 30 6.2.3 PowerQuicc I Signal Description The 7955 provides a MPC860/850 PowerQuicc I compliant interface mode. The following PowerQuicc I signals are supported. It is important to note that bus transactions have certain restrictions for the transfer type, alignment, and size that must be adhered to for proper operation. Only word and burst type bus accesses are supported by the 7955. Table 17 specifies the supported encodings of PQI_TSIZ[0:1]. All word bus transfers must be aligned on a 32-bit word boundary. Local memory, address range 0x8000 - 0xFFFC, can be accessed using word, or burst transfers. The remaining address space, address range 0x0000 - 0x33FC, can only be accessed using word transfers. Should a bus transaction violate the restrictions, the device will immediately terminate the transaction with the transfer error acknowledge signal PQI_TEA# asserted. Table 17 PowerQuicc I Signals PowerQuicc I Signal I/O (Buffer type) PQI_CLK PQI_RST# PQI_CS# PQI_A[0:31] PQI_BURST# PQI_D[0:31] PQI_RD/WR# PQI_TA# Input (I-PQ) Input (I-PQ) Input (I-PQ) Input (I/O-PQ) Input (I/O-PQ) I/O (I/O-PQ) Input (I/O-PQ) Tri-state Output (I/OPQ) Tri-state Output (TSPQ) Input (I-PQ) Input (I/O-PQ) PQI_TEA# PQI_TS# PQI_TSIZ[0:1] PQI_INT# Open-Drain Output (TSPQ) Description Clock input, for the PowerQuicc I interface bus clock Chip reset. Master reset for 7955. The device chip select. Active low. PowerQuicc I address bus. PowerQuicc I transfer burst PowerQuicc I data bus PowerQuicc I read/write enable PowerQuicc I transfer acknowledge PowerQuicc I transfer error acknowledge PowerQuicc I transfer start PowerQuicc I transfer size PQI_TSIZ[0:1] PQI_BURST# 00 1 00 0 Transfer Size 4 bytes 16 bytes Access All address space Local Memory only PowerQuicc I interrupt request Notes: Buffer Type: I-PQ=PQ input, I/O-PQ=PQ Bi-directional, TS-PQ=PQ Tri-State output 7955 - Data Sheet, DS-0114-08 Hifn Confidential 31 6.2.4 EEPROM Signal Description The 7955 has an EEPROM 5 pin serial interface. The following signals are used in this interface. Table 18 EEPROM Signals EEPROM Signal I/O (Buffer type) Description EEPROM_EN Input (I) EEPROM_CS I/O (I/O-O4) EEPROM_DI I/O (I) EEPROM_DO I/O (I/O-O4) EEPROM_SK I/O (I/O-O4) When high, an EEPROM device is used to configure the 7955. When low, an EEPROM device is not used and the EEPROM device pins are used as Hardware Configuration inputs. See Section 5.2 for more details. EEPROM chip select / HW Configuration Address bit[0] EEPROM serial data in / HW Configuration Address bit[1] EEPROM serial data out / HW Configuration Address bit[2] EEPROM clock / HW Configuration Address bit[3] Notes: Buffer Type: I=Input, I/O-O4=I/O with 4mA output driver 6.2.5 Clock and Test Signal Description The 7955 has a phase locked loop reference signal that must be connected to a clock source in all configurations. Bypassing the PLL is not a supported mode of operation for the 7955. 7955 - Data Sheet, DS-0114-08 Hifn Confidential 32 Table 19 PLL Signals PLL Signal PLL_REF I/O Description Input (CI) PLL reference clock input or system clock (7955 Security Accelerator). This signal is completely asynchronous to the host bus interface, HBI_CLK, (PQI_CLK, PQII_CLK and PCI_CLK). On 7955 Security Accelerator, this signal is the input to a clockmultiplier PLL, which provides the clock for the packet engine and PK processor subsystems. Notes: The 7955 requires a clock source to drive the PLL_REF input pin in all configurations. This clock input pin must not be grounded when register to a 0b0 to select the HBI_CLK as the PLL source will fail unless PLL the HBI_CLK (PQI_CLK or PCI_CLK) is used to drive the internal PLL. Programming bit 0 (PLL_REF_SEL) of the PLL Configuration _REF is driven by a clock source. Once the PLL Configuration register has been programmed, the PLL_REF input requires four rising edges to complete the PLL clock source reconfiguration. Once the four clocks have been completed, the PLL lock time, as specified in the Timing Specifications shown in Table 24 for PLL_REF, will begin. When using PLL_REF as the clock source to the PLL, all timing requirements as stated in Table 24 must be met. When using PLL_REF to reconfigure the PLL source to the HBI_CLK, the clock frequency still must not exceed the values specified in Table 24 but the minimum frequency doesn't apply. Any source that will provide the required four clocks can be used. One solution for customers that use an EEPROM (EEPROM_EN=0b1) to configure the device is to connect the EEPROM_SK signal to the PLL_REF input pin as well as to the EEPROM. In this case, the PLL clock source is guaranteed to be configured to the HBI_CLK within 2050 PCI clock periods after writing to the PLL Configuration register. Note: Buffer Type: CI=clock input The following signals are used for testing the 7955. Table 20 Test and JTAG signals Test Signal I/O (Buffer type) Description TEST_EN JTDI JTDO JTMS JTCK JTRST# Input (I) Input (PI) Output (TS-O4) Input (PI) Input (PI) Input (PI) Test mode enable. It is normally tied low at all times JTAG test data in JTAG test data out JTAG test mode select JTAG test clock JTAG test mode reset. This should not be tied to the system reset signal. It is normally tied low at all times except JTAG testing. Note: Buffer Type: PI-Input with pull-up resistor, TS-O4=Tri-State with 4mA output driver 7955 - Data Sheet, DS-0114-08 Hifn Confidential 33 6.2.6 Power and Ground Signal Description The following power and ground signals must be connected as shown below for proper device operation. Table 21 Power and Ground signals Misc. Signal I/O Description VSS Ground VSS2 Ground VDDC VDDS Power Power VDDS2 Power VDDS12 Power AVS AVD RESERVED_VSS RESERVED_NC Ground Power Input Output Digital ground for output buffers Digital ground for input buffers, internal arrays & prebuffers Power for 1.5 V internal logic Power for 3.3 V output buffers Power for 3.3 V input buffers & preTie these buffers together Power for 3.3 V input & output buffers & pre-buffers PLL Analog ground PLL 1.5 V Analog supply Must be tied to VSS (series resistor is optional) Must not be connected 7955 - Data Sheet, DS-0114-08 Hifn Confidential 34 Timing Specifications 7 7.1 Table 22 AC Operating Conditions AC Operating Conditions Symbol Parameter Conditions* VDDC Supply voltage - Core 1.5V 5% VDDS Supply voltage - I/O 3.3V 10% VSS Ground potential 0V TA Ambient operating temperature 0C to +70C Note: (*) See de-rating information below for other load conditions. 7.2 Host Bus Interface Clock 4 5 2 3 1 Figure 8 Table 23 PCI_CLK Timing Number Description 1 Clock Clock Clock Clock Clock Clock 2 3 4 5 Input Bus Clock Timing frequency period width high width low rise time from VIL to VIH fall time from VIH to VIL 7955 - Data Sheet, DS-0114-08 Hifn Confidential Min DC Infinite 6 6 Max 66 15 2 2 Units MHz ns ns ns ns ns 35 Table 24 PQI_CLK Timing Number Description 1 Clock Clock Clock Clock Clock Clock 2 3 4 5 Table 25 frequency period width high width low rise time from VIL to VIH fall time from VIH to VIL Max 40 25 2 2 Units MHz ns ns ns ns ns PQII_CLK Timing Number Description 1 Clock Clock Clock Clock Clock Clock 2 3 4 5 Table 26 Min DC Infinite 6 6 frequency period width high width low rise time from VIL to VIH fall time from VIH to VIL Min DC Infinite 6 6 Max 66 15 2 2 Units MHz ns ns ns ns ns PLL_REF Clock Number Description Min Max Units 1 Clock frequency Clock Period Clock width high Clock width low Clock rise time from VIL to VIH Clock fall time from VIH to VIL Duty cycle Jitter (peak to peak) PLL lock time 20 50 4.5 4.5 100 10 MHz ns ns ns ns ns % ps usec 2 3 4 5 n/a n/a n/a 45 2 2 55 100 100*n Note: n = (PLL_ND+1)*2 (see the PLL Configuration Register description in the 7954/7955/7956 Hardware Users Guide (UG-0034) for more information on the PLL_ND setting). 7955 - Data Sheet, DS-0114-08 Hifn Confidential 36 7.3 PCI Timing Table 27 PCI Timing Parameters Symbol Parameter Min Max Units Tval PCI_CLK to Signal Valid Delay - bused signals PCI_CLK to Signal Valid Delay - point to point signals Float to Active Delay Active to Float Delay Input setup time to PCI_CLK - bused signals Input setup time to PCI_CLK - point to point signals Input Hold time from PCI_CLK Reset Active Time after power stable Reset Active Time after PCI_CLK stable Reset Active to output float delay PCI_REQ64# to PCI_RST# setup time PCI_RST# to PCI_REQ# hold time PCI_RST# high to first Configuration access PCI_RST# high to first PCI_FRAME# assertion 2 6 ns 2 6 ns 14 3 ns ns ns 5 ns 0 1 ns ms 100 ms Tval (ptp) Ton Toff Tsu Tsu (ptp) Th Trst Trst-clk Trst-off Trrsu trrh Trhfa Trhff 2 40 10Tcyc 0 ns ns 50 ns 2 clocks 5 clock Notes: These specifications are taken from the PCI 2.2 Standard, section 7.6.4.2. PCI_REQ# and PCI_GNT# are point to point signals and have different input setup times than do bused signals. 7955 - Data Sheet, DS-0114-08 Hifn Confidential 37 7.4 PowerQuicc I Timing Table 28 Read/Write Timing (PQI bus) Number Description 1 PQI_A[0:31], PQI_TSIZ[0:1] input setup time PQI_CS#, PQI_TS#, PQI_BURST#, PQI_RD/WR#, PQI_D[0:31] input setup time PQI_A[0:31], PQI_TS#, PQI_CS#, PQI_TSIZ[0:1], PQI_BURST#, PQI_RD/WR#, PQI_D[0:31] input hold time PQI_D[0:31],PQI_TA#, PQI_TEA# valid delay PQI_D[0:31],PQI_TA#, PQI_TEA# active to float delay PQI_D[0:31],PQI_TA#, PQI_TEA# float to active delay 2 3 4 5 6 Min Max Units 3 ns 5 ns 0 ns 2 2 7 ns 14 ns ns Notes All signals are synchronous to PQI_CLK. Max values for output signals are for a 50 pF load and Min values are for a 10 pF load. PQI_TEA# is not shown in the timing diagram. 7955 - Data Sheet, DS-0114-08 Hifn Confidential 38 PQI_CLK PQI_TS# 2 3 PQI_A[0:31] PQI_TSIZ[0:1] 1 3 PQI_CS# 2 3 PQI_BURST# 2 3 PQI_TA# 4,6 5 4 Write Operation PQI_RD/WR# 2 3 PQI_D[0:31] 2 3 Read Operation PQI_RD/WR# 3 2 PQI_D[0:31] 6 Figure 9 7.5 4 4,5 PQI bus Read/Write Timing PowerQuicc II Timing Table 29 Read/Write Timing (PQII bus) Number 1 2 3 4 5 6 Description PQII_A[0:31], PQII_TSIZ[0:3], PQII_TT[0:4] input setup time PQII_CS#, PQII_TS#, PQII_TBST#, PQII_D[0:31], PQII_DBB# input setup time PQII_A[0:31], PQII_TS#, PQII_CS#, PQII_TSIZ[0:3], PQII_TBST#, PQII_TT[0:4], PQII_D[0:31] , PQII_DBB# input hold time PQII_D[0:31], PQII_TA#, PQII_AACK#, PQII_PSDVAL#, PQII_TEA# valid delay PQII_D[0:31], PQII_TA#, PQII_AACK#, PQII_PSDVAL#, PQII_TEA# active to float delay PQII_D[0:31], PQII_TA#, PQII_AACK#, PQII_PSDVAL#, PQII_TEA# float to active delay Min Max Units 3 ns 5 ns 0 ns 2 2 7 ns 14 ns ns Notes 7955 - Data Sheet, DS-0114-08 Hifn Confidential 39 All signals are synchronous to PQII_CLK. Max values for output signals are for a 50 pF load and Min values are for a 10 pF load. PQII_TEA# is not shown in the timing diagram. PQII_CLK PQII_TS# 2 PQII_A[0:31] PQII_TSIZ[0:3] PQII_TT[0:4] 3 3 1 PQII_CS# 2 3 PQII_AACK# 4,6 4 5 PQII_TBST 2 3 PQII_DBB# 3 2 PQII_TA# 4,6 4 5 4 5 Write Operation PQII_PSDVAL# 4,6 PQII_D[0:31] 3 2 Read Operation PQII_PSDVAL# 4,6 4 5 PQII_D[0:31] 6 4 4,5 Figure 10 PQII bus Read/Write Timing 7955 - Data Sheet, DS-0114-08 Hifn Confidential 40 7.6 EEPROM The EEPROM interface signal timing is derived from the PCI_CLK divided by 256. Table 30 EEPROM Timing Number Symbol 1 2 3 4 5 6 7 8 9 10 11 12 Fsk Tskh Tskl Tsks Tcs Tcss Tdh Tdis Tcsh Tdih Tpd0 Tpd1 Min 128 128 128 256 128 0 128 0 127 tPCI_CLK tPCI_CLK tPCI_CLK tPCI_CLK tPCI_CLK Max - - - - - Units 256 tPCI_CLK 5 5 5 5 10 ns ns ns ns ns ns ns ns ns ns ns ns tPCI_CLK - 10 tPCI_CLK - 10 127 tPCI_CLK - 10 127 tPCI_CLK - 10 Synchronous Data Timing EEPROM_CS VIH 5 1 VIL 4 EEPROM_SK 6 2 9 3 VIH VIL VIH 8 10 EEPROM_DO VIL 11 EEPROM_DI VOH VOL 12 7 7 Figure 11 EEPROM Timing 7955 - Data Sheet, DS-0114-08 Hifn Confidential 41 DC Specifications 8 8.1 Absolute Maximum Ratings Table 31 Absolute Maximum Ratings DC Supply Voltage (VDDS, VDDS2, VDDS12) DC Supply Voltage (VDDC, AVD) DC Input Voltage (Signals) Storage Temperature -0.3V to +5.0V -0.3V to +3.3V -0.3V to VDDS+0.3 -40C to +125C Warning Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 8.2 Power Sequencing The +1.5V and +3.3V power supply voltages must be asserted at the same time. Otherwise, the device may be damaged by reverse currents. To prevent damage to the device, these voltages must be enabled within the time given in the recommended operating conditions. The power supply should be designed to assert power within the time limits given under the recommended operating conditions. 7955 - Data Sheet, DS-0114-08 Hifn Confidential 42 8.3 Recommended Operating Conditions Table 32 Recommended Operating Conditions DC Supply Voltage (VDDS, VDDS2, VDDS12) DC Supply Voltage (VDDC, AVD) Delay from 1.5V (VDDC, PLL_AVD) power supply reaching 80% of its final value to 3.3V power supply (VDDS, VDDS2, VDDS12) reaching 80% of its final value. Delay from 3.3V power supply (VDDS, VDDS2, VDDS12) falling below 80% of its initial value to 1.5V (VDDC, PLL_AVD) power supply falling below 80% of its initial value. Operating Temperature +3.0V to +3.6V +1.425V to +1.575V 0 - 100ms 0 - 100ms 0C to +70C I/O Voltage* 80% Core Voltage* 80% GND 0 ms min 0 ms min 100 ms max 100 ms max Turn On Turn Off Figure 12 Power Sequence Specifications 8.4 DC Characteristics Table 33 DC Electrical Characteristics Symbol Parameter VIL Low level input voltage (I, PI, I/OO4) Conditions I-PCI, I/O-PCI, I-PQ, I/O-PQ Min -0.5 Clock Input (CI) VIH 1.425 High level input current (I, I/OO4) I-PCI, I/O-PCI, I-PQ, I/O-PQ 7955 - Data Sheet, DS-0114-08 Hifn Confidential 0.8 V 1.17 V 4.1 2.4 VIN = VSS VDDS = 3.6V With pull-up (PI) I-PCI, I/O-PCI, I-PQ, I/O-PQ IIH Units 2.0 Clock Input (CI) Low level input current (I, I/O-O4) Max 0.72 High level input voltage (I, PI, I/O-O4) I-PCI, I/O-PCI, I-PQ, I/O-PQ IIL Typ VIN = VDDS VDDS = 3.6V -10 10 10 -10 200 10 -10 10 -10 10 A A 43 Symbol Parameter Conditions VOL Low level output voltage VDDS = 3.0V (O4) Min Typ High level output voltage (O4) 0.4 0.36 VDDS = 3.0V IOH = -4mA I/O-PCI, TS-PCI, I/O-PQ, TSPQ IOZ High impedance output leakage current IDD Quiescent supply current CIN Input capacitance (I, PI) Units V IOL = 4mA I/O-PCI, TS-PCI, I/O-PQ, TSPQ VOH Max V 2.4 2.7 VO = VSS or VDDS VDDS = 3.6V -10 A 300 VDDS = 3.3V 2.4 pF I-PCI, I/O-PCI, I-PQ, I/O-PQ 10 PCI_IDSEL 8 PCI_CLK, PQI_CLK, PQII_CLK 5 A 12 COUT Output capacitance (TS-O4) VDDS = 3.3V 5.6 pF CI/O I/O capacitance (I/O-O4) VDDS = 3.3V 6.6 IDD core Active Supply Current (VDDC) VDDC=1.575V 166 178 mA IDD I/O Active Supply Current (VDDS) VDDS = 3.6V 115 165 mA IAVD PLL analog power supply current AVD = 1.575V 6 mA pF Notes: Host Bus pins are shared between 32-bit PowerQuicc I & II and the 64-bit PCI. Buffer Type: I=input, I/O-O4=Bi-directional with 4mA output driver, CI=Clock input, PI-Input with pull-up resistor, TS-O4=Tri-State with 4mA output driver, I-PCI=PCI input, I/O-PCI=PCI Input/Output, TS-PCI=PCI Tri-State output, I-PQ=PQ input, I/O-PQ=PQ Input/Output, TS-PQ=PQ Tri-State output 7955 - Data Sheet, DS-0114-08 Hifn Confidential 44 9 Thermal Specifications Table 34 Thermal Specifications Parameter Min Typ Max Units Junction Temperature (Tj) 0 100* 125* C Ambient Operating Temperature (Ta) 0 70 C Storage Temperature -40 125 C Power Dissipation (P) @ VDDS = 3.6V 0.64 0.89 W * For proper operation, the maximum junction temperature must not exceed 125 C. However, the life of the part may be shortened if the average operating junction temperature is allowed to exceed 100 C. Table 35 LQFP Thermal Resistance Parameter Thermal Resistance, Junction to Ambient ( ja) Thermal Resistance, Junction to Ambient ( jma at 1 m/s) Internal Thermal Resistance ( jc) Temperature Correlation, Center Top of Pkg to Junction (jt) 9.1 Max 44.4 38.5 12 0.4 Units C/W C/W C/W C/W Heat Sink Requirements Refer to the 7954/7955/7956 Thermal Characteristics Application Note for additional information to help determine the heat sink requirements. 9.2 Junction Temperature Specifications The maximum operating junction temperature is 125 C. Above this temperature, operating the part is not guaranteed. For maximum operating life the junction temperature in the device should be no more than 100 C. Worst case device dissipation should be used when performing thermal calculations. Refer to Thermal Management Application Note, AN-0038 for additional information to help determine application specific junction temperatures and heat sink requirements. 7955 - Data Sheet, DS-0114-08 Hifn Confidential 45 10 Pin List 10.1 LQFP PCI-Mode Pin List Table 36 LQFP PCI-Mode Pin List (Numerically) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name TEST_EN JTDO JTCK JTRST# EEPROM_EN VDDS2 EEPROM_DO EEPROM_CS EEPROM_SK EEPROM_DI VSS2 VDDC PCI_INTA# PCI_RST# VDDS PCI_CLK PCI_GNT# VDDC PCI_REQ# PCI_AD31 PCI_AD30 PCI_AD29 VSS PCI_AD28 PCI_AD27 PCI_AD26 VDDS PCI_AD25 PCI_AD24 VDDS2 PCI_CBE#3 PCI_IDSEL PCI_AD23 VSS2 VDDC PCI_AD22 7955 - Data Sheet, DS-0114-08 Hifn Confidential Pin Name Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PCI_AD21 PCI_AD20 PCI_AD19 VDDS PCI_AD18 PCI_AD17 PCI_AD16 VSS PCI_CBE#2 PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_DEVSEL# PCI_STOP# VDDS PCI_PERR# VSS VSS2 VDDS2 PCI_SERR# PCI_PAR VDDC PCI_CBE#1 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 VSS PCI_AD11 VDDS PCI_AD10 PCI_AD9 PCI_AD8 PCI_CBE#0 PCI_AD7 PCI_AD6 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Name VSS2 PCI_AD5 PCI_AD4 VSS PCI_AD3 VDDS VDDS2 PCI_AD2 PCI_AD1 PCI_AD0 PCI_ACK64# PCI_REQ64# PCI_CBE#7 PCI_CBE#6 PCI_CBE#5 VSS PCI_CBE#4 VDDS12 PCI_PAR64 VDDC PCI_AD63 VSS2 PCI_AD62 PCI_AD61 PCI_AD60 PCI_AD59 PCI_AD58 PCI_AD57 VDDS2 VSS PCI_AD56 VDDS PCI_AD55 PCI_AD54 PCI_AD53 PCI_AD52 Pin 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name PCI_AD51 PCI_AD50 PCI_AD49 PCI_AD48 VSS2 VDDS PCI_AD47 VSS PCI_AD46 PCI_AD45 PCI_AD44 PCI_AD43 PCI_AD42 PCI_AD41 VDDC PCI_AD40 VDDS2 VDDS PCI_AD39 VSS PCI_AD38 PCI_AD37 PCI_AD36 PCI_AD35 PCI_AD34 PCI_AD33 PCI_AD32 VSS2 RESERVED_NC VDDS AVS AVD VSS JTMS JTDI PLL_REF 46 Table 37 LQFP PCI-Mode Pin List (Alphabetically) Pin 140 139 8 10 7 5 9 3 143 2 142 4 83 82 81 80 77 75 74 72 71 69 68 67 65 63 62 61 60 43 42 41 39 38 37 36 Name AVD AVS EEPROM_CS EEPROM_DI EEPROM_DO EEPROM_EN EEPROM_SK JTCK JTDI JTDO JTMS JTRST# PCI_ACK64# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 7955 - Data Sheet, DS-0114-08 Hifn Confidential Pin 33 29 28 26 25 24 22 21 20 135 134 133 132 131 130 129 127 124 122 121 120 119 118 117 115 112 111 110 109 108 107 106 105 103 100 99 Name PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_AD32 PCI_AD33 PCI_AD34 PCI_AD35 PCI_AD36 PCI_AD37 PCI_AD38 PCI_AD39 PCI_AD40 PCI_AD41 PCI_AD42 PCI_AD43 PCI_AD44 PCI_AD45 PCI_AD46 PCI_AD47 PCI_AD48 PCI_AD49 PCI_AD50 PCI_AD51 PCI_AD52 PCI_AD53 PCI_AD54 PCI_AD55 PCI_AD56 PCI_AD57 PCI_AD58 Pin 98 97 96 95 93 70 59 45 31 89 87 86 85 16 49 46 17 32 13 47 57 91 52 19 84 14 56 50 48 144 137 1 12 18 35 58 Name PCI_AD59 PCI_AD60 PCI_AD61 PCI_AD62 PCI_AD63 PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3 PCI_CBE#4 PCI_CBE#5 PCI_CBE#6 PCI_CBE#7 PCI_CLK PCI_DEVSEL# PCI_FRAME# PCI_GNT# PCI_IDSEL PCI_INTA# PCI_IRDY# PCI_PAR PCI_PAR64 PCI_PERR# PCI_REQ# PCI_REQ64# PCI_RST# PCI_SERR# PCI_STOP# PCI_TRDY# PLL_REF RESERVED_NC TEST_EN VDDC VDDC VDDC VDDC Pin 92 123 15 27 40 51 66 78 104 114 126 138 90 6 30 55 79 101 125 23 44 53 64 76 88 102 116 128 141 11 34 54 73 94 113 136 Name VDDC VDDC VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS12 VDDS2 VDDS2 VDDS2 VDDS2 VDDS2 VDDS2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 47 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PCI_AD52 PCI_AD53 PCI_AD54 PCI_AD55 VDDS PCI_AD56 VSS VDDS2 PCI_AD57 PCI_AD58 PCI_AD59 PCI_AD60 PCI_AD61 PCI_AD62 VSS2 PCI_AD63 VDDC PCI_PAR64 VDDS12 PCI_CBE#4 VSS PCI_CBE#5 PCI_CBE#6 PCI_CBE#7 PCI_REQ64# PCI_ACK64# PCI_AD0 PCI_AD1 PCI_AD2 VDDS2 VDDS PCI_AD3 VSS PCI_AD4 PCI_AD5 VSS2 10.2 LQFP PCI Mode Pinout 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PCI_AD6 PCI_AD7 PCI_CBE#0 PCI_AD8 PCI_AD9 PCI_AD10 VDDS PCI_AD11 VSS PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_CBE#1 VDDC PCI_PAR PCI_SERR# VDDS2 VSS2 VSS PCI_PERR# VDDS PCI_STOP# PCI_DEVSEL# PCI_TRDY# PCI_IRDY# PCI_FRAME# PCI_CBE#2 VSS PCI_AD16 PCI_AD17 PCI_AD18 VDDS PCI_AD19 PCI_AD20 PCI_AD21 TEST_EN JTDO JTCK JTRST# EEPROM_EN VDDS2 EEPROM_DO EEPROM_CS EEPROM_SK EEPROM_DI VSS2 VDDC PCI_INTA# PCI_RST# VDDS PCI_CLK PCI_GNT# VDDC PCI_REQ# PCI_AD31 PCI_AD30 PCI_AD29 VSS PCI_AD28 PCI_AD27 PCI_AD26 VDDS PCI_AD25 PCI_AD24 VDDS2 PCI_CBE#3 PCI_IDSEL PCI_AD23 VSS2 VDDC PCI_AD22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PCI_AD51 PCI_AD50 PCI_AD49 PCI_AD48 VSS2 VDDS PCI_AD47 VSS PCI_AD46 PCI_AD45 PCI_AD44 PCI_AD43 PCI_AD42 PCI_AD41 VDDC PCI_AD40 VDDS2 VDDS PCI_AD39 VSS PCI_AD38 PCI_AD37 PCI_AD36 PCI_AD35 PCI_AD34 PCI_AD33 PCI_AD32 VSS2 RESERVED_NC VDDS AVS AVD VSS JTMS JTDI PLL_REF Figure 13 LQFP PCI Mode Pinout Drawing 7955 - Data Sheet, DS-0114-08 Hifn Confidential 48 10.3 LQFP PQI Mode Pin List Table 38 LQFP PQI Mode Pin List (Numerically) Pin Name Pin Name Pin Name Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 TEST_EN JTDO JTCK JTRST# EEPROM_EN VDDS2 EEPROM_DO EEPROM_CS EEPROM_SK EEPROM_DI VSS2 VDDC PQI_INT# PQI_RST# VDDS PQI_CLK PQI_TS# VDDC RESERVED_NC PQI_A0 PQI_A1 PQI_A2 VSS PQI_A3 PQI_A4 PQI_A5 VDDS PQI_A6 PQI_A7 VDDS2 PQI_TSIZ1 PQI_CS# PQI_A8 VSS2 VDDC PQI_A9 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PQI_A10 PQI_A11 PQI_A12 VDDS PQI_A13 PQI_A14 PQI_A15 VSS PQI_TSIZ0 RESERVED_VDD PQI_BURST# RESERVED_VSS RESERVED_VSS RESERVED_VSS VDDS PQI_TA# VSS VSS2 VDDS2 PQI_TEA# RESERVED_VSS VDDC RESERVED_VSS PQI_A16 PQI_A17 PQI_A18 PQI_A19 VSS PQI_A20 VDDS PQI_A21 PQI_A22 PQI_A23 RESERVED_VSS PQI_A24 PQI_A25 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 VSS2 PQI_A26 PQI_A27 VSS PQI_A28 VDDS VDDS2 PQI_A29 PQI_A30 PQI_A31 RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS VSS PQI_RW# VDDS12 RESERVED_VSS VDDC PQI_D0 VSS2 PQI_D1 PQI_D2 PQI_D3 PQI_D4 PQI_D5 PQI_D6 VDDS2 VSS PQI_D7 VDDS PQI_D8 PQI_D9 PQI_D10 PQI_D11 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PQI_D12 PQI_D13 PQI_D14 PQI_D15 VSS2 VDDS PQI_D16 VSS PQI_D17 PQI_D18 PQI_D19 PQI_D20 PQI_D21 PQI_D22 VDDC PQI_D23 VDDS2 VDDS PQI_D24 VSS PQI_D25 PQI_D26 PQI_D27 PQI_D28 PQI_D29 PQI_D30 PQI_D31 VSS2 RESERVED_NC VDDS AVS AVD VSS JTMS JTDI PLL_REF 7955 - Data Sheet, DS-0114-08 Hifn Confidential 49 Table 39 LQFP PQI Mode Pin List (Alphabetically) Pin Name Pin Name Pin Name Pin Name 140 139 8 10 7 5 9 3 143 2 142 4 144 20 21 22 24 25 26 28 29 33 36 37 38 39 41 42 43 60 61 62 63 65 67 68 AVD AVS EEPROM_CS EEPROM_DI EEPROM_DO EEPROM_EN EEPROM_SK JTCK JTDI JTDO JTMS JTRST# PLL_REF PQI_A0 PQI_A1 PQI_A2 PQI_A3 PQI_A4 PQI_A5 PQI_A6 PQI_A7 PQI_A8 PQI_A9 PQI_A10 PQI_A11 PQI_A12 PQI_A13 PQI_A14 PQI_A15 PQI_A16 PQI_A17 PQI_A18 PQI_A19 PQI_A20 PQI_A21 PQI_A22 69 71 72 74 75 77 80 81 82 47 16 32 93 95 96 97 98 99 100 103 105 106 107 108 109 110 111 112 115 117 118 119 120 121 122 124 PQI_A23 PQI_A24 PQI_A25 PQI_A26 PQI_A27 PQI_A28 PQI_A29 PQI_A30 PQI_A31 PQI_burst# PQI_CLK PQI_CS# PQI_D0 PQI_D1 PQI_D2 PQI_D3 PQI_D4 PQI_D5 PQI_D6 PQI_D7 PQI_D8 PQI_D9 PQI_D10 PQI_D11 PQI_D12 PQI_D13 PQI_D14 PQI_D15 PQI_D16 PQI_D17 PQI_D18 PQI_D19 PQI_D20 PQI_D21 PQI_D22 PQI_D23 127 129 130 131 132 133 134 135 13 14 89 52 56 17 45 31 19 46 85 86 87 59 70 48 49 50 57 83 84 91 137 1 12 18 35 58 PQI_D24 PQI_D25 PQI_D26 PQI_D27 PQI_D28 PQI_D29 PQI_D30 PQI_D31 PQI_INT# PQI_RST# PQI_rw# PQI_TA# PQI_tea# PQI_Ts# PQI_tsiz0 PQI_tsiz1 RESERVED_NC RESERVED_VDD RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_NC TEST_EN VDDC VDDC VDDC VDDC 92 123 15 27 40 51 66 78 104 114 126 138 90 6 30 55 79 101 125 23 44 53 64 76 88 102 116 128 141 11 34 54 73 94 113 136 VDDC VDDC VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS12 VDDS2 VDDS2 VDDS2 VDDS2 VDDS2 VDDS2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 7955 - Data Sheet, DS-0114-08 Hifn Confidential 50 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PQI_D11 PQI_D10 PQI_D9 PQI_D8 VDDS PQI_D7 VSS VDDS2 PQI_D6 PQI_D5 PQI_D4 PQI_D3 PQI_D2 PQI_D1 VSS2 PQI_D0 VDDC RESERVED_VSS VDDS12 PQI_RW# VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS PQI_A31 PQI_A30 PQI_A29 VDDS2 VDDS PQI_A28 VSS PQI_A27 PQI_A26 VSS2 10.4 LQFP PQI Mode Pinout 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PQI_A25 PQI_A24 RESERVED_VSS PQI_A23 PQI_A22 PQI_A21 VDDS PQI_A20 VSS PQI_A19 PQI_A18 PQI_A17 PQI_A16 RESERVED_VSS VDDC RESERVED_VSS PQI_TEA# VDDS2 VSS2 VSS PQI_TA# VDDS RESERVED_VSS RESERVED_VSS RESERVED_VSS PQI_BURST# RESERVED_VDD PQI_TSIZ0 VSS PQI_A15 PQI_A14 PQI_A13 VDDS PQI_A12 PQI_A11 PQI_A10 TEST_EN JTDO JTCK JTRST# EEPROM_EN VDDS2 EEPROM_DO EEPROM_CS EEPROM_SK EEPROM_DI VSS2 VDDC PQI_INT# PQI_RST# VDDS PQI_CLK PQI_TS# VDDC RESERVED_NC PQI_A0 PQI_A1 PQI_A2 VSS PQI_A3 PQI_A4 PQI_A5 VDDS PQI_A6 PQI_A7 VDDS2 PQI_TSIZ1 PQI_CS# PQI_A8 VSS2 VDDC PQI_A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PQI_D12 PQI_D13 PQI_D14 PQI_D15 VSS2 VDDS PQI_D16 VSS PQI_D17 PQI_D18 PQI_D19 PQI_D20 PQI_D21 PQI_D22 VDDC PQI_D23 VDDS2 VDDS PQI_D24 VSS PQI_D25 PQI_D26 PQI_D27 PQI_D28 PQI_D29 PQI_D30 PQI_D31 VSS2 RESERVED_NC VDDS AVS AVD VSS JTMS JTDI PLL_REF Figure 14 LQFP PQI Mode Pinout Drawing 7955 - Data Sheet, DS-0114-08 Hifn Confidential 51 10.5 LQFP PQII Mode Pin List Table 40 LQFP PQII Mode Pin List (Numerically) Pin Name Pin Name Pin Name Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 TEST_EN JTDO JTCK JTRST# EEPROM_EN VDDS2 EEPROM_DO EEPROM_CS EEPROM_SK EEPROM_DI VSS2 VDDC PQII_INT# PQII_RST# VDDS PQII_CLK PQII_TS# VDDC RESERVED_NC PQII_A0 PQII_A1 PQII_A2 VSS PQII_A3 PQII_A4 PQII_A5 VDDS PQII_A6 PQII_A7 VDDS2 PQII_TSIZ3 PQII_CS# PQII_A8 VSS2 VDDC PQII_A9 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PQII_A10 PQII_A11 PQII_A12 VDDS PQII_A13 PQII_A14 PQII_A15 VSS PQII_TSIZ2 RESERVED_VDD PQII_TBST# PQII_DBB# RESERVED_VSS RESERVED_VSS VDDS PQII_TA# VSS VSS2 VDDS2 PQII_TEA# RESERVED_VSS VDDC PQII_TSIZ1 PQII_A16 PQII_A17 PQII_A18 PQII_A19 VSS PQII_A20 VDDS PQII_A21 PQII_A22 PQII_A23 PQII_TSIZ0 PQII_A24 PQII_A25 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 VSS2 PQII_A26 PQII_A27 VSS PQII_A28 VDDS VDDS2 PQII_A29 PQII_A30 PQII_A31 PQII_PSDVAL# PQII_AACK# PQII_TT4 PQII_TT3 PQII_TT2 VSS PQII_TT1 VDDS12 PQII_TT0 VDDC PQII_D0 VSS2 PQII_D1 PQII_D2 PQII_D3 PQII_D4 PQII_D5 PQII_D6 VDDS2 VSS PQII_D7 VDDS PQII_D8 PQII_D9 PQII_D10 PQII_D11 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PQII_D12 PQII_D13 PQII_D14 PQII_D15 VSS2 VDDS PQII_D16 VSS PQII_D17 PQII_D18 PQII_D19 PQII_D20 PQII_D21 PQII_D22 VDDC PQII_D23 VDDS2 VDDS PQII_D24 VSS PQII_D25 PQII_D26 PQII_D27 PQII_D28 PQII_D29 PQII_D30 PQII_D31 VSS2 RESERVED_NC VDDS AVS AVD VSS JTMS JTDI PLL_REF 7955 - Data Sheet, DS-0114-08 Hifn Confidential 52 Table 41 LQFP PQII Mode Pin List (Alphabetically) Pin Name Pin Name Pin Name Pin Name 140 139 8 10 7 5 9 3 143 2 142 4 144 20 21 22 24 25 26 28 29 33 36 37 38 39 41 42 43 60 61 62 63 65 67 68 AVD AVS EEPROM_CS EEPROM_DI EEPROM_DO EEPROM_EN EEPROM_SK JTCK JTDI JTDO JTMS JTRST# PLL_REF PQII_A0 PQII_A1 PQII_A2 PQII_A3 PQII_A4 PQII_A5 PQII_A6 PQII_A7 PQII_A8 PQII_A9 PQII_A10 PQII_A11 PQII_A12 PQII_A13 PQII_A14 PQII_A15 PQII_A16 PQII_A17 PQII_A18 PQII_A19 PQII_A20 PQII_A21 PQII_A22 69 71 72 74 75 77 80 81 82 84 16 32 93 95 96 97 98 99 100 103 105 106 107 108 109 110 111 112 115 117 118 119 120 121 122 124 PQII_A23 PQII_A24 PQII_A25 PQII_A26 PQII_A27 PQII_A28 PQII_A29 PQII_A30 PQII_A31 PQII_AACK# PQII_CLK PQII_CS# PQII_D0 PQII_D1 PQII_D2 PQII_D3 PQII_D4 PQII_D5 PQII_D6 PQII_D7 PQII_D8 PQII_D9 PQII_D10 PQII_D11 PQII_D12 PQII_D13 PQII_D14 PQII_D15 PQII_D16 PQII_D17 PQII_D18 PQII_D19 PQII_D20 PQII_D21 PQII_D22 PQII_D23 127 129 130 131 132 133 134 135 48 13 83 14 52 47 56 17 70 59 45 31 91 89 87 86 85 19 46 49 50 57 137 1 12 18 35 58 PQII_D24 PQII_D25 PQII_D26 PQII_D27 PQII_D28 PQII_D29 PQII_D30 PQII_D31 PQII_DBB# PQII_INT# PQII_PSDVAL# PQII_RST# PQII_TA# PQII_TBST# PQII_TEA# PQII_TS# PQII_TSIZ0 PQII_TSIZ1 PQII_TSIZ2 PQII_TSIZ3 PQII_TT0 PQII_TT1 PQII_TT2 PQII_TT3 PQII_TT4 RESERVED_NC RESERVED_VDD RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_NC TEST_EN VDDC VDDC VDDC VDDC 92 123 15 27 40 51 66 78 104 114 126 138 90 6 30 55 79 101 125 23 44 53 64 76 88 102 116 128 141 11 34 54 73 94 113 136 VDDC VDDC VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS12 VDDS2 VDDS2 VDDS2 VDDS2 VDDS2 VDDS2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 7955 - Data Sheet, DS-0114-08 Hifn Confidential 53 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PQII_D11 PQII_D10 PQII_D9 PQII_D8 VDDS PQII_D7 VSS VDDS2 PQII_D6 PQII_D5 PQII_D4 PQII_D3 PQII_D2 PQII_D1 VSS2 PQII_D0 VDDC PQII_TT0 VDDS12 PQII_TT1 VSS PQII_TT2 PQII_TT3 PQII_TT4 PQII_AACK# PQII_PSDVAL# PQII_A31 PQII_A30 PQII_A29 VDDS2 VDDS PQII_A28 VSS PQII_A27 PQII_A26 VSS2 10.6 LQFP PQII Mode Pinout 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PQII_A25 PQII_A24 PQII_TSIZ0 PQII_A23 PQII_A22 PQII_A21 VDDS PQII_A20 VSS PQII_A19 PQII_A18 PQII_A17 PQII_A16 PQII_TSIZ1 VDDC RESERVED_VSS PQI_TEA# VDDS2 VSS2 VSS PQII_TA# VDDS RESERVED_VSS RESERVED_VSS PQII_DBB# PQII_TBST# RESERVED_VDD PQII_TSIZ2 VSS PQII_A15 PQII_A14 PQII_A13 VDDS PQII_A12 PQII_A11 PQII_A10 TEST_EN JTDO JTCK JTRST# EEPROM_EN VDDS2 EEPROM_DO EEPROM_CS EEPROM_SK EEPROM_DI VSS2 VDDC PQII_INT# PQII_RST# VDDS PQII_CLK PQII_TS# VDDC RESERVED_NC PQII_A0 PQII_A1 PQII_A2 VSS PQII_A3 PQII_A4 PQII_A5 VDDS PQII_A6 PQII_A7 VDDS2 PQII_TSIZ3 PQII_CS# PQII_A8 VSS2 VDDC PQII_A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PQII_D12 PQII_D13 PQII_D14 PQII_D15 VSS2 VDDS PQII_D16 VSS PQII_D17 PQII_D18 PQII_D19 PQII_D20 PQII_D21 PQII_D22 VDDC PQII_D23 VDDS2 VDDS PQII_D24 VSS PQII_D25 PQII_D26 PQII_D27 PQII_D28 PQII_D29 PQII_D30 PQII_D31 VSS2 RESERVED_NC VDDS AVS AVD VSS JTMS JTDI PLL_REF Figure 15 LQFP PQII Mode Pinout Drawing 7955 - Data Sheet, DS-0114-08 Hifn Confidential 54 11 Physical Specifications 11.1 LQFP 144-pin Plastic Quad Flatpack 22.00.2 M 0~10 0.145 +0.055 -0.04 5 0.08 1.7 MAX 0.08 +0.05 -0.04 1.40.05 0.5 0.10.05 0.22 1.25 TYP 22.00.2 20.00.1 20.00.1 0.45min, 0.75max All units in millimeters Figure 16 144 LQFP Package 7955 - Data Sheet, DS-0114-08 Hifn Confidential 55 Document Changes/Revisions Documentation Changes include additions, deletions, and modifications made to this document. This section identifies the changes made in each release of the document. Document Revision 01 Update 1. Added PCI Mode and PQI Mode Pinout drawings. Section 10. Document Revision 02 Update 1. Added MPC8260 PowerQuicc II Mode throughout document. Corrected PCI Register Configuration without EEPROM Device ID from to 0x0020 to 0x001D. Section 5.2.2, Table 10, page 16. Update 2. Added PowerQuicc II timing diagrams to new section 7.5. Section 7.5, Table 27 and Figure 10, pages 34-35. Update 3. Added access type to transfer size description. Section 6.2.2, Table 15, page 25. Section 6.2.3, Table 16, page 26. Update 4. Added definition of transfer type for PowerQuicc II access. Section 6.2.2, Table 15, page 25. Update 5. Clearly stated that PLL bypass mode is not supported. Section 6.2.5, page 28. Document Revision 03 Update 1. Removed 33 MHz and 66 MHz speeds on PCI timing specifications. Section 7.3, Table 27. Update 2. Added EEPROM chip select methods for PowerQuiccI and PowerQuicc II. Section 5.2.1, Table 8 (new). Update 3. Added bus transaction restrictions for PowerQuiccI and PowerQuicc II. Sections 6.2.2 and 6.2.3. Update 4. Added PQII_TBST#, PQII_CS# signals to the timing diagrams and timing specifications for PowerQuicc II. Section 7.5, Table 29, Figure 10. 7955 - Data Sheet, DS-0114-08 Hifn Confidential 56 Update 5. Changed transfer size access types allowed for the bus transactions in PowerQuiccI and PowerQuicc II. Section 6.2.2, Table 16 and Section 6.2.3, Table 17. Update 6. Modified the timing parameters for PowerQuiccI and PowerQuicc II read and write bus transactions and the timing diagrams accordingly. Section 7.5, Table 29 and Figure 10. Section 7.4, Table 28 and Figure 9. Update 7. Changed all references to "Context" memory to "Local" memory. Section 4.1, Table 6, Figure 2 Document Revision 04 Update 1. Changed Device ID default value to 0x0020. Section 5.2.2, Table 11 Document Revision 05 Update 1. Updated PCI Configuration space table. Section 5.2.2, Table 11 Update 2. Changed text for EEPROM_EN signal. EEPROM configuration is selected when the EEPROM_EN input is high. Section 6.2.4, Table 18 Update 3. Corrected RESERVED_VSS input connection to high instead of VSS. Section 6.2.6, Table 21 Update 4. Removed power down sequence deassertion delay to the Absolute maximum ratings. Section 8.1, Table 31 Update 5. Added power down sequence deassertion delay to the Recommended Operating conditions and added new Figure 12, Power Sequence Specifications. Section 8.3, Table 32 and Figure 12 Update 6. Corrected EEPROM address 0x0B reset value to 0x01. Section 5.2.1, Table 7. Document Revision 06 Update 1. Updated template. All sections. Update 2. Updated power dissipation in section 9 Thermal Specifications, Table 34. Document Revision 07 Update 1. Internal change. 7955 - Data Sheet, DS-0114-08 Hifn Confidential 57 Document Revision 08 Update 1. Internal change. 7955 - Data Sheet, DS-0114-08 Hifn Confidential 58 750 University Avenue Los Gatos, California 95032 tel: 408.399.3500 fax: 408.399.3501 www.hifn.com Hifn Confidential