Features
• Function compatible with HCPL-4504
• Surface mountable
• Very small, low prole JEDEC registered package
outline
• Compatible with infrared vapor phase reow and
wave soldering processes
• Short propagation delays for TTL and IPM
applications
• Very high common mode transient immunity:
Guaranteed 15 kV/µs at VCM = 1500 V
• High CTR: >25% at 25°C
• Guaranteed specications for common IPM
applications
• TTL compatible
• Guaranteed ac and dc performance over
temperature: 0°C to 70°C
• Open collector output
• Safety approval:
UL Recognized 3750 Vac / 1 min. per UL 1577
IEC/EN/DIN EN 60747-5-2
Approved VIORM = 560 Vpeak for Option 060.
CSA Approved
• Lead free option “-000E”
Applications
• Inverter Circuits and Intelligent Power Module
(IPM) Interfacing: Shorter propagation delays and
guaranteed (tPLH - tPHL) specications. (See power
inverter dead time section)
• High speed logic ground isolation: TTL/TTL, TTL/LTTL,
TTL/CMOS, TTL/LSTTL
• Line Receivers: High common mode transient
immunity (>15 kV/µs for a TTL load/drive) and low
input-output capacitance (0.6 pF)
• Replace pulse transformers: ave board space and
weight
• Analog signal ground isolation: Integrated
photon detector provides improved linearity over
phototransistors
CAUTION: The small junction sizes inherent to the design of this bipolar component increase the component's susceptibility to
damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.
HCPL-M454
Ultra High CMR, Small Outline, 5 Lead, High Speed Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
The HCPL-M454 is similar to Avago’s other high speed
transistor output optocouplers, but with shorter propa-
gation delays and higher CTR. The HCPL-M454 also has
a guaranteed propagation delay dierence (tPLH - tPHL).
These features make the HCPL-M454 an excellent solu-
tion to IPM inverter dead time and other switching prob-
lems.
The HCPL-M454 CTR, propagation delays, and CMR are
specied both for TTL load and drive conditions and for
IPM (Intelligent Power Module) load and drive condi-
tions. Specications and typical performance plots for
both TTL and IPM conditions are provided for ease of ap-
plication.
This diode-transistor optocoupler uses an insulating lay-
er between the light emitting diode and an integrated
photon detector to provide electrical insulation between
input and output. Separate connections for the photo-
diode bias and output transistor collector increase the
speed up to a hundred times over that of a conventional
MXXX
XXX
6
5
43
1
7.0 ± 0.2
(0.276 ± 0.008)
2.5 ± 0.1
(0.098 ± 0.004)
0.102 ± 0.102
(0.004 ± 0.004)
V
CC
V
OUT
GNDCATHODE
ANODE
4.4 ± 0.1
(0.173 ± 0.004)
1.27
(0.050)
BSC
0.15 ± 0.025
(0.006 ± 0.001)
0.71
(0.028)MIN.
0.4 ± 0.05
(0.016 ± 0.002)
3.6 ± 0.1*
(0.142 ± 0.004)
TYPE NUMBER (LAST 3 DIGITS)
DATE CODE
MAX. LEAD COPLANARITY
= 0.102 (0.004)
DIMENSIONS IN MILLIMETERS (INCHES)
* MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006)
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
7° MAX.
Outline Drawing (JEDEC MO-155)
Ordering Information
HCPL-M454 is UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part RoHS non RoHS Surface Tape IEC/EN/DIN
Number Compliant Compliant Package Mount & Reel EN 60747-5-2 Quantity
-000E no option X 100 per tube
HCPL-M454 -500E #500 SO-5 X X 1500 per reel
-060E -060 X X 100 per tube
-560E -560 X X X 1500 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-M454-560E to order product of SO-5 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-2 Safety Approval and RoHS compliant.
Example 2:
HCPL-M454 to order product of SO-5 Surface Mount package inTube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15, 2001 and
RoHS compliant will use ‘–XXXE.’
Absolute Maximum Ratings
(No Derating Required up to 85°C)
Storage Temperature .............................................................................-55°C to +125°C
Operating Temperature ........................................................................-55°C to +100°C
Average Input Current - IF .................................................................................25 mA[1]
Peak Input Current - IF ........................................................................................50 mA[2]
(50% duty cycle, 1 ms pulse width)
Peak Transient Input Current - IF ............................................................................1.0 A
(≤1 µs pulse width, 300 pps)
Reverse Input Voltage - VR (Pin 3-1) .............................................................................5 V
Input Power Dissipation ......................................................................................45 mW[3]
Average Output Current - IO (Pin 5) .......................................................................8 mA
Peak Output Current .................................................................................................16 mA
Output Voltage - VO (Pin 5-4) .....................................................................-0.5 V to 20 V
Supply Voltage - V
CC (Pin 6-4) ....................................................................-0.5 V to 30 V
Output Power Dissipation ............................................................................... 100 mW[4]
Infrared and Vapor Phase Reow Temperature ....................................... see below
Solder Reow Thermal Prole
0
TIME (SECONDS)
TEMPERATURE (°C)
200
100
50 150100 200 250
300
0
30
SEC.
50 SEC.
30
SEC.
160°C
140°C
150°C
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
SOLDERING
TIME
200°C
PREHEATING TIME
150°C, 90 + 30 SEC.
2.5°C ± 0.5°C/SEC.
3°C + 1°C/–0.5°C
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
Note: Non-halide ux should be used.
Insulation Related Specications
Parameter Symbol Value Units Conditions
Minimum External Air Gap L(IO1) ≥ 5 mm Measured from input terminals
(Clearance) to output terminals
Minimum External Tracking Path L(IO2) ≥ 5 mm Measured from input terminals
(Creepage) to output terminals
Minimum Internal Plastic Gap 0.08 mm Through insulation distance
(Clearance) conductor to conductor
Tracking Resistance CTI 175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group (per DIN VDE 0109) IIIa Material Group DIN VDE 0109
Schematic Land Pattern Recommendation
HCPL-M454 Schematic
I
F
SHIELD
6
5
4
GND
V
CC
1
3
V
O
I
CC
V
F
I
O
ANODE
CATHODE
+
–
Recommended Pb-Free IR Prole
8.27
(0.325)
2.0
(0.080)
2.5
(0.10)
1.3
(0.05)
0.64
(0.025)
4.4
(0.17)
DIMENSION IN MILLIMETERS (INCHES)
217 °C
RAMP-DOWN
6 °C/SEC. MAX.
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
260 +0/-5 °C
t 25 °C to PEAK
60 to 150 SEC.
20-40 SEC.
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
t
p
t
s
PREHEAT
60 to 180 SEC.
t
L
T
L
T
smax
T
smin
25
T
p
TIME
TEMPERATURE
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
T
smax
= 200 °C, T
smin
= 150 °C
Note: Non-halide ux should be used.
DC Electrical Specications
Over recommended temperature (T
A = 0°C to 70°C) unless otherwise specied. (See note 11)
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Current CTR 25 32 60 % T
A = 25°C VO = 0.4 V IF = 16 mA 1,2,4 5
Transfer
Ratio 21 34 VO = 0.5 V VCC = 4.5 V
Current CTR 26 35 65 % T
A = 25°C VO = 0.4 V IF = 12 mA 1,2,4 5
Transfer
Ratio 22 37 VO = 0.5 V VCC = 4.5 V
Logic Low VOL 0.2 0.4 V T
A = 25°C IO = 3.0 mA IF = 16 mA
Output
Voltage 0.2 0.5 IO = 2.4 mA VCC = 4.5 V
Logic High IOH 0.003 0.5 µA T
A = 25°C VO = VCC = 5.5 V IF = 0 mA 5
Output
Current 0.01 1.0 TA = 25°C VO = VCC = 15 V
50
Logic Low ICCL 50 200 µA IF = 16 mA VCC = 15 V VO = open 11
Supply
Current
Logic High ICCH 0.02 1 µA T
A = 25°C IF = 0 mA VCC = 15 V 11
Supply VO = open
Current 0.02 2
Input V
F 1.5 1.7 V T
A = 25°C IF = 16 mA 3
Forward
Voltage 1.5 1.8
Input BVR 5 V IR = 10 µA
Reverse
Breakdown
Current
Tempera- ∆VF/∆T
A -1.6 mV/°C IF = 16 mA
ture Co-
ecient of
Forward
Voltage
Input CIN 60 pF f = 1 MHz VF = 0 V
Capacitance
Input- VISO 3750 V
RMS RH < 50% t = 1 min 6,12
Output T
A = 25°C
Insulation
Voltage
Resistance RI-O 10[12] Ω VI-O = 500 Vdc 6
(Input-
Output)
Capacitance CI-O 0.6 pF f = 1 MHz 6
(Input-
Output)
Switching Specications
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specied
Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note
Propagation tPHL 0.2 0.3 µs TA = 25°C Pulse: f = 20 kHz 8, 9 9
Delay Time Duty Cycle = 10%
to Logic 0.2 0.5 IF = 16 mA VCC = 5.0 V
Low at RL = 1.9 kΩ CL = 15 pF
Output VTHHL = 1.5 V
0.2 0.5 0.7 TA = 25°C Pulse: f = 10 kHz 10- 10
Duty Cycle = 50% 14
0.1 0.5 1.0 IF = 12 mA VCC = 15.0 V
RL = 20 kΩ CL = 100 pF
VTHHL = 1.5 V
Propagation tPLH 0.3 0.5 µs TA = 25°C Pulse: f = 20 kHz 8, 9 9
Delay Time Duty Cycle = 10%
to Logic 0.3 0.7 IF = 16 mA VCC = 5.0 V
High at RL = 1.9 kΩ CL = 15 pF
Output VTHLH = 1.5 V
0.3 0.8 1.1 TA = 25°C Pulse: f = 10 kHz 10- 10
Duty Cycle = 50% 14
0.2 0.8 1.4 IF = 12 mA VCC = 15.0 V
RL = 20 kΩ CL = 100 pF
VTHLH = 2.0 V
Propagation tPLH- -0.4 0.3 0.9 µs TA = 25°C Pulse: f = 10 kHz 10- 13
Delay tPHL Duty Cycle = 50% 14
Dierence -0.7 0.3 1.3 IF = 12 mA VCC = 15.0 V
Between RL = 20 kΩ CL = 100 pF
Any 2 Parts VTHHL = 1.5 V VTHLH = 2.0 V
Common |CMH| 15 30 kV/µs TA = 25°C VCC = 5.0 V RL = 1.9 kΩ 7 7,9
Mode CL = 15 pF IF = 0 mA
Transient VCM = 1500 VP-P
Immunity
at Logic 15 30 TA = 25°C VCC = 15.0 V RL = 20 kΩ 7 8,10
High Level CL = 100 pF IF = 0 mA
Output VCM = 1500 VP-P
Common |CML
| 15 30 kV/µs TA = 25°C VCC = 5.0 V RL = 1.9 kΩ 7 7,9
Mode CL = 15 pF IF = 16 mA
Transient VCM = 1500 VP-P
Immunity
at Logic 10 30 TA = 25°C VCC = 15.0 V RL = 20 kΩ 7 8,10
Low Level CL = 100 pF IF = 12 mA
Output VCM = 1500 VP-P
15 30 TA = 25°C VCC = 15.0 V RL = 20 kΩ 7 8,10
CL = 100 pF IF = 16 mA
VCM = 1500 VP-P
Figure 4. Current Transfer Ratio vs. Temperature. Figure 5. Logic High Output Current vs. Temperature.
Figure 1. DC and Pulsed Transfer Characteristics. Figure 2. Current Transfer Ratio vs. Input Current. Figure 3. Input Current vs. Forward Voltage.
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C.
2. Derate linearly above 70°C free-air temperature at a rate of 1.6mA/°C.
3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mA/°C.
4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mA/°C.
5. CURRENT TRANSFER RATIO in percent is dened as the ratio of output collector current (IO), to the forward LED input current (IF), times 100.
6. Device considered a two-terminal device: Pins 1 and 3 shorted together and Pins 4, 5 and 6 shorted together.
7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dVCM/dt on
the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 2.0 V). Common mode
transient immunity in a Logic Low level is the maximum tolerable (negative) dVCM/dt on the trailing edge of the common mode pulse signal,
VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V).
8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is the maxi-
mum tolerable dVCM/dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e.,
VO > 3.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt on the trailing edge of the common
mode pulse signal,VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 1.0 V).
9. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 kΩ pull-up resistor.
10. The RL = 20 kΩ, CL = 100 pF load represents an IPM (Intelligent Power Mode) load.
11. Use of a 0.1 µF bypass capacitor connected between pins 4 and 6 is recommended.
12. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 VRMS for 1 second (leakage detec-
tion current limit, Ii-e ≤ 5 µA).
13. The dierence between tPLH and tPHL, between any two HCPL-M454 parts under the same test condition. (See Power Inverter Dead Time and
Propagation Delay Specications section).
HCPL-M454 fig 1
010 20
VO – OUTPUT VOLTAGE – V
IO – OUTPUT CURRENT – mA
10
5
0
T = 25°C
V = 5.0 V
A
CC
40 mA
35 mA
30 mA
25 mA
20 mA
15 mA
10 mA
I = 5 mA
F
IF – INPUT CURRENT – mA
NORMALIZED CURRENT TRANSFER RATIO
1.5
1.0
0.5
0.0 2 4 6 8 10 12 14 16 18
0
HCPL-M454 fig 2
20 22 24 26
IF = 16 mA
VO = 0.4 V
VCC = 5.0 V
TA = 25°C
NORMALIZED
T
A
– TEMPERATURE – °C
NORMALIZED CURRENT TRANSFER RATIO
1.0
0.8
0.6
HCPL-M454 fig 4
1.1
0.7
0.9
-40 -20 020 40 60 80 100 120-60
I
F
= 16 mA
V
O
= 0.4 V
V
CC
= 5.0 V
T
A
= 25°C
NORMALIZED
T
A
– TEMPERATURE – °C
I
OH
– LOGIC HIGH OUTPUT CURRENT – nA
HCPL-M454 fig 5
10 4
10 3
10 2
10 1
10 0
10-1
10-2
-40 -20 0 20 40 60 80 100 120
-60
I
F
= 0 mA
V
O
= V
CC
= 5.0 V
Figure 6. Switching Test Circuit.
Figure 7. Test Circuit for Transient Immunity and Typical Waveforms.
Figure 8. Propagation Delay Time vs. Temperature. Figure 9. Propagation Delay Time vs. Load Resistance. Figure 10. Propagation Delay Time vs. Load Resis-
tance.
HCPL-M454 fig 6
V
O
PULSE
GEN.
Z
O
= 50 Ω
t
r
= 5 ns
I
F
MONITOR
I
F
0.1µF
R
L
C
L
R
M
0
t
PHL
t
PLH
V
O
I
F
V
OL
V
THHL
V
THLH
V
CC
1
3
6
5
4
HCPL-M454
V
CC
HCPL-M454 Figure 7
V
O
0.1µF
R
L
A
B
PULSE GEN.
V
CM
+
V
FF
C
L
V
CC
–
1
3
6
5
4
HCPL-M454
V
O
V
OL
V
O
0 V 10%
90% 90%
10%
SWITCH AT A: I = 0 mA
F
SWITCH AT B: I = 12 mA, 16 mA
F
V
CM
t
r
t
f
V
CC
10 V I
F
TA – TEMPERATURE – °C
tp – PROPAGATION DELAY – µs
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10 -40 -20 0 20 40 60 80 100 120
-60
HCPL-M454 fig 8
VCC = 5.0 V
RL
= 1.9 kΩ
CL
= 15 pF
VTHHL tPLH
tPHL
IF = 10 mA
IF = 16 mA
= VTHLH = 1.5 V
10% DUTY CYCLE
R
L
– LOAD RESISTANCE – kΩ
t
p
– PROPAGATION DELAY – µs
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0 2 4 6 8 10 12 14 16 18
0
HCPL-M454 fig 9
20
t
PHL
V
CC
= 5.0 V
T
A
= 25° C
C
L
= 15 pF
V = V = 1.5 V
I
F
= 10 mA
I
F
= 16 mA
t
PLH
10% DUTY CYCLE
THHL THLH
R
L
– LOAD RESISTANCE – kΩ
t
p
– PROPAGATION DELAY – µs
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0 2 4 6 8 10 12 14 16 180
HCPL-M454 fig 10
20
1.6
1.8
2.0
2.2
2.4
2.6 V
CC
= 5.0 V
T
A
= 25° C
C
L
= 100 pF
V
THHL
= 1.5 V
V
THLH
= 2.0 V
I
F
= 10 mA
I
F
= 16 mA
t
PLH
t
PHL
50% DUTY CYCLE
Figure 11. Propagation Delay Time vs. Temperature. Figure 12. Propagation Delay Time vs. Load Resis-
tance.
Figure 13. Propagation Delay Time vs. Load Capaci-
tance.
Figure 14. Propagation Delay Time vs. Supply Voltage.
T
A
– TEMPERATURE – °C
t
p
– PROPAGATION DELAY – µs
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3 -40 -20 0 20 40 60 80 100 120
-60
HCPL-M454 fig 11
V
CC
= 15.0 V
R
L
= 20 kΩ
C
L
= 100 pF
V
THHL
= 1.5 V
V
THLH
= 2.0 V t
PLH
t
PHL
I
F
= 10 mA
I
F
= 16 mA
50% DUTY CYCLE
R
L
– LOAD RESISTANCE – kΩ
t
p
– PROPAGATION DELAY – µs
1.6
1.4
1.2
1.0
0.6
0.2
0.0 5 10 15 20 25 30 35 40 450
HCPL-M454 fig 12
V
CC
= 15.0 V
T
A
= 25° C
C
L
= 100 pF
V
THHL
= 1.5 V
V
THLH
= 2.0 V
50
t
PLH
t
PHL
1.8
0.4
0.8
I
F
= 10 mA
I
F
= 16 mA
50% DUTY CYCLE
VCC – SUPPLY VOLTAGE – V
tp – PROPAGATION DELAY – µs
0.9
0.8
0.6
0.2 11 12 13 14 15 16 17 18 1910
HCPL-M454 fig 14
20
1.0
1.1
1.2
0.7
TA
= 25° C
RL
= 20 kΩ
CL
= 100 pF
V
V
0.5
0.4
0.3
tPLH
tPHL
IF = 10 mA
IF = 16 mA
50% DUTY CYCLE
THHL = 1.5 V
= 2.0 V
THLH
Figure 15. Typical Power Inverter.
Figure 16. LED Delay and Dead Time Diagram.
BASE/GATE
DRIVE CIRCUIT
HCPL-M454
1
3
6
5
4
+HV
Q1
LED 1
OUT 1
BASE/GATE
DRIVE CIRCUIT
1
3
6
5
4
–HV
Q2
LED 2
OUT 2
HCPL-M454 fig 15
+
+
HCPL-M454
t
PHL MIN.
(t
PHL
MAX.
– t
PHL
MIN.
)
t
PHL MAX.
MAXIMUM DEAD TIME
TURN ON DELAY
(t
PLH
MAX.
– t
PLH
MIN.
)
t
PLH MIN.
t
PLH MAX.
(t
PLH
MAX.
– t
PLH
MIN.
)
LED 1
OUT 1
LED 2
OUT 2
HCPL-M454 fig 16
Power Inverter Dead Time and Propagation Delay Specica-
tions
The HCPL-M454 includes a specication intended to help
designers minimize “dead time” in their power inverter
designs. The new “propagation delay dierence” speci-
cation (tPLH - tPHL) is useful for determining not only how
much optocoupler switching delay is needed to prevent
“shoot-through” current, but also for determining the
best achievable wort-case dead time for a given design.
When inverter power transistors switch (Q1 and Q2 in
Figure 15), it is essential that they never conduct at the
same time. Extremely large currents will ow if there is
any overlap in their conduction during switching transi-
tions, potentially damaging the transistor and even the
surrounding circuitry. This “shoot-through” current is
eliminated by delaying the turn-on of one transistor (Q2)
long enough to ensure that the opposing transistor (Q1)
has completely turned o. This delay introduces a small
amount of “dead time” at the output of the inverter dur-
ing which both transistors are o during switching tran-
sitions. Minimizing this dead time is an important design
goal for an inverter designer.
The amount of turn-on delay needed depends on the
propagation delay characteristics of the optocoupler,
as well as the characteristics of the transistor base/gate
drive circuit. Considering only the delay characteristics
of the optocoupler (the characteristics of the base/gate
drive circuit can be analyzed in the same way), it is im-
portant to know the minimum and maximum turn-on
(tPHL) and turn-o (tPLH) propagation delay specica-
tions, preferably over the desired operating temperature
range. The importance of these specications is illustrat-
ed in Figure 16. The waveforms labeled “LED1”, “LED2”,
“OUT1”, and “OUT2” are the input and output voltages
of the optocoupler circuits driving Q1 and Q2 respec-
tively. Most inverters are designed such that the power
transistor turns on when the optocoupler LED turns on;
this ensures that both power transistors will be o in the
event of a power loss in the control circuit. Inverters can
also be designed such that the power transistor turns o
when the optocoupler LED turns on; this type of design,
however, requires additional fail-safe circuitry to turn o
the power transistor if an over-current condition is de-
tected. The timing illustrated in Figure 16 assumes that
the power transistor turns on when the optocoupler LED
turns on.
The LED signal to turn on Q2 should be delayed enough
so that an optocoupler with the very fastest turn-on
propagation delay (tPHLmin) will never turn on before
an optocoupler with the very slowest turn-o propaga-
tion delay (tPLHmax) turns o. To ensure this, the turn-on
of the optocoupler should be delayed by an amount no
less than (tPLHmax - tPHLmin), which also happens to be the
maximum data sheet value for the propagation delay dif-
ference specication, (tPLH - tPHL). The HCPL-M454 speci-
es a maximum (tPLH - tPHL) of 1.3 µs over an operating
temperature range of 0-70°C.
Although (tPLH - tPHL)max tells the designer how much
delay is needed to prevent shoot-through current, it is
insucient to tell the designer how much dead time a
design will have. Assuming that the optocoupler turn-
on delay is exactly equal to (tPLH - tPHL)max, the minimum
dead time is zero (i.e., there is zero time between the
turn-o of the very slowest optocoupler and the turn-on
of the very fastest optocoupler).
Calculating the maximum dead time is slightly more
complicated. Assuming that the LED turn-on delay is still
exactly equal to (tPLH - tPHL)max, it can be seen in Figure 16
that the maximum dead time is the sum of the maximum
dierence in turn-on delay plus the maximum dierence
in turn-o delay,
[(tPLHmax-tPLHmin) + (tPHLmax-tPHLmin)],
This expression can be rearranged to obtain
[(tPLHmax-tPHLmin) - (tPHLmin-tPHLmax)],
and further rearranged to obtain
[(tPLH-tPHL)max - (tPLH-tPHL)min],
which is the maximum minus the minimum data sheet
values of (tPLH - tPHL). The dierence between the maxi-
mum and minimum values depends directly on the to-
tal spread of propagation delays and sets the limit on
how good the worst-case dead time can be for a given
design. Therefore, optocouplers with tight propagation
delay specications (and not just shorter delays or lower
pulse-width distortion) can achieve short dead times in
power inverters. The HCPL-M454 species a minimum
(tPLH - tPHL) of -0.7 µs over an operating temeprature
range of 0-70°C, resulting in a maximum dead time of 2.0
µs when the LED turn-on delay is equal to (tPLH - tPHL)max,
or 1.3 µs.
It is important to maintain accurate LED turn-on delays
because delays shorter than (tPLH - tPHL)max may allow
shoot-through currents, while longer delays will increase
the worst-case dead time.
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Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0553EN
AV02-0967EN January 11, 2008