HCPL-M454 Ultra High CMR, Small Outline, 5 Lead, High Speed Optocoupler Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The HCPL-M454 is similar to Avago's other high speed transistor output optocouplers, but with shorter propagation delays and higher CTR. The HCPL-M454 also has a guaranteed propagation delay difference (tPLH - tPHL). These features make the HCPL-M454 an excellent solution to IPM inverter dead time and other switching problems. * Function compatible with HCPL-4504 The HCPL-M454 CTR, propagation delays, and CMR are specified both for TTL load and drive conditions and for IPM (Intelligent Power Module) load and drive conditions. Specifications and typical performance plots for both TTL and IPM conditions are provided for ease of application. This diode-transistor optocoupler uses an insulating layer between the light emitting diode and an integrated photon detector to provide electrical insulation between input and output. Separate connections for the photodiode bias and output transistor collector increase the speed up to a hundred times over that of a conventional Applications * Inverter Circuits and Intelligent Power Module (IPM) Interfacing: Shorter propagation delays and guaranteed (tPLH - tPHL) specifications. (See power inverter dead time section) * High speed logic ground isolation: TTL/TTL, TTL/LTTL, TTL/CMOS, TTL/LSTTL * Surface mountable * Very small, low profile JEDEC registered package outline * Compatible with infrared vapor phase reflow and wave soldering processes * Short propagation applications delays for TTL and IPM * Very high common mode transient immunity: Guaranteed 15 kV/s at VCM = 1500 V * High CTR: >25% at 25C * Guaranteed applications specifications for common IPM performance over * TTL compatible * Guaranteed ac and dc temperature: 0C to 70C * Open collector output * Safety approval: UL Recognized 3750 Vac / 1 min. per UL 1577 IEC/EN/DIN EN 60747-5-2 Approved VIORM = 560 Vpeak for Option 060. CSA Approved * Lead free option "-000E" * Line Receivers: High common mode transient immunity (>15 kV/s for a TTL load/drive) and low input-output capacitance (0.6 pF) * Replace pulse transformers: ave board space and weight * Analog signal ground isolation: Integrated photon detector provides improved linearity over phototransistors CAUTION: The small junction sizes inherent to the design of this bipolar component increase the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Outline Drawing (JEDEC MO-155) ANODE 1 MXXX XXX 4.4 0.1 (0.173 0.004) 6 7.0 0.2 (0.276 0.008) VCC 5 VOUT CATHODE 3 0.4 0.05 (0.016 0.002) 4 GND TYPE NUMBER (LAST 3 DIGITS) DATE CODE 3.6 0.1* (0.142 0.004) 0.102 0.102 (0.004 0.004) 2.5 0.1 (0.098 0.004) 0.15 0.025 (0.006 0.001) 7 MAX. 0.71 MIN. (0.028) 1.27 BSC (0.050) MAX. LEAD COPLANARITY = 0.102 (0.004) DIMENSIONS IN MILLIMETERS (INCHES) * MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006) NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX. Ordering Information HCPL-M454 is UL Recognized with 3750 Vrms for 1 minute per UL1577. Option Part RoHS non RoHS Number Compliant Compliant Package HCPL-M454 Surface Mount Tape & Reel IEC/EN/DIN EN 60747-5-2 Quantity -000E no option X 100 per tube -500E #500 X 1500 per reel -060E -060 X X 100 per tube -560E -560 X X 1500 per reel SO-5 X X To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-M454-560E to order product of SO-5 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval and RoHS compliant. Example 2: HCPL-M454 to order product of SO-5 Surface Mount package inTube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation `#XXX' is used for existing products, while (new) products launched since July 15, 2001 and RoHS compliant will use `-XXXE.' Absolute Maximum Ratings (No Derating Required up to 85C) Storage Temperature..............................................................................-55C to +125C Operating Temperature.........................................................................-55C to +100C Average Input Current - IF ..................................................................................25 mA[1] Peak Input Current - IF .........................................................................................50 mA[2] (50% duty cycle, 1 ms pulse width) Peak Transient Input Current - IF .............................................................................1.0 A (1 s pulse width, 300 pps) Reverse Input Voltage - VR (Pin 3-1)..............................................................................5 V Input Power Dissipation.......................................................................................45 mW[3] Average Output Current - IO (Pin 5)........................................................................ 8 mA Peak Output Current..................................................................................................16 mA Output Voltage - VO (Pin 5-4)......................................................................-0.5 V to 20 V Supply Voltage - VCC (Pin 6-4).....................................................................-0.5 V to 30 V Output Power Dissipation................................................................................ 100 mW [4] Infrared and Vapor Phase Reflow Temperature........................................ see below Solder Reflow Thermal Profile 300 TEMPERATURE (C) PREHEATING RATE 3C + 1C/-0.5C/SEC. REFLOW HEATING RATE 2.5C 0.5C/SEC. 200 PEAK TEMP. 245C PEAK TEMP. 240C 2.5C 0.5C/SEC. 30 SEC. 160C 150C 140C PEAK TEMP. 230C SOLDERING TIME 200C 30 SEC. 3C + 1C/-0.5C 100 PREHEATING TIME 150C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 0 50 100 150 TIME (SECONDS) Note: Non-halide flux should be used. 200 250 Recommended Pb-Free IR Profile tp 260 +0/-5 C Tp TEMPERATURE TL Tsmax TIME WITHIN 5 C of ACTUAL PEAK TEMPERATURE 20-40 SEC. 217 C RAMP-UP 3 C/SEC. MAX. 150 - 200 C RAMP-DOWN 6 C/SEC. MAX. Tsmin ts PREHEAT 60 to 180 SEC. 25 tL 60 to 150 SEC. t 25 C to PEAK TIME NOTES: THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 C, Tsmin = 150 C Note: Non-halide flux should be used. Schematic Land Pattern Recommendation ICC ANODE 4.4 (0.17) VCC IF + 1 VF CATHODE 6 IO - 5 1.3 (0.05) 2.5 (0.10) VO 3 SHIELD 4 2.0 (0.080) GND 0.64 (0.025) 8.27 (0.325) DIMENSION IN MILLIMETERS (INCHES) HCPL-M454 Schematic Insulation Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap L(IO1) 5 mm (Clearance) Measured from input terminals to output terminals Minimum External Tracking Path L(IO2) 5 mm (Creepage) Measured from input terminals to output terminals Minimum Internal Plastic Gap 0.08 mm (Clearance) Through insulation distance conductor to conductor Tracking Resistance DIN IEC 112/VDE 0303 Part 1 CTI Isolation Group (per DIN VDE 0109) 175 V IIIa Material Group DIN VDE 0109 DC Electrical Specifications Over recommended temperature (TA = 0C to 70C) unless otherwise specified. (See note 11) Parameter Symbol Current CTR Transfer Ratio Min. Typ. Max. 25 32 60 21 Units Test Conditions 1,2,4 5 1,2,4 5 IF = 16 mA 34 VO = 0.5 V VCC = 4.5 V 26 35 VO = 0.4 V IF = 12 mA 22 37 VO = 0.5 V VCC = 4.5 V 0.2 0.4 IO = 3.0 mA IF = 16 mA 0.2 0.5 IO = 2.4 mA VCC = 4.5 V 0.003 0.5 TA = 25C VO = VCC = 5.5 V IF = 0 mA 0.01 1.0 TA = 25C VO = VCC = 15 V IF = 16 mA VCC = 15 V VO = open 11 Logic High ICCH 0.02 1 A TA = 25C Supply Current 0.02 2 IF = 0 mA VO = open VCC = 15 V 11 Input VF Forward Voltage IF = 16 mA Logic Low VOL Output Voltage Logic High IOH Output Current Logic Low Supply Current Input Reverse Breakdown Current Tempera ture Co efficient of Forward Voltage Input Capacitance ICCL BVR 50 65 % V A TA = 25C Note VO = 0.4 V Current CTR Transfer Ratio % Fig. TA = 25C TA = 25C 5 50 200 1.5 1.7 1.5 1.8 5 A V TA = 25C V IR = 10 A VF/TA -1.6 mV/C IF = 16 mA CIN 60 pF f = 1 MHz InputVISO 3750 VRMS Output Insulation Voltage 3 VF = 0 V RH < 50% TA = 25C t = 1 min 6,12 Resistance (InputOutput) RI-O 10[12] VI-O = 500 Vdc 6 Capacitance (InputOutput) CI-O 0.6 pF f = 1 MHz 6 Switching Specifications Over recommended temperature (TA = 0C to 70C) unless otherwise specified Parameter Sym. Min. Typ. Max. Units Propagation tPHL 0.2 0.3 s TA = 25C Delay Time to Logic 0.2 0.5 Low at Output 0.2 0.5 0.7 TA = 25C 0.1 0.5 1.0 Propagation tPLH 0.3 0.5 s TA = 25C Delay Time to Logic 0.3 0.7 High at Output Test Conditions Fig. Note Pulse: f = 20 kHz 8, 9 Duty Cycle = 10% IF = 16 mA VCC = 5.0 V RL = 1.9 k CL = 15 pF V THHL = 1.5 V 9 Pulse: f = 10 kHz Duty Cycle = 50% IF = 12 mA RL = 20 k V THHL = 1.5 V 10 1014 VCC = 15.0 V CL = 100 pF Pulse: f = 20 kHz 8, 9 Duty Cycle = 10% IF = 16 mA VCC = 5.0 V RL = 1.9 k CL = 15 pF V THLH = 1.5 V 9 0.3 0.8 1.1 TA = 25C 0.2 0.8 1.4 Pulse: f = 10 kHz Duty Cycle = 50% IF = 12 mA RL = 20 k V THLH = 2.0 V 1014 VCC = 15.0 V CL = 100 pF 10 Propagation tPLH-0.4 0.3 0.9 s TA = 25C Delay tPHL Difference -0.7 0.3 1.3 Between Any 2 Parts Pulse: f = 10 kHz Duty Cycle = 50% IF = 12 mA RL = 20 k V THHL = 1.5 V 1014 VCC = 15.0 V CL = 100 pF V THLH = 2.0 V 13 Common |CMH| 15 30 kV/s TA = 25C Mode Transient Immunity at Logic 15 30 TA = 25C High Level Output VCC = 5.0 V CL = 15 pF VCM = 1500 VP-P RL = 1.9 k IF = 0 mA 7 7,9 VCC = 15.0 V CL = 100 pF VCM = 1500 VP-P RL = 20 k IF = 0 mA 7 8,10 Common |CML| 15 30 kV/s TA = 25C Mode Transient Immunity at Logic 10 30 TA = 25C Low Level Output VCC = 5.0 V CL = 15 pF VCM = 1500 VP-P RL = 1.9 k IF = 16 mA 7 7,9 VCC = 15.0 V CL = 100 pF VCM = 1500 VP-P RL = 20 k IF = 12 mA 7 8,10 15 30 TA = 25C VCC = 15.0 V CL = 100 pF VCM = 1500 VP-P RL = 20 k IF = 16 mA 7 8,10 35 mA 30 mA 25 mA 5 20 mA 15 mA 10 mA 0 IF = 5 mA 0 10 20 1.5 1000 1.0 NORMALIZED IF = 16 mA VO = 0.4 V VCC = 5.0 V TA = 25C 0.5 0.0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 IF - INPUT CURRENT - mA VO - OUTPUT VOLTAGE - V Figure 1. DC and Pulsed Transfer Characteristics. Figure 2. Current Transfer Ratio vs. Input Current. HCPL-M454 fig 2 0.9 0.8 0.7 NORMALIZED IF = 16 mA VO = 0.4 V VCC = 5.0 V TA = 25C 0.6 -60 -40 -20 0 20 40 60 80 100 120 TA - TEMPERATURE - C Figure 4. Current Transfer Ratio vs. Temperature. IOH - LOGIC HIGH OUTPUT CURRENT - nA NORMALIZED CURRENT TRANSFER RATIO 1.0 10 4 10 3 10 2 IF = 0 mA VO = VCC = 5.0 V 10 1 10 0 10 -1 10-2 -60 -40 -20 0 20 40 60 80 100 120 TA - TEMPERATURE - C Figure 5. Logic High Output Current vs. Temperature. HCPL-M454 fig 5 HCPL-M454 fig 4 100 IF TA = 25C + VF - 10 1.0 0.1 0.01 0.001 1.1 1.2 1.3 1.4 1.5 1.6 VF - FORWARD VOLTAGE - VOLTS Figure 3. Input Current vs. Forward Voltage. HCPL-M454 fig 3 HCPL-M454 fig 1 1.1 IF - FORWARD CURRENT - mA 40 mA TA = 25C 10 VCC = 5.0 V NORMALIZED CURRENT TRANSFER RATIO IO - OUTPUT CURRENT - mA Notes: 1. Derate linearly above 70C free-air temperature at a rate of 0.8 mA/C. 2. Derate linearly above 70C free-air temperature at a rate of 1.6mA/C. 3. Derate linearly above 70C free-air temperature at a rate of 0.9 mA/C. 4. Derate linearly above 70C free-air temperature at a rate of 2.0 mA/C. 5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (IO), to the forward LED input current (IF), times 100. 6. Device considered a two-terminal device: Pins 1 and 3 shorted together and Pins 4, 5 and 6 shorted together. 7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dVCM /dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 2.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable (negative) dVCM/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V). 8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable dVCM /dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 3.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt on the trailing edge of the common mode pulse signal,VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 1.0 V). 9. The 1.9 k load represents 1 TTL unit load of 1.6 mA and the 5.6 k pull-up resistor. 10. The RL = 20 k, CL = 100 pF load represents an IPM (Intelligent Power Mode) load. 11. Use of a 0.1 F bypass capacitor connected between pins 4 and 6 is recommended. 12. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 4500 VRMS for 1 second (leakage detection current limit, Ii-e 5 A). 13. The difference between tPLH and tPHL, between any two HCPL-M454 parts under the same test condition. (See Power Inverter Dead Time and Propagation Delay Specifications section). HCPL-M454 IF PULSE GEN. ZO = 50 tr = 5 ns 0 VCC VO VTHHL IF 1 RL 5 VO 0.1F VTHLH 3 IF MONITOR VOL tPHL VCC 6 4 CL RM tPLH Figure 6. Switching Test Circuit. HCPL-M454 fig 6 HCPL-M454 10 V VCM 90% IF 90% 10% 0V 10% tr RL B 5 VCC SWITCH AT B: IF = 12 mA, 16 mA VO 0.1F 3 SWITCH AT A: IF = 0 mA VO VCC 6 A tf VO 1 4 VFF CL VOL + VCM - PULSE GEN. Figure 7. Test Circuit for Transient Immunity and Typical Waveforms. HCPL-M454 Figure 7 1.4 tPLH 0.25 0.20 IF = 10 mA IF = 16 mA 0.15 0.10 -60 -40 -20 0 20 40 60 80 100 120 TA - TEMPERATURE - C Figure 8. Propagation Delay Time vs. Temperature. HCPL-M454 fig 8 VCC = 5.0 V 1.2 TA = 25 C CL = 15 pF 1.0 VTHHL = VTHLH = 1.5 V 10% DUTY CYCLE 0.8 tPLH 0.6 t PHL 0.4 IF = 10 mA IF = 16 mA 0.2 0.0 0 2 4 6 8 10 12 14 16 18 20 RL - LOAD RESISTANCE - k Figure 9. Propagation Delay Time vs. Load Resistance. HCPL-M454 fig 9 tp - PROPAGATION DELAY - s VCC = 5.0 V 0.45 RL = 1.9 k CL = 15 pF 0.40 VTHHL = VTHLH = 1.5 V 10% DUTY CYCLE 0.35 t PHL 0.30 tp - PROPAGATION DELAY - s tp - PROPAGATION DELAY - s 0.50 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 VCC = 5.0 V TA = 25 C CL = 100 pF VTHHL = 1.5 V VTHLH = 2.0 V 50% DUTY CYCLE t PLH t PHL 0 2 4 6 IF = 10 mA IF = 16 mA 8 10 12 14 16 18 20 RL- LOAD RESISTANCE - k Figure 10. Propagation Delay Timefigvs.10 Load ResisHCPL-M454 tance. t PLH 50% DUTY CYCLE 0.7 0.6 0.5 0.4 tPHL 0.3 -60 -40 -20 0 20 40 60 80 100 120 TA - TEMPERATURE - C Figure 11. Propagation Delay Time vs. Temperature. HCPL-M454 fig 11 tp - PROPAGATION DELAY - s 1.2 1.1 1.0 0.9 0.8 0.7 t PLH TA = 25 C RL = 20 k CL = 100 pF VTHHL = 1.5 V VTHLH = 2.0 V 50% DUTY CYCLE 0.6 0.5 0.4 0.3 t PHL IF = 10 mA IF = 16 mA 0.2 10 11 12 13 14 15 16 17 18 19 20 VCC - SUPPLY VOLTAGE - V Figure 14. Propagation Delay Time vs. Supply Voltage. HCPL-M454 fig 14 3.5 1.8 IF = 10 mA IF = 16 mA VCC = 15.0 V 1.6 TA = 25 C CL = 100 pF 1.4 VTHHL = 1.5 V 1.2 VTHLH = 2.0 V 50% DUTY CYCLE 1.0 0.8 t PLH t PHL 0.6 0.4 IF = 10 mA IF = 16 mA 0.2 0.0 0 5 10 15 20 25 30 35 40 45 50 RL - LOAD RESISTANCE - k Figure 12. Propagation Delay Time vs. Load Resistance. HCPL-M454 fig 12 tp - PROPAGATION DELAY - s VCC = 15.0 V 1.0 RL = 20 k CL = 100 pF 0.9 V THHL = 1.5 V VTHLH = 2.0 V 0.8 tp - PROPAGATION DELAY - s tp - PROPAGATION DELAY - s 1.1 VCC = 15.0 V 3.0 TA = 25 C RL = 20 k 2.5 VTHHL = 1.5 V VTHLH = 2.0 V 2.0 50% DUTY CYCLE t PLH t PHL 1.5 1.0 IF = 10 mA IF = 16 mA 0.5 0.0 0 200 400 600 800 1000 RL - LOAD CAPACITANCE - pF Figure 13. Propagation Delay Time vs. Load Capacitance. HCPL-M454 fig 13 +HV HCPL-M454 + 6 1 LED 1 5 3 OUT 1 BASE/GATE DRIVE CIRCUIT Q1 BASE/GATE DRIVE CIRCUIT Q2 4 + HCPL-M454 6 1 LED 2 5 3 OUT 2 4 -HV Figure 15. Typical Power Inverter. HCPL-M454 fig 15 LED 1 OUT 1 tPLH MIN. (tPLH MAX. - tPLH MIN.) tPLH MAX. TURN ON DELAY (tPLH MAX. - tPLH MIN.) LED 2 OUT 2 tPHL MIN. (tPHL MAX. - tPHL MIN.) tPHL MAX. MAXIMUM DEAD TIME Figure 16. LED Delay and Dead Time Diagram. HCPL-M454 fig 16 Power Inverter Dead Time and Propagation Delay Specifications The HCPL-M454 includes a specification intended to help designers minimize "dead time" in their power inverter designs. The new "propagation delay difference" specification (tPLH - tPHL) is useful for determining not only how much optocoupler switching delay is needed to prevent "shoot-through" current, but also for determining the best achievable wort-case dead time for a given design. When inverter power transistors switch (Q1 and Q2 in Figure 15), it is essential that they never conduct at the same time. Extremely large currents will flow if there is any overlap in their conduction during switching transitions, potentially damaging the transistor and even the surrounding circuitry. This "shoot-through" current is eliminated by delaying the turn-on of one transistor (Q2) long enough to ensure that the opposing transistor (Q1) has completely turned off. This delay introduces a small amount of "dead time" at the output of the inverter during which both transistors are off during switching transitions. Minimizing this dead time is an important design goal for an inverter designer. The amount of turn-on delay needed depends on the propagation delay characteristics of the optocoupler, as well as the characteristics of the transistor base/gate drive circuit. Considering only the delay characteristics of the optocoupler (the characteristics of the base/gate drive circuit can be analyzed in the same way), it is important to know the minimum and maximum turn-on (tPHL) and turn-off (tPLH) propagation delay specifications, preferably over the desired operating temperature range. The importance of these specifications is illustrated in Figure 16. The waveforms labeled "LED1", "LED2", "OUT1", and "OUT2" are the input and output voltages of the optocoupler circuits driving Q1 and Q2 respectively. Most inverters are designed such that the power transistor turns on when the optocoupler LED turns on; this ensures that both power transistors will be off in the event of a power loss in the control circuit. Inverters can also be designed such that the power transistor turns off when the optocoupler LED turns on; this type of design, however, requires additional fail-safe circuitry to turn off the power transistor if an over-current condition is detected. The timing illustrated in Figure 16 assumes that the power transistor turns on when the optocoupler LED turns on. The LED signal to turn on Q2 should be delayed enough so that an optocoupler with the very fastest turn-on propagation delay (tPHLmin) will never turn on before an optocoupler with the very slowest turn-off propagation delay (tPLHmax) turns off. To ensure this, the turn-on of the optocoupler should be delayed by an amount no less than (tPLHmax - tPHLmin), which also happens to be the maximum data sheet value for the propagation delay difference specification, (tPLH - tPHL). The HCPL-M454 specifies a maximum (tPLH - tPHL) of 1.3 s over an operating temperature range of 0-70C. Although (tPLH - tPHL)max tells the designer how much delay is needed to prevent shoot-through current, it is insufficient to tell the designer how much dead time a design will have. Assuming that the optocoupler turnon delay is exactly equal to (tPLH - tPHL)max, the minimum dead time is zero (i.e., there is zero time between the turn-off of the very slowest optocoupler and the turn-on of the very fastest optocoupler). Calculating the maximum dead time is slightly more complicated. Assuming that the LED turn-on delay is still exactly equal to (tPLH - tPHL)max, it can be seen in Figure 16 that the maximum dead time is the sum of the maximum difference in turn-on delay plus the maximum difference in turn-off delay, [(tPLHmax-tPLHmin) + (tPHLmax-tPHLmin)], This expression can be rearranged to obtain [(tPLHmax-tPHLmin) - (tPHLmin-tPHLmax)], and further rearranged to obtain [(tPLH-tPHL)max - (tPLH-tPHL)min], which is the maximum minus the minimum data sheet values of (tPLH - tPHL). The difference between the maximum and minimum values depends directly on the total spread of propagation delays and sets the limit on how good the worst-case dead time can be for a given design. Therefore, optocouplers with tight propagation delay specifications (and not just shorter delays or lower pulse-width distortion) can achieve short dead times in power inverters. The HCPL-M454 specifies a minimum (tPLH - tPHL) of -0.7 s over an operating temeprature range of 0-70C, resulting in a maximum dead time of 2.0 s when the LED turn-on delay is equal to (tPLH - tPHL)max, or 1.3 s. It is important to maintain accurate LED turn-on delays because delays shorter than (tPLH - tPHL)max may allow shoot-through currents, while longer delays will increase the worst-case dead time. For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright (c) 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0553EN AV02-0967EN January 11, 2008