Integrated Device Technology, Inc. CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 IDT7203 IDT7204 IDT7205 IDT7206 FEATURES: First-In/First-Out Dual-Port memory 2048 x 9 organization (1DT7203) 4096 x 9 organization (1DT7204) 8192 x 9 organization (1OT7205) 16384 x 9 organization (IDT7206) High-speed: 12ns access time Low power consumption Active: 770mMW (max.) Power-down: 44mW (max.) Asynchronous and simultaneous read and write Fully expandable in both word depth and width Pin and functionally compatible with IDT720X family Status Flags: Empty, Half-Full, Full Retransmit capability High-performance CMOS technology Military product compliant to MIL-STD-883, Class B Standard Military Drawing for #5962-88669 (IDT7203), 5962-89567 (IDT7203), and 5962-89568 (IDT7204) are listed on this function. DESCRIPTION: The IDT7203/7204/7205/7206 are dual-port memory buff- ers with internal pointers that load and empty data on a first- inffirst-out basis. The device uses Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. Data is toggled in and out of the device through the use of the Write (W) and Read (R) pins. The devices 9-bit width provides a bit for a control or parity at the user's option. It also features a Retransmit (RT) capa- bility that allows the read pointer to be reset to its initial position when RT is pulsed LOW. A Half-Full Flag is available in the single device and width expansion modes. The 1D17203/7204/7205/7206 are fabricated using IOTs high-speed CMOS technology. They are designed for appli- cations requiring asynchronous and simultaneous read/writes in multiprocessing, rate buffering, and other applications. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B. FUNCTIONAL BLOCK DIAGRAM DATA INPUTS (Do Da) _ WRITE -o___ Ww CONTROL COMTI bs , e WRITE RAM ARRAY READ 2048 x 9 POINTER 4096 x9 POINTER 8192 x9 [ 16384 x 9 e 2 2 TELE TET tT THREE- STATE : _ BUFFERS RS DATA OUIPUTS t a AEAD os RF! CONTROL Hisar e_ FLAG =o cE AAT EF FL/AT = > FF EXPANSION oe x ___>- LOGIC *-_ XO/HF 2661 drw 01 The IDT logo Is a registered trademark of Integraled Device Tachology, inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 421996 Integraled Device Technology, Inc. 5. DECEMBER 1995 OSC-2661/8 26 11DT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x9 PIN CONFIGURATIONS wWO1 28 11 Vcc De Qe 270) Da D3 43 260 Ds D244 251 De bids poo 24.2 D7 Do He bee 2310 FURT X47 poe3 2D BS FF 8 soog-3 21 EF Qo 4 20 XO/HF Qi 10 191 Q7 Qe 11 190 Q6 a3 QO 12 170 Q5 Qs 413 16 FD Qa GND C14 ISR 2661 drw 02a DIP TOP VIEW NOTES: 1. The THINDIPs P28-2 and D28-3 are only available for the 7203/7204/ 7205. 2. The small outline package SO28-3 is only available for the 7204. 3. Consult factory for CERPACK pinout. ABSOLUTE MAXIMUM RATINGS) Symbol Rating Commercial Military Unit VTERM Terminal 0.5to+7.0 | -0.5 to +7.0 Vv Voltage with Respect to GND TA Operating 0 to +70 -55 to +125 | C Temperature TBIAS Temperature | -55to +125 | -65to+135 | C Under Bias TSTG Storage -55 to+ 125 | -65to+155 | C Temperature IOUT DC Output 50 50 mA Current NOTE: 2661 tbl 01 1. Stresses greater than those listad under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damags to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. MILITARY AND COMMERCIAL TEMPERATURE RANGES PLCC/LCC TOP VIEW RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Min. j Typ. | Max. | Unit Vccm | Military Supply 4.5 5.0 5.5 Vv Voltage vcecc | Commercial Supply 4.5 5.0 5.5 Vv Voltage GND Supply Voltage 0 0 0 Vv VIH | Input High Voltage 2.0 ~ Vv Commercial vin) | input High Voltage | 2.2 _ Vv Military vit) | Input Low Voltage _ _ 0.8 v Commercial and Military NOTE: 2661 tbl 02 1. 1.5V undershoots are allowed for 10ns once per cycle. 2 5.261D7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 DC ELECTRICAL CHARACTERISTICS FOR THE 7203 AND 7204 MILITARY AND COMMERCIAL TEMPERATURE RANGES (Commercial: Vcc = 5.0V+10%, TA = OC to +70C; Military: Vcc = 5.0V410%, TA = -55C to +125C) IDT7203/7204 IDT7203/7204 Commercial Military ta = 12, 15, 20, 25, 35, 50 ns ta = 20, 30, 40, 50, 65, 80, 120 ns Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit wu?) Input Leakage Current (Any Input) -1 1 -1 ~ 1 HA Lo) Output Leakage Current -10 _ 10 -10 _ 10 HA VOH Output Logic 1 Voltage |oH = -2mA 2.4 2.4 _ Vv VoL Output Logic 0 Voltage lol = 8mA _ 0.4 _ 0.4 Vv tec 4} Active Power Supply Current _ 12015) 150) mA Ioc2"4) Standby Current (R= W=RS=FU/RT=Vin) 12 25 mA Icca(Ly'4) Power Down Current (All input = Vcc -0.2V)} 2 _- 4 mA icca(S) | Power Down Current (All Input = Vcc -0.2V) | 8 12 mA NOTES: 2661 Ibi 03 1. Speed grades 65, 80, and 120ns are only available in the ceramic DIP. 2. Measurements with 0.4 < Vin s Vcc. 3. A2 Vin, 0.4 < Vout < Voc. 4. !cc measurements are made with outputs open (only capacitive loading). 5. Tested at f = 20MHz. DC ELECTRICAL CHARACTERISTICS FOR THE 7205 AND 7206 (Commercial: Vcc = 5.0V+10%, TA = 0C to +70C; Military: Vcc = 5.0Vt10%, TA = -55C to +125C) 1DT7205/7206 10T7205/7206 Commercial Military ta = 15, 20, 25, 35, 50 ns ta = 20, 30, 50 ns Symbol Parameter Min. Typ. Max, Min. Typ. Max. Unit i) Input Leakage Current (Any Input) -1 { -1 _ 1 pA Ito) Output Leakage Current -10 _ 10 -10 _ 10 pA VOH Output Logic 1 Voltage loH = -2mA 2.4 _ _ 2.4 _ _ v VoL Output Logic 0 Voltage lo. = 8mA _ _ 0.4 _ _ 0.4 Vv Icc1 8) Active Power Supply Current = 1204) = 150!) mA Icc2'3) Standby Current (ReW=RS=FL/RT=Vin) _ 12 _ 25 mA Icca(L)) | Power Down Current (All Input = Voc - 0.2V)} _ 8 12 mA NOTES: 2661 tbl o< 1, Measurements with 0.4 < Vin < Vcc. 2. R2 Vin, 0.4 < Vout < Vcc. 3. Icc measurements are made with outputs open (only capacitive loading). 4, Tested at f = 20MHz. 5.261DT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 AC ELECTRICAL CHARACTERISTICS") (Commercial: Vcc = 5V + 10%, TA = OC to +70C; Military: Vcc = 5V + 10%, TA = -55C to +125C) MILITARY AND COMMERCIAL TEMPERATURE RANGES Commercial Com'l & Mil. Com'! Military Com'! 7203S/L12 | 7203S/L15 | 7203S/L20 | 7203S/L25 | 7203S/L30 | 7203S/L35 7204S/L12 | 7204S/L15 | 7204S/L20 | 7204S/L25 | 7204S/L30 | 7204S/L35 7205L15 7205L20 7205L25 7205L30 | 7205L35 7206L15 7206L20 7206L25 7206L30 | 7206L35 Symbol | Parameters Min. Max.| Min. Max.| Min. Max. | Min. Max.] Min. Max.|Min. Max.| Unit fs Shift Frequency _ 50 _ 40 - 333] 285] 25 | 22.2|;MHz {RC Read Cycle Time 200 ao 30 35 = 40 |45 J|ns ta Access Time _ 12 _ 15 _ 20 _ 25 _ 30 | 35 | ns tRR Read Recovery Time 8 _ 10 _ 10 _ 10 _ 10 | 10 | ns tRPW Read Pulse Width? 12 15 | 20 25 | 30 | 35 |ons tALz Read LOW to Data Bus LOW) 3 _~ 5 _ 5 5 _ 5 |] 5 | ons twiz Write HIGH to Data Bus Low-2%] 3 _ 5 _ 5 _ 5 5 |10 I]|ons tov Data Valid from Read HIGH 5 _ 5 _ 5 _ 5 _ 5 _ 5 |ns tAHZ Read HIGH to Data Bus High-Z | 12] 5] 15 - wf/ 20]/ 20] ns two Write Cycle Time 20 25 _ 30 _ 35 - 40 |45 I]ns twew Write Pulse Width 12. 15 | 20 _ 25 | 30 | 35 ]|ns twa Write Recovery Time 8 = 10 _ 10 _ 10 = 10 | 10 _|ns tps Data Set-up Time 9 _ 11 ~ 12 =~ 56 18 |]18 =\]ns {DH Data Hold Time 0 0 _ 0 0 _ 0 - 0 | ns tasc Reset Cycle Time 20 | 25 | 30 _ 33 | 40 |]45 ]Xns tRS Reset Pulse Width?) 12 ]|] 15 | 20 _ 25 |30 ]35 I]ns tass Reset Set-up Time 12 ] 15 | 20 2 |] 30 |] 35 | ns tRTR Reset Recovery Time 8 _ 10 _ 10 _ 10 10 ]10 J]ns tATC Retransmit Cycle Time 20 _ 25 _ 30 ~ 35 _ 40 | 45 | ns tRT Retransmit Pulse Width?) 12 ] 15 | 20 _ 25 -]30 ]35 I]ns tATS Retransmit Set-up Time 12 ] 15 | 20 _ 2 | 30 ]35 | ns tAsSR Retransmit Recovery Time 8 {10 J] 10 _ 10 ~ | 10 ]10 ]|ns tEFL Reset to EF LOW 121/ 2 ]/- 3f- 3 {| 40|/ 45] ns tHFH, tFFH| Reset to HF and FF HIGH _ 17 25 _ 30 _ 35 _ 40 | 45 | ns tRTF Retransmit LOW to Flags Valid 2], 22a] 30 - 3] 40| 45] ns tREF Read LOW to EF LOW iw2]- 6]- 2 |- 2 ] 30] 30|ns {AFF Read HIGH to FF HIGH 4] 156 ] 2 {|- 22 f 30] 30|{ ns tAPE Read Pulse Width after EF HIGH 12 _ 15 _ 20 25 _ 30 | 35 | ns {WEF Write HIGH to EF HIGH _ 12 _ 15 _ 20 _ 25 _ 30 | 30 | ns tWFF Write LOW to FF LOW _ 14 _ 15 _ 20 _ 25 _ 30 | 30 | ns tWHF Write LOW to HF Flag LOW - 17 - 25] 30 _ 35 - 40] 45 | ns tRHF Read HIGH to HF Flag HIGH 17 _ 2] 30 _ 35 _ 40 | 45 | ns twPF Write Pulse Width after FF HIGH 12 _ 15 | 20 _ 25 | 30 | 35 | ns txoL Read/Write LOW to XO LOW i2])- 6]- 2 | 2 ] 30] 35| ns txOH ReadMrite HIGH to XO HIGH - 12 _ 15] 20 _ 25 | 30 | 35 | ns re XI Pulse Width) 1 |] 15 !] 20 | 25 ]|30 |35 |ns bar XI Recovery Time 8 _ 10 _ 10 _ 10 = 10 | 10 }ons xis XI Set-up Time 8 _ 10 _ 10 _ 10 _ 10 _ 15 _ ns NOTES: 2661 tb! 05 1. Timings referenced as in AC Test Conditions. 2. Pulse widths less than minimum are not allowed, 3. Values guaranteed by design, not currently tested. 4. Only applies to read data flow-through mode. 5.26 4IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 AC ELECTRICAL CHARACTERISTICS") (Continued) (Commercial: Vcc = 5V + 10%, Ta = 0C to +70C; Military: Vcc = 5V + 10%, TA = -55C to +125C) MILITARY AND COMMERCIAL TEMPERATURE RANGES Military Com't & Mil. Military? 7203S/L40 7203S/L50 | 7203S/L65 | 7203S/L80 | 7203S/L120 7204S/L40 7204S/L50 | 7204S/L65 | 7204S/L80 | 7204S/L120 7205L50 7206L50 Symbol Parameters Min. Max. | Min. Max.| Min. Max.| Min. Max.) Min. Max. | Unit fs Shift Frequency _ 20 _ 15 _ 12.5] 10 _ 7 MHz tRC Read Cycle Time 50 _ 65 | 80 | 100 | 140 _ ns tA Access Time _ 40 _ 50 | 65 _ 80 120 ns {AR Read Recovery Time 10 _ 15 _ 15 _ 20 _ 20 _ ns tRPW Read Pulse Width? 40. | 50 [e |s8 |120 | ns tALZ Read LOW to Data Bus LOW) _ 10 | 10 | 10 | 10 ns twLz Write HIGH to Data Bus Low-z'* ) 10 _ 15 | 15 | 20 | 20 ns tDv Data Valid from Read HIGH 5 _ 5 _ 5 _ 5 _ 5 _ ns tRHZ Read HIGH to Data Bus High-Z) 25 30 | 30 | 30] 35 ns twe Write Cycle Time 50 _ 65 | 80 }100 -] 140) ns twew Write Pulse Width 40 _ 50 | 65 | 80 |120 ns twa Write Recovery Time 10 _ 15 15 _ 20 20 _ ns tos Data Set-up Time 20 _ 30 ~ 30 _ 40 _ 40 _ ns toH Data Hold Time 0 _ 5 _ 10 > 10 _ 10 _ ns tAasc Reset Cycle Time 50 _ 65 _ 80 | 100 | 140 - ns trs Reset Pulse Width 40 50 | 65 | 80 | 120 ns tass Reset Set-up Time 40 _ 50 | 65 | 80 | 120 _ ns tRSA Reset Recovery Time 10 - 15 15 | 20 | 20 ~ ns tRTC Retransmit Cycle Time 50 _ 65 _ 80 | 100 | 140 _ ns tRT Retransmit Pulse Width 40 _ 50 | 65 | 80 | 120 ns tATS Retransmit Set-up Time 40 50 | 65 | 80 |]|120 ns tRSR Retransmit Recovery Time 10 _ 15 _ 15 _ 20 _ 20 _ ns TEFL Reset to EF LOW 50 [| 6 | 80 | 100] 140] ns tHEH, tfFH | Reset to HF and FF HIGH _ 50 _ 65 _ 80 _ 100]; 140 ns {ATF Retransmit LOW to Flags Valid = 50 _ 65) 80 } 100; 140 ns {REF Read LOW to EF Flag LOW 35 45] 60 | 60 - 60 ns tRFF Read HIGH to FF HIGH - 35 _ 45], 60 | 60 -_ 60 ns tAPE Read Pulse Width after EF HIGH 40 _ 50 _ 65 _ 80 | 120 ns tWEF Write HIGH to EF HIGH _ 35 _- 45 _ 60 | 60} 60 ns tWFF Write LOW to FF LOW 36 | 445] 6o{[ 60] _ 60 ns tWHF Write LOW to HF LOW _ 50 _ 65 _ 80 _ 100], 140 ns tRHF Read HIGH to HF HIGH _ 50 _ 65 | so | 100} 140 ns twer Write Pulse Width after FF HIGH 40 _ 50 _ 65 _ 80 | 120 _ ns {xOL Read/Write LOW to XO LOW _ 40 _ 50 _ 65 _ 80 _ 120 ns {xOH Read/Write HIGH to XO HIGH _ 40 _ 50 _ 65 _ 80 _ 120 ns txt XI Pulse Width 40 _ 50 )}) 65 _ 80 | 120 -_ ns {xin XI Recovery Time 10 = 10 {10 |]10 ]| 0 ns Ixis XI Set-up Time 15 | 15 ~! 15 [ 15 ] 1 = ns NOTES: 2661 tbl 06 1. Timings referenced as in AC Test Conditions. 2. Speed grades 65, 80, and 120ns are only available in the ceramic DIP. 3. Pulse widths less than minimum are not allowed. 4. Values guaranteed by design, not currently tested. 5. Only applies to read data flow-through mode. 5.26 IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 AC TEST CONDITIONS Input Pulse Levels GND to 3.0V (Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figure 1 2661 tol 07 CAPACITANCE") (Ta = +25C, f = 1.0 MHz) Symbol Parameter Condition Max. | Unit Cin Input Capacitance Vin = OV 10 pF Court) | Output Capacitance | Vout = 0V 10 pF NOTES: 2661 tbi 08 1. This parameter is sampled and not 100% tested. 2. With output deselected. SIGNAL DESCRIPTIONS Inputs: DATA IN (DoDa) Data inputs for 9-bit wide data. Controls: RESET (RS) Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place. Both the Read Enable (R) and Write Enable (W) inputs must be in the HIGH state during the window shown in Figure 2 (i.e. tass before the rising edge of RS) and should not change until tasr after the rising edge of RS. WRITE ENABLE (W) A write cycleis initiated on the falling edge of this input if the Full Flag (FF) is not set. Data set-up and hold times must be adhered-to, with respect to the rising edge of the Write Enable (W). Data is stored in the RAM array sequentially and independently of any on-going read operation. After half of the memory is filled, and at the falling edge of the next write operation, the Ha!f-Full Flag (HF) will be set to LOW, and will remain set until the difference between the write pointer and read pointer is less-than or equal to one-half of the total memory of the device. The Half-Full Flag (HF) is reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go LOW on the falling edge of the last write signal, which inhibits further write operations. Upon the completion of a valid read operation, the Full Flag (FF) will go HIGH after tfFF, allowing a new valid write to begin. When the FIFO is full, the internal write pointer is blocked from W, so external changes in Wwillnot affect the FIFO when it is full. MILITARY AND COMMERCIAL TEMPERATURE RANGES 5V 1.1KQ D.U.T. 6802 30pF* 2661 drw 03 OR EQUIVALENT CIRCUIT Figure 1. Output Load includes jig and scope capacitances. READ ENABLE (R) A read cycle is initiated on the falling edge of the Read Enable (R), provided the Empty Flag (EP) is not set. The data is accessed on a First-In/First-Out basis, inde- pendent of any ongoing write operations. After Read Enable (R) goes HIGH, the Data Outputs (Qo through Qs) will return to a high-impedance condition until the next Read operation. When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, allowing the final read cycle but inhibiting further read operations, with the data outputs remaining in a high- impedance state. Once a valid write operation has been accom- plished, the Empty Flag (EF) will go HIGH after twer and a valid Read can then begin. When the FIFO is empty, the internal read pointer is blocked from R so external changes will not affect the FIFO when it is empty. FIRST LOAD/RETRANSMIT (FL/AT) This is a dual- purpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first device loaded (see Operating Mades). The Single Device Mode is initiated by grounding the Expansion !n (XI). The 1DT7203/7204/7205/7206 can be made to retransmit data when the Retransmit Enable Control (RT) input is pulsed LOW. Aretransmit operation will set the internal read pointer to the first location and will not affect the write pointer. The status of the Flags will change depending on the relative locations of the read and write pointers. Read Enable (R) and Write Enable (W) must be in the HIGH state during retransmit. This feature is useful when less than 2048/4096/8192/16384 writes are per- formed between resets. The retransmit feature is not compat- ible with the Depth Expansion Mode. EXPANSION IN (XI) This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (XI) is connected to Expan- sion Out (XO) of the previous device in the Depth Expansion or Daisy-Chain Mode.D17203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 Outputs: FULL FLAG (FF) The Full Flag (FF) will go LOW, inhibiting further write operations, when the device is full. If the read pointer is not moved after Reset (RS), the Full Flag (FF) will go LOW after 2048/4096/81 92/16384 writes. EMPTY FLAG (EF) The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. EXPANSION OUT/HALF-FULL FLAG (XO/HF) This is a dual-purpose output. In the single device mode, when Expan- sion In (XI) is grounded, this output acts as an indication of a halt- full memory. After half of the memory is filled, and at the falling edge of the next write operation, the Half-Full Flag (AF) will be set to LOW MILITARY AND COMMERCIAL TEMPERATURE RANGES and will remain set until the difference between the write pointer and read pointer is less than or equal to one haif of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is con- nected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. There will be an XO pulse when the Write pointer reaches the last location of memory, and an additional XO pulse when the Read pointer reaches the last location of memory. DATA OUTPUTS (Qo-Qs) Qo-Qs are data outputs for 9- bit wide data. These outputs are in a high-impedance condition whenever Read (R) is in a HIGH state. RS W R EF tHFH, tFFH FF, FF 2661 drw 04 NOTE: _ _ 1. Wand R = Vix around the rising edge of AS. Figure 2. Reset +t tRC >| t{RPW~] ta tAR>| [j~_ A - t4} SS _ A a a, we! triz tov ht tRHZ > Qo-Os DATAoUTVALID KX 9K DATAouT VALID XX } twe > ot t{wew ~ twR_> W XK KF UK tos-=[ tpbH >~ Do-Ds DATAIN VALID DATAIN VALID 2661 drw 05 Figure 3. Asynchronous Write and Read OperationIDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x9 MILITARY AND COMMERCIAL TEMPERATURE RANGES FIRST READ tRFF i 2661 drw 06 FIRST WRITE , | IGNORED LAST WRITE WRITE R wW NN] twre FE Figure 4. Full FlagTiming From Last Write to First Read LAST READ IGNORED W R tREF tWEF EF U V DATA out K> K VALID > xX 2661 drw 07 Figure 5. Empty Flag Timing From Last Read to First Write NOTE: 1. EF, FF and HF may change status during Retransmit, but flags will be valid at tac. Figure 6. Retransmit FLAG VALID 2661 drw OB 5.26IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES wo zx tWer EF 7 1 t RPE BR NAARRDRDAADRRDDADRRAR?RAC ES. # Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse. R \ {RFF FF a * t wer Wo NAAANAARAANANAS SS # 2661 drw 10 Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse. W R Le-tvme HALF-FULL OR LESS MORE THAN HALF-FULL HALF-FULL OR LESS 2661 drw 11 Figure 9. Half-Full Flag Timing WRITE TO LAST PHYSICAL LOCATION Sl Dl READ FROM LAST PHYSICAL LOCATION eNO 2661 dew 12 txou Figure 10. Expansion Out 5.261DT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES xl txts WRITE TO _ FIRST PHYSICAL W LOCATION READ FROM FIRST PHYSICAL R LOCATION 2661 drew 11 Figure 11. Expansion In OPERATING MODES: Care must be taken to assure that the appropriate flag is monitored by each system (i.e. FF is monitored on the device where W is used; EF is monitored on the device where R is used). For additional information, refer to Tech Note 8: Oper- ating FIFOs on Full and Empty Boundary Conditions and Tech Note 6: Designing with FIFOs. Single Device Mode A single IDT7203/7204/7205/7206 may be used when the application requirements are for 2048/4096/8192/16384 words or less. The IDT7203/7204/7205/7206 is in a Single Device Configuration when the Expansion In (XI) control input is grounded (see Figure 12). Depth Expansion The 1DT7203/7204/7205/7206 can easily be adapted to applications when the requirements are for greater than 2048/ 4096/8192/16384 words. Figure 14 demonstrates Depth Ex- pansion using three IDT7203/7204/7205/7206s. Any depth can be attained by adding additional 1DT7203/7204/7205/ 7206s. The |DT7203/7204/7205/7206 operates in the Depth Expansion mode when the following conditions are met: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (XI) pin of the next device. See Figure 14. 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (E (EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all must be set to generate the correct composite FI FF or EF). See Figure 14. 5. The Retransmit (AT) function and Half-Full Flag (HF) are not available in the Depth Expansion Mode. For additional information, refer to Tech Note 9: Cascading FIFOs or FIFO Modules. USAGE MODES: Width Expansion Word width may be increased simply by connecting the corresponding input contro! signals of multiple devices. Sta- tus flags (EF, FF and HF) can be detected from any one device. Figure 13 demonstrates an 18-bit word width by using two 1DT7203/7204/7205/7206s. Any word width can be attained by adding additional IDT7203/7204/7205/7206s (Figure 13). Bidirectional Operation Applications which require data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing 1D17203/7204/7205/7206s as shown in Figure 16. Both Depth Expansion and Width Expan- sion may be used in this mode. Data Flow-Through Two types of flow-through modes are permitted, a read flow-through and write flow-through mode. For the read flow- through mode (Figure 17), the FIFO permits a reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in (tweF + ta) ns after the rising edge of W, called the first write edge, and it remains on the bus until the R line is raised from LOW-to-HIGH, after which the bus would go into a three-state mode after tRHZns. The EFline would have a pulse showing temporary deassertion and then would be asserted. In the write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO. The R line causes the FF to be deasserted but the Wline being LOW causes it to be asserted again in anticipation of a new data word. On the rising edge of W, the new word is loaded in the FIFO. The Ww line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write pointer. Compound Expansion The two expansion techniques described above can be applied together in a straightforward manner to achieve large FIFO arrays (see Figure 15). 5.26 101017203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES (HALF-FULL FLAG) (HF) WRITE (W) }~_ READ (A) ) IDT 9 DATA IN (D) 7 + 7203/ _a DATA OUT (Q) FULL FLAG (FF) } 7o08/ | "EMPTY FLAG EF) RESET (R5) | 7206 }- RETRANSMIT (RT) EXPANSION IN (Xi) t 2661 drw 14 Figure 12. Block Diagram of 2048 x 9/4096 x 9/8192 x 9/16384 x 9 FIFO Used in Single Device Mode HF HF 18 9 4 9 4 DATAIN (D) WRITE (W) +} - ----- - !OT a4, ------4 + READ (FI FULL FLAG FF) + rey 7208! " 7 _ 7205/ 7204/ EMPTY FLAG (EF) a 7206 7205/ RESET (RS) *_ - - ---- 7206 st. 7TTTI 3 _RETRANSMIT (RT) Wa i Z Z 7 7 = = 218 L > DATA out (Q) 2661 drw 15 NOTE: 1, Flag detection is accomplished by monitoring the FF, EF and HF signals on either (any) device used in the width expansion configuration. Do not connect any output signals together. Figure 13. Block Diagram of 2048 x 18/4096 x 18/8192 x 18/16384 x 18 FIFO Memery Used in Width Expansion Mode 5.26 111DT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 TRUTH TABLES TABLE | - RESET AND RETRANSMIT SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE MILITARY AND COMMERCIAL TEMPERATURE RANGES Inputs Internal Status Outputs Mode RS RT Xl | Read Pointer | Write Pointer EF FF HF Reset 0 X 0 Location Zero Location Zero 0 i 1 Retransmit 1 0 0 Location Zero Unchanged x x X Read/Write 1 1 0 | Increment! Increment!) x x x NOTE: 2661 tbl 09 1. Pointer will Increment if flag is HIGH. TABLE Il - RESET AND FIRST LOAD DEPTH EXPANSION/COMPOUND EXPANSION MODE Inputs Internal Status Outputs Mode RS A xl Read Pointer Write Pointer EF FF Reset First Device 0 0 (1) Location Zero Location Zero 0 1 Reset all Other Devices 0 1 (1) Location Zero Location Zero 0 1 Read/Write 1 X (1) X xX Xx NOTES: 2661 tbl 10 1. Xlis connected to XO of previous device. See Figure 14. 2. RS = Reset Input, FLAT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output = FULL 2661 drw 16 Figure 14. Block Diagram of 6149 x 9/12298 x 9/24596 x 9/49152 x 9 FIFO Memory (Depth Expansion) .26 12IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES Qo-Qa Q3-Q17 Qin-8) -QN [ Qo-Qa | | Q9-Q17 | | QiN-8) -QN IDT7203/ 1DT7203/ IDT7203/ IDT7204/ IDT7204/ (IDT7204/ IDT7205/ IDT7205/ IDT7205/ saa IDT7206 IDT7206 IDT7206 R,W,RS DEPTH DEPTH s* ) DEPTH EXPANSION EXPANSION EXPANSION BLOCK BLOCK BLOCK oe Do -Ds 5 Do -Di7 4 Din-8)-DN Do-Dn eee Dg -ON Dis -DN D(n-8)-DN 2661 drw 17 NOTES: 1. For depth expansion block see section on Depth Expansion and Figure 14. 2. For Flag detection see section on Width Expansion and Figure 13. Figure 15. Compound FIFO Expansion <a _Ra -> FFs Wa | IpT 7203/ 7204/ 7205/ 7206 FFa~* pS Da 0-8 QB 0-8 SYSTEM A > SYSTEM B \OT 7203/ 7204/ 7205/ 7206 -* FFB 2661 drw 18 Figure 16. Bidirectional FIFO Operation DATAIN x [_ trPE HK / twer tRer twuz ta DATA out xxxKx > DATA VALID out 2661 drw 19 Figure 17. Read Data Flow-Through Mode 131DT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES R S WA _ L tree FF A \ h* twrr >| vi DATAIN DATAIN VALID t | a tos DATAout CXC X DATAouT VALID <x> 2661 drw 20 Figure 18. Write Data Flow-Through Mode ORDERING INFORMATION IDT XXXX xX XX xX x Device Power Speed Package Process/ Type Temperature Range | Blank Commercial (0C to +70C) Military (-55C to +126C) Compliant to MIL-STD-883, Class B Plastic DIP Plastic THINDIP (all except 7206) Ceramic DIP Ceramic THINDIP (all except 7206) Plastic Leaded Chip Carrier Leadless Chip Carrier (Military only) Small Outline IC (7204 only) 12 Commercial 7203/04 Only 15 Commercial Only 20 25 Commercial Only ; 30 Military Only Access Time (tA) 35 Commercial Only Speed in ns 40 Military 7203/04 Only 50 65 80 Military 7203/04DB Only 120 Js Standard Power (7203/7204 only) JL Low Power 7203. 2048x9 FIFO 7204 4096 x9 FIFO 7205 8192x9 FIFO 7206 16384 x 9 FIFO 2661 drw 21 .26 4