DM74LS533NX - Fairchild Semiconductor

October 1988

Revised March 2000

DM74LS533 Octal Transparent Latch with 3-STATE Outputs

DM74LS533

Octal Transparent Latch with 3-STATE Outputs

General Descript ion

The DM74LS533 consists of eight latches with 3-STATE

outputs for bus organized system applications. The flip-

flops appear transparent to the data when Latch Enable

(LE) is HIGH. When LE is LOW, the data that meets the

setup time s is lat ched. Data appears on the bus when the

Output Enable (OE) is LOW. When OE is HIGH the bus

output is in the h ig h impedance state. The D M74LS533 i s

the same as the DM74LS373, except that the outputs are

inverted. For detailed specifications please see the

DM74LS373 data sheet, but note that the propagation

delays from data to output are 5.0 ns longer for the

DM74LS533 than for the DM74LS373.

Features

■Eight latches in a single package

■3-STATE outputs for bus interfacing

Ordering Code:

Devices also available in Tape and Reel. S pecify by ap pending the suffix let t er “X” to the orderin g c ode.

Logic Symbol

VCC = Pin 20

GND = Pin 10

Pin Descriptions

Connection Diagram

Function Table

L = LOW State

H = HIGH State

X = Don't Care

Z = High Imp edance St at e

QO = Previou s C ondition of O

Order Number Package Number Package Description

DM74LS533WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JE DEC MS-013, 0.300 Wide

DM74LS533N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names Description

D0, D7 Data Inputs

LE Latch Enable Input (Active HIGH)

OE Output Enable Input (Active LOW)

O0–O7 Complementary 3-STATE Outputs

OUTPUT Latch D Output

Enable Enable O

LHHL

LHLH

LLXQ

HXXZ

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DM74LS533

Absolute Maximum Ratings(N o te 1) Note 1: The “Ab solute Maxim um Ratings are those values beyo nd which

the saf ety of the device cannot be guarante ed. The device s hould not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum ratings.

The “Re comme nded Operat ing Co ndition s” table will define the cond itions

for actu al device operation.

Recommended Operating Conditions

Electrical Characteristics

Over recommended operating free air temperature range (unless otherwise noted)

Note 2: All typic als are at VCC = 5V, TA = 25°C.

Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteri stics

VCC = +5.0V, TA = +25°C

Supply Voltage 7V

Input Vol tag e 7V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH High Level Input Voltage 2 V

VIL Low Level Input Voltage 0.8 V

IOH High Level Output Current −2.6 mA

IOL Low Level Output Current 24 mA

TAFree Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min Typ Max Units

(Note 2)

VIInput Clamp Voltage VCC = Mi n, I I = −18 mA −1.5 V

VOH HIGH Level VCC = Min, I OH = Max, 2.4 3.4 V

Output Voltage VIL = Max

VOL LOW Level VCC = Min, IOL = Max, 0.35 0.5

Output Voltage VIH = Min V

IOL = 12 mA, VCC = Min 0.4

IIInput Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA

IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA

IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA

IOS Short Circuit VCC = Max −20 −100 mA

Output Current (Note 3)

ICCZ Supply Current VCC = Ma x 46 mA

IOZL 3-STATE Output Off VCC = VCCH −20.0 µA

Current LOW VOZL = 0.4 V

IOZH 3-STATE Output Off VCC = VCCH 20.0 µA

Current HIGH VOZH = 2.7V

CL = 50 pF

Symbol Parameter RL = 2 kΩUnits

Min Max

tPLH Propagation Delay 23 ns

tPHL Data to Qx23

tPLH Propagation Delay 30 ns

tPHL LE to Qx25

tPZL Output Enable Time 22 ns

tPZH OE to Qx20

tPHZ Output Enable Time 20 ns

tPLZ OE to Qx25

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DM74LS533

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M20B

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DM74LS533 Octal Transparent Latch with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N20A

Fairchild does no t assume any responsibility for use of any c ir cuitry described, no circuit patent license s are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a life su pport

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa i lure of the life su pp ort

device or system, or to affect its safety or effectiveness.