24AA16 16K 1.8V ?C Serial EEPROM FEATURES * Single supply with operation down to 1.8V + Low power CMOS technology - 1 mA active current typical - 10 pA standby current typical at 5.5V - 3 yA standby current typical at 1.8V * Organized as 8 blocks of 256 bytes (8 x 256 x 8) * 2-wire serial interface bus, I7C compatible * Schmitt trigger, filtered inputs for noise suppres- sion * Output slope control to eliminate ground bounce * 100 kHz (1.8V) and 400 kHz (5V) compatibility * Self-timed write cycle (including auto-erase) * Page-write buffer for up to 16 bytes * 2 ms typical write cycle time for page-write * Hardware write protect for entire memory * Can be operated as a serial ROM * ESD protection > 4,000V * 1,000,000 erase/write cycles guaranteed + Data retention > 200 years * 8-pin DIP, 8-lead or 14-lead SOIC packages * Available for extended temperature ranges - Commercial (C): 0C to +70C - Industrial (I): -40C to +85C DESCRIPTION The Microchip Technology Inc. 24AA16 is a 1.8 volt 16K bit Electrically Erasable PROM. The device is organized as eight blocks of 256 x 8-bit memory with a 2-wire serial interface. Low voltage design permits operation down to 1.8 volts with standby and active cur- rents of only 3 pA and 1 mA, respectively. The 24AA16 also has a page-write capability for up to 16 bytes of data. The 24AA16 is available in the standard 8-pin DIP and both 8-lead and 14-lead surface mount SOIC pack- ages. C is a trademark of Philips Corporation. PACKAGE TYPES PDIP T Ao[]1 8[]Vcc At [2 8 7 ]we > a2t]3 = 6{Jscr vss []4 5[_|SDA 8-lead WY SOIC pg] 81 vec Ai] 2 eo 7 | we > aoc] 3 a 61 sci vsst_| 4 5T spa 14-lead SOIC W ne C41 14 Le AO Cc 2 13 | Vcc aC? yw %E we nc C4 > 11 [7 Nc a2 C-l5 10 [4 sei vss C-6 [spa nc C4 [+ NC BLOCK DIAGRAM WP | VO MEMORY HV GENERATOR XDEC ~ EEPROM ARRAY PAGE LATCHES A A j I SENSE AMP CONTROL beet CONTROL} >4 LOGIC LOGIC SDA SCL Vcc [}} Vss []}+ RAV CONTROL 1998 Microchip Technology Inc. DS21054F-page 124AA16 1.0 ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* VCC Lee ee te enter rece ere cere tee ne tee nese setneerseeneereenee 7.0V All inputs and outputs w.r.t. VSS ...0.6V to Vcc +1.0V Storage temperature... eens -65C to +150C Ambient temp. with power applied................. -65C to +125C Soldering temperature of leads (10 seconds) ............. +300C ESD protection on all Pins wo... secs sseeesseeesseeneee 24kV *Notice: Stresses above those listed under Maximum ratings may cause permanent damage to the device. This is a stress rat- ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability TABLE 1-2: DC CHARACTERISTICS TABLE 1-1: PIN FUNCTION TABLE Name Function Vss Ground SDA Serial Address/Data I/O SCL Serial Clock WP Write Protect Input Vec +1.8V to 5.5V Power Supply AO, A1, A2 No Internal Connection Vcc = 1.8V to +5.5V Commercial (C): Tamb = 0C to +70C Industrial (I): Tamb = -40C to +85C Parameter Symbol Min Typ Max | Units Conditions WP, SCL and SDA pins: High level input voltage VIH .7 Vcc _ Vv Low level input voltage VIL .3 VCC Vv Hysteresis of Schmitt trigger inputs | VHYs | .05 Vcc _ V_ | (Note) Low level output voltage VOL 40 Vs | loL= 3.0 mA, Voc = 1.8V Input leakage current ILI 10 HA | Vin=.1V to Vcc Output leakage current ILO 10 HA | Vout=.1V to Voc Pin capacitance CIN, 10 pF | Vcc = 5.0V (Note 1) (all inputs/outputs) COUT Tamb = 25C, Feik = 1 MHz Operating current Icc Write _ 3 mA | Vcc = 5.5V, SCL = 400 kHz 0.5 _ mA | Vcc = 1.8V, SCL = 100 kHz Icc Read _ 1 mA | Vcc = 5.5V, SCL = 400 kHz 0.05 _ mA | Vcc = 1.8V, SCL = 100 kHz Standby current Iccs 100 HA | Vcc = 5.5V, SDA=SCL=Vcc _ 30 HA |Vcc=3.0V, SDA=SCL=Vcc 3 _ HA |Vcc= 1.8V, SDA=SCL=Vcc WP = Vss Note: This parameter is periodically sampled and not 100% tested. FIGURE 1-1: BUS TIMING START/STOP SCL SDA ' ' START DS21054F-page 2 1998 Microchip Technology Inc.24AA16 TABLE 1-3: AC CHARACTERISTICS STANDARD Vcc = 4.5-5.5V Parameter Symbol MODE FAST MODE Units Remarks Min Max Min Max Clock frequency FCLK _ 100 _ 400 kHz Clock high time THIGH 4000 _ 600 _ ns Clock low time TLOW 4700 1300 _ ns SDA and SCL rise time TR _ 1000 _ 300 ns (Note 1) SDA and SCL fall time TF _ 300 _ 300 ns (Note 1) START condition hold THD:STA 4000 600 ns___| After this period the first time clock pulse is generated START condition setup TSU:STA 4700 _ 600 _ ns Only relevant for repeated time START condition Data input hold time THD:DAT 0 _ 0 _ ns Data input setup time TSU:DAT 250 _ 100 _ ns STOP condition setup TSU:STO 4000 600 ns time Output valid from clock TAA _ 3500 _ 900 ns (Note 2) Bus free time TBUF 4700 1300 ns | Time the bus must be free before a new transmission can start Output fall time from Vin TOF 250 20 +0.1 250 ns_ | (Note 1), Ca < 100 pF min to ViL max Ca Input filter spike suppres- TSP _ 50 _ 50 ns (Note 3) sion (SDA and SCL pins) Write cycle time TWR _ 10 _ 10 ms_ | Byte or Page mode Endurance _ 1M _ 1M _ cycles | 25C, Vcc = 5.0V, Block Mode (Note 4) Note 1: Not 100% tested. Ca = total capacitance of one bus line in pF. 2: As atransmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions 3: The combined Tsp and Vuys =specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website. FIGURE 1-2: BUSTIMING DATA TF TR THIGH TLOW SCL _ YF PR oe NEY i SL TSU:STA THD:DAT TSU:DAT Tsu:sTO>| THD:STA SDA TSP WA IN WM NY PN TAA TBUF SDA OUT 1998 Microchip Technology Inc. DS21054F-page 324AA16 2.0 FUNCTIONAL DESCRIPTION The 24AA16 supports a Bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24AA16 works as slave. Both, master and slave can operate as trans- mitter or receiver but the master device determines which mode is activated. 3.0 BUS CHARACTERISTICS The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-1). 3.1 Bus not Busy (A) Both data and clock lines remain HIGH. 3.2 Start Data Transfer (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condi- tion. 3.3 Stop Data Transfer (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. 3.4 Data Valid (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last 16 will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion. 3.5 Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24AA16 does not generate any acknowledge bits if an internal program- ming cycle is in progress. The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. FIGURE 3-1: _DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) (D) (C) | (A) SCL oo So > JT Tf Lt ee rt START ADDRESS OR DATA STOP CONDITION ACKNOWLEDGE ALLOWED CONDITION VALID TO CHANGE DS21054F-page 4 1998 Microchip Technology Inc.24AA16 3.6 Device Addressing Acontrol byte is the first byte received following the start condition from the master device. The control byte con- sists of a 4-bit control code, for the 24AA16 this is set as 1010 binary for read and write operations. The next three bits of the control byte are the block select bits (B2, B1, BO). They are used by the master device to select which of the eight 256 word blocks of memory are to be accessed. These bits are in effect the three most signif- icant bits of the word address. It should be noted that the protocol limits the size of the memory to eight blocks of 256 words, therefore the protocol can support only one 24AA16 per system. The last bit of the control byte defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operation is selected. Following the start condition, the 24AA16 monitors the SDA bus checking the device type identifier being transmitted, upon a 1010 code the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24AA16 will select a read 4.0 WRITE OPERATION 4.1 Byte Write Following the start condition from the master, the device code (4 bits), the block address (3 bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will fol- low after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmit- ted by the master is the word address and will be writ- ten into the address pointer of the 24AA16. After receiving another acknowledge signal from the 24AA16 the master device will transmit the data word to be written into the addressed memory location. The 24AA16 acknowledges again and the master gener- ates a stop condition. This initiates the internal write cycle, and during this time the 24AA16 will not generate acknowledge signals (Figure 4-1). or write operation. 4.2 Page Write : Control . . Operation Block Select R/W The write control byte, word address and the first data Code byte are transmitted to the 24AA16 in the same way as Read 1010 Block Address in a byte write. But instead of generating a stop condi- Write 1010 Block Address 0 tion the master transmits up to sixteen data bytes to the 24AA16 which are temporarily stored in the on-chip FIGURE 3-2: CONTROL BYTE page buffer and will be written into the memory after the ALLOCATION master has transmitted a stop condition. After the START READ/WRITE receipt of each word, the four lower order address pointer bits are internally incremented by one. The JavEApORESS higher order seven bits of the word address remains ve AD RES RW) A constant. If the master should transmit more than 16 ; , words prior to generating the stop condition, the a , address counter will roll over and the previously - received data will be overwritten. As with the byte write 1 0 1 0 B2 Bt BO operation, once the stop condition is received an inter- nal write cycle will begin (Figure 4-2). X = Don't care FIGURE 4-1: BYTE WRITE s s BUS ACTIVITY h CONTROL WORD DATA T MASTER R BYTE ADDRESS oO TY A oe AY A . ?P rT Td rT TT 7? Td SDA LINE S$ P | | | | | | | | | | | 4 A A A BUS ACTIVITY Cc Cc Cc K K K FIGURE 4-2: PAGE WRITE Ss s BUS ACTIVITY h T MASTER R CONTROL ADbabes (n) DATA n DATA n + 1 DATA n+ 15 . T A A A A A SDA LINE Le TTTITITI ETT ETE) (AY TT ETT Gl bivitrid bititrit bivitrit A\ LET 1 A A A A BUS ACTIVITY Cc Cc Cc Cc Cc K K K K K 1998 Microchip Technology Inc. DS21054F-page 524AA16 5.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master send- ing a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for flow diagram. FIGURE 5-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle t Send Start J Send Control Byte with R/W = 0 Did Device Acknowledge Next Operation 6.0 WRITE PROTECTION The 24AA16 can be used as a serial ROM when the WP pin is connected to Vcc. Programming will be inhib- ited and the entire memory will be write-protected. 7.0 READ OPERATION Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 7.1 Current Address Read The 24AA16 contains an address counter that main- tains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n+ 1. Upon receipt of the slave address with R/W bit set to one, the 24AA16 issues an acknowl- edge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24AA16 discontinues transmission (Figure 7-1). 7.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24AA16 as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24AA16 will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24AA16 dis- continues transmission (Figure 7-2). 7.3 Sequential Read Sequential reads are initiated in the same way as a ran- dom read except that after the 24AA16 transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24AA16 to transmit the next sequentially addressed 8-bit word (Figure 7-3). To provide sequential reads the 24AA16 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. 7.4 Noise Protection The 24AA16 employs a Vcc threshold detector circuit which disables the internal erase/write logic if the Vcc is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. DS21054F-page 6 1998 Microchip Technology Inc.24AA16 FIGURE 7-1: CURRENT ADDRESS READ S ; : BUS ACTIVITY CONTROL MASTER A BYTE DATA n > T, M. MD. . SDA LINE | | A N BUS ACTIVITY C Oo A C K FIGURE 7-2: RANDOM READ ; ; ; BUS ACTIVITY CONTROL WORD CONTROL Oo MASTER R BYTE ADDRESS (n) A BYTE DATA (n) P T, A A T. A A fs oils oil FF SDA LINE z z R N C C C Oo K K K BUS ACTIVITY A C K FIGURE 7-3: SEQUENTIAL READ S } teat IVITY CONTROL DATA n DATA n +1 DATA n+ 2 DATA n+ X Pp __. A. AN A oA 1 TTTTITT To. TTT TTT ToT TTT? \ TTTTTqT. SDA LINE | Ltt ft i td 1 J i | | jt J Litt | | 4 Lit it tt fi A A A A N BUS ACTIVITY Cc C C C Oo K K K K A C K 8.0 PIN DESCRIPTIONS 8.3 WP 8.1 SDA Serial Address/Data Input/ Output This is a Bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pullup resistor to Vcc (typical 10KQ for 100 kHz, 2 KQ for 400 kHz) from 24LC04B/08B. For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP condi- tions. 8.2 SCL Serial Clock This input is used to synchronize the data transfer from and to the device. This pin must be connected to either Vss or Vcc. If tied to VSs, normal memory operation is enabled (read/write the entire memory). If tied to Vcc, WRITE operations are inhibited. The entire memory will be write-protected. Read operations are not affected. This feature allows the user to use the 24AA16 as a serial ROM when WP is enabled (tied to Vcc). 8.4 AO, Ai, A2 These pins are not used by the 24AA16. They may be left floating or tied to either Vss or Vcc. 1998 Microchip Technology Inc. DS21054F-page 724AA16 NOTES: DS21054F-page 8 1998 Microchip Technology Inc.24AA16 NOTES: 1998 Microchip Technology Inc. DS21054F-page 924AA16 NOTES: DS21054F-page 10 1998 Microchip Technology Inc.24AA16 24AA16 Product Identification System To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed sales offices. 24AA16 - IP P = Plastic DIP (300 mil Body), 8-lead Package: SL = Plastic SOIC (150 mil Body), 14-lead SN = Plastic SOIC (150 mil Body), 8-lead Temperature Blank = 0C to +/0C Range: I = -40C to +85C Device: 24AA16 1.8K, 16K I?C Serial EEPROM , 24AA16T 1.8K, 16K I?C Serial EEPROM (Tape and Reel) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip Worldwide Web Site (www.microchip.com) 1998 Microchip Technology Inc. DS21054F-page 11MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http:/Avww.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588 Dayton Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175 Detroit Microchip Technology Inc. 42705 Grand River, Suite 201 Novi, MI 48375-1727 Tel: 248-374-1888 Fax: 248-374-2878 Los Angeles Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 714-263-1888 Fax: 714-263-1338 New York Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 516-273-5305 Fax: 516-273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 AMERICAS (continued) Toronto Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253 ASIA/PACIFIC Hong Kong Microchip Asia Pacific RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431 India Microchip Technology Inc. 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Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883 6/11/98 @ ANSI-RAB , * ts :* eww 9001 REGISTERED FIRM DNV Certification, Inc. DNV MSC USA The Netherlands of ED ', Accredited by the RvA . nN, Microchip received 1SO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmable PICmicro 8-bit MCUs, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO). All rights reserved. 1998, Microchip Technology Incorporated, USA. 7/98 > Printed on recycled paper. Information cxttained in this publication regarding device applications and the like is intended for suggestion oily and may he superseded by updates. No representation or warranty is given and no liakility is assumed by Microchip Technology Incorporated with respect to the acauracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical amporents in life support systems is not authorized emect with express written agoroval by Microchip. No licenses are amveyed, implicitly or otherwise, under any intellectual property rights. The Microchip lego and name are registered trademarks of Microchip Tecilcgy Inc. in the U.S.A. and other camtries. All rights reserved. All other trademarks mentioned herein are the property of their respective cmpanies. DS21058l-page 16 1998 Microchip Technology Inc.