Product Brief
August 2000
TAPC640
High-Speed Switching ATM Port Controller (APC)
Introduction
The ATM port controller (APC) IC is part of the Agere
Systems, Inc. high-speed switching chip set that
provides a highly integrated, innovative, and com-
plete VLSI solution for implementing the ATM layer
func ti ona l ity/ c ore of a n ATM switch syst em. The ch i p
set enables construction of high-performance, fea-
ture rich, and cost-effective asynchronous transfer
mode (ATM) switches, scalable over a wide range of
switching capacities.
Features
■Provides a comprehensive single-chip solution for
implementing all ATM layer functions needed at an
ATM switch port.
■Can be configured in a variety of switching modes
for flexible operation:
— Performs as an ATM switch port card by sup-
porting linear aggregation of up to 622 Mbits/s of
ATM traffic at the physical layer interface (full
duplex).
— Operates as a stand-alone, single-chip 32 × 32
shared memory switch or an N:1 concentrator
(622 Mbits/s tot al switching) .
— Operates in conjunction with another APC as a
2 × 2 (1.2 Gbits/s total switching capacity) dual
APC-based switch (no separate ext ernal switch
fabric needed).
■Performs ATM layer user network interface (UNI )
and network nod e interfac e (NN I) man age men t
functions.
■Provides two independently operating full-duplex
UTOPIA II compatible interfaces:
— Controls up to 31 full-duplex multiple physical
layer (MPHY) p orts on the physical layer side.
— Allows either UTOPIA interface to operate as
16-bit or 8-bit data.
— Allows any MPHY to be configured as a UNI or
NNI.
■Supports up to 64K connections with scalable
external memory:
— Manages virtual connection parameter table in
external memory.
— Optionally performs the ATM Forum compliant
dual leaky-bucket policing for up to 64K VCs.
— Facilitates call setup and tear down through VC
parameter table update via high-performance
microprocessor port .
— Optionally translates or passes the generic flow
control (GFC) field of the egress ATM cell
header for NNI or UNI applications.
— Performs virtual path identifier (VPI)/virtual
channel identifier (VCI) translation for up to 64K
connections on egress while allowing reusability
of same VPI/VCI on different UNIs.
■Maintains a variety of optional per-connection, per-
port, and per-device statistics counters in external
memory and on-chip.
■Provides dual interfaces to high-speed switching
switch fabrics to facilitate construction of redundant
systems for fault tolerance.
■Supports spatial and logical multicasting for up to
32 destination ports on egress (31 MPHY ports
and 1 microprocessor interface port).
■Provides a generic 32-bit microprocessor interface
with interrupt.
■Supports high-speed read and write direct memory
access (DMA) modes for cell extraction and inser-
tion via the microproc essor interface.
■Provides input/output (bidirectional) queue man-
agement for an N × N switch fabric for over
100 Gbits/s capacity and up to 31 MPHY ports
and one microprocessor port:
— Queues up to 512K ATM cells in external mem-
ory, organized in a per-VC, fully-shared queue-
ing architecture.
— Supp orts five traffic classes via novel schedul-
ing algorithms, including a WFQ type scheduler
to provide per-VC QoS assurance.
2Agere Systems Inc.
Product Brief
August 2000
High-Speed Switching ATM Port Controller (APC)
TAPC640
Features (continued)
■Implements a flexible, efficient buffer/congestion
management scheme based on a Bell Labs’ pat-
ented adaptive dynamic thresholding (ADT) algo-
rithm:
— Supports selective cell discard and early/partial
packet d i scard (EPD/ PPD).
— Provides capability for minimum buffer reserva-
tions on per-connection, per-class, and per-port
basis.
■Pe rforms ATM Forum-compliant available bit rate
(ABR) explicit rate flow control using a Bell Labs’ pat-
ented algorithm. Provides optional support for EFCI
marking as well.
■Provides operations, administration, and mainte-
nance (OA&M) Fault Management functions for loop-
back, continuity check, defect indication on all
connections, and performance monitoring on up to
127 connections.
■Can be used in conjunction with an external switch
fabric (LUC4AS01 (ASX) and LUC4AC01 (ACE) ICs,
part of the high-speed switching chip set) to provide
a scalable, nonblocking switch solution for over
100 Gbits/ s capacity.
■Supports bandwidth scalability to OC-48 rates via
use of external PIMUX devices on the PHY layer
side.
■Provides an enhanced services interface (ESI) to
support operation of an optional external adjunct
device for comprehensive statistical data collection.
■Facilitates circuit board testing with on-chip IEEE*
boundary scan.
■Fabricated as a low-power, monolithic IC in submi-
cron 0.25 µm, 3.3 V CMOS technology, with 5 V tol-
erant and TTL-level compatible I/O.
■Available in a 600-pin LBGA package.
Applications
■ATM swi tches
■x-DSL systems
■DLC systems
■ADM
■Access multiplexers
■Routers
■PBX
■Wireless infrastructure equipment
■VP rings
*IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Agere Systems Inc. 3
Product Brief
August 2000 High-Speed Switching ATM Port Controller (APC)
TAPC640
Description
Block Diagram
Figure 1 presents a block diagram of the APC chip. Each high-level block function is summarized in this section.
5-8009(F)r.2
Figure 1. High-Level Block Diagram of the APC IC
SXI
FABRIC
INTERFACE
FABRIC
INTERFACE
B
A
HLX
HEADER LOOK-UP
AND TRANSLATION GCR
POLICING GCR/BMX
THRESHOLDING BRI
CELL BUFFER/POINTER
MEMORY INTERFACE
UPI
UTOPIA
INTERFACE
UTOPIA
INTERFACE
B
A
SOX/NMX
STATISTICS AND
OAM CONTROLLER
AFE/XRE
ABR FLOW
CONTROL ENGINE
iQSC
INGRESS QUEUE
SCHEDULER
MPI
MICROPROCESSOR I/F
AND CONFIG. REGISTERS
TCT
TIME WCK
WORLD ESI
ENHANCED
SERVICE RST
RESET
COUNTER CLOCK INTERFACE DRIVERS
JTG
TEST ACCESS
PORT AND SCAN
CONTROLLER
CRAM
CONTROL
MEMORY
PRAM
POINTER
MEMORY
BRAM
CELL BUFFER
MEMORY
VCRAM
VC TABLES
MEMORY
UTOPIA 2+
(PORT A)
UTOPIA 2+
(PORT B)
TO/FROM
MPHY DEVICES
TO/FROM AN
ATLANTA
™ FABRIC
PORT A
PORT B
MICROPROCESSOR SYNCHRONIZATION
PULSE SYSTEM
CLOCK ADJUNCT
DEVICE SYSTEM
RESET SYSTEM
TEST
SSRAM SDRAM
APC IC
VCT
VIRTUAL
CONNECTION
TABLE MEMORY I/F
eQSC
EGRESS QUEUE
SCHEDULER
4Agere Systems Inc.
Product Brief
August 2000
High-Speed Switching ATM Port Controller (APC)
TAPC640
Description (continued)
UTOPIA Interface (UPI)
The UPI controls the transfer of ATM cells between the
APC and mul tiple physical layer devices (MPHYs) con-
nected to it, via two full-duplex UTOPIA Level II com-
patible interfaces operating independently at up to
52 MHz.
The UPI supports linear aggregation of ATM traffic up
to 622 Mbits/s. Each UTOPIA interface can be enabled
independently and is always a bus master. Receive
parity checking can be enabled or disabled. Transmit
parity generation can be configured as odd or even.
Each transmit interface can be configured to internally
loopback cells to its receive interface independently for
diagnostic purposes.
Additionally, the UPI can support an extended cell for-
mat and an external port inverse multiplexer (PIMUX)
device to interface with link rates greater than
622 Mbits/s such as OC-48 trunks.
Each interface can be independently configured to
operate in 16-bit or 8-bit mode (for UTOPIA Level 1
compatibility), with a standard or extended cell format
and its own contiguous UTOPIA poll address range to
support up to 31 MPHY devices*.
For spec ial cel ls (OA&M and RM) , the UPI als o checks
(on receive) and inserts (on transmit) the payload CRC-
10 field.
Header Look-Up and Con t rol Memory Inter-
face (HLX)
The HLX performs a three-level ingress look-up and
one-level egress look-up in external memory to fetch
connection information for up to 64K ingress and
egress connections. The HLX supports MPHY port
configuration (UNI or NNI), VP or VC switching, ATM
header validation, ingress cell capture and cell recogni-
tion (e.g., RM and OA&M cells).
Additionally, the HLX accesses control memory tables
maintained in external synchronous static memory,
SSRAM (CRAM), to support queuing, scheduling
(QSC), and OA&M (NMXSOX) operations.
Virtual Connection Table Memor y Interface
(VCT)
The VCT handles all the necessary operations needed
to read, write, and refresh the ingress and egress vir-
tual connection parameter tables, maintained in exter-
nal SDRAM (VCRAM) for up to 64K connections.
Policing Generic Cell Rate (GCR)
The GCR implements two instances of the generic cell
rate algorithm (GCRA) for each connection to police
cells for conformance to their negotiated traffic con-
tracts. It uses the virtual scheduling algorithm outlined
in ITU-T I.371 to determine conformance. Seven possi-
ble policing configurations are supported for each
GCRA instance including all the conformance defini-
tions specified in ATM Forum Traffic Management
Specification Version 4.0.
Policing can be enabled or disabled on a per-connec-
tion basis, or globally enabled or disabled. The policing
action, monitor, tag, or drop can be programmed sepa-
rately for each individual leaky bucket on a per-connec-
tion basis. The range of policed rates goes from
424 bits/s (one cell per second) to the maximum sup-
ported rate of 622 Mbits/s.
Buff er Management Controll er (BMX)
The GCRBMX block performs buffer management
functions, by checking a variety of per-connection, per-
port, and per-traffic class thresholds. They are used to
drop a cell before it is queued.
A CLP0 +1 di scard thr esho ld, an opt ion al CL P1 d iscar d
threshold, and an optional early packet discard (EPD)
threshold are provided for each connection on ingress
and egress. These thresholds can be configured as
static or dynamic.
The dynamic threshold is based on an effective buffer
allocation for the connection. This allocation is not used
directly as the discard threshold. The overall reserve
and specific congestion conditions add to or subtract
from the buffer allocation to continuously adjust the
threshold. These adjustments are based on the avail-
able reserve of the common buffer pool and the con-
gestion threshold established for the traffic class to
which the connection belongs. This balances the
losses of the given circuit against the overall state of
the system. A guaranteed minimum buffer space is
supported during periods of heavy buffer use.
* Only 31 MPHY dev ice s c an be s uppor ted over the two UTOPIA interfaces
combined.
Agere Systems Inc. 5
Product Brief
August 2000 High-Speed Switching ATM Port Controller (APC)
TAPC640
Description (continued)
Buffer Management Controller (BMX)
(continued)
The buffer is logically partitioned so that each traffic
class can support a different buffer reservation inde-
pendent of other classes. Additional mechanisms are
provided to control the sharing of buffers between ports
with minimum guarantees for each port.
An opt ional partial packet discar d (PPD) mode is sup-
ported for each connection. A static selective explicit
forward congestion indicator (SEFCI) marking thresh-
old is also provided. EFCI marking can be selectively
enabled for each connection.
Cell Buffer Memory Interface (BRI)
The BRI handles all the necessary operations needed
to read, write, and refresh the cell data in ingress and
egress cell buffer pools maintained in external SDRAM
(BRAM). The BRI supports up to 512K cell buffers
which can be statically partitioned between ingress
and egress without restriction. The BRI performs cell
enqueue and dequeue operations and serves also as
interme diate cel l sto ra ge to suppor t NMXS OX and
XREAF E operation s.
Additionally, the BRI manages the communication
between the APC and the ingress and egress cell
pointer memory maintained in external SDRAM
(PRAM).
Ingress Que ue Sch edu le r (iQ SC )
The iQSC implements a sophisticated per virtual con-
nection queue architecture and hierarchical scheduling
algorithms for ingress.
The iQSC performs the virtual connection enqueue and
dequeue operations, which are supported by the HLX,
VCT, and BRI blocks.
The iQSC provides novel scheduling algorithms to ser-
vice up to 64K VC queues and five traffic classes
(CBR, rt-VBR, nrt-VBR, ABR, and UBR) using a three-
level hierarchy. The first (VC) level of the hierarchy
contains per-VC schedulers for each of the five traffic
classes. Each VC scheduler can support all 64K VC
queues as needed. The second (class) level of the
hierarchy contains two class schedulers: one to pro-
vide guaranteed bandwidth and one to distribute
excess bandwidth to each work-conserving VC sched-
uler. The third (port merge) level of the hierarchy
merges the CBR VC scheduler and the two class
schedulers together.
The CBR scheduler uses a non-work-conserving
shaped virtual clock (ShVC) algorithm to shape CBR
virtual connections to any one of up to 32 user-pro-
grammable rates.
The rt-VBR scheduler uses a work-conserving starting
potential fair queuing (SPFQ) algorithm to schedule vir-
tual connections using any one of up to 16 user-pro-
gra mmable rat es/weights.
nrt-VBR, ABR, and UBR schedulers each use a work-
conserving variable length frame based weighted
round-robin (WRR) algorithm to schedule virtual con-
nections using one of up to 256K different weights.
The guaranteed traffic class scheduler (GTS) uses the
ShVC algorithm to provide guaranteed bandwidth to
each of four classes (the rt-VBR, nrt-VBR, ABR, and
UBR VC schedulers). A user-programmable rate is
provided for each class.
The excess bandwidth class scheduler (EBS) uses a
work-conserving self-clocked fair queuing (SCFQ)
algorithm to fairly allocate excess bandwidth to each of
four classes (the rt-VBR, nrt-VBR, ABR, and UBR VC
schedulers). A user-programmable weight is provided
for each class.
The port merge sc hed uler merg es the CBR VC sched -
uler and the GTS class scheduler together with strict
priority over the EBS class scheduler. CBR and GTS
service is arbitrated at this level using timestamps.
Switch Fabric Interface (SXI)
The SXI implements an interface to ATLANTA swi tc h
fabrics, as well as a loopback mode for a single APC
stand-alone operation. The SXI interface consists of an
8-bit parallel data bus plus additional control signals
and clock, operating at up to 100 MHz. The SXI termi-
nates the simple ATLANTA fabric interface protocol.
The transmit interface can be configured to generate
odd or even parity. The receive interface checks for
odd parity and protocol violations. It also extracts the
fabric backpressure information from the cell header.
This interface is duplicated to allow construction of
redundant switch fabric architectures for fault toler-
ance, and 1.2 Gbits/s fabric-less switches using two
APCs. Each transmit interface can be independently
enabled and dis ab led .
6Agere Systems Inc.
Product Brief
August 2000
High-Speed Switching ATM Port Controller (APC)
TAPC640
Description (continued)
Egress Queue Scheduler (eQSC )
The eQSC implements a sophisticated per virtual con-
nection queue architecture and hierarchical scheduling
algorithm for egress.
The eQSC performs the virtual connection enqueue,
dequeue, and subport spatial and logical multicast
operations, which are supported by the HLX, VCT,
and BRI blocks.
It provides novel scheduling algorithms to service up to
64K VC queues, five traffic classes (CBR, rt-VBR, nrt-
VBR, ABR, and UBR), and 32 subports using a four-
level hierarchy.
Subports 0 to 15 are designated as type 1 and have
dedicated three-level hierarchical schedulers similar to
iQSC. The first (VC) level of the hierarchy contains per-
VC schedulers for each of the five traffic classes. Each
VC scheduler can support all 64K VC queues as
needed. The second (class) level of the hierarchy con-
tains two class schedulers: one to provide guaranteed
bandwidth and one to distribute excess bandwidth to
each work-conserving VC scheduler. The third (port
merge) level of the hierarchy merges the CBR VC
scheduler and the two class schedulers together .
The type 1 CBR scheduler uses a non-work-conserv-
ing asynchronously shaped virtual clock (AShVC) algo-
rithm to shape CBR vi rtual conne ct ion s to any one of
up to 32 user-programmable rates.
The type 1 rt-VBR scheduler uses a work-conserving
starting potential fair queuing (SPFQ) algorithm to
schedule virtual connections using any one of up to
16 user-p rogr amm abl e rat es/ wei ghts.
The type 1 nrt-VBR, ABR, and UBR schedulers each
use a work-conserving variable length frame based
weighted round-robin (WRR) algorithm to schedule
virtual connections using one of up to 256K different
weights.
The guaranteed traffic class scheduler (GTS) uses the
ShVC algorithm to provide guaranteed bandwidth to
each of four classes (the rt-VBR, nrt-VBR, ABR, and
UBR VC schedulers). A user-programmable rate is
provided for each class.
The excess bandwidth class scheduler (EBS) uses a
work-conserving self-clocked fair queuing (SCFQ)
algorithm to fairly allocate excess bandwidth to each of
four classes (the rt-VBR, nrt-VBR, ABR, and UBR VC
schedulers). A user-programmable weight is provided
for each class.
The port merge scheduler merges the CBR VC sched-
uler and the GTS class scheduler together with strict
priority over the EBS class scheduler. CBR and GTS
service is arbitrated at this level using timestamps.
Subports 16 to 31 are designated as type 2 and have
dedicated two-level hierarchical schedulers. The first
(VC) level of the hierarchy contains per-VC schedulers
for each of the five traffic classes. Each VC scheduler
can support all 64K VC queues as needed. The second
(class) level of the hierarchy merges the VC schedulers
together.
The type 2 CBR, rt-VBR, nrt-VBR, ABR, and UBR
schedulers each use a work-conserving variable length
frame based weighted round-robin (WRR) algorithm
to schedule virtual connections using one of up to
256K different weights.
The type 2 clas s scheduler s can be configured (fo r all
16 subports as a group) to use either an AShVC algo-
rithm to shape each of the VC schedulers or a SCFQ
algorithm to fairly allocate bandwidth to each of the
classes. A user-programmable rate or weight is pro-
vided for each class. When the type 2 schedulers are
configured for AShVC, they each provide five shaped
pipes of virtual connections.
The top level (subport scheduler) of the hierarchy uses
a non-work-conserving shaped virtual clock (ShVC)
algorithm to shape each of the subport schedulers to its
user-programmable rate. Two additional configuration
options are provided to allow excess bandwidth to be
granted to subport 31 (the microprocessor capture
port) and a user-identified SAR port for work-conserv-
ing operation on those ports.
Following the subport scheduler is a virtual MPHY
mapping function. The default configuration provides a
one-to-one mapping between subport scheduler and
MPHY address. This function can be configured by the
user to map multiple subport schedulers to the same
UTOPIA port. This allows multiple virtual MPHYs to be
created within one physical MPHY device.
Agere Systems Inc. 7
Product Brief
August 2000 High-Speed Switching ATM Port Controller (APC)
TAPC640
Description (continued)
St atistics/OA&M Controller (NMXSOX)
The NMXSOX implements ingress and egress OA&M
functions as specified in the ITU and Bellcore recom-
mendations.
Its main functions are OA&M cell type recognition and
validation, and implementation of fault management
defect indication, loopback, continuity check on all
connections, and performance monitoring for up to
127 OA&M processes.
The N MXSOX also maintains per-connecti on as well
as per-port and global cell event information (arriving/
departing, enqueued/dequeued cells, and related time-
stamps) which can be communicated to an external
adjunct device for connection statistics collection and
performance monitoring data collection.
Enhanced Services Interfac e (ESI)
NMXESI implements a 16-bit parallel interface
between the APC and an optional external adjunct
device to support value-added enhanced services. The
APC reports a rich set of events through this interface
to support the implementation of virtually any customer
desired per-connection, per-port, or per-device statistic
in the external device.
ABR Flow Control Engine (XREAFE)
The ABR flow control engine (AFE) operates on
ingress and egress ABR traffic to control switch and
network congestion. The user has the option to globally
select among different flow control algorithms imple-
mented by the AFE. These are the selective EFCI
marking algorithm and a Bell Labs’ patented algorithm.
The ABR flow control algorithm can selectively operate
on a minimum cell rate (MCR) plus equal share or pro-
portional to MCR basis.
Only one ABR flow control algorithm can be active at a
given time. The AFE also supports backward RM cell
consolidation for up to 1023 fabric port multicast con-
nections and 1023 egress subport multicast connec-
tions.
To support its operations, the AFE performs RM cell
validation and calculates queue lengths and traffic load
on subports (egress) or fabric ports (ingress).
Micropro cessor Interface (MPI)
The MPI provides a generic 32-bit asynchronous
microprocessor interface with maskable interrupts.
This allows an external processor to access the APC
for configuration, maintenance, statistics, internal and
external memory reads and writes, as well as interrupt
services.
The MPI also provides high-performance DMA support
for fast cell insertion and extraction via FIFOs at the
microprocessor interface.
Global Time Counter (TCT)
The TCT generates all the signals necessary for inter-
nal event synchronization. It also generates the exter-
nal synchronization pulse GTSYNC.
Global Clock (WCK)
WCK generates all the clocks needed in the APC, as
well as the output fabric clocks.
Reset Driver (RST)
RST synchronizes an externally applied, active-low,
asynchronous reset pulse, and generates all the sig-
nals needed to reset the internal blocks of the APC.
Reset is applied synchronously on each of the internal
clock domains of the APC.
JTAG Test Access Port (JTG)
The APC incorporates logic to support a standard 5-pin
test access port (TAP), compatible with the IEEE
1149.1 standard (JTAG), used for boundary scan. TAP
contains instruction registers, data registers, and con-
trol logic. It is controlled externally by a JTAG bus mas-
ter. The JTG gives the APC board-level test capability.
Copyright © 2000 Agere Systems Inc.
All Rights Reserved
August 2000
PB00-120ATM
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.
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