DAC128S085CISQX/NOPB - NATIONAL SEMICONDUCTOR

DAC128S085

DAC128S085 12-Bit Micro Power OCTAL Digital-to-Analog Converter with

Rail-to-Rail Outputs

Literature Number: SNAS407D

DAC128S085

March 10, 2009

12-Bit Micro Power OCTAL Digital-to-Analog Converter

with Rail-to-Rail Outputs

General Description

The DAC128S085 is a full-featured, general purpose OCTAL

12-bit voltage-output digital-to-analog converter (DAC) that

can operate from a single +2.7V to +5.5V supply and con-

sumes 1.95 mW at 3V and 4.85 mW at 5V. The DAC128S085

is packaged in a 16-lead LLP package and a 16-lead TSSOP

package. The LLP package makes the DAC128S085 the

smallest OCTAL DAC in its class. The on-chip output ampli-

fiers allow rail-to-rail output swing and the three wire serial

interface operates at clock rates up to 40 MHz over the entire

supply voltage range. Competitive devices are limited to 25

MHz clock rates at supply voltages in the 2.7V to 3.6V range.

The serial interface is compatible with standard SPI™, QSPI,

MICROWIRE and DSP interfaces. The DAC128S085 also of-

fers daisy chain operation where an unlimited number of

DAC128S085s can be updated simultaneously using a single

serial interface.

There are two references for the DAC128S085. One refer-

ence input serves channels A through D while the other

reference serves channels E through H. Each reference can

be set independently between 0.5V and VA, providing the

widest possible output dynamic range. The DAC128S085 has

a 16-bit input shift register that controls the mode of operation,

the power-down condition, and the DAC channels' register/

output value. All eight DAC outputs can be updated simulta-

neously or individually.

A power-on reset circuit ensures that the DAC outputs power

up to zero volts and remain there until there is a valid write to

the device. The power-down feature of the DAC128S085 al-

lows each DAC to be independently powered with three dif-

ferent termination options. With all the DAC channels

powered down, power consumption reduces to less than 0.3

µW at 3V and less than 1 µW at 5V. The low power consump-

tion and small packages of the DAC128S085 make it an

excellent choice for use in battery operated equipment.

The DAC128S085 is one of a family of pin compatible DACs,

including the 8-bit DAC088S085 and the 10-bit DAC108S085.

All three parts are offered with the same pinout, allowing sys-

tem designers to select a resolution appropriate for their

application without redesigning their printed circuit board. The

DAC128S085 operates over the extended industrial temper-

ature range of −40°C to +125°C.

Features

■Guaranteed Monotonicity

■Low Power Operation

■Rail-to-Rail Voltage Output

■Daisy Chain Capability

■Power-on Reset to 0V

■Simultaneous Output Updating

■Individual Channel Power Down Capability

■Wide power supply range (+2.7V to +5.5V)

■Dual Reference Voltages with range of 0.5V to VA

■Operating Temperature Range of −40°C to +125°C

■Industry's Smallest Package

Key Specifications

■Resolution 12 bits

■INL ±8 LSB (max)

■DNL +0.75 / −0.4 LSB (max)

■Settling Time 8.5 µs (max)

■Zero Code Error +15 mV (max)

■Full-Scale Error −0.75 %FSR (max)

■Supply Power

■—Normal 1.95 mW (3V) / 4.85 mW (5V) typ

—Power Down 0.3 µW (3V) / 1 µW (5V) typ

Applications

■Battery-Powered Instruments

■Digital Gain and Offset Adjustment

■Programmable Voltage & Current Sources

■Programmable Attenuators

■Voltage Reference for ADCs

■Sensor Supply Voltage

■Range Detectors

Ordering Information

Order Numbers Temperature Range Package Top Mark

DAC128S085CISQ −40°C ≤ TA ≤ +125°C 16-Lead LLP

DAC128S085CISQX −40°C ≤ TA ≤ +125°C LLP Tape-and-Reel

DAC128S085CIMT −40°C ≤ TA ≤ +125°C 16-Lead TSSOP X78C

DAC128S085CIMTX −40°C ≤ TA ≤ +125°C TSSOP Tape-and-Reel X78C

DAC128S085EB Evaluation Board - BOTH

SPI™ is a trademark of Motorola, Inc.

DAC128S085 12-Bit Micro Power OCTAL Digital-to-Analog Converter with Rail-to-Rail Outputs

Block Diagram

30016903

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DAC128S085

Pin Configuration

30016901

30016902

Pin Descriptions

LLP

Pin No.

TSSOP

Pin No. Symbol Type Description

1 3 VOUTA Analog Output Channel A Analog Output Voltage.

2 4 VOUTB Analog Output Channel B Analog Output Voltage.

3 5 VOUTC Analog Output Channel C Analog Output Voltage.

4 6 VOUTD Analog Output Channel D Analog Output Voltage.

5 7 VASupply Power supply input. Must be decoupled to GND.

6 8 VREF1 Analog Input Unbuffered reference voltage shared by Channels A, B, C, and D.

Must be decoupled to GND.

7 9 VREF2 Analog Input Unbuffered reference voltage shared by Channels E, F, G, and H.

Must be decoupled to GND.

8 10 GND Ground Ground reference for all on-chip circuitry.

9 11 VOUTH Analog Output Channel H Analog Output Voltage.

10 12 VOUTG Analog Output Channel G Analog Output Voltage.

11 13 VOUTF Analog Output Channel F Analog Output Voltage.

12 14 VOUTE Analog Output Channel E Analog Output Voltage.

13 15 SYNC Digital Input

Frame Synchronization Input. When this pin goes low, data is

written into the DAC's input shift register on the falling edges of

SCLK. After the 16th falling edge of SCLK, a rising edge of SYNC

causes the DAC to be updated. If SYNC is brought high before the

15th falling edge of SCLK, the rising edge of SYNC acts as an

interrupt and the write sequence is ignored by the DAC.

14 16 SCLK Digital Input Serial Clock Input. Data is clocked into the input shift register on

the falling edges of this pin.

15 1 DIN Digital Input Serial Data Input. Data is clocked into the 16-bit shift register on

the falling edges of SCLK after the fall of SYNC.

16 2 DOUT Digital Output

Serial Data Output. DOUT is utilized in daisy chain operation and is

connected directly to a DIN pin on another DAC128S085. Data is

not available at DOUT unless SYNC remains low for more than 16

SCLK cycles.

17 PAD

(LLP only) Ground

Exposed die attach pad can be connected to ground or left floating.

Soldering the pad to the PCB offers optimal thermal performance

and enhances package self-alignment during reflow.

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DAC128S085

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage, VA6.5V

Voltage on any Input Pin −0.3V to 6.5V

Input Current at Any Pin (Note 3) 10 mA

Package Input Current (Note 3) 30 mA

Power Consumption at TA = 25°C See (Note 4)

ESD Susceptibility (Note 5)

Human Body Model

Machine Model

Charge Device Mode

2500V

250V

1000V

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

Operating Ratings (Notes 1, 2)

Operating Temperature Range −40°C ≤ TA ≤ +125°C

Supply Voltage, VA+2.7V to 5.5V

Reference Voltage, VREF1,2 +0.5V to VA

Digital Input Voltage (Note 7) 0.0V to 5.5V

Output Load 0 to 1500 pF

SCLK Frequency Up to 40 MHz

Package Thermal Resistances

Package θJA

16-Lead LLP 38°C/W

16-Lead TSSOP 130°C/W

Soldering process must comply with National

Semiconductor's Reflow Temperature Profile specifications.

Refer to www.national.com/packaging. (Note 6)

Electrical Characteristics

The following specifications apply for VA = +2.7V to +5.5V, VREF1 = VREF2 = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code

range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.

Symbol Parameter Conditions Typical Limits

(Note 8)

Units

(Limits)

STATIC PERFORMANCE

Resolution 12 Bits (min)

Monotonicity 12 Bits (min)

INL Integral Non-Linearity ±2.0 ±8 LSB (max)

DNL Differential Non-Linearity +0.15 +0.75 LSB (max)

−0.09 −0.4 LSB (min)

ZE Zero Code Error IOUT = 0 +5 +15 mV (max)

FSE Full-Scale Error IOUT = 0 −0.1 −0.75 % FSR (max)

GE Gain Error −0.2 −1.0 % FSR (max)

ZCED Zero Code Error Drift −20 µV/°C

TC GE Gain Error Tempco −1.0 ppm/°C

OUTPUT CHARACTERISTICS

Output Voltage Range 0

VREF1,2

V (min)

V (max)

IOZ

High-Impedance Output

Leakage Current (Note 9) ±1 µA (max)

ZCO Zero Code Output

VA = 3V, IOUT = 200 µA 10 mV

VA = 3V, IOUT = 1 mA 45 mV

VA = 5V, IOUT = 200 µA 8 mV

VA = 5V, IOUT = 1 mA 34 mV

FSO Full Scale Output

VA = 3V, IOUT = 200 µA 2.984 V

VA = 3V, IOUT = 1 mA 2.933 V

VA = 5V, IOUT = 200 µA 4.987 V

VA = 5V, IOUT = 1 mA 4.955 V

IOS

Output Short Circuit Current

(source) (Note 10)

VA = 3V, VOUT = 0V,

Input Code = FFFh −50 mA

VA = 5V, VOUT = 0V,

Input Code = FFFh −60 mA

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DAC128S085

Symbol Parameter Conditions Typical Limits

(Note 8)

Units

(Limits)

IOS

Output Short Circuit Current (sink)

(Note 10)

VA = 3V, VOUT = 3V,

Input Code = 000h 50 mA

VA = 5V, VOUT = 5V,

Input Code = 000h 70 mA

Continuous Output Current per

channel (Note 9)

TA = 105°C 10 mA (max)

TA = 125°C 6.5 mA (max)

CLMaximum Load Capacitance RL = ∞1500 pF

RL = 2kΩ1500 pF

ZOUT DC Output Impedance 8 Ω

REFERENCE INPUT CHARACTERISTICS

VREF1,2

Input Range Minimum 0.5 2.7 V (min)

Input Range Maximum VAV (max)

Input Impedance 30 kΩ

LOGIC INPUT CHARACTERISTICS

IIN Input Current (Note 9) ±1 µA (max)

VIL Input Low Voltage VA = 2.7V to 3.6V 1.0 0.6 V (max)

VA = 4.5V to 5.5V 1.1 0.8 V (max)

VIH Input High Voltage VA = 2.7V to 3.6V 1.4 2.1 V (min)

VA = 4.5V to 5.5V 2.0 2.4 V (min)

CIN Input Capacitance (Note 9) 3pF (max)

POWER REQUIREMENTS

Supply Voltage Minimum 2.7 V (min)

Supply Voltage Maximum 5.5 V (max)

Normal Supply Current for supply

pin VA

fSCLK = 30 MHz,

output unloaded

VA = 2.7V

to 3.6V 460 560 µA (max)

VA = 4.5V

to 5.5V 650 830 µA (max)

Normal Supply Current for VREF1 or

VREF2

fSCLK = 30 MHz,

output unloaded

VA = 2.7V

to 3.6V 95 130 µA (max)

VA = 4.5V

to 5.5V 160 220 µA (max)

IST

Static Supply Current for supply pin

fSCLK = 0,

output unloaded

VA = 2.7V

to 3.6V 370 µA

VA = 4.5V

to 5.5V 440 µA

Static Supply Current for VREF1 or

VREF2

fSCLK = 0,

output unloaded

VA = 2.7V

to 3.6V 95 µA

VA = 4.5V

to 5.5V 160 µA

IPD

Total Power Down Supply Current

for all PD Modes

(Note 9)

fSCLK = 30 MHz, SYNC =

VA and DIN = 0V after PD

mode loaded

VA = 2.7V

to 3.6V 0.2 1.5 µA (max)

VA = 4.5V

to 5.5V 0.5 3.0 µA (max)

fSCLK = 0, SYNC = VA and

DIN = 0V after PD mode

loaded

VA = 2.7V

to 3.6V 0.1 1.0 µA (max)

VA = 4.5V

to 5.5V 0.2 2.0 µA (max)

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DAC128S085

Symbol Parameter Conditions Typical Limits

(Note 8)

Units

(Limits)

Total Power Consumption (output

unloaded)

fSCLK = 30 MHz

output unloaded

VA = 2.7V

to 3.6V 1.95 3.0 mW (max)

VA = 4.5V

to 5.5V 4.85 7.0 mW (max)

fSCLK = 0

output unloaded

VA = 2.7V

to 3.6V 1.68 mW

VA = 4.5V

to 5.5V 3.80 mW

PPD

Total Power Consumption in all PD

Modes,

(Note 9)

fSCLK = 30 MHz, SYNC =

VA and DIN = 0V after PD

mode loaded

VA = 2.7V

to 3.6V 0.6 5.4 µW (max)

VA = 4.5V

to 5.5V 2.5 16.5 µW (max)

fSCLK = 0, SYNC = VA and

DIN = 0V after PD mode

loaded

VA = 2.7V

to 3.6V 0.3 3.6 µW (max)

VA = 4.5V

to 5.5V 111 µW (max)

A.C. and Timing Characteristics

The following specifications apply for VA = +2.7V to +5.5V, VREF1,2 = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range

48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.

Symbol Parameter Conductions Typical Limits

(Note 8)

Units

(Limits)

fSCLK SCLK Frequency 40 30 MHz (max)

Output Voltage Settling Time

(Note 9)

400h to C00h code change

RL = 2kΩ, CL = 200 pF 68.5 µs (max)

SR Output Slew Rate 1 V/µs

GI Glitch Impulse Code change from 800h to 7FFh 40 nV-sec

DF Digital Feedthrough 0.5 nV-sec

DC Digital Crosstalk 0.5 nV-sec

CROSS DAC-to-DAC Crosstalk 1 nV-sec

MBW Multiplying Bandwidth VREF1,2 = 2.5V ± 2Vpp 360 kHz

THD+N Total Harmonic Distortion Plus Noise VREF1,2 = 2.5V ± 0.5Vpp

100Hz < fIN < 20kHz −80 dB

ONSD Output Noise Spectral Density DAC Code = 800h, 10kHz 40 nV/sqrt(Hz)

ON Output Noise BW = 30kHz 14 µV

tWU Wake-Up Time VA = 3V 3 µsec

VA = 5V 20 µsec

1/fSCLK SCLK Cycle Time 25 33 ns (min)

tCH SCLK High time 7 10 ns (min)

tCL SCLK Low Time 7 10 ns (min)

tSS

SYNC Set-up Time prior to SCLK

Falling Edge 310 ns (min)

1 / fSCLK - 3 ns (max)

tDS

Data Set-Up Time prior to SCLK

Falling Edge 1.0 2.5 ns (min)

tDH

Data Hold Time after SCLK Falling

Edge 1.0 2.5 ns (min)

tSH

SYNC Hold Time after the 16th falling

edge of SCLK 03ns (min)

1 / fSCLK - 3 ns (max)

tSYNC SYNC High Time 5 15 ns (min)

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DAC128S085

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 30 mA maximum package

input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to three.

Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the

junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values

for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond

the operating ratings, or the power supply polarity is reversed). Such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0 Ω. Charge device model

simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.

Note 6: Reflow temperature profiles are different for lead-free packages.

Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of VA, will not cause errors in the conversion result. For

example, if VA is 3V, the digital input pins can be driven with a 5V logic device.

30016904

Note 8: Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 9: This parameter is guaranteed by design and/or characterization and is not tested in production.

Note 10: This parameter does not represent a condition which the DAC can sustain continuously. See the continuous output current specification for the maximum

DAC output current per channel.

Timing Diagrams

30016906

FIGURE 1. Serial Timing Diagram

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DAC128S085

Specification Definitions

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB,

which is VREF / 4096 = VA / 4096.

DAC-to-DAC CROSSTALK is the glitch impulse transferred

to a DAC output in response to a full-scale change in the out-

put of another DAC.

DIGITAL CROSSTALK is the glitch impulse transferred to a

DAC output at mid-scale in response to a full-scale change in

the input register of another DAC.

DIGITAL FEEDTHROUGH is a measure of the energy inject-

ed into the analog output of the DAC from the digital inputs

when the DAC outputs are not updated. It is measured with a

full-scale code change on the data bus.

FULL-SCALE ERROR is the difference between the actual

output voltage with a full scale code (FFFh) loaded into the

DAC and the value of VA x 4095 / 4096.

GAIN ERROR is the deviation from the ideal slope of the

transfer function. It can be calculated from Zero and Full-

Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE

is Full-Scale Error and ZE is Zero Error.

GLITCH IMPULSE is the energy injected into the analog out-

put when the input code to the DAC register changes. It is

specified as the area of the glitch in nanovolt-seconds.

INTEGRAL NON-LINEARITY (INL) is a measure of the de-

viation of each individual code from a straight line through the

input to output transfer function. The deviation of any given

code from this straight line is measured from the center of that

code value. The end point method is used. INL for this product

is specified over a limited range, per the Electrical Tables.

LEAST SIGNIFICANT BIT (LSB) is the bit that has the small-

est value or weight of all bits in a word. This value is

LSB = VREF / 2n

where VREF is the supply voltage for this product, and "n" is

the DAC resolution in bits, which is 12 for the DAC128S085.

MAXIMUM LOAD CAPACITANCE is the maximum capaci-

tance that can be driven by the DAC with output stability

maintained.

MONOTONICITY is the condition of being monotonic, where

the DAC has an output that never decreases when the input

code increases.

MOST SIGNIFICANT BIT (MSB) is the bit that has the largest

value or weight of all bits in a word. Its value is 1/2 of VA.

MULTIPLYING BANDWIDTH is the frequency at which the

output amplitude falls 3dB below the input sine wave on

VREF1,2 with the DAC code at full-scale.

NOISE SPECTRAL DENSITY is the internally generated ran-

dom noise. It is measured by loading the DAC to mid-scale

and measuring the noise at the output.

POWER EFFICIENCY is the ratio of the output current to the

total supply current. The output current comes from the power

supply. The difference between the supply and output cur-

rents is the power consumed by the device without a load.

SETTLING TIME is the time for the output to settle to within

1/2 LSB of the final value after the input code is updated.

TOTAL HARMONIC DISTORTION PLUS NOISE (THD+N)

is the ratio of the harmonics plus the noise present at the out-

put of the DACs to the rms level of an ideal sine wave applied

to VREF1,2 with the DAC code at mid-scale.

WAKE-UP TIME is the time for the output to exit power-down

mode. This is the time from the rising edge of SYNC to when

the output voltage deviates from the power-down voltage of

0V.

ZERO CODE ERROR is the output error, or voltage, present

at the DAC output after a code of 000h has been entered.

Transfer Characteristic

30016905

FIGURE 2. Input / Output Transfer Characteristic

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DAC128S085

Typical Performance Characteristics VA = +2.7V to +5.5V, VREF1,2 = VA, fSCLK = 30 MHz, TA = 25°C,

unless otherwise stated

INL vs Code

30016952

DNL vs Code

30016955

INL/DNL vs VREF

30016957

INL/DNL vs fSCLK

30016924

INL/DNL vs VA

30016922

INL/DNL vs Temperature

30016927

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DAC128S085

Zero Code Error vs. VA

30016930

Zero Code Error vs. VREF

30016931

Zero Code Error vs. fSCLK

30016934

Zero Code Error vs. Temperature

30016936

Full-Scale Error vs. VA

30016937

Full-Scale Error vs. VREF

30016932

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DAC128S085

Full-Scale Error vs. fSCLK

30016933

Full-Scale Error vs. Temperature

30016939

IVA vs. VA

30016944

IVA vs. Temperature

30016945

IVREF vs. VREF

30016925

IVREF vs. Temperature

30016935

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DAC128S085

Settling Time

30016928

Glitch Response

30016946

Wake-Up Time

30016951

DAC-to-DAC Crosstalk

30016938

Power-On Reset

30016947

Multiplying Bandwidth

30016950

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DAC128S085

1.0 Functional Description

1.1 DAC ARCHITECTURE

The DAC128S085 is fabricated on a CMOS process with an

architecture that consists of switches and resistor strings that

are followed by an output buffer. The reference voltages are

externally applied at VREF1 for DAC channels A through D and

VREF2 for DAC channels E through H.

For simplicity, a single resistor string is shown in Figure 3.

This string consists of 4096 equal valued resistors with a

switch at each junction of two resistors, plus a switch to

ground. The code loaded into the DAC register determines

which switch is closed, connecting the proper node to the

amplifier. The input coding is straight binary with an ideal out-

put voltage of:

VOUTA,B,C,D = VREF1 x (D / 4096)

VOUTE,F,G,H = VREF2 x (D / 4096)

where D is the decimal equivalent of the binary code that is

loaded into the DAC register. D can take on any value be-

tween 0 and 4095. This configuration guarantees that the

DAC is monotonic.

30016907

FIGURE 3. DAC Resistor String

Since all eight DAC channels of the DAC128S085 can be

controlled independently, each channel consists of a DAC

of an individual channel in the DAC128S085. Depending on

the mode of operation, data written into a DAC register causes

the 12-bit DAC output to be updated or an additional com-

mand is required to update the DAC output. Further descrip-

tion of the modes of operation can be found in the Serial

Interface description.

30016969

FIGURE 4. Single Channel Block Diagram

1.2 OUTPUT AMPLIFIERS

The output amplifiers are rail-to-rail, providing an output volt-

age range of 0V to VA when the reference is VA. All amplifiers,

even rail-to-rail types, exhibit a loss of linearity as the output

approaches the supply rails (0V and VA, in this case). For this

reason, linearity is specified over less than the full output

range of the DAC. However, if the reference is less than VA,

there is only a loss in linearity in the lowest codes.

The output amplifiers are capable of driving a load of 2 kΩ in

parallel with 1500 pF to ground or to VA. The zero-code and

full-scale outputs for given load currents are available in the

Electrical Characteristics Table.

1.3 REFERENCE VOLTAGE

The DAC128S085 uses dual external references, VREF1 and

VREF2, that are shared by channels A, B, C, D and channels

E, F, G, H respectively. The reference pins are not buffered

and have an input impedance of 30 kΩ. It is recommended

that VREF1 and VREF2 be driven by voltage sources with low

output impedance. The reference voltage range is 0.5V to

VA, providing the widest possible output dynamic range.

1.4 SERIAL INTERFACE

The three-wire interface is compatible with SPI, QSPI and

MICROWIRE, as well as most DSPs and operates at clock

rates up to 40 MHz. A valid serial frame contains 16 falling

edges of SCLK. See the Timing Diagram for information on a

write sequence.

A write sequence begins by bringing the SYNC line low. Once

SYNC is low, the data on the DIN line is clocked into the 16-

bit serial input register on the falling edges of SCLK. To avoid

mis-clocking data into the shift register, it is critical that

SYNC not be brought low on a falling edge of SCLK (see

minimum and maximum setup times for SYNC in the Timing

Characteristics and Figure 5). On the 16th falling edge of

SCLK, the last data bit is clocked into the register. The write

sequence is concluded by bringing the SYNC line high. Once

SYNC is high, the programmed function (a change in the DAC

channel address, mode of operation and/or register contents)

is executed. To avoid mis-clocking data into the shift register,

it is critical that SYNC be brought high between the 16th and

17th falling edges of SCLK (see minimum and maximum hold

times for SYNC in the Timing Characteristics and Figure 5).

30016965

FIGURE 5. CS Setup and Hold Times

If SYNC is brought high before the 15th falling edge of SCLK,

the write sequence is aborted and the data that has been

shifted into the input register is discarded. If SYNC is held low

beyond the 17th falling edge of SCLK, the serial data pre-

sented at DIN will begin to be output on DOUT. More informa-

tion on this mode of operation can be found in the Daisy Chain

Section. In either case, SYNC must be brought high for the

minimum specified time before the next write sequence is ini-

tiated with a falling edge of SYNC.

Since the DIN buffer draws more current when it is high, it

should be idled low between write sequences to minimize

power consumption. On the other hand, SYNC should be

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DAC128S085

idled high to avoid the activation of daisy chain operation

where DOUT is active.

1.5 DAISY CHAIN OPERATION

Daisy chain operation allows communication with any number

of DAC128S085s using a single serial interface. As long as

the correct number of data bits are input in a write sequence

(multiple of sixteen bits), a rising edge of SYNC will properly

update all DACs in the system.

To support multiple devices in a daisy chain configuration,

SCLK and SYNC are shared across all DAC128S085s and

DOUT of the first DAC in the chain is connected to DIN of the

second. Figure 6 shows three DAC128S085s connected in

daisy chain fashion. Similar to a single channel write se-

quence, the conversion for a daisy chain operation begins on

a falling edge of SYNC and ends on a rising edge of SYNC.

A valid write sequence for n devices in a chain requires n

times 16 falling edges to shift the entire input data stream

through the chain. Daisy chain operation is guaranteed for a

maximum SCLK speed of 30MHz.

30016967

FIGURE 6. Daisy Chain Configuration

The serial data output pin, DOUT, is available on the

DAC128S085 to allow daisy-chaining of multiple

DAC128S085 devices in a system. In a write sequence,

DOUT remains low for the first fourteen falling edges of SCLK

before going high on the fifteenth falling edge. Subsequently,

the next sixteen falling edges of SCLK will output the first six-

teen data bits entered into DIN. Figure 7 shows the timing of

three DAC128S085s in Figure 6. In this instance, It takes

forty-eight falling edges of SCLK followed by a rising edge of

SYNC to load all three DAC128S085s with the appropriate

function is executed in each DAC128S085 simultaneously.

30016968

FIGURE 7. Daisy Chain Timing Diagram

1.6 SERIAL INPUT REGISTER

The DAC128S085 has two modes of operation plus a few

special command operations. The two modes of operation are

Write Register Mode (WRM) and Write Through Mode

(WTM). For the rest of this document, these modes will be

referred to as WRM and WTM. The special command oper-

ations are separate from WRM and WTM because they can

be called upon regardless of the current mode of operation.

The mode of operation is controlled by the first four bits of the

control register, DB15 through DB12. See Table 1 for a de-

tailed summary.

TABLE 1. Write Register and Write Through Modes

DB[15:12] DB[11:0] Description of Mode

1 0 0 0 X X X X X X X X X X X X WRM: The registers of each DAC Channel can be written to

without causing their outputs to change.

1 0 0 1 X X X X X X X X X X X X WTM: Writing data to a channel's register causes the DAC

output to change.

www.national.com 14

DAC128S085

When the DAC128S085 first powers up, the DAC is in WRM.

In WRM, the registers of each individual DAC channel can be

written to without causing the DAC outputs to be updated.

This is accomplished by setting DB15 to "0", specifying the

DAC register to be written to in DB[14:12], and entering the

new DAC register setting in DB[11:0] (see Table 2).The

DAC128S085 remains in WRM until the mode of operation is

changed to WTM. The mode of operation is changed from

WRM to WTM by setting DB[15:12] to "1001". Once in WTM,

writing data to a DAC channel's register causes the DAC's

output to be updated as well. Changing a DAC channel's reg-

ister in WTM is accomplished in the same manner as it is done

in WRM. However, in WTM the DAC's register and output are

updated at the completion of the command (see Table 2).

Similarly, the DAC128S085 remains in WTM until the mode

of operation is changed to WRM by setting DB[15:12] to

"1000".

TABLE 2. Commands Impacted by WRM and WTM

DB15 DB[14:12] DB[11:0] Description of Mode

0 0 0 0 D11 D10 ... D1 D0 WRM: D[11:0] written to ChA's data register only

WTM: ChA's output is updated by data in D[11:0]

0 0 0 1 D11 D10 ... D1 D0 WRM: D[11:0] written to ChB's data register only

WTM: ChB's output is updated by data in D[11:0]

0 0 1 0 D11 D10 ... D1 D0 WRM: D[11:0] written to ChC's data register only

WTM: ChC's output is updated by data in D[11:0]

0 0 1 1 D11 D10 ... D1 D0 WRM: D[11:0] written to ChD's data register only

WTM: ChD's output is updated by data in D[11:0]

0 1 0 0 D11 D10 ... D1 D0 WRM: D[11:0] written to ChE's data register only

WTM: ChE's output is updated by data in D[11:0]

0 1 0 1 D11 D10 ... D1 D0 WRM: D[11:0] written to ChF's data register only

WTM: ChF's output is updated by data in D[11:0]

0 1 1 0 D11 D10 ... D1 D0 WRM: D[11:0] written to ChG's data register only

WTM: ChG's output is updated by data in D[11:0]

0 1 1 1 D11 D10 ... D1 D0 WRM: D[11:0] written to ChH's data register only

WTM: ChH's output is updated by data in D[11:0]

As mentioned previously, the special command operations

can be exercised at any time regardless of the mode of op-

eration. There are three special command operations. The

first command is exercised by setting data bits DB[15:12] to

"1010". This allows a user to update multiple DAC outputs

simultaneously to the values currently loaded in their respec-

tive control registers. This command is valuable if the user

wants each DAC output to be at a different output voltage but

still have all the DAC outputs change to their appropriate val-

ues simultaneously (see Table 3).

The second special command allows the user to alter the DAC

output of channel A with a single write frame. This command

is exercised by setting data bits DB[15:12] to "1011" and data

bits DB[11:0] to the desired control register value. It also has

the added benefit of causing the DAC outputs of the other

channels to update to their current control register values as

well. A user may choose to exercise this command to save a

write sequence. For example, the user may wish to update

several DAC outputs simultaneously, including channel A. In

order to accomplish this task in the minimum number of write

frames, the user would alter the control register values of all

the DAC channels except channel A while operating in WRM.

The last write frame would be used to exercise the special

command "Channel A Write Mode". In addition to updating

channel A's control register and output to a new value, all of

the other channels would be updated as well. At the end of

this sequence of write frames, the DAC128S085 would still

be operating in WRM (see Table 3).

The third special command allows the user to set all the DAC

control registers and outputs to the same level. This com-

mand is commonly referred to as "broadcast" mode since the

same data bits are being broadcast to all of the channels si-

multaneously. This command is exercised by setting data bits

DB[15:12] to "1100" and data bits DB[11:0] to the value that

the user wishes to broadcast to all the DAC control registers.

Once the command is exercised, each DAC output is updated

by the new control register value. This command is frequently

used to set all the DAC outputs to some known voltage such

as 0V, VREF/2, or Full Scale. A summary of the commands

can be found in Table 3.

TABLE 3. Special Command Operations

DB[15:12] DB[11:0] Description of Mode

1 0 1 0 X X X X H G F E D C B A Update Select: The DAC outputs of the channels selected with

a "1" in DB[7:0] are updated simultaneously to the values in

their respective control registers.

1 0 1 1 D11 D10 ... D1 D0 Channel A Write: Channel A's control register and DAC output

are updated to the data in DB[11:0]. The outputs of the other

seven channels are also updated according to their respective

control register values.

1 1 0 0 D11 D10 ... D1 D0 Broadcast: The data in DB[11:0] is written to all channels'

control register and DAC output simultaneously.

15 www.national.com

DAC128S085

1.7 POWER-ON RESET

The power-on reset circuit controls the output voltages of the

eight DACs during power-up. Upon application of power, the

DAC registers are filled with zeros and the output voltages are

set to 0V. The outputs remain at 0V until a valid write se-

quence is made.

1.8 POWER-DOWN MODES

The DAC128S085 has three power-down modes where dif-

ferent output terminations can be selected (see Table 4). With

all channels powered down, the supply current drops to 0.1

µA at 3V and 0.2 µA at 5V. By selecting the channels to be

powered down in DB[7:0] with a "1", individual channels can

be powered down separately or multiple channels can be

powered down simultaneously. The three different output ter-

minations include high output impedance, 100k ohm to

ground, and 2.5k ohm to ground.

The output amplifiers, resistor strings, and other linear cir-

cuitry are all shut down in any of the power-down modes. The

bias generator, however, is only shut down if all the channels

are placed in power-down mode. The contents of the DAC

registers are unaffected when in power-down. Therefore,

each DAC register maintains its value prior to the

DAC128S085 being powered down unless it is changed dur-

ing the write sequence which instructed it to recover from

power down. Minimum power consumption is achieved in the

power-down mode with SYNC idled high, DIN idled low, and

SCLK disabled. The time to exit power-down (Wake-Up Time)

is typically 3 µsec at 3V and 20 µsec at 5V.

TABLE 4. Power-Down Modes

DB[15:12] DB[11:8] 7 6 54 3 2 1 0 Output Impedance

1 1 0 1 X X X X H G F E D C B A High-Z outputs

1 1 1 0 X X X X H G F E D C B A 100 kΩ outputs

1 1 1 1 X X X X H G F E D C B A 2.5 kΩ outputs

2.0 Applications Information

2.1 EXAMPLES PROGRAMMING THE DAC128S085

This section will present the step-by-step instructions for pro-

gramming the serial input register.

2.1.1 Updating DAC Outputs Simultaneously

When the DAC128S085 is first powered on, the DAC is op-

erating in Write Register Mode (WRM). Operating in WRM

allows the user to program the registers of multiple DAC

channels without causing the DAC outputs to be updated. As

an example, here are the steps for setting Channel A to a full

scale output, Channel B to three-quarters full scale, Channel

C to half-scale, Channel D to one-quarter full scale and having

all the DAC outputs update simultaneously.

As stated previously, the DAC128S085 powers up in WRM.

If the device was previously operating in Write Through Mode

(WTM), an extra step to set the DAC into WRM would be re-

quired. First, the DAC registers need to be programmed to the

desired values. To set Channel A to an output of full scale,

write "0FFF" to the control register. This will update the data

A. Second, set Channel B to an output of three-quarters full

scale by writing "1C00" to the control register. This will update

the data register for Channel B. Once again, the output of

Channel B and Channel A will not be updated since the DAC

is operating in WRM. Third, set Channel C to half scale by

writing "2800" to the control register. Fourth, set Channel D

to one-quarter full scale by writing "3400" to the control reg-

ister. Finally, update all four DAC channels simultaneously by

writing "A00F" to the control register. This procedure allows

the user to update four channels simultaneously with five

steps.

Since Channel A was one of the DACs to be updated, one

command step could have been saved by writing to Channel

A last. This is accomplished by writing to Channel B, C, and

D first and using the the special command "Channel A Write"

to update Channel A's DAC register and output. This special

command has the added benefit of updating all DAC outputs

while updating Channel A. With this sequence of commands,

the user was able to update four channels simultaneously with

four steps. A summary of this command can be found in Table

2.1.2 Updating DAC Outputs Independently

If the DAC128S085 is currently operating in WRM, change

the mode of operation to WTM by writing "9XXX" to the control

nel can be updated in one step. For example, if a design

required Channel G to be set to half scale, the user can write

"6800" to the control register and Channel G's data register

and DAC output will be updated. Similarly, if Channel F's out-

put needed to be set to full scale, "5FFF" would need to be

written to the control register. Channel A is the only channel

that has a special command that allows its DAC output to be

updated in one command regardless of the mode of opera-

tion. Setting Channel A's DAC output to full scale could be

accomplished in one step by writing "BFFF" to the control

2.2 USING REFERENCES AS POWER SUPPLIES

While the simplicity of the DAC128S085 implies ease of use,

it is important to recognize that the path from the reference

input (VREF1,2) to the DAC outputs will have zero Power Sup-

ply Rejection Ratio (PSRR). Therefore, it is necessary to

provide a noise-free supply voltage to VREF1,2. In order to uti-

lize the full dynamic range of the DAC128S085, the supply

pin (VA) and VREF1,2 can be connected together and share the

same supply voltage. Since the DAC128S085 consumes very

little power, a reference source may be used as the reference

input and/or the supply voltage. The advantages of using a

reference source over a voltage regulator are accuracy and

stability. Some low noise regulators can also be used. Listed

below are a few reference and power supply options for the

DAC128S085.

www.national.com 16

DAC128S085

2.2.1 LM4132

The LM4132, with its ±0.05% accuracy over temperature, is

a good choice as a reference source for the DAC128S085.

The 4.096V version is useful if a 0V to 4.095V output range

is desirable. Bypassing the LM4132 voltage input pin with a

4.7µF capacitor and the voltage output pin with a 4.7µF ca-

pacitor will improve stability and reduce output noise. The

LM4132 comes in a space-saving 5-pin SOT23.

30016913

FIGURE 8. The LM4132 as a power supply

2.2.2 LM4050

Available with accuracy of ±0.1%, the LM4050 shunt refer-

ence is also a good choice as a reference for the

DAC128S085. It is available in 4.096V and 5V versions and

comes in a space-saving 3-pin SOT23.

30016914

FIGURE 9. The LM4050 as a power supply

The minimum resistor value in the circuit of Figure 9 must be

chosen such that the maximum current through the LM4050

does not exceed its 15 mA rating. The conditions for maxi-

mum current include the input voltage at its maximum, the

LM4050 voltage at its minimum, and the DAC128S085 draw-

ing zero current. The maximum resistor value must allow the

LM4050 to draw more than its minimum current for regulation

plus the maximum DAC128S085 current in full operation. The

conditions for minimum current include the input voltage at its

minimum, the LM4050 voltage at its maximum, the resistor

value at its maximum due to tolerance, and the DAC128S085

draws its maximum current. These conditions can be sum-

marized as

R(min) = ( VIN(max) − VZ(min) ) /IZ(max)

and

R(max) = ( VIN(min) − VZ(max) ) / ( (IDAC(max) + IZ(min) )

where VZ(min) and VZ(max) are the nominal LM4050 output

voltages ± the LM4050 output tolerance over temperature, IZ

(max) is the maximum allowable current through the LM4050,

IZ(min) is the minimum current required by the LM4050 for

proper regulation, and IDAC(max) is the maximum

DAC128S085 supply current.

2.2.3 LP3985

The LP3985 is a low noise, ultra low dropout voltage regulator

with a ±3% accuracy over temperature. It is a good choice for

applications that do not require a precision reference for the

DAC128S085. It comes in 3.0V, 3.3V and 5V versions, among

others, and sports a low 30 µV noise specification at low fre-

quencies. Since low frequency noise is relatively difficult to

filter, this specification could be important for some applica-

tions. The LP3985 comes in a space-saving 5-pin SOT23 and

5-bump micro SMD packages.

30016915

FIGURE 10. Using the LP3985 regulator

An input capacitance of 1.0µF without any ESR requirement

is required at the LP3985 input, while a 1.0µF ceramic ca-

pacitor with an ESR requirement of 5mΩ to 500mΩ is required

at the output. Careful interpretation and understanding of the

capacitor specification is required to ensure correct device

operation.

2.2.4 LP2980

The LP2980 is an ultra low dropout regulator with a ±0.5% or

±1.0% accuracy over temperature, depending upon grade. It

is available in 3.0V, 3.3V and 5V versions, among others.

30016916

FIGURE 11. Using the LP2980 regulator

Like any low dropout regulator, the LP2980 requires an output

capacitor for loop stability. This output capacitor must be at

least 1.0µF over temperature, but values of 2.2µF or more will

provide even better performance. The ESR of this capacitor

should be within the range specified in the LP2980 data sheet.

Surface-mount solid tantalum capacitors offer a good combi-

17 www.national.com

DAC128S085

nation of small size and low ESR. Ceramic capacitors are

attractive due to their small size but generally have ESR val-

ues that are too low for use with the LP2980. Aluminum

electrolytic capacitors are typically not a good choice due to

their large size and high ESR values at low temperatures.

2.3 BIPOLAR OPERATION

The DAC128S085 is designed for single supply operation and

thus has a unipolar output. However, a bipolar output may be

achieved with the circuit in Figure 12. This circuit will provide

an output voltage range of ±5 Volts. A rail-to-rail amplifier

should be used if the amplifier supplies are limited to ±5V.

30016917

FIGURE 12. Bipolar Operation

The output voltage of this circuit for any code is found to be

VO = (VA x (D / 4096) x ((R1 + R2) / R1) - VA x R2 / R1)

where D is the input code in decimal form. With VA = 5V and

R1 = R2,

VO = (10 x D / 4096) - 5V

A list of rail-to-rail amplifiers suitable for this application are

indicated in Table 5.

TABLE 5. Some Rail-to-Rail Amplifiers

AMP PKGS Typ VOS Typ ISUPPLY

LMP7701 SOT23-5 ±37 µV 0.79 mA

LMV841 SOT23-5 −17 µV 1.11 mA

LMC7111 SOT23-5 900 µV 25 µA

LM7301 SOT23-5 30 µV 620 µA

LM8261 SOT23-5 700 µV 1 mA

2.4 VARIABLE CURRENT SOURCE OUTPUT

The DAC128S085 is a voltage output DAC but can be easily

converted to a current output with the addition of an opamp.

In Figure 13, one of the channels of the DAC128S085 is con-

verted to a variable current source capable of sourcing up to

40mA.

30016958

FIGURE 13. Variable Current Source

The output current of this circuit (IO) for any DAC code is found

to be

IO = (VREF x (D / 4096) x (R2) / (R1 x RB)

where D is the input code in decimal form and R2 = RA + RB.

2.5 APPLICATION CIRCUITS

The following figures are examples of the DAC128S085 in

typical application circuits. These circuits are basic and will

generally require modification for specific circumstances.

2.5.1 Industrial Application

Figure 14 shows the DAC128S085 controlling several differ-

ent circuits in an industrial setting. Channel A is shown pro-

viding the reference voltage to the ADC121S625, one of

National Semiconductor's general purpose Analog-to-Digital

Converters (ADCs). The reference for the ADC121S625 may

be set to any voltage from 0.2V to 5.5V, providing the widest

dynamic range possible. Typically, the ADC121S625 will be

monitoring a sensor and would benefit from the ADC's refer-

ence voltage being adjustable. Channel B is providing the

drive or supply voltage for a sensor. By having the sensor

supply voltage adjustable, the output of the sensor can be

optimized to the input level of the ADC monitoring it. Channel

C is defined to adjust the offset or gain of an amplifier stage

in the system. Channel D is configured with an opamp to pro-

vide an adjustable current source. Being able to convert one

of the eight channels of the DAC128S085 to a current output

eliminates the need for a separate current output DAC to be

added to the circuit. Channel E, in conjunction with an opamp,

provides a bipolar output swing for devices requiring control

voltages that are centered around ground. Channel F and G

are used to set the upper and lower limits for a range detector.

Channel H is reserved for providing voltage control or acting

as a voltage setpoint.

www.national.com 18

DAC128S085

30016953

FIGURE 14. Industrial Application

2.5.2 ADC Reference

Figure 15 shows Channel A of the DAC128S085 providing the

drive or supply voltage for a bridge sensor. By having the

sensor supply voltage adjustable, the output of the sensor can

be optimized to the input level of the ADC monitoring it. The

output of the sensor is amplified by a fixed gain amplifier stage

with a differential gain of 1 + 2 × (RF / RI). The advantage of

this amplifier configuration is the high input impedance seen

by the output of the bridge sensor. The disadvantage is the

poor common-mode rejection ratio (CMRR). The common-

mode voltage (VCM) of the bridge sensor is half of Channel

A's DAC output. The VCM is amplified by a gain of 1V/V by the

amplifier stage and thus becomes the bias voltage for the in-

put of the ADC121S705. Channel B of the DAC128S085 is

providing the reference voltage to the ADC121S705. The ref-

erence for the ADC121S705 may be set to any voltage from

1V to 5V, providing the widest dynamic range possible.

The reference voltage for Channel A and B is powered by an

external 5V power supply. Since the 5V supply is common to

the sensor supply voltage and the reference voltage of the

ADC, fluctuations in the value of the 5V supply will have a

minimal effect on the digital output code of the ADC. This type

of configuration is often referred to as a "Ratio-metric" design.

For example, an increase of 5% to the 5V supply will cause

the sensor supply voltage to increase by 5%. This causes the

gain or sensitivity of the sensor to increase by 5%. The gain

of the amplifier stage is unaffected by the change in supply

voltage. The ADC121S705 on the other hand, also experi-

ences a 5% increase to its reference voltage. This causes the

size of the ADC's least significant bit (LSB) to increase by 5%.

As a result of the sensor's gain increasing by 5% and the LSB

size of the ADC increasing by the same 5%, there is no net

effect on the circuit's performance. It is assumed that the am-

plifier gain is set low enough to allow for a 5% increase in the

sensor output. Otherwise, the increase in the sensor output

level may cause the output of the amplifiers to clip.

30016956

FIGURE 15. Driving an ADC Reference

19 www.national.com

DAC128S085

2.5.3 Programmable Attenuator

Figure 16 shows one of the channels of the DAC128S085

being used as a single-quadrant multiplier. In this configura-

tion, an AC or DC signal can be driven into one of the refer-

ence pins. The SPI interface of the DAC can be used to

digitally attenuate the signal to any level from 0dB (full scale)

to 0V. This is accomplished without adding any noticeable

level of noise to the signal. An amplifier stage is shown in

Figure 16 as a reference for applications where the input sig-

nal requires amplification. Note how the AC signal in this

application is ac-coupled to the amplifier before being ampli-

fied. A separate bias voltage is used to set the common-mode

voltage for the DAC128S085's reference input to VA / 2, al-

lowing the largest possible input swing. The multiplying band-

width of VREF1,2 is 360kHz with a VCM of 2.5V and a peak-to-

peak signal swing of 2V.

30016954

FIGURE 16. Programmable Attenuator

2.6 DSP/MICROPROCESSOR INTERFACING

Interfacing the DAC128S085 to microprocessors and DSPs

is quite simple. The following guidelines are offered to hasten

the design process.

2.6.1 ADSP-2101/ADSP2103 Interfacing

Figure 17 shows a serial interface between the DAC128S085

and the ADSP-2101/ADSP2103. The DSP should be set to

operate in the SPORT Transmit Alternate Framing Mode. It is

programmed through the SPORT control register and should

be configured for Internal Clock Operation, Active Low Fram-

ing and 16-bit Word Length. Transmission is started by writing

a word to the Tx register after the SPORT mode has been

enabled.

30016909

FIGURE 17. ADSP-2101/2103 Interface

2.6.2 80C51/80L51 Interface

A serial interface between the DAC128S085 and the

80C51/80L51 microcontroller is shown in Figure 18. The

SYNC signal comes from a bit-programmable pin on the mi-

crocontroller. The example shown here uses port line P3.3.

This line is taken low when data is transmitted to the

DAC128S085. Since the 80C51/80L51 transmits 8-bit bytes,

only eight falling clock edges occur in the transmit cycle. To

load data into the DAC, the P3.3 line must be left low after the

first eight bits are transmitted. A second write cycle is initiated

to transmit the second byte of data, after which port line P3.3

is brought high. The 80C51/80L51 transmit routine must rec-

ognize that the 80C51/80L51 transmits data with the LSB first

while the DAC128S085 requires data with the MSB first.

30016910

FIGURE 18. 80C51/80L51 Interface

2.6.3 68HC11 Interface

A serial interface between the DAC128S085 and the 68HC11

microcontroller is shown in Figure 19. The SYNC line of the

DAC128S085 is driven from a port line (PC7 in the figure),

similar to the 80C51/80L51.

The 68HC11 should be configured with its CPOL bit as a zero

and its CPHA bit as a one. This configuration causes data on

the MOSI output to be valid on the falling edge of SCLK. PC7

is taken low to transmit data to the DAC. The 68HC11 trans-

mits data in 8-bit bytes with eight falling clock edges. Data is

transmitted with the MSB first. PC7 must remain low after the

first eight bits are transferred. A second write cycle is initiated

to transmit the second byte of data to the DAC, after which

PC7 should be raised to end the write sequence.

30016911

FIGURE 19. 68HC11 Interface

2.6.4 Microwire Interface

Figure 20 shows an interface between a Microwire compatible

device and the DAC128S085. Data is clocked out on the rising

edges of the SK signal. As a result, the SK of the Microwire

device needs to be inverted before driving the SCLK of the

DAC128S085.

30016912

FIGURE 20. Microwire Interface

www.national.com 20

DAC128S085

2.7 LAYOUT, GROUNDING, AND BYPASSING

For best accuracy and minimum noise, the printed circuit

board containing the DAC128S085 should have separate

analog and digital areas. The areas are defined by the loca-

tions of the analog and digital power planes. Both of these

planes should be located in the same board layer. A single

ground plane is preferred if digital return current does not flow

through the analog ground area. Frequently a single ground

plane design will utilize a "fencing" technique to prevent the

mixing of analog and digital ground current. Separate ground

planes should only be utilized when the fencing technique is

inadequate. The separate ground planes must be connected

in one place, preferably near the DAC128S085. Special care

is required to guarantee that digital signals with fast edge

rates do not pass over split ground planes. They must always

have a continuous return path below their traces.

For best performance, the DAC128S085 power supply should

be bypassed with at least a 1µF and a 0.1µF capacitor. The

0.1µF capacitor needs to be placed right at the device supply

pin. The 1µF or larger valued capacitor can be a tantalum

capacitor while the 0.1µF capacitor needs to be a ceramic

capacitor with low ESL and low ESR. If a ceramic capacitor

with low ESL and low ESR is used for the 1µF value and it

can be placed right at the supply pin, the 0.1µF capacitor can

be eliminated. Capacitors of this nature typically span the

same frequency spectrum as the 0.1µF capacitor and thus

eliminate the need for the extra capacitor. The power supply

for the DAC128S085 should only be used for analog circuits.

It is also advisable to avoid the crossover of analog and digital

signals. This helps minimize the amount of noise from the

transitions of the digital signals from coupling onto the sensi-

tive analog signals such as the reference pins and the DAC

outputs.

21 www.national.com

DAC128S085

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead LLP

Order Numbers DAC128S085CISQ

NS Package Number SQA16A

16-Lead TSSOP

Order Numbers DAC128S085CIMT

NS Package Number MTC16

www.national.com 22

DAC128S085

Notes

23 www.national.com

DAC128S085

Notes

DAC128S085 12-Bit Micro Power OCTAL Digital-to-Analog Converter with Rail-to-Rail Outputs

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