ANALOG DEVICES 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs AD7853/AD7853L* FEATURES Specified for Vpp of 3 V to 5.5 V Read-Only Operation AD7853-200 kSPS; AD7853L-100 kSPS System and Self-Calibration with Autocalibration on Power-Up Low Power: AD7853: 15mW (Vopp = 3 V) AD7853L: 5.5 mW (Vopp = 3 VI Automatic Power Down After Conversion (25 pW) Flexible Serial interface: 8051/SPI/QSP1/pP Compatible 24-Pin DIP, SOIC and SSOP Packages APPLICATIONS Battery-Powered Systems (Personal Digital Assistants, Medical Instruments, Mobile Communications) Pen Computers Instrumentation and Control Systems High Speed Modems GENERAL DESCRIPTION The AD7853/AD7853L are high speed, low power, 12-bit ADCs that operate from a single 3 V or 5 V power supply, the AD7853 being optimized for speed and the AD7853L for low power. The ADC powers up with a set of default conditions at which time it can be operated as a read-only ADC. The ADC contains self-calibration and system-calibration options to en- sure accurate operation over time and temperature and have a number of power-down options for low power applications. The part powers up with a set of default conditions and can op- erate as a read only ADC. The AD7853 is capable of 200 kHz throughput rate while the AD7853L is capable of 100 kHz throughput rate. The input track-and-hold acquires a signal in 500 ns and features a pseudo- differential sampling scheme. The AD7853/AD7853L voltage range is 0 to Vpyp with both straight binary and 2s complement output coding. Input signal range is to the supply, and the part is capable of converting full power signals to 100 kHz. CMOS construction ensures low power dissipation of typically 5.4 mW for normal operation and 3.6 pW in power-down mode. The part is available in 24-pin, 0.3 inch wide dual-in-line pack- age (DIP), 24-lead small outline SOIC) and 24-lead small shrink outline (SSOP) packages. PRODUCT HIGHLIGHTS 1. Specified for 3 V and 5 V supplies. 2. Automatic calibration on power-up. 3. Flexible power management options including automatic power-down after conversion. *Patent pending. FUNCTIONAL BLOCK DIAGRAM AYop AGND AGND AD7853/AD7853L y @ AMODE SAR + ADC CONTROL CALIBRATION BUSY MEMORY _ AND CONTROLLER SieEee Tf 5G SMi SM2 SYNC DIN DOUT SCLK POLARITY 4. Operates with reference voltages from 1.2 V to Vop. 5. Analog input ranges from 0 V to Vip. 6. Self and system calibration. 7, Versatile serial 'O port (SPIQSPL'8051/uP). 8. Lower power version AD7853L. _ ORDERING GUIDE Linearity Power Error Dissipation | Package Model (LSB)! (mW) Option AD7853AN +1 20 N-24 AD7853BN 41/2 20 N-24 AD7853LAN' +1 6.85 N-24 AD7853LBN' +1 6.85 N-24 AD7853AR +1 20 R-24 AD7853BR +1/2 20 R-24 AD7853LAR +1 6.85 R-24 AD7853LBR +1 6.85 R-24 AD7853LARS' +1 6.85 RS-24 EVAL-AD7853CB* EVAL-~-CONTROL BOARD NOTE Linearity error refers to the integral linearity errar. N = Plastic DIP; R = SOIC; RS = SSOP. For outline information see Package Information secuon. L. signifies the low power version. *Phis can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluationdemanstration purposes. *This board is a complete unit allowing a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. To obtain the most recent version or complete data sheet, call our fax retrieval system at 1-800-446-6212 or visit our World Wide Web site at http://www.analog.com. REV.A A/D CONVERTERS & DATA ACQUISITION SUBSYSTEMS 2-77AD7853/AD7853LSPECIFICATIONS * iy, ova = ss0vt0 4554, 28%, ftfon =25 External Reference, forgy = 4 MHz (1.8 MHz B Grade (0C to +70C), 1 MHz A and B Grades (-40C to +85C) for L Version); fsaupie = 200 kHz (AD7853) 100 kHz (AD7853L); SLEEP = Logic High; T, = Ty to Tax, unless otherwise noted.) Specifications in () apply to the AD7853L. Parameter AVersion' |B Version! | Units Test Conditions/Comments DYNAMIC PERFORMANCE Signal to Noise + Distortion Ratio? 70 71 dB min Typically SNR is 72 dB (SNR) Vin = 10 kHz Sine Wave, fasipre = 200 kHz (100 kHz) Total Harmonic Distortion (THD) -78 78 dB max Vin = 10 kHz Sine Wave, faspre = 200 kHz (100 kHz) Peak Harmonic or Spurious Noise 78 78 dB max Vin = 10 kHz Sine Wave, foaspy pe = 200 kHz (100 kHz) Intermodulation Distortion (IMD) Second Order Terms -78 80 dB typ ta = 9.983 kHz, fb = 10.05 kHz, foamprp = 200 kHz (100 kHz) Third Order Terms _. 78 80 dB typ ta = 9.983 kHz, fb = 10.05 kHz, fsampr: = 200 kHz (100 kHz) DC ACCURACY Resolution 12 12 Bits Integral Nonlinearity +} +1 LSB max 2.5 V External Reference Vip = 3 V. Vpp = 5 V (B Grade Only) 41 40.5 LSB max 5 V External Reference Vpp = 5 V (thy LSB max (CL. Version, 5 V External Reference, Vpp = 5 V) G1) LSB max (L Version) Differential Nonlinearity +1 +1 LSB max Guaranteed No Missed Codes to 12 Bits. 2.5 V External Reference Vpp = 3 , 5 V External Reference Vpp = 5 V Total Unadjusted Error 4) tI LSB typ Unipolar Offset Error tt tl LSB max 2.5 V External Reference Vpp = 3 V, 5 V External Reference Vpp = 5 V Unipolar Offset Error (42.5) (42.5) LSB max (L Versions, 2.5 V External Reference Vp = 3 V, 5 V External Reference Vp, = 5 V) Positive Full-Scale Error 42.5 2.5 LSB max 2.5 V External Reference Vpn = 3 V, 5 V External Reference Vpp = 5 V Positive Fuil-Scale Error (+4) (t4) LSB max (L. Versions, 2.5 V External Reference Vpp = 3 V, 5 V External Reference Vpp = 5 ) Negative Full-Scale Error 25 +25 LSB max 25 V External Reference Vpp = 3 V, 5 V Extemal Reference Vop = 5 V Negative Full-Scale Error (44) (t+) LSB max {L. Versions, 2.5 V External Reference Vy) = 3 V, 5 V External Reference Vp) = 5 V) Bipolar Zeru Error +2 t2 LSB max 2.5 V External Reference Vi) = 3 Vo V External Reterence Vp = 5 V Bipolar Zero Error f42.5) {t2.5) LSB max {L. Versions, 2.5 V External Reference Vpyjy = 3 V, 5 V External _| Reference Von = 3 ) ANALOG INPUT Input Voltage Ranges Oto Veer 0 to Veg Volts te, AEN(+) AIN( ) = 0 to Veep, ATN( ) can be biased up but AIN(+) cannot go below AIN(-) EVegul2 Vent? Volts ie, AING+) AING) =- Vapp!2 to #Vyqq/2, AINC) should be biased to +Vpepf2 and AIN(+) can go helow AIN( ) but cannot go below 0 V Leakage Current +] tI HA max Input Capacitance 20 | 20 pF typ oe REFERENCE INPUT/OUTPUT REF), Input Voltage Range 2.3'Vin 25Vap V min/max Functional from 1.2 V Input Impedance 150 150 kQQ typ REF,y Output Voltage 2.3/2.7 2.32.7 V min/max REFour Tempco 20 20 ppm/C typ LOGIC INPUTS Input High Voltage, Vir 2 2.4 V min AVpp = DVpp = 4.5 V to 5.5 V 2. 2.1 V min AVpn = DVpp = 3.0 V to 3.6 V Input Low Voltage, Vig OR 0.8 V max AVon = DVpp = 4.5 V to 5.5 V Oo 0.6 V max AVpp = DVpn = 3.0 V to 3.6 V Input Current, Ix +10 10 HA max Typically 10 nA, Vig = 0 V or Vpp Input Capacitance, Cyy* | 10 10 pF max LOGIC OUTPUTS Output High Voltage, Vou Thocrce = 200 pA 4 4 min AVop = DVpp = 4.5 Vite 5.5 V 2.4 24 V min AVon = DVpn = 3.0 Vt t6 Output Low Voltage, Vor 0.4 Ob V max Tusk = 0.8 mA Floating-State Leakage Current tbo +10 pA max Floating-State Output Capacitance? | 10 10 pF max Output Coding Straight (Natural) Binary Unipolar Input Range 2s Complement Bipolar Input Range CONVERSION RATE Conversion Time 4.6 (18) 4.0 (18) pis max (1. Versions Only, 40C to +85'C, 1 MHz CLEIN) (10) pis max (L. Versions Only, OPC to +70'C, 1.8 MHz CLKIN) Track'Hold Acquisition Time 0.4 (1) OG) pis min (1. Versions Only) Specifications subject to change without notice. 2-78 A/D CONVERTERS & DATA ACQUISITION SUBSYSTEMS REV.A