STM32MP151A Arm(R) Cortex(R)-A7 650 MHz + Cortex(R)-M4 MPU, TFT, 35 comm. interfaces, 25 timers, adv. analog Datasheet - production data Features TFBGA LFBGA Core LFBGA448 (18 x 18mm) LFBGA354 (16 x 16mm) Pitch 0.8mm * 32-bit Arm(R) Cortex(R)-A7 - L1 32-Kbyte I / 32-Kbyte D - 256-Kbyte unified level 2 cache - Arm(R) NEONTM and Arm(R) TrustZone(R) TFBGA361 (12 x 12 mm) TFBGA257 (10 x 10 mm) min Pitch 0.5mm * Controls for PMIC companion chip * 32-bit Arm(R) Cortex(R)-M4 with FPU/MPU - Up to 209 MHz (Up to 703 CoreMark(R)) Low-power consumption Memories Clock management * External DDR memory up to 1 Gbyte - up to LPDDR2/LPDDR3-1066 16/32-bit - up to DDR3/DDR3L-1066 16/32-bit * Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator * 708 Kbytes of internal SRAM: 256 KB of AXI SYSRAM + 384 KB of AHB SRAM + 64 KB of AHB SRAM in backup domain and 4 KB of SRAM in backup domain * Dual mode Quad-SPI memory interface * Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs and SLC NAND memories with up to 8-bit ECC Security/safety * Total current consumption down to 6 A * External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator * 5 x PLLs with fractional mode General-purpose input/outputs * Up to 176 I/O ports with interrupt capability - Up to 8 secure I/Os - Up to 6 Wakeup, 3 Tamper, 1 ActiveTamper Interconnect matrix Reset and power management * 2 bus matrices - 64-bit Arm(R) AMBA(R) AXI interconnect, up to 266 MHz - 32-bit Arm(R) AMBA(R) AHB interconnect, up to 209 MHz * 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os) 3 DMA controllers to unload the CPU * TrustZone(R) peripherals, active tamper * Cortex(R)-M4 resources isolation * POR, PDR, PVD and BOR * On-chip LDOs (RETRAM, BKPSRAM, USB 1.8 V, 1.1 V) * Backup regulator (~0.9 V) * Internal temperature sensors * Low-power modes: Sleep, Stop and Standby * 48 physical channels in total * 1 x high-speed general-purpose master direct memory access controller (MDMA) * 2 x dual-port DMAs with FIFO and request router capabilities for optimal peripheral management * LPDDR2/3 retention in Standby mode February 2019 This is information on a product in full production. DS12500 Rev 1 1/245 www.st.com STM32MP151A * RTC with sub-second accuracy and hardware calendar Up to 35 communication peripherals * 6 x I2C FM+ (1 Mbit/s, SMBus/PMBus) * 4 x UART + 4 x USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave) * 6 x SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy via internal audio PLL or external clock) * 4 x SAI (stereo audio: I2S, PDM, SPDIF Tx) * SPDIF Rx with 4 inputs * HDMI-CEC interface * MDIO Slave interface * 3 x SDMMC up to 8-bit (SD / e*MMCTM / SDIO) * 2 x USB 2.0 high-speed Host + 1 x USB 2.0 full-speed OTG simultaneously - or 1 x USB 2.0 high-speed Host + 1 x USB 2.0 high-speed OTG simultaneously * 10/100M or Gigabit Ethernet GMAC - IEEE 1588v2 hardware, MII/RMII/GMII/RGMII * 4 Cortex(R)-A7 system timers (secure, nonsecure, virtual, hypervisor) * 1 x SysTick M4 timer * 3 x watchdogs (2 x independent and window) Hardware acceleration * HASH (MD5, SHA-1, SHA224, SHA256), HMAC * 2 x true random number generator (3 oscillators each) * 2 x CRC calculation unit Debug mode * Arm(R) CoreSightTM trace and debug: SWD and JTAG interfaces * 8-Kbyte embedded trace buffer 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user * 8- to 14-bit camera interface up to 140 Mbyte/s All packages are ECOPACK(R)2 compliant 6 analog peripherals * 2 x ADCs with 16-bit max. resolution (12 bits 5 Msps, 14 bits 4.4 Msps, 16 bits 250 ksps) * 1 x temperature sensor * 2 x 12-bit D/A converters (1 MHz) * 1 x digital filters for sigma delta modulator (DFSDM) with 8 channels/6 filters * Internal or external ADC/DAC reference VREF+ Graphics * LCD-TFT controller, up to 24-bit // RGB888 - up to WXGA (1366 x 768) @60 fps - Two layers with programmable colour LUT Up to 25 timers and 3 watchdogs * 2 x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input * 2 x 16-bit advanced motor control timers * 10 x 16-bit general-purpose timers (including 2 basic timers without PWM) * 5 x 16-bit low-power timers 2/245 DS12500 Rev 1 STM32MP151A Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 Arm(R) Cortex(R)-A7 subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 Arm(R) Cortex(R)-M4 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3.1 External SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4 DDR3/DDR3L/LPDDR2/LPDDR3 controller (DDRCTRL) . . . . . . . . . . . . 23 3.5 TrustZone address space controller for DDR (TZC) . . . . . . . . . . . . . . . . 24 3.6 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.7.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.8 Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.9 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.9.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.9.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.10 Hardware semaphore (HSEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.11 Inter-processor communication controller (IPCC) . . . . . . . . . . . . . . . . . . 30 3.11.1 IPCC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.12 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.13 TrustZone protection controller (ETZPC) . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.14 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.15 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.16 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 34 3.17 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 34 3.18 Cyclic redundancy check calculation unit (CRC1, CRC2) . . . . . . . . . . . . 35 DS12500 Rev 1 3/245 6 Contents 4/245 STM32MP151A 3.19 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.20 Dual Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . 35 3.21 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.23 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.24 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.25 Digital-to-analog converters (DAC1, DAC2) . . . . . . . . . . . . . . . . . . . . . . . 37 3.26 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.27 Digital filter for sigma delta modulators (DFSDM1) . . . . . . . . . . . . . . . . . 38 3.28 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.29 LCD-TFT display controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.30 True random number generator (RNG1, RNG2) . . . . . . . . . . . . . . . . . . . 40 3.31 Hash processors (HASH1, HASH2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.32 Boot and security and OTP control (BSEC) . . . . . . . . . . . . . . . . . . . . . . . 41 3.33 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.33.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.33.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.33.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.33.4 Low-power timer (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . . 44 3.33.5 Independent watchdog (IWDG1, IWDG2) . . . . . . . . . . . . . . . . . . . . . . . 44 3.33.6 System window watchdog (WWDG1) . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.33.7 SysTick timer (Cortex-M4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.33.8 Generic timers (Cortex-A7 CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.34 System timer generation (STGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.35 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.36 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.37 Inter-integrated circuit interface (I2C1, I2C2, I2C3, I2C4, I2C5, I2C6) . . . 48 3.38 Universal synchronous asynchronous receiver transmitter (USART1, USART2, USART3, USART6 and UART4, UART5, UART7, UART8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.39 Serial peripheral interface (SPI1, SPI2, SPI3, SPI4, SPI5, SPI6)- inter- integrated sound interfaces (I2S1, I2S2, I2S3) . . . . . . . . . . 49 3.40 Serial audio interfaces (SAI1, SAI2, SAI3, SAI4) . . . . . . . . . . . . . . . . . . . 50 3.41 SPDIF receiver interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DS12500 Rev 1 STM32MP151A Contents 3.42 Management data input/output (MDIOS) . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.43 Secure digital input/output MultiMediaCard interface (SDMMC1, SDMMC2, SDMMC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.44 Universal serial bus high-speed host (USBH) . . . . . . . . . . . . . . . . . . . . . 51 3.45 USB on-the-go high-speed (OTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.46 Gigabit Ethernet MAC interface (ETH1) . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.47 High-definition multimedia interface (HDMI) - Consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.48 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 55 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 126 6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 128 6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.3.5 Embedded regulators characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 144 6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 149 6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 154 6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 DS12500 Rev 1 5/245 6 Contents 7 STM32MP151A 6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 159 6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 6.3.17 NRST and NRST_CORE pin characteristics . . . . . . . . . . . . . . . . . . . . 167 6.3.18 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.3.19 QUADSPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.3.20 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.3.21 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.3.22 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 6.3.23 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 200 6.3.24 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 6.3.25 DTS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 6.3.26 VBAT ADC monitoring characteristics and charging characteristics . . 202 6.3.27 Temperature and VBAT monitoring characteristics for temper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.3.28 VDDCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.3.29 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.3.30 Digital filter for sigma-delta modulators (DFSDM) characteristics . . . . 203 6.3.31 Camera interface (DCMI) characteristics . . . . . . . . . . . . . . . . . . . . . . . 207 6.3.32 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 207 6.3.33 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 6.3.34 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 6.3.35 USART interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 7.1 TFBGA 257 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 7.2 LFBGA354 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 7.3 TFBA361 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 7.4 LFBGA448 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 6/245 DS12500 Rev 1 STM32MP151A List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. STM32MP151A features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 System versus domain power mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 STM32MP151A pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 128 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Embedded reference voltage calibration value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 REG1V1 embedded regulator (USB_PHY) characteristics . . . . . . . . . . . . . . . . . . . . . . . 131 REG_1V8 embedded regulator (USB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Current consumption (IDDCORE) in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Current consumption (IDD) in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Current consumption in LPLV-Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 High-speed external user clock characteristics (digital bypass) . . . . . . . . . . . . . . . . . . . . 144 High-speed external user clock characteristics (analog bypass) . . . . . . . . . . . . . . . . . . . 144 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 8-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 PLL1_1600, PLL2_1600 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 PLL3_800, PLL4_800 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 USB_PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 OTP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 DC specifications - DDR3L mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 DC specifications - DDR3L mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 DS12500 Rev 1 7/245 9 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. 8/245 STM32MP151A Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Output timing characteristics (HSLV ON, _h IO structure) . . . . . . . . . . . . . . . . . . . . . . . . 165 Output timing characteristics (HSLV ON, _e IO structure) . . . . . . . . . . . . . . . . . . . . . . . . 166 NRST and NRST_CORE pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 170 Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 170 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 171 Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 172 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 173 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 175 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 180 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 185 QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Dynamics characteristics: Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Minimum sampling time versus RAIN with 47 pF PCB capacitor up to 125 C and VDDA = 1.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Minimum delay for interleaved conversion versus resolution . . . . . . . . . . . . . . . . . . . . . . 193 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 DTS characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 VBAT ADC monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Temperature and VBAT monitoring characteristics for temper detection . . . . . . . . . . . . . 203 VDDCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 DFSDM measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 I2C FM+ pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 MDIOS timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Dynamic characteristics: SD / MMC / e*MMC characteristics, VDD = 2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 DS12500 Rev 1 STM32MP151A Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. List of tables Dynamic characteristics: SD / MMC / e*MMC characteristics VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Dynamics characteristics: Ethernet MAC timings for MDIO/SMA. . . . . . . . . . . . . . . . . . . 223 Dynamics characteristics: Ethernet MAC timings for RMII . . . . . . . . . . . . . . . . . . . . . . . . 224 Dynamics characteristics: Ethernet MAC timings for MII . . . . . . . . . . . . . . . . . . . . . . . . . 225 Dynamics characteristics: Ethernet MAC signals for GMII . . . . . . . . . . . . . . . . . . . . . . . 226 Dynamics characteristics: Ethernet MAC signals for RGMII . . . . . . . . . . . . . . . . . . . . . . 226 USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 TFBGA - 257 balls, 10x10 mm, 0.5/0.65 mm pitch, low profile fine pitch ball grid array mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 TFBGA - 257 balls, recommended PCB design rules (0.5/0.65 mm pitch, BGA) . . . . . . . 231 LFBGA - 354balls, 16x16 mm, 0.8 mm pitch, low profile fine pitch ball grid array mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 LFBGA - 354 balls, recommended PCB design rules (0.8 mm pitch, BGA) . . . . . . . . . . . 235 TFBGA - 361 ball, 12x12 mm, 0.5/0.65 mm pitch, thin profile fine pitch ball grid array mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 TFBGA - 361 ball, recommended PCB design rules (0.5/0.65 mm pitch BGA) . . . . . . . . 238 LFBGA - 448 balls, 18x18 mm, 0.8 mm pitch, low profile fine pitch ball grid array mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 LFBGA - 448 balls, recommended PCB design rules (0.8 mm pitch, BGA) . . . . . . . . . . . 241 STM32MP151A ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 DS12500 Rev 1 9/245 9 List of figures STM32MP151A List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 10/245 STM32MP151A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STM32MP151A bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 STM32MP151AADxx TFBGA257 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 STM32MP151AABxx LFBGA354 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 STM32MP151AACxx TFBGA361 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 STM32MP151AAA LFBGA448 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 VDDCORE rise time from reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 VDDCORE rise time from LPLV-Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 High-speed external clock source AC timing diagram (digital bypass) . . . . . . . . . . . . . . . 144 High-speed external clock source AC timing diagram (analog bypass) . . . . . . . . . . . . . . 145 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Typical application with a 24 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Recommended NRST and NRST_CORE pin protection . . . . . . . . . . . . . . . . . . . . . . . . . 168 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 169 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 171 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 172 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 174 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 180 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 184 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 184 QUADSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 QUADSPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 I2S master timing diagram (Philips protocol)(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 DS12500 Rev 1 STM32MP151A Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. List of figures SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 MDIOS timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Ethernet MDIO/SMA timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Ethernet GMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Ethernet RGMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 TFBGA - 257 balls, 10x10 mm, 0.5/0.65 mm pitch, low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 TFBGA - 257 balls, 10x10 mm, 0.5/0.65 mm pitch, low profile fine pitch ball grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 TFBGA257 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 LFBGA - 354balls, 16x16 mm, 0.8 mm pitch, low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 LFBGA - 354balls, 16x16 mm, 0.8 mm pitch, low profile fine pitch ball grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 LFBGA354 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 TFBGA - 361 ball, 12x12 mm, 0.5/0.65 mm pitch, thin profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 TFBGA - 361 ball, 12x12 mm, 0.5/0.65 mm pitch, thin profile fine pitch ball grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 TFBGA361 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 LFBGA - 448 balls, 18x18 mm, 0.8 mm pitch, low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 LFBGA - 448 balls, 18x18 mm, 0.8 mm pitch, low profile fine pitch ball grid array recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 LFBGA448 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 DS12500 Rev 1 11/245 11 Introduction 1 STM32MP151A Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32MP151A microprocessors. This document should be read in conjunction with the STM32MP151x reference manual (RM0441), available from the STMicroelectronics website www.st.com. For information on the Arm(R)(a) Cortex(R)-A7 and Cortex(R)-M4 cores, refer to the Cortex(R)-A7 and Cortex(R)-M4 Technical Reference Manuals. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 12/245 DS12500 Rev 1 STM32MP151A 2 Description Description The STM32MP151A devices are based on the high-performance Arm(R) Cortex(R)-A7 32-bit RISC core operating at up to 650 MHz. The Cortex-A7 processor includes a 32-Kbyte L1 instruction cache, a 32-Kbyte L1 data cache and a 256-Kbyte level2 cache. The Cortex-A7 processor is a very energy-efficient application processor designed to provide rich performance in high-end wearables, and other low-power embedded and consumer applications. It provides up to 20% more single thread performance than the Cortex-A5 and provides similar performance than the Cortex-A9. The Cortex-A7 incorporates all features of the high-performance Cortex-A15 and CortexA17 processors, including virtualization support in hardware, NEONTM, and 128-bit AMBA(R)4 AXI bus interface. The STM32MP151A devices also embed a Cortex(R) -M4 32-bit RISC core operating at up to 209 MHz frequency. Cortex-M4 core features a floating point unit (FPU) single precision which supports Arm(R) single-precision data-processing instructions and data types. The Cortex(R) -M4 supports a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32MP151A devices provide an external SDRAM interface supporting external memories up to 8-Gbit density (1 Gbyte), 16 or 32-bit LPDDR2/LPDDR3 or DDR3/DDR3L up to 533 MHz. The STM32MP151A devices incorporate high-speed embedded memories with 708 Kbytes of Internal SRAM (including 256 Kbytes of AXI SYSRAM, 3 banks of 128 Kbytes each of AHB SRAM, 64 Kbytes of AHB SRAM in backup domain and 4 Kbytes of SRAM in backup domain), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, a 32-bit multi-AHB bus matrix and a 64-bit multi layer AXI interconnect supporting internal and external memories access. DS12500 Rev 1 13/245 54 Description STM32MP151A All the devices offer two ADCs, two DACs, a low-power RTC, 12 general-purpose 16-bit timers, two PWM timers for motor control, five low-power timers, a true random number generator (RNG). The devices support six digital filters for external sigma delta modulators (DFSDM). They also feature standard and advanced communication interfaces. * Standard peripherals - * Six I2Cs - Four USARTs and four UARTs - Six SPIs, three I2Ss full-duplex master/slave. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. - Four SAI serial audio interfaces - One SPDIF Rx interface - Management data input/output slave (MDIOS) - Three SDMMC interfaces - An USB high-speed Host with two ports two high-speed PHYs and a USB OTG high-speed with full-speed PHY or high-speed PHY shared with second port of USB Host. - A Gigabit Ethernet interface - HDMI-CEC Advanced peripherals including - A flexible memory control (FMC) interface - A Quad-SPI Flash memory interface - A camera interface for CMOS sensors - An LCD-TFT display controller Refer to Table 1: STM32MP151A features and peripheral counts for the list of peripherals available on each part number. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32MP151A devices are proposed in 4 packages ranging from 257 to 448 balls with pitch 0.5 mm to 0.8 mm. The set of included peripherals changes with the device chosen. These features make the STM32MP151A suitable for a wide range of consumer, industrial, white goods and medical applications. shows the general block diagram of the device family. Features Package 14/245 STM32MP151 STM32MP151 STM32MP151 STM32MP151 AADxx AABxx AACxx AAAxx TFBGA257 LFBGA354 TFBGA361 LFBGA448 Body size (mm) 10x10 16x16 12x12 18x18 Pitch (mm) 0.5(1) 0.8 0.5(1) 0.8 Ball size (mm) 0.30 0.40 0.30 0.40 Thickness (mm) <1.2 <1.4 <1.2 <1.4 Ball count 257 354 361 448 DS12500 Rev 1 Miscellaneous Table 1. STM32MP151A features and peripheral counts - STM32MP151A Description Features STM32MP151 STM32MP151 STM32MP151 STM32MP151 AADxx AABxx AACxx AAAxx TFBGA257 LFBGA354 TFBGA361 LFBGA448 CPU Miscellaneous Table 1. STM32MP151A features and peripheral counts (continued) Cortex-A7 FPU Neon TrustZone 32-Kbyte L1 data cache Caches size 32-Kbyte L1 instruction cache - 256-Kbyte level 2 unified coherent cache 650 MHz(2) Frequency MCU core Cortex-M4 FPU Frequency ROM 128 Kbytes (secure) 256 Kbytes (securable) MCU subsystem 384 Kbytes MCU retention 64 Kbytes SDRAM (securable) Backup LPDDR2/3 DDR3/3L 4 Kbytes (securable, tamper protected) 16-bit 533 MHz Up to 1 Gbyte, single rank - 32-bit 533 MHz - - 16-bit 533 MHz 32-bit 533 MHz Backup registers Up to 1 Gbyte, single rank - - Up to 1 Gbyte, single rank - - 128 bytes (32x32-bit, securable, tamper protected) Advanced 16 bits 2 General purpose 16 bits 8 32 bits 2 Basic 16 bits 2 Low power 16 bits 5 A7 timers 64 bits 4 (secure, non-secure, virtual, hypervisor) M4 SysTick 24 bits 1 RTC/AWU - 25 timers Embedded SRAM 708 Kbytes CPU system Timers - 209 MHz 1 (securable) DS12500 Rev 1 15/245 54 Description STM32MP151A Features Watchdog STM32MP151 STM32MP151 STM32MP151 STM32MP151 AADxx AABxx AACxx AAAxx TFBGA257 LFBGA354 TFBGA361 LFBGA448 Miscellaneous Table 1. STM32MP151A features and peripheral counts (continued) 3 (independent, independent secure, window) - SPI 6 (1 securable) Having I2S 3 Communication peripherals I2C (with SMB/PMB support) USART (smartcard, SPI, IrDA, LIN) + UART (IrDA, LIN) SAI OTG HS/FS (dual role port) Embedded PHYs - 4 + 4 (including 1 securable USART) some can be a boot source Boot 4 (up to 8 audio channels), with I2S master/slave, PCM input, SPDIF-TX Boot 2 ports - Embedded HS PHY with BCD - Yes, embedded FS or HS PHY with BCD, can be a boot source Boot 3 (2 x high-speed + 1 x full-speed) - SPDIF-RX 4 inputs - HDMI-CEC 1 - Including the following securable SDMMC (SD, SDIO, e*MMC) QuadSPI Parallel address/data 8/16-bit FMC 6 (2 securable) EHCI/OHCI Host USB - 1 x USART, 1 x SPI, 2 x I2C - 3 (8 + 8 + 4 bits), e*MMC or SD can be a boot source Boot Yes (dual-quad), can be a boot source Boot - 4 x CS, up to 4 x 64 Mbyte 4 x CS, up to 4 x 64 Mbytes No boot Yes, 1 x CS, SLC, BCH4/8, can be a boot source Boot Parallel AD-Mux 8/16-bit NAND 8/16-bit 1 x USART, 1 x SPI, 2 x I2C on securable GPIOs Gigabit Ethernet - 10/100M Ethernet MII, RMII with PTP and EEE MII, RMII, GMII, RGMII with PTP and EEE - up to 24-bit data (up to 1366x768 60 fps) - DMA 3 instances (1 securable), 48 physical channels in total - Hash SHA-256, MD5, HMAC dual instances (secure and non-secure) - True random number generator True-RNG, dual instances (secure and non-secure) - Fuses (one-time programmable) 3072 effective bits (secure, >1500 bits available for user) - 14-bit - LCD-TFT Camera interface 16/245 Parallel interface Bus width DS12500 Rev 1 STM32MP151A Description Features STM32MP151 STM32MP151 STM32MP151 STM32MP151 AADxx AABxx AACxx AAAxx TFBGA257 LFBGA354 TFBGA361 LFBGA448 GPIOs with interrupt (total count) 98 148 176 Securable GPIOs - 8 Wakeup pins 4 6 2 (1) 3 (1) Tamper pins (active tamper) DFSDM Up to 16-bit synchronized ADC Miscellaneous Table 1. STM32MP151A features and peripheral counts (continued) 8 input channels with 6 filters - - 2 (up to 0.25/4.4/5/5.7/6.7 Msps on 16/14/12/10/8-bit each) Low noise 16 bit (differential) - 2 (1) 16 bit (differential) 6 (1) 7 (1) 14 bit (differential) 11 (3) 13 (3) 17 22 ADC channels in total 12-bit DAC 2 Internal ADC/DAC VREF 1.5 V, 1.8 V, 2.048 V, 2.5 V or VREF+ input VREF+ input pin Yes - - 1. With inner matrix balls having 0.65 mm pitch to allow optimized PCB routing for supplies. 2. Limited to 600 MHz when used for industrial application. DS12500 Rev 1 17/245 54 Description STM32MP151A Figure 1. STM32MP151A block diagram @VDD_ANA HSI @VDD LSI @VDD_PLL T IWDG1 T T FIFO 16 DLYBSD2 GPIOE 16b 16 GPIOF 16b 16 GPIOG 16b 16 GPIOH 16b 16 GPIOI 16b 16 GPIOJ 16b 16 GPIOK 8b 8 TIM2 32b 5 TIM3 16b 5 TIM4 16b 5 TIM5 32b 5 TIM6 16b MDMA 32 Channels STM D-Bus S-Bus NVIC SYSTICK SRAM1 128KB SRAM2 128KB RETSRAM 64KB STGENR CRC2 APB4 RNG2 HASH2 T DDRPHYC @VDDA 16b LPTIM4 1 16b LPTIM5 SAI4 13 3 BOOT pins 8 8b SYSCFG TIM1 / PWM 16b TIM8 / PWM AHB2APB 16b Voltage Regulators TIM15 TIM16 16b TIM17 13 SAI1 8 SAI2 FIFO 16b 3 8 SAI3 FIFO 3 FIFO 4 4 2 4 UART5 4 UART7 4 UART8 4 DAC1 DAC2 1 1 12b 12b Smartcard IrDA 5 Smartcard IrDA 5 I2C1 / SMBUS 3 I2C2 / SMBUS 3 I2C3 / SMBUS 3 I2C5 / SMBUS 3 1 SPDIFRX SPI2 / I2S2 5 SPI3 / I2S3 5 4ch 4 WWDG1 APB2 (104.5 MHz) 16b 16b UART4 FIFO DTS (Digital temperature sensor) 10 1 LPTIM1 CEC (HDMI-CEC) 2x2 Matrix HDP 10 16b FIFO 1 1 TIM14 FIFO LPTIM3 @VDD Supply Supervision @VDD_ANA 64 bits AXI 64bits AXI master 32 bits AHB 32 bits AHB master 32 bits APB T AHB2APB TrustZone(R) security protection APB2 (104.5 MHz) 16b DMA1 8 Streams DMAMUX1 DMA2 8 Streams APB3 (104.5 MHz) 1 LPTIM2 2 16b USART3 AHB2APB VREFBUF 16b FIFO 4 16b TIM13 USART2 FIFO @VDDA DDRPERFM 1 16b FIFO @VSW IWDG2 TIM7 TIM12 MDIOS T USBPHYC DLY T T FIFO FIFO 16b HSEM (USB 2 x PHY control) Interface GPIOD SRAM3/SRAM4 64K/64K @VSW STGENC 16 DLYBSD1 T @VSW @VDD Sys. Timing GENeration 16b Cortex-M4 CPU 209 MHz + MPU + FPU T LSE (32kHz XTAL) 2 GPIOC (SDMMC2 DLY control) TAMP / Backup Regs T 3 16 CRC1 FIFO @VSW ETZPC T RTC / AWU 16 16b I-Bus OTP Fuses 2 16b GPIOB Filter T BSEC GPIOA DLYBQS Filter SPI6 4 20 14 (QUADSPI DLY control) (SDMMC1 DLY control) AHB2APB ADC1 ADC2 Filter 4 USART1 HASH1 16b 16b Filter I2C6 / SMBUS Smartcard IrDA @VDDA (HS/FS) FIFO 3 T 10 OTG FIFO 8KB FIFO T 5 RNG1 T async I2C4 / SMBUS 3 4b SDMMC3 T FIFO Trace port 17 FIFO 16b 14b (Camera I/F) FIFO 17 DCMI 9 FIFO T T APB5 (133MHz) GPIOZ FIFO 8b FIFO 8 176 USART6 FIFO LTDC (LCD) 24b FIFO 31 BKPSRAM 4KB Interface PLLUSB 16ext SPI4 4 FIFO 2 x PHY USBH (2 x HS Host) EXTI SPI5 4 FIFO T T 5 DLYBSD3 APB1 (104.5 MHz) SDMMC2 DLY 8b 2 2 T PWR (SDMMC3 DLY control) ROM 128KB T AXIMC TT SDMMC1 FIFO FMC 8b FIFO 16b 14 FIFO 37 DLY 8b 14 async 32b PHY DLY QUADSPI (dual) 13 RCC T MLAHB: ARM 32-bit multi-AHB bus matrix (209 MHz) DDRCTRL LPDDR2/3 DDR3/3L (JTAG / SWD) FIFO 77 10/100/1000 TZC T ETH1 GMAC (R)(G)MII FIFO 29 T T T SYSRAM 256KB FIFO CNT (Timer) ETM DAP T @VSW 32K I$ AXIM: ARM 64-bit AXI interconnect (266 MHz) T async 128 bits 2 PLL1/2/3/4 debug TimeStamp GENerator TSGEN T 32K D$ 256KB L2$ + SCU T GIC Cortex-A7 CPU 650 MHz + MMU + FPU + NEON T HSE (XTAL) T async CSI PHY IC Supplies SPI1 / I2S1 DFSDM1 Smartcard IrDA 5 5 8ch 17 APB2 (104.5 MHz) MSv47452V3 18/245 DS12500 Rev 1 STM32MP151A Functional overview 3 Functional overview 3.1 Arm(R) Cortex(R)-A7 subsystem 3.1.1 Features 3.1.2 * ARMv7-A architecture * 32-Kbyte L1 instruction cache * 32-Kbyte L1 data cache * 256-Kbyte level2 cache * Arm(R) + Thumb(R)-2 instruction set * Arm(R) TrustZone(R) security technology * Arm(R) NEONTM Advanced SIMD * DSP and SIMD extensions * VFPv4 floating-point * Hardware virtualization support * Embedded trace module (ETM) * Integrated generic interrupt controller (GIC) with 256 shared peripheral interrupts * Integrated generic timer (CNT) Overview The Cortex-A7 processor is a very energy-efficient applications processor designed to provide rich performance in high-end wearables, and other low-power embedded and consumer applications. It provides up to 20 % more single thread performance than the Cortex-A5 and provides similar performance than the Cortex-A9. The Cortex-A7 incorporates all features of the high-performance Cortex-A15 and CortexA17 processors, including virtualization support in hardware, NEONTM, and 128-bit AMBA(R)4 AXI bus interface. The Cortex-A7 processor builds on the energy-efficient 8-stage pipeline of the Cortex-A5 processor. It also benefits from an integrated L2 cache designed for low-power, with lower transaction latencies and improved OS support for cache maintenance. On top of this, there is improved branch prediction and improved memory system performance, with 64-bit loadstore path, 128-bit AMBA 4 AXI buses and increased TLB size (256 entry, up from 128 entry for Cortex-A9 and Cortex-A5), increasing performance for large workloads such as web browsing. Thumb-2 technology Delivers the peak performance of traditional Arm(R) code while also providing up to a 30 % reduction in memory requirement for instructions storage. TrustZone technology Ensures reliable implementation of security applications ranging from digital rights management to electronic payment. Broad support from technology and industry partners. DS12500 Rev 1 19/245 54 Functional overview STM32MP151A NEON NEON technology can accelerate multimedia and signal processing algorithms such as video encode/decode, 2D/3D graphics, gaming, audio and speech processing, image processing, telephony, and sound synthesis. The Cortex-A7 provides an engine that offers both the performance and functionality of the Cortex-A7 floating-point unit (FPU) and an implementation of the NEON advanced SIMD instruction set for further acceleration of media and signal processing functions. The NEON extends the Cortex-A7 processor FPU to provide a quad-MAC and additional 64-bit and 128-bit register set supporting a rich set of SIMD operations over 8-, 16- and 32-bit integer and 32-bit floating-point data quantities. Hardware virtualization Highly efficient hardware support for data management and arbitration, whereby multiple software environments and their applications are able to simultaneously access the system capabilities. This enables the realization of devices that are robust, with virtual environments that are well isolated from each other. Optimized L1 caches Performance and power optimized L1 caches combine minimal access latency techniques to maximize performance and minimize power consumption. Integrated L2 cache controller Provides low-latency and high-bandwidth access to cached memory in high-frequency, or to reduce the power consumption associated with off-chip memory access. Cortex-A7 floating-point unit (FPU) The FPU provides high-performance single and double precision floating-point instructions compatible with the Arm VFPv4 architecture that is software compatible with previous generations of Arm floating-point coprocessor. Snoop control unit (SCU) The SCU is responsible for managing the interconnect, arbitration, communication, cache to cache and system memory transfers, cache coherence and other capabilities for the processor. This system coherence also reduces software complexity involved in maintaining software coherence within each OS driver. Generic interrupt controller (GIC) Implementing the standardized and architected interrupt controller, the GIC provides a rich and flexible approach to inter-processor communication and the routing and prioritization of system interrupts. Supporting up to 288 independent interrupts, under software control, hardware prioritized, and routed between the operating system and TrustZone software management layer. This routing flexibility and the support for virtualization of interrupts into the operating system, provides one of the key features required to enhance the capabilities of a solution utilizing a hypervisor. 20/245 DS12500 Rev 1 STM32MP151A 3.2 Functional overview Arm(R) Cortex(R)-M4 with FPU The Arm(R) Cortex(R)-M4 with FPU core is a 32-bit RISC processor that features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. Note: Cortex-M4 with FPU core is binary compatible with the Cortex-M3 core. Memory protection unit (MPU) The memory protection unit (MPU) manages the Cortex(R)-M4 access rights and the attributes of the system resources. It has to be programmed and enabled before use. Its main purposes are to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by a privileged task, but also to protect data processes or read-protect memory regions. The MPU defines access rules for privileged accesses and user program accesses. It allows the definition of up to 16 protected regions that can in turn be divided into up to 8 independent subregions, where region address, size, and attributes can be configured. The protection area ranges from 32 bytes to 4 Gbytes of addressable memory. When an unauthorized access is performed, a memory management exception is generated. DS12500 Rev 1 21/245 54 Functional overview 3.3 Memories 3.3.1 External SDRAM STM32MP151A The STM32MP151A devices embed a controller for external SDRAM which support the following devices 3.3.2 * LPDDR2 or LPDDR3, 16- or 32-bit data, up to 1 Gbyte, up to 533 MHz clock. * DDR3 or DDR3L, 16- or 32-bit data, up to 1 Gbyte, up to 533 MHz clock. Embedded SRAM All devices feature: * SYSRAM in MPU domain: 256 Kbytes * SRAM1 in MCU domain: 128 Kbytes * SRAM2 in MCU domain: 128 Kbytes * SRAM3 in MCU domain: 64 Kbytes * SRAM4 in MCU domain: 64 Kbytes * RETRAM (retention RAM): 64 Kbytes * BKPSRAM (backup SRAM): 4 Kbyte The content of this area can be retained in Standby or VBAT mode. The content of this area is protected against possible unwanted write accesses, and can be retained in Standby or VBAT mode. BKPSRAM can be defined (in ETZPC) as accessible by secure software only. 22/245 DS12500 Rev 1 STM32MP151A 3.4 Functional overview DDR3/DDR3L/LPDDR2/LPDDR3 controller (DDRCTRL) DDRCTRL combined with DDRPHYC provides a complete memory interface solution for DDR memory subsystem. * Two 64-bit AMBA 4 AXI4 ports interface (XPI) * AXI clock asynchronous to the controller * Supported standards: - JEDEC DDR3 SDRAM specification, JESD79-3E for DDR3/3L with 32-bit interface - JEDEC LPDDR2 SDRAM specification, JESD209-2E for LPDDR2 with 32-bit interface - JEDEC LPDDR3 SDRAM specification, JESD209-3B for LPDDR3 with 32-bit interface * Advanced scheduler and SDRAM command generator * Programmable full data width (32-bit) or half data width (16-bit) * Advanced QoS support with 3 traffic class on read and 2 traffic classes on write * Options to avoid starvation of lower priority traffic * Guaranteed coherency for write-after-read (WAR) and read-after-write (RAW) on AXI ports * Programmable support for burst length options (4, 8,16) * Write combine to allow multiple writes to the same address to be combined into a single write * Single rank configuration * Supports automatic SDRAM power-down entry and exit caused by lack of transaction arrival for programmable time * Supports automatic clock stop (LPDDR2/3) entry and exit caused by lack of transaction arrival * Supports automatic low power mode operation caused by lack of transaction arrival for programmable time via hardware low power interface * Programmable paging policy * Supports automatic or under software control self-refresh entry and exit * Support for deep power-down entry and exit under software control (LPDDR2) * Support for explicit SDRAM mode register updates under software control * Flexible address mapper logic to allow application specific mapping of row, column, bank bits * User-selectable refresh control options * DDRPERFM associated block to help for performance monitoring and tuning DDRCTRL and DDRPHYC can be defined (in ETZPC) as accessible by secure software only. DS12500 Rev 1 23/245 54 Functional overview 3.5 STM32MP151A TrustZone address space controller for DDR (TZC) TZC is used to filter read/write accesses to DDR controller according to TrustZone rights and according to non-secure master (NSAID) on up to 9 programmable regions. 24/245 * Configuration is supported by trusted software only * 2 filter units working concurrently 9 regions: - region 0 is always enabled and covers the whole address range. - regions 1 to 8 have programmable base/end address and can be assigned to any one or both filters. * Secure and non-secure access permissions programmed per region * Non-secure accesses are filtered according to NSAID * Regions controlled by same filter must not overlap * Fail modes with error and/or interrupt * Acceptance capability = 256 * Gate keeper logic to enable and disable of each filter * Speculative accesses DS12500 Rev 1 STM32MP151A 3.6 Functional overview Boot modes At startup, the boot source used by the internal BootROM is selected by the BOOT pin and OTP bytes. Table 2. Boot modes BOOT2 BOOT1 BOOT0 Initial boot mode 0 0 0 UART and USB(1) Wait incoming connection on: - USART2/3/6 and UART4/5/7/8 on default pins - USB high-speed device(2) 0 0 1 Serial NOR Flash(3) Serial NOR Flash on QUADSPI(4) 0 1 0 e*MMC(3) e*MMC on SDMMC2 (default)(4)(5) 0 1 1 NAND Flash(3) SLC NAND Flash on FMC 1 0 0 Reserved (NoBoot) Used to get debug access without boot from Flash memory card(3) Comments SD card on SDMMC1 (default)(4)(5) 1 0 1 SD 1 1 0 UART and USB(1)(3) Wait incoming connection on: - USART2/3/6 and UART4/5/7/8 on default pins - USB high-speed device on OTG_HS_DP/DM pins(2) 1 1 1 Serial NAND Flash(3) Serial NAND Flash on QUADSPI(4) 1. can be disabled by OTP settings. 2. USB requires 24 MHz HSE clock/crystal if OTP is not programmed for different frequency. 3. Boot source can be changed by OTP settings (e.g. initial boot on SD card, then e*MMC with OTP settings). 4. Default pins can be altered by OTP. 5. Alternatively, another SDMMC1 or SDMMC2 interface than this default can be selected by OTP. DS12500 Rev 1 25/245 54 Functional overview STM32MP151A 3.7 Power supply management 3.7.1 Power supply scheme * The VDD is the main supply for I/Os and internal part kept powered during Standby mode. Useful voltage range is 1.71 V to 3.6 V (e.g. 1.8 V, 2.5 V, 3.0 V or 3.3 V typ.) - VDD_PLL and VDD_ANA must be star-connected to VDD. * The VDDCORE is the main digital voltage and is usually shutdown during Standby mode. Voltage range is 1.10 V to 1.28 V (1.2 V typ.). * The VBAT pin can be connected to the external battery (1.2 V < VBAT < 3.6 V). If no external battery is used, it is mandatory to connect this pin to VDD. * The VDDA pin is the analog (ADC/DAC/VREF), supply voltage range is 1.71 V to 3.6 V. DAC can only be used when VDDA is above or equal 1.8 V. Using Internal VREF+ requires VDDA equal to or higher than VREF+ + 0.3 V. * The VDDA1V8_REG pin is the output of internal regulator and connected internally to USB PHY and USB PLL. Internal VDDA1V8_REG regulator is enabled by default and can be controlled by software. It is always shut down during Standby mode. There is specific BYPASS_REG1V8 pin that must be connected either to VSS or VDD to activate or deactivate the voltage regulator. It is mandatory to bypass the 1.8 V regulator when VDD is below 2.25 V (BYPASS_REG1V8 = VDD). In that case, VDDA1V8_REG pin must be connected to VDD (if below 1.98 V) or to a dedicated 1.65 V - 1.98 V supply (1.8 V typ.). * Caution: * VDDA1V1_REG pin is the output of internal regulator connected internally to USB PHY. Internal VDDA1V1_REG regulator is enabled by default and can be controlled by software. It is always shut down during Standby mode. * VDD3V3_USBHS and VDD3V3_USBFS are respectively the USB high-speed and full-speed PHY supply. Voltage range is 3.1 V to 3.6 V. VDD3V3_USBFS is used to supply VBUS and ID pins. So, VDD3V3_USBFS must be supplied as well when USB high-speed OTG device is used. If not used, must be connected to VDD. VDD3V3_USBHS must not be present unless VDDA1V8_REG is present, otherwise permanent STM32MP151A damage could occur. Must be ensured by PMIC ranking order or with external component in case of discrete component power supply implementation. * VDDQ_DDR is the DDR IO supply. - Voltage range is 1.425 V to 1.575 V for interfacing DDR3 memories (1.5 V typ.). - Voltage range is 1.283 V to 1.45 V for interfacing DDR3L memories (1.35 V typ.). - Voltage range is 1.14 V to 1.3 V for interfacing LPDDR2 or LPDDR3 memories (1.2 V typ.). During power-up and power-down phases, the following power sequence requirements must be respected: * When VDD is below 1 V, other power supplies (VDDCORE, VDDA, VDDA1V8_REG, VDDA1V1_REG, VDD3V3_USBHS/FS, VDDQ_DDR) must remain below VDD + 300 mV. * When VDD is above 1 V, all power supplies are independent. During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the STM32MP151A device remains below 1 mJ; this allows 26/245 DS12500 Rev 1 STM32MP151A Functional overview external decoupling capacitors to be discharged with different time constants during the power- down transient phase. Figure 2. Power-up/down sequence V 3.6 VDDX(1) VDD VBOR0 1 0.3 Power-on Invalid supply area Operating mode VDDX < VDD + 300 mV Power-down VDDX independent from VDD time MSv47490V1 1. VDDX refers to any power supply among VDDCORE, VDDA, VDDA1V8_REG, , VDDA1V1_REG, VDD3V3_USBHS/FS, VDDQ_DDR. 3.7.2 Power supply supervisor The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry: * Power-on reset (POR) The POR supervisor monitors VDD power supply and compares it to a fixed threshold. The devices remain in reset mode when VDD is below this threshold, * Power-down reset (PDR) The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops below a fixed threshold. The PDR supervisor can be enabled/disabled through PDR_ON pin. * Brownout reset (BOR) The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to 2.7 V) can be configured through option bytes. A reset is generated when VDD drops below this threshold. * Power-on reset VDDCORE (POR_VDDCORE) The POR_VDDCORE supervisor monitors VDDCORE power supply and compares it to a fixed threshold. The VDDCORE domain remain in reset mode when VDDCORE is below this threshold, * Power-down reset VDDCORE (PDR_VDDCORE) The PDR_VDDCORE supervisor monitors VDDCORE power supply. A VDDCORE domain reset is generated when VDDCORE drops below a fixed threshold. The PDR_VDDCORE supervisor can be enabled/disabled through PDR_ON_CORE pin. DS12500 Rev 1 27/245 54 Functional overview 3.8 STM32MP151A Low-power strategy There are several ways to reduce power consumption on STM32MP151A: * Decrease dynamic power consumption by slowing down the CPU clocks and/or the bus matrix clocks and/or controlling individual peripheral clocks. * Save power consumption when the CPU is IDLE, by selecting among the available lowpower mode according to the user application needs. This allows the best compromise between short startup time, low-power consumption, as well as available wakeup sources, to be achieved. The CPUs feature several low-power modes: * CSleep (CPU clock stopped) * CStop (CPU sub-system clock stopped) * Stop (bus matrix clocks stalled, the oscillators can be stopped) * CStandby (MPU sub-system clock stopped and wakeup via reset) * Standby (system powered down) * LP-Stop and LPLV-Stop (bus matrix clocks stalled, the oscillators can be stopped, lowpower mode signaled to external regulator) CSleep and CStop low-power modes are entered by the CPU when executing the WFI (wait for interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of the Cortex-M4 core is set after returning from an interrupt service routine. If part of the domain is not in low-power mode, the domain remains in the current mode. Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared and the CPUs are in CStop or CStandby mode. Table 3. System versus domain power mode System power mode MPU CRun or CSleep Run mode 28/245 CStop or CStandby MCU CRun or CSleep CRun or CSleep CStop Stop mode LP-Stop mode LPLV-Stop mode CStop or CStandby CStop Standby mode CStandby or (CStop and MPU PDDS = 1 and MPU CSTBYDIS = 1) CStop and MCU PDDS = 1 DS12500 Rev 1 STM32MP151A 3.9 Functional overview Reset and clock controller (RCC) The clock and reset controller manages the generation of all the clocks, as well as the clock gating and the control of the system and peripheral resets. It provides a high flexibility in the choice of clock sources and allows application of clock ratios to improve the power consumption. In addition, on some communication peripherals that are capable to work with two different clock domains (either a bus interface clock or a kernel peripheral clock), the system frequency can be changed without modifying the baudrate. 3.9.1 Clock management The devices embed four internal oscillators, two oscillators with external crystal or resonator, three internal oscillators with fast startup time and four PLLs. The RCC receives the following clock source inputs: * * Internal oscillators: - 64 MHz HSI clock (1% accuracy) - 4 MHz CSI clock - 32 kHz LSI clock External oscillators: - 8-48 MHz HSE clock - 32.768 kHz LSE clock The RCC provides four PLLs: * The PLL1 is dedicated to the MPU clocking * The PLL2 provides: * * - The clocks for the AXI-SS (including APB4, APB5, AHB5 and AHB6 bridges) - The clocks for the DDR interface The PLL3 provides: - The clocks for the MCU, and its bus matrix (including the APB1, APB2, APB3, AHB1, AHB2, AHB3 and AHB4) - The kernel clocks for peripherals The PLL4 is dedicated to the generation of the kernel clocks for various peripherals The system starts on the HSI clock. The user application can then select the clock configuration. DS12500 Rev 1 29/245 54 Functional overview 3.9.2 STM32MP151A System reset sources The power-on reset initializes all registers while the system reset reinitializes the system except for the debug, part of the RCC and power controller status registers, as well as the backup power domain. An application reset is generated from one of the following sources: - a reset from NRST pad - a reset from POR and PDR signal (generally called power-on reset) - a reset from BOR (generally called brownout) - a reset from the independent watchdogs 1 - a reset from the independent watchdogs 2 - a software reset from the Cortex-M4 (MCU) - a software reset from the Cortex-A7 (MPU) - a failure on HSE, when the clock security system feature is activated A system reset is generated from one of the following sources: 3.10 - An application reset, - A reset from POR_VDDCORE signal, - Every time the system exits from Standby. Hardware semaphore (HSEM) The HW semaphore block provides 64 (32-bit) register-based semaphores. The semaphores can be used to ensure synchronization between different processes running on a core and between different cores. The HSEM provides a non blocking mechanism to lock semaphores in an atomic way. The following functions are provided: * * Locking a semaphore can be done in 2 ways: - 2-step lock: by writing CoreID and ProcessID to the semaphore, followed by a read check. - 1-step lock: by reading the CoreID from the semaphore. Interrupt generation when a semaphore is freed. - * Semaphore clear protection. - * 3.11 Each semaphore may generated an interrupt on one of the interrupt lines. A semaphore is only cleared when CoreID and ProcessID matches. Global semaphore clear per CoreID. Inter-processor communication controller (IPCC) The inter-processor communication controller (IPCC) is used for communicating data between two processors. The IPCC block provides a non blocking signaling mechanism to post and retrieve communication data in an atomic way. It provides the signaling for four channels: 30/245 * two channels in the direction from processor 1 to processor 2 * two channels in the opposite direction. DS12500 Rev 1 STM32MP151A Functional overview It is then possible to have two different communication types in each direction. The IPCC communication data must be located in a common memory, which is not part of the IPCC block. 3.11.1 IPCC main features * Status signaling for the four channels - * * * 3.12 Channel occupied/free flag, also used as lock Two interrupt lines per processor - One for RX channel occupied (communication data posted by sending processor) - One for TX channel free (communication data retrieved by receiving processor) Interrupt masking per channel - Channel occupied mask - Channel free mask Two channel operation modes - Simplex (each channel has its own communication data memory location) - Half duplex (a single channel in associated to a bidirectional communication data information memory location) General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. After reset, all GPIOs are in analog mode to reduce power consumption. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Additionally, GPIO pins on port Z can be individually set as secure, which would mean that software accesses to these GPIOs and associated peripherals defined as secure are restricted to secure software running on Cortex-A7. 3.13 TrustZone protection controller (ETZPC) ETZPC is used to configure TrustZone security of bus masters and slaves with programmable-security attributes (securable resources) such as: * On-chip SYSRAM with programmable secure region size * AHB and APB peripherals to be made secure Notice that by default, SYSRAM and peripheral are set to secure access only, so, not accessible by non-secure masters such as Cortex-M4 or DMA1/DMA2. ETZPC can also allocate peripherals and SRAM to be accessible only by the Cortex-M4 and/or DMA1/DMA2. This ensures the safe execution of the Cortex-M4 firmware, protected from other masters (e.g. Cortex-A7) unwanted accesses. DS12500 Rev 1 31/245 54 Functional overview 3.14 STM32MP151A Bus-interconnect matrix The devices feature an AXI bus matrix, one main AHB bus matrix and bus bridges that allow bus masters to be interconnected with bus slaves (see Figure 3, the dots represent the enabled master/slave connections). 32/245 DS12500 Rev 1 STM32MP151A Functional overview LTDC MDMA SDMMC2 SDMMC1 CPU 128-bit ETH USBH From MCU interconnect DBG Figure 3. STM32MP151A bus matrix M10 M0 M1 M2 M3 M4 M5 M6 M7 M9 S0 MPU_AXI_DDR1 S1 MPU_AXI_DDR2 S2 MPU_AHB6 S3 MPU_AHB_MCU S4 MPU_AXI_FMC S5 MPU_AXI_QUADSPI S6 MPU_AXI_SYSRAM S7 MPU_AXI_ROM S8 MPU_AXI_STM S9 MPU_AHB5 S10 MPU_APB5 S11 MPU_DBG_APB AXIM DDRCTRL 533 MHz AHB bridge to AHB6 To MCU interconnect FMC/NAND QUADSPI SYSRAM 256 KB ROM 128 KB STM AHB bridge to AHB5 APB bridge to APB5 APB bridge to DBG APB Default slave AXIMC Masters access S0 XOR S1 layer AXI 64 synchronous master port NIC-400 AXI 64 bits 266 MHz - 10 masters / 12 slaves AXI 64 asynchronous slave port M2 M3 M4 M5 M6 M7 AHB 32 asynchronous master port I-BUS D-BUS S-BUS M1 AHB 32 synchronous slave port M8 AHB 32 asynchronous slave port M9 MLAHB M0 AHB 32 synchronous master port CM4 USBO DMA2 SDMMC3 AXI 64 asynchronous master port DMA1 From MPU interconnect AXI 64 synchronous slave port S0 MCU_AHB_MEM0 S1 MCU_AHB_MEM1 S2 MCU_AHB_MEM2 S8 MCU_AHB_MEM3 S3 MCU_AHB3 S4 MCU_AHB2 S5 MCU_AHB_MPU S6 MCU_AHB_RET S7 MCU_AHB4 Interconnect AHB 32 bits 209 MHz - 7 masters / 9 slaves DS12500 Rev 1 SRAM1 SRAM2 SRAM3 SRAM4 Bridge to AHB3 Bridge to AHB2 To MPU interconnect RetentionRAM Bridge to AHB4 MSv47456V2 33/245 54 Functional overview 3.15 STM32MP151A DMA controllers The devices features three DMA modules to unload CPU activity: * A master direct memory access (MDMA) The MDMA is a high-speed DMA controller, which is in charge of all types of memory transfers (peripheral to memory, memory to memory, memory to peripheral), without any CPU action. It features a master AXI interface. The MDMA is located in MPU domain. It is able to interface with the other DMA controllers located in MCU domain to extend the standard DMA capabilities, or can manage peripheral DMA requests directly. Each of the 32 channels can perform block transfers, repeated block transfers and linked list transfers. The MDMA can be set to make secure transfers to secured memories. * Two DMA controllers (DMA1, DMA2), located in MCU domain. Each controller is a dual-port AHB, for a total of 16 DMA channels to perform FIFO-based block transfers. The DMAMUX is an extension of the DMA1 and DMA2 controllers. It multiplexes and routes the DMA peripheral requests to the DMA1 or DMA2 controllers, with a high flexibility, maximizing the number of DMA requests that run concurrently, as well as generating DMA requests from peripheral output trigger or DMA event. 3.16 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt lines of the Cortex(R)M4 with FPU core. * Closely coupled NVIC gives low-latency interrupt processing * Interrupt entry vector table address passed directly to the core * Allows early processing of interrupts * Processing of late arriving, higher-priority interrupts * Support tail chaining * Processor context automatically saved * Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 3.17 Extended interrupt and event controller (EXTI) The extended interrupt and event controller (EXTI) manages individual CPU and system wakeup through configurable and direct event inputs. It provides wake-up requests to the power control, and generates an interrupt request to the CPUs NVIC or GIC and events to the CPUs event inputs. For each CPU an additional event generation block (EVG) is needed to generate the CPU event signal. The EXTI wake-up requests allow the system to be woken up from Stop mode, and the CPUs to be woken up from CStop and CStandby modes. The interrupt request and event request generation can also be used in Run mode. 34/245 DS12500 Rev 1 STM32MP151A Functional overview The block also includes the EXTI IOport selection. Each interrupt or event can be set as secure in order to restrict access to secure software only. 3.18 Cyclic redundancy check calculation unit (CRC1, CRC2) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a programmable polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps computing a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.19 Flexible memory controller (FMC) The FMC controller main features are the following: * Interface with static-memory mapped devices including: 3.20 - NOR Flash memory - Static or pseudo-static random access memory (SRAM, PSRAM) - NAND Flash memory with 4-bit/8-bit BCH hardware ECC * 8-,16-bit data bus width * Independent chip select control for each memory bank * Independent configuration for each memory bank * Write FIFO Dual Quad-SPI memory interface (QUADSPI) The QUADSPI is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes: * indirect mode: all the operations are performed using the QUADSPI registers * status polling mode: the external Flash memory status register is periodically read and an interrupt can be generated in case of flag setting * memory-mapped mode: the external Flash memory is mapped to the address space and is seen by the system as if it was an internal memory Both throughput and capacity can be increased two-fold using dual-flash mode, where two Quad-SPI Flash memories are accessed simultaneously. QUADSPI is coupled with a delay block (DLYBQS) allowing the support of external data frequency above 100 MHz. DS12500 Rev 1 35/245 54 Functional overview 3.21 STM32MP151A Analog-to-digital converters (ADCs) The STM32MP151A devices embed two analog-to-digital converters, which resolution can be configured to 16, 14, 12, 10 or 8 bits. Each ADC shares up to 20 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: * simultaneous ADC1/ADC2 conversion * interleaved ADC1/ADC2 conversion. The ADC can be served by the DMA controller, thus allowing the automatic transfer of ADC converted values to a destination location without any software action. In addition, an analog watchdog feature can accurately monitor the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. In order to synchronize A/D conversion and timers, the ADCs can be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, LPTIM1, LPTIM2 and LPTIM3 timers. 3.22 Temperature sensor The STM32MP151A devices embed a temperature sensor that generates a voltage (VTS) that varies linearly with the temperature. This temperature sensor is internally connected to ADC2_INP12. It can measure the device ambient temperature ranging from -40 to +125 C with a precision of 2%. The temperature sensor has a good linearity, but it has to be calibrated to obtain a good overall accuracy of the temperature measurement. As the temperature sensor offset varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the OTP area, which is accessible in read-only mode. 3.23 Digital temperature sensor (DTS) The device embeds a frequency output temperature sensor. This block counts the frequency based on the LSE or PCLK to provide the temperature information. Following functions can be supported: 3.24 * Interrupt generation by temperature threshold. * Wakeup signal generation by temperature threshold. VBAT operation The VBAT power domain contains the RTC, the backup registers, the retention RAM and the backup SRAM. 36/245 DS12500 Rev 1 STM32MP151A Functional overview In order to optimize battery duration, this power domain is supplied by VDD when available or by the voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched when the PDR detects that VDD has dropped below the PDR level. The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or directly by VDD. In the later case, VBAT mode is not functional. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers, the retention RAM and the backup SRAM. Note: None of these events: external interrupts, TAMP event, or RTC alarm/events are able to directly restore the VDD supply and force the STM32MP151A device out of the VBAT operation. Nevertheless, TAMP events and RTC alarm/events can be used to generate a signal to an external circuitry (typically a PMIC) that can restore the STM32MP151A VDD supply. When PDR_ON pin is connected to VSS (internal reset OFF), the VBAT functionality is no more available and VBAT pin must be connected to VDD. 3.25 Digital-to-analog converters (DAC1, DAC2) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital interface supports the following features: * Two DAC converters: one for each output channel * 8-bit or 12-bit monotonic output * Left or right data alignment in 12-bit mode * Synchronized update capability * Noise-wave generation * Triangular-wave generation * Sample and hold mode to reduce the power consumption * Dual DAC channel independent or simultaneous conversions * DMA capability for each channel including DMA underrun error detection * External triggers for conversion * input voltage reference VREF+ or internal VREFBUF reference. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. DS12500 Rev 1 37/245 54 Functional overview 3.26 STM32MP151A Voltage reference buffer (VREFBUF) The STM32MP151A devices embed a voltage reference buffer which can be used as voltage reference for ADC, DACs and also as voltage reference for external components through the VREF+ pin. The internal voltage reference buffer supports four voltages: * 1.5 V * 1.8 V * 2.048 V * 2.5 V An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off. Figure 4. Voltage reference buffer VREFBUF VDDA Bandgap + DAC, ADC VREF+ Low frequency cut-off capacitor 100 nF MSv40197V1 3.27 Digital filter for sigma delta modulators (DFSDM1) The device embeds one DFSDM with support for 6 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs. The DFSDM peripheral is dedicated to interface external modulators to STM32MP151A and perform digital filtering of the received data streams. modulators are used to convert analog signals into digital serial streams that constitute the inputs of the DFSDM. The DFSDM can also interface PDM (pulse density modulation) microphones and perform the PDM to PCM conversion and filtering (hardware accelerated). The DFSDM features optional parallel data stream inputs from internal ADC peripherals or STM32MP151A memory (through DMA/CPU transfers into DFSDM). The DFSDM transceivers support several serial interface formats (to support various modulators). DFSDM digital filter modules perform digital processing according user-defined filter parameters with up to 24-bit final ADC resolution. 38/245 DS12500 Rev 1 STM32MP151A Functional overview The DFSDM peripheral supports: * * 8 multiplexed input digital serial channels: - configurable SPI interface to connect various SD modulator(s) - configurable Manchester coded 1-wire interface support - PDM (pulse density modulation) microphone input support - maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) - clock output for SD modulator(s): 0...20 MHz Alternative inputs from 8 internal digital parallel channels (up to 16-bit input resolution): - * internal sources: ADC data or memory data streams (DMA) 6 digital filter modules with adjustable digital signal processing: - Sincx filter: filter order/type (1...5), oversampling ratio (1...1024) - integrator: oversampling ratio (1...256) * Up to 24-bit output data resolution, signed output data format * Automatic data offset correction (offset stored in register by user) * Continuous or single conversion * Start-of-conversion triggered by: * * - software trigger - internal timers - external events - start-of-conversion synchronously with first digital filter module (DFSDM0) Analog watchdog feature: - low value and high value data threshold registers - dedicated configurable Sincx digital filter (order = 1...3, oversampling ratio = 1...32) - input from final output data or from selected input digital serial channels - continuous monitoring independently from standard conversion Short circuit detector to detect saturated analog input values (bottom and top range): - up to 8-bit counter to detect 1...256 consecutive 0's or 1's on serial data stream - monitoring continuously each input serial channel * Break signal generation on analog watchdog event or on short circuit detector event * Extremes detector: - storage of minimum and maximum values of final conversion data - refreshed by software * DMA capability to read the final conversion data * Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence * "Regular" or "injected" conversions: - "regular" conversions can be requested at any time or even in continuous mode without having any impact on the timing of "injected" conversions - "injected" conversions for precise timing and with high conversion priority DS12500 Rev 1 39/245 54 Functional overview 3.28 STM32MP151A Digital camera interface (DCMI) The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock and 14-bit of data. It features: 3.29 * Programmable polarity for the input pixel clock and synchronization signals * Parallel data communication can be 8-, 10-, 12- or 14-bit * Supports 8-bit progressive video monochrome or raw Bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) * Supports continuous mode or snapshot (a single frame) mode * Capability to automatically crop the image LCD-TFT display controller (LTDC) The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to WXGA (1366x768) @60 fps resolution with the following features: 3.30 * 2 display layers with dedicated FIFO * Color look-up table (CLUT) up to 256 colors (256x24-bit) per layer * Up to 8 input color formats selectable per layer * Flexible blending between two layers using alpha value (per pixel or constant) * Flexible programmable parameters for each layer * Color keying (transparency color) * Up to 4 programmable interrupt events * AXI master interface True random number generator (RNG1, RNG2) All the devices embed two RNG that deliver 32-bit random numbers generated by an integrated analog circuit. RNG1 can be defined (in ETZPC) as accessible by secure software only. 3.31 Hash processors (HASH1, HASH2) The devices embed two processors that support the advanced algorithms usually required to ensure authentication, data integrity and non-repudiation when exchanging messages with a peer: * Universal HASH - SHA-1, SHA224 and SHA256 (secure HASH algorithms) - MD5 - HMAC The accelerator supports DMA request generation. HASH1 can be defined (in ETZPC) as accessible by secure software only. 40/245 DS12500 Rev 1 STM32MP151A 3.32 Functional overview Boot and security and OTP control (BSEC) The BSEC (boot and security and OTP control) is intended to control an OTP (one time programmable) fuse box, used for embedded non-volatile storage for device configuration and security parameters. Some part of BSEC should be configured as accessible by secure software only. 3.33 Timers and watchdogs The devices include two advanced-control timers, ten general-purpose timers, two basic timers, five low-power timers, three watchdogs, a SysTick timer in Cortex-M4 and 4 system timers in Cortex-A7. All timer counters can be frozen in debug mode. Table 4 compares the features of the advanced-control, general-purpose, basic and lowpower timers. Table 4. Timer feature comparison Timer Advanced -control TIM1, TIM8 16-bit Up, Any integer down, between 1 up/down and 65536 Yes 4 Yes 100 209 TIM2, TIM5 32-bit Up, Any integer down, between 1 up/down and 65536 Yes 4 No 100 209 TIM3, TIM4 16-bit Up, Any integer down, between 1 up/down and 65536 Yes 4 No 100 209 TIM12 16-bit Up Any integer between 1 and 65536 No 2 No 100 209 TIM13, TIM14 16-bit Up Any integer between 1 and 65536 No 1 No 100 209 TIM15 16-bit Up Any integer between 1 and 65536 Yes 2 1 100 209 TIM16, TIM17 16-bit Up Any integer between 1 and 65536 Yes 1 1 100 209 General purpose Counter Counter resolution type Prescaler factor Max Max DMA Capture/ Compleinterface timer request compare mentary clock clock generation channels output (MHz) (MHz)(1) Timer type DS12500 Rev 1 41/245 54 Functional overview STM32MP151A Table 4. Timer feature comparison (continued) Counter Counter resolution type Prescaler factor Max Max DMA Capture/ Compleinterface timer request compare mentary clock clock generation channels output (MHz) (MHz)(1) Timer type Timer Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 100 209 Lowpower LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5 16-bit Up 1, 2, 4, 8, 16, 32, 64, 128 No 0 No 100 209 1. The maximum timer clock is up to 209 MHz depending on TIMGxPRE bit in the RCC. 42/245 DS12500 Rev 1 STM32MP151A 3.33.1 Functional overview Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: * Input capture * Output compare * PWM generation (edge- or center-aligned modes) * One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The advanced-control timer can work together with the general-purpose timers via the timer link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. 3.33.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17) There are ten synchronizable general-purpose timers embedded in the STM32MP151A devices (see Table 4 for differences). * TIM2, TIM3, TIM4, TIM5 The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and TIM5. TIM2 and TIM5 are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. All timers feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the timer link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. * TIM12, TIM13, TIM14, TIM15, TIM16, TIM17 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12 and TIM15 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers or used as simple timebases. DS12500 Rev 1 43/245 54 Functional overview 3.33.3 STM32MP151A Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. 3.33.4 Low-power timer (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the device from Stop mode. These low-power timer supports the following features: 3.33.5 * 16-bit up counter with 16-bit autoreload register * 16-bit compare register * Configurable output: pulse, PWM * Continuous / one-shot mode * Selectable software / hardware input trigger * Selectable clock source: * Internal clock source: LSE, LSI, HSI or APB clock * External clock source over LPTIM input (working even with no internal clock source running, used by the pulse counter application) * Programmable digital glitch filter * Encoder mode Independent watchdog (IWDG1, IWDG2) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC(LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. IWDG1 can be defined (in ETZPC) as accessible by secure software only. 3.33.6 System window watchdog (WWDG1) The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.33.7 SysTick timer (Cortex-M4) This timer is embedded inside Cortex-M4 core and dedicated to real-time operating systems, but can also be used as a standard downcounter. It features: 44/245 * A 24-bit downcounter * Autoreload capability * Maskable system interrupt generation when the counter reaches 0 * Programmable clock source. DS12500 Rev 1 STM32MP151A 3.33.8 Functional overview Generic timers (Cortex-A7 CNT) Cortex-A7 generic timers embedded inside Cortex-A7 are fed by value from system timing generation (STGEN). The Cortex-A7 processor provides a set of four timers: * Physical timer for use in secure and non-secure modes. The registers for the physical timer are banked to provide secure and non-secure copies. * Virtual timer for use in non-secure modes. * Physical timer for use in hypervisor mode. Generic timers are not memory mapped peripherals, they are accessible only by specific Cortex-A7 coprocessor instructions (cp15). 3.34 System timer generation (STGEN) The system timing generation (STGEN) generates a time count value that provides a consistent view of time for all Cortex-A7 generic timers. The system timing generation has the following key features: * 64-bit wide to avoid roll-over issues. * Starts from zero or a programmable value. * A control APB interface (STGENC) enables the timer to be saved and restored across powerdown events. * Read-only APB interface (STGENR) enables the timer value to be read by non-secure software and debug tools. * The timer value incrementing can be stopped during system debug. STGENC can be defined (in ETZPC) as accessible by secure software only. 3.35 Real-time clock (RTC) The RTC provides an automatic wakeup to manage all low-power modes. The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a timeof-day clock/calendar with programmable alarm interrupts. The RTC includes also a periodic programmable wakeup flag with interrupt capability. Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of month), month, and year, expressed in binary coded decimal format (BCD). The sub-seconds value is also available in binary format. Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed automatically. Daylight saving time compensation can also be performed. Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. A digital calibration feature is available to compensate for any deviation in crystal oscillator accuracy. After backup domain reset, all RTC registers are protected against possible parasitic write accesses. DS12500 Rev 1 45/245 54 Functional overview STM32MP151A As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, Low-power mode or under reset). The RTC unit main features are the following: * Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year. * Daylight saving compensation programmable by software. * Programmable alarm with interrupt function. The alarm can be triggered by any combination of the calendar fields. * Automatic wakeup unit generating a periodic flag that triggers an automatic wakeup interrupt. * Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. * Accurate synchronization with an external clock using the subsecond shift feature. * Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a calibration window of several seconds * Timestamp function for event saving * Maskable interrupts/events: * 3.36 - Alarm A - Alarm B - Wakeup interrupt - Timestamp TrustZone support: - RTC fully securable - Alarm A, alarm B, wakeup timer and timestamp individual secure or non-secure configuration Tamper and backup registers (TAMP) 32 x 32-bit backup registers are retained in all low-power modes and also in VBAT mode. They can be used to store sensitive data as their content is protected by an tamper detection circuit. 3 tamper pins and 5 internal tampers are available for anti-tamper detection. The external tamper pins can be configured for edge detection, edge and level, level detection with filtering, or active tamper which increases the security level by auto checking that the tamper pins are not externally opened or shorted. 46/245 DS12500 Rev 1 STM32MP151A Functional overview TAMP main features * 32 backup registers: - * the backup registers (TAMP_BKPxR) are implemented in the RTC domain that remains powered-on by VBAT when the VDD power is switched off. 3 external tamper detection events. - Each external event can be configured to be active or passive. - External passive tampers with configurable filter and internal pull-up. * 5 internal tamper events. * Any tamper detection can generate a RTC timestamp event. * Any tamper detection erases the backup registers. * TrustZone support: - Tamper secure or non-secure configuration. - Backup registers configuration in 3 configurable-size areas: 1 read/write secure area. 1 write secure/read non-secure area. 1 read/write non-secure area. * Monotonic counter. DS12500 Rev 1 47/245 54 Functional overview 3.37 STM32MP151A Inter-integrated circuit interface (I2C1, I2C2, I2C3, I2C4, I2C5, I2C6) The STM32MP151A embeds six I2C interfaces. The I2C bus interface handles communications between the STM32MP151A and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: * * I2C-bus specification and user manual rev. 5 compatibility: - Slave and master modes, multimaster capability - Standard-mode (Sm), with a bitrate up to 100 kbit/s - Fast-mode (Fm), with a bitrate up to 400 kbit/s - Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os - 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses - Programmable setup and hold times - Optional clock stretching System management bus (SMBus) specification rev 2.0 compatibility: - Hardware PEC (packet error checking) generation and verification with ACK control - Address resolution protocol (ARP) support - SMBus alert * Power system management protocol (PMBusTM) specification rev 1.1 compatibility * Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. * Wakeup from Stop mode on address match * Programmable analog and digital noise filters * 1-byte buffer with DMA capability I2C4 and I2C6 can be defined (in ETZPC) as accessible by secure software only. 3.38 Universal synchronous asynchronous receiver transmitter (USART1, USART2, USART3, USART6 and UART4, UART5, UART7, UART8) The STM32MP151A devices have four embedded universal synchronous receiver transmitters (USART1, USART2, USART3 and USART6) and four universal asynchronous receiver transmitters (UART4, UART5, UART7 and UART8). Refer to Table 5 for a summary of USARTx and UARTx features. These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN master/slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to communicate at speeds of up to 10 Mbit/s. USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816 compliant) and SPI-like communication capability. 48/245 DS12500 Rev 1 STM32MP151A Functional overview All USART have a clock domain independent from the CPU clock, allowing the USARTx to wake up the STM32MP151A from Stop mode using baudrates up to 200 Kbaud.The wake up events from Stop mode are programmable and can be: * Start bit detection * Any received data frame * A specific programmed data frame All USART interfaces can be served by the DMA controller. Table 5. USART features USART modes/features(1) USART1/2/3/6 UART4/5/7/8 Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode (master/slave) X - Smartcard mode X - Single-wire half-duplex communication X X IrDA SIR ENDEC block X X LIN mode X X Dual clock domain and wakeup from low power mode X X Receiver timeout interrupt X X Modbus communication X X Auto baud rate detection X X Driver Enable X X USART data length 7, 8 and 9 bits 1. X = supported. USART1 can be defined (in ETZPC) as accessible by secure software only. 3.39 Serial peripheral interface (SPI1, SPI2, SPI3, SPI4, SPI5, SPI6)- inter- integrated sound interfaces (I2S1, I2S2, I2S3) The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that allow communication at up to 50 Mbit/s in master and slave modes, in half-duplex, fullduplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode, hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability. Three standard I2S interfaces (I2S1, I2S2, I2S3, multiplexed with SPI1, SPI2 and SPI3) are available. They can be operated in master or slave mode, in full-duplex and half-duplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling DS12500 Rev 1 49/245 54 Functional overview STM32MP151A frequency. All I2S interfaces support 16x 8-bit embedded Rx and Tx FIFOs with DMA capability. SPI6 can be defined (in ETZPC) as accessible by secure software only. 3.40 Serial audio interfaces (SAI1, SAI2, SAI3, SAI4) The devices embed 4 SAIs that allow the design of many stereo or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC'97. An SPDIF output is available when the audio block is configured as a transmitter. To bring this level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks. Each block has it own clock generator and I/O line controller. Audio sampling frequencies up to 192 kHz are supported. In addition, up to 8 microphones can be supported thanks to an embedded PDM interface. The SAI can work in master or slave configuration. The audio sub-blocks can be either receiver or transmitter and can work synchronously or asynchronously (with respect to the other one). The SAI can be connected with other SAIs to work synchronously. 3.41 SPDIF receiver interface (SPDIFRX) The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1). The main SPDIFRX features are the following: * Up to 4 inputs available * Automatic symbol rate detection * Maximum symbol rate: 12.288 MHz * Stereo stream from 32 to 192 kHz supported * Supports audio IEC-60958 and IEC-61937, consumer applications * Parity bit management * Communication using DMA for audio samples * Communication using DMA for control and user channel information * Interrupt capabilities The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and decode the incoming data stream. The user can select the wanted SPDIF input, and when a valid signal is available, the SPDIFRX re-samples the incoming signal, decode the Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the CPU decoded data, and associated status flags. The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF sub-frame rate that is used to compute the exact sample rate for clock drift algorithms. 50/245 DS12500 Rev 1 STM32MP151A 3.42 Functional overview Management data input/output (MDIOS) The devices embed a MDIO slave interface. It includes the following features: * - 32 x 16-bit firmware read/write, MDIO read-only output data registers - 32 x 16-bit firmware read-only, MDIO write-only input data registers * Configurable slave (port) address * Independently maskable interrupts/events: * 3.43 32 MDIO register addresses, each of which is managed using separate input and output data registers: - MDIO register write - MDIO register read - MDIO protocol error Able to operate in and wake up from Stop mode Secure digital input/output MultiMediaCard interface (SDMMC1, SDMMC2, SDMMC3) Three secure digital input/output MultiMediaCard interfaces (SDMMC) provide an interface between the AHB bus and SD memory cards, SDIO cards and MMC devices. The SDMMC features include the following: * Full compliance with MultiMediaCard System Specification Version 4.51. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit. * Full compatibility with previous versions of MultiMediaCards (backward compatibility). * Full compliance with SD memory card specifications version 4.1. (SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and UHS-II mode not supported). * Full compliance with SDIO card specification version 4.0. Card support for two different databus modes: 1-bit (default) and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and UHS-II mode not supported). * Data transfer up to 208 Mbyte/s for the 8-bit mode. (depending maximum allowed I/O speed). * Data and command output enable signals to control external bidirectional drivers. * The SDMMC host interface embeds a dedicated DMA controller allowing high-speed transfers between the interface and the SRAM. * IDMA linked list support Each SDMMC is coupled with a delay block (DLYBSD) allowing support of an external data frequency above 100 MHz. 3.44 Universal serial bus high-speed host (USBH) The devices embed one USB high-speed host (up to 480 Mbit/s) with two physical ports. USBH supports both low, full-speed (OHCI) as well as high-speed (EHCI) operations DS12500 Rev 1 51/245 54 Functional overview STM32MP151A independently on each port. It integrates two transceivers which can be used for either lowspeed (1.2 Mbit/s), full-speed (12 Mbit/s) or high-speed operation (480 Mbit/s), the second high-speed transceiver is shared with OTG high-speed. The USB HS is compliant with the USB 2.0 specification. The USB HS controllers require dedicated clocks that are generated by a PLL inside the USB high-speed PHY. 3.45 USB on-the-go high-speed (OTG) The devices embed one USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. OTG supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 Mbit/s) and high-speed operation (480 Mbit/s) shared with USB Host second port. The USB OTG HS is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controllers require a dedicated 48 MHz clock that is generated by a PLL inside RCC or inside the USB high-speed PHY. The main features are: 52/245 * Combined Rx and Tx FIFO size of 4 Kbyte with dynamic FIFO sizing * Supports the session request protocol (SRP) and host negotiation protocol (HNP) * 8 bidirectional endpoints * 16 host channels with periodic OUT support * Software configurable to OTG1.3 and OTG2.0 modes of operation * USB 2.0 LPM (link power management) support * Battery charging specification revision 1.2 support * Internal FS or HS OTG PHY support * Internal USB DMA * HNP/SNP/IP inside (no need for any external resistor) * For OTG/Host modes, a power switch is needed in case bus-powered devices are connected DS12500 Rev 1 STM32MP151A 3.46 Functional overview Gigabit Ethernet MAC interface (ETH1) The devices provide an IEEE-802.3-2002-compliant gigabit media access controller (GMAC) for Ethernet LAN communications through an industry-standard mediumindependent interface (MII), a reduced medium-independent interface (RMII), a gigabit medium-independent interface (GMII) or a reduced gigabit medium-independent interface (RGMII). The STM32MP151A requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device port using 17 signals for MII, 7 signals for RMII, 26 signals for GMII or 13 signals for RGMII, and can be clocked using the 25 MHz (MII, RMII, GMII, RGMII) or 125 MHz (GMII, RGMII) from the STM32MP151A or from the PHY. The devices include the following features: * * * * * Operation modes and PHY interfaces - 10, 100, and 1000 Mbps data transfer rates - Support of both full-duplex and half-duplex operations - MII, RMII, GMII and RGMII PHY interfaces Multiple queues support and audio video bridging (AVB) management - Separate channels or queues for AV data transfer in 100 and 1000 Mbps modes - Two queues on the Rx paths and two queues on the Tx path for AV traffic - One DMA for Rx path and two DMA for Tx path (one per transmit channels) - Several arbitration algorithms between queues: weighted round robin (WRR), strict priority (SP), weighted strict priority (WSP), IEEE 802.1-Qav specified creditbased shaper (CBS) algorithm for Transmit channels Processing control - Multi-layer Packet filtering: MAC filtering on source (SA) and destination (DA) address with perfect and hash filter, VLAN tag-based filtering with perfect and hash filter, Layer 3 filtering on IP source (SA) or destination (DA) address, Layer 4 filtering on source (SP) or destination (DP) port - Double VLAN processing: insertion of up to two VLAN tags in transmit path, tag filtering in receive path - IEEE 1588-2008/PTPv2 support - Supports network statistics with RMON/MIB counters (RFC2819/RFC2665) Hardware offload processing - Preamble and start-of-frame data (SFD) insertion or deletion - Integrity Checksum offload engine for IP header and TCP/UDP/ICMP payload: transmit checksum calculation and insertion, receive checksum calculation and comparison - Automatic ARP request response with the device's MAC address - TCP Segmentation: Automatic split of large transmit TCP packet into multiple small packets Low-power mode - Energy efficient Ethernet (Standard IEEE 802.3az-2010) - Remote wakeup packet and AMD Magic PacketTM detection DS12500 Rev 1 53/245 54 Functional overview 3.47 STM32MP151A High-definition multimedia interface (HDMI) - Consumer electronics control (CEC) The device embeds a HDMI-CEC controller that provides hardware support for the consumer electronics control (CEC) protocol (supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC controller to wake up the STM32MP151A from Stop mode on data reception. 3.48 Debug infrastructure The devices offer a comprehensive set of debug and trace features to support software development and system integration. * Breakpoint debugging * Code execution tracing * Software instrumentation * JTAG debug port * Serial-wire debug port * Trigger input and output * Serial-wire trace port * Trace port * Arm(R) CoreSightTM debug and trace components The debug can be controlled via a JTAG/serial-wire debug access port, using industry standard debugging tools. A trace port allows data to be captured for logging and analysis. 54/245 DS12500 Rev 1 STM32MP151A 4 Pinouts, pin description and alternate functions Pinouts, pin description and alternate functions Figure 5. STM32MP151AADxx TFBGA257 pinout 1 2 3 4 A VSS PD1 PB7 PC6 B PG15 PE6 PD7 PA15 C PE12 PE0 PD4 PD5 D PG12 PE11 PE15 E PD8 NRST PE13 PC15OSC32_ OUT VSS PC14OSC32_ IN PC13 F G H VSS BOOT2 J PH0OSC_IN BOOT0 PH1OSC_ OUT NRST_ CORE K PWR_LP PDR_ON _CORE BOOT1 L PA14 PA13 PDR_ON M PWR_ON 6 7 8 VSS PD3 PG6 PB4 PE5 PD0 PA9 PB3 9 10 PC8 PE4 PA8 PC9 PC10 PB15 PB9 PC7 11 12 13 DNU DNU DNU DNU DNU PC11 DNU VDD_ Unused 14 15 16 17 18 19 JTDOTRACES WO JTCKSWCLK DDR_ DQ0 DDR_ DQ1 VSS NJTRST JTDI DDR_ DQ3 DDR_ DQ7 DDR_ DQS0N DDR_ DQS0P VSS JTMSSWDIO DDR_ RESETN DDR_ DQM0 DDR_ DQ2 DDR_ DQ6 VSS DDR_ DQ4 DDR_ DQ5 DDR_A13 DDR_A9 DDR_A2 VSS DDR_A3 VSS DDR_A0 DDR_ BA0 DDR_ BA2 DDR_ ODT DDR_ CSN DDR_ WEN DDR_ CASN VSS DDR_ CLKN VSS DDR_ CLKP DDR_A15 DDR_A10 DDR_A12 DDR_A1 VSS DDR_A14 DDR_A11 DDR_ CKE DDR_ BA1 DDR_A4 DDR_ DQ8 VSS DDR_A8 DDR_ DQ13 DDR_ DQ10 1 2 3 4 5 6 7 8 9 1A PE1 PD10 PE3 PB14 PD2 VSS VDD1V2_ Unused DDR_ZQ DDR_A7 1B PD6 PE14 VDD CORE PC12 VDD CORE VDDA 1V8_ Unused VDD1V2_ Unused VSS VDDQ_ DDR 1C PD9 PD15 VSS VDD CORE VSS VDD CORE VSS DDR_ DTO1 DDR_A5 VDD CORE VSS VDD VSS VDDA VDDA VSSA VSS 1D VBAT 1E PD14 1F 1G VSS VDD CORE VSS VDD CORE DDR_ DTO0 VDDQ_ DDR VDD CORE VSS VDD CORE VSS VDD CORE DDR_ RASN VDD VSS VDD CORE VSS VDD CORE DDR_ ATO VDDQ_ DDR VDD VDD VSS VDD CORE VSS VDD CORE DDR_A6 VREF+ N VSS PA3 PA0 P PE2 PC2 PC3 PG14 PG13 R 5 1H PA5 VSS VSS VSS VDDA 1V8_ REG VSS VDD 3V3_ USB VSS VDDQ_ DDR 1J PA4 PB13 VDD PE9 VSS VDDA 1V1_ REG PF10 USB_ RREF VSS T PA1 PC1 PA2 U PB1 PB0 PB11 PC0 PB10 PG11 PG10 PD11 VSS PF6 BYPASS _REG1V8 PE8 PD13 PD12 PA11 PA10 DDR_ DQ14 DDR_ DQS1N DDR_ DQ9 V PC5 PC4 PB12 PB8 PB5 PG8 PE7 PF8 PF9 USB_ DP2 PG7 PE10 PB2 USB_ DP1 PA12 OTG_ VBUS DDR_ DQ15 DDR_ DQM1 DDR_ DQS1P W VSS PA7 PA6 PF11 VSS PF7 PG9 USB_ DM2 PB6 VSS USB_ DM1 DDR_ VREF DDR_ DQ12 DDR_ DQ11 VSS MSv47441V2 The above figure shows the package top view. DS12500 Rev 1 55/245 119 Pinouts, pin description and alternate functions STM32MP151A Figure 6. STM32MP151AABxx LFBGA354 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 DNU 14 15 16 17 18 19 DNU DNU VDD1V2_ Unused DDR_ DQ0 DDR_ DQ1 VSS A VSS PG15 PD0 PD1 PE3 PG6 PB3 PB15 PC7 PC9 PC11 VDD_ Unused B PE1 VSS PE6 PD7 PB7 VSS PE5 PA8 PB4 PD2 PE4 VDDA 1V8_ Unused DNU DNU DNU VDD1V2_ Unused DDR_ DQ3 DDR_ DQ7 DDR_ DQS0N C PE11 PE13 VSS PE0 PD10 PD3 PA15 PA9 PB14 PC12 PC8 VSS VSS VSS VSS VSS VSS DDR_ DQM0 DDR_ DQS0P D VSS PE12 PE14 VSS VSS PD4 PD5 VSS PB9 PC6 PC10 NJTRST JTDI JTDOTRACE SWO JTMSSWDIO JTCKSWCLK DDR_ DQ5 DDR_ DQ2 DDR_ DQ6 E PE15 VSS PD6 VSS VSS VSS VDD CORE VSS VDD CORE VSS VDD CORE VSS VDD CORE VSS VDDQ_ DDR VSS DDR_A7 DDR_ DQ4 F PG12 PD8 PD14 VDD CORE VSS VDD CORE VSS VDD CORE VSS VDD CORE VSS VDD CORE VSS_ PLL2 VDDQ_ DDR VSS DDR_A13 DDR_ZQ DDR_A3 G PD15 VSS PD9 VSS VDD CORE VSS VDD CORE VSS VDD CORE VSS VDD CORE VSS VDD_ PLL2 VSS VDDQ_ DDR DDR_A9 DDR_A2 DDR_ BA0 H PC14OSC32_ IN PC15OSC32_ OUT VBAT VDD CORE VSS VDD CORE VSS VDD CORE VSS VDD CORE VSS VDD CORE VSS VDDQ_ DDR VSS DDR_A5 DDR_A0 DDR_ ODT J NRST NRST_ CORE VSS VSS_PLL VDD_PLL VSS VDD CORE VSS VDD CORE VSS VDD CORE VSS VDD CORE VSS VDDQ_ DDR DDR_ WEN DDR_ CSN DDR_ DTO1 K BOOT0 VSS PC13 BOOT1 VSS VDD VSS VDD CORE VSS VDD CORE VSS VDD CORE VSS VDDQ_ DDR VSS DDR_ CASN DDR_ DTO0 DDR_ CLKN L PWR_ON BOOT2 VDD_ ANA VSS_ ANA VDD VSS VDD VSS VDD CORE VSS VDD CORE VSS VDD CORE VSS VDDQ_ DDR DDR_A12 DDR_ RASN DDR_ CLKP M PH0OSC_IN PH1OSC_ OUT VREF- VDDA VSS VDD VSS VDD VSS VDD CORE VSS VDD CORE VSS VDDQ_ DDR VSS DDR_A1 DDR_A11 DDR_A10 N PDR_ON _CORE PDR_ON VREF+ VSSA VDD VSS VDD VSS VDD VSS VDD CORE VSS VDD CORE VSS VDDQ_ DDR DDR_ BA1 DDR_A14 DDR_ ATO P PWR_LP PA13 PA3 PA5 VSSA VDD VSS VDD VSS VDD VSS VDD CORE VSS VDDQ_ DDR VSS DDR_A4 DDR_ DQ8 DDR_ CKE R PA14 VSS PA0 PA4 VSSA VSS VDD VSS VDD VSS VDD VSS VDD CORE VSS VDDQ_ DDR VSS DDR_A8 DDR_ DQ10 T PE2 PC2 PC3 VSS PA6 PA7 PC0 PB5 PB13 PE7 PE8 PB6 PB2 PG9 BYPASS _REG1V8 PA10 DDR_ DQ9 DDR_ DQ13 DDR_ DQS1N U PG14 PG13 VSS PA1 PF11 VSS PG8 VSS PF10 PF8 PD12 PD13 VSS_ USBHS VSS_ USBHS OTG_ VBUS PA12 VSS DDR_ DQM1 DDR_ DQS1P V PB11 PC1 PB1 PC5 PB12 PG11 PG10 PD11 PF6 PE10 VDDA 1V8_ REG VSS_ USBHS USB_ DM2 USB_ DP1 VSS_ USBHS USB_ RREF PA11 DDR_ DQ14 DDR_ DQ11 W VSS PA2 PB0 PC4 PB10 PB8 PE9 PF7 PF9 PG7 VDDA 1V1_ REG VDD3V3_ USBHS USB_ DP2 USB_ DM1 VDD3V3_ USBFS DDR_ VREF DDR_ DQ15 DDR_ DQ12 VSS DDR_ RESETN DDR_ BA2 DDR_A15 DDR_A6 MSv47442V2 The above figure shows the package top view. 56/245 DS12500 Rev 1 STM32MP151A Pinouts, pin description and alternate functions Figure 7. STM32MP151AACxx TFBGA361 pinout 1 2 3 4 5 A VSS PH5 PE13 PE11 PF1 B PH15 PH12 PH4 PE12 PD10 C PI0 PH10 PH14 PH11 D PH13 PD6 PE15 VSS E PI3 PI2 PI1 PI4 PI7 PI5 PI6 F G PZ1 PZ4 PZ0 PZ3 H PZ6 PZ5 VSS PI9 PD15 PZ7 PZ2 J K L PD9 PC15OSC32 _OUT M N BOOT0 P PH0OSC_IN R PC13 PD8 7 8 PD5 PA9 PD4 PG15 PD0 PH9 PE14 VSS PH8 PE0 PF5 1 1A 9 10 11 PG6 PB3 PD1 PB9 PC7 PE1 PE3 PE6 PF0 PF4 PD7 2 12 13 14 PA8 PF2 PB15 PB4 PC6 PE5 VSS PB14 PB7 PD2 PC12 15 16 17 18 20 21 22 23 JTDOTRACE SWO 19 JTDI DDR_ DQ20 DDR_ DQ23 VSS DNU DNU DNU DNU DNU VDD_ Unused NJ TRST JTCKSWCLK DDR_ DQ19 DDR_ DQ16 DDR_ DQS2N VDDA 1V8_ Unused DNU VSS VDD 1V2_ Unused VDD 1V2_ Unused PA15 JTMSSWDIO VSS DDR_ DQS2P DDR_ DQM2 PD3 PC10 PC11 PC9 PC8 PE4 DDR_ RESET N DDR_ DQ22 DDR_ DQ17 DDR_ DQ18 DDR_ A7 DDR_ DQ3 DDR_ DQ0 DDR_ DQ21 DDR_ A13 VSS DDR_ DQ1 DDR_ A9 DDR_ DQ7 DDR_ DQS0P DDR_ DQS0N DDR_ A5 DDR_ DQ2 DDR_ DQ6 DDR_ DQM0 DDR_ A2 DDR_ DQ4 DDR_ DQ5 DDR_ DTO0 VSS DDR_ A3 DDR_ ZQ DDR_ A0 DDR_ DTO1 DDR_ ODT DDR_ BA0 DDR_ WEN DDR_ BA2 DDR_ CSN DDR_ CASN DDR_ RASN DDR_ CLKP DDR_ CLKN DDR_ A15 VSS DDR_ A1 DDR_ A12 DDR_ A11 DDR_ A14 DDR_ A10 DDR_ CKE DDR_ DQ8 DDR_ DQ10 DDR_ DQ13 DDR_ BA1 DDR_ DQ9 DDR_ DQS1P DDR_ DQS1N 3 4 5 6 7 8 VDD CORE VSS VDD CORE VSS VDD CORE VSS VDDQ_ DDR 9 1B VDD CORE VSS VDD CORE VSS VDD CORE VSS VDDQ_ DDR VSS VDDQ_ DDR 1C VSS VDD CORE VSS VDD CORE VSS VDD CORE VSS VDDQ_ DDR VSS 1D VDD CORE VSS VDD CORE VSS VDD CORE VSS VDD CORE VSS VDDQ_ DDR 1E VSS VDD CORE VSS VDD CORE VSS VDD CORE VSS VDDQ_ DDR VSS 1F VBAT VSS VDD VSS VDD CORE VSS VDD CORE VSS VDDQ_ DDR 1G VSS_ ANA VDD_ ANA VSS VDD VSS VDD CORE VSS VDDQ_ DDR VSS VDDA VSSA VDD VSS VDD VSS VDD CORE VSS VDDQ_ DDR VDD VSS VDD VSS VDD VSS VDDQ_ DDR PG12 PC14OSC32 _IN PD14 PI8 BOOT2 NRST NRST_ CORE PA13 PWR_ LP BOOT1 VSS PI11 PH1OSC_ OUT 6 PWR_ ON PDR_ ON VREF+ T PI10 PA14 PDR_ ON_ CORE PG3 U PF3 PA3 ANA0 ANA1 PG2 PA5 PA4 DDR_ A4 VSS DDR_ DQM1 DDR_ A6 DDR_ DQ11 DDR_ DQ14 DDR_ DQ12 V 1H 1J W PG1 PC3 VSS PH7 Y PE2 PC2 PB10 PF15 PF13 PG5 PG11 PB5 PF12 PF11 PH6 PF10 PG9 PB6 PE10 PB2 PA10 PD12 DDR_ ATO DDR_ A8 DDR_ DQ15 DDR_ DQ25 DDR_ DQ24 AA PG14 PG13 PH3 PA1 VSS PC1 PB1 VSS PE9 PB13 PE7 VSS PF6 PF9 VDD 3V3_ USBHS VSS_ USBHS VDD 3V3_ USBFS PA11 PD13 DDR_ DQM3 VSS DDR_ DQ31 DDR_ DQ30 AB PB11 PG4 PA0 PH2 PC0 PB0 PC5 PA7 PG8 PB8 PG10 PF7 BYPAS S_REG 1V8 VDDA 1V8_ REG VDDA 1V1_ REG USB_ DM2 USB_ DM1 USB_ RREF PA12 DDR_ DQ27 DDR_ DQ26 DDR_ DQS3P DDR_ DQS3N AC VSS PG0 PA2 PF14 PB12 PC4 PA6 PD11 PF8 PE8 PG7 USB_ DP2 USB_ DP1 OTG_ VBUS DDR_ VREF DDR_ DQ29 DDR_ DQ28 VSS MSv47443V2 The above figure shows the package top view. DS12500 Rev 1 57/245 119 Pinouts, pin description and alternate functions STM32MP151A Figure 8. STM32MP151AAA LFBGA448 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DNU 16 17 18 19 20 21 22 DNU DNU VDD 1V2_ Unused VSS DDR_ DQ20 DDR_ DQ23 VSS A VSS PH5 PH4 PE13 PK6 PK4 PJ13 PD10 PD5 PE3 PA9 PB3 PB14 VDD_ Unused B PH10 VSS PH11 PE14 PK7 PK3 PJ14 PJ12 PF1 PD1 PD3 PB15 PA8 VDDA 1V8_ Unused DNU DNU DNU VDD 1V2_ Unused VSS DDR_ DQ19 DDR_ DQ16 DDR_ DQS2N C PH15 PH14 VSS PE15 PE0 PK5 PJ15 VSS PD4 PD0 VSS PE5 PB4 VSS VSS VSS VSS VSS VSS VSS DDR_ DQS2P DDR_ DQM2 D PI0 PI14 PH13 VSS PE11 PH8 PE1 PK0 PF5 PG15 PG6 PD2 PC7 PC9 PC11 JTDI JTCKSWCLK VDD_ PLL2 VSS_ PLL2 DDR_ DQ22 DDR_ DQ17 DDR_ DQ18 E PI2 PI1 PI3 PE12 VSS PH9 PK1 PK2 PE6 PF0 PA15 PC12 PC6 PC8 NJ TRST JTDOTRACE SWO JTMSSWDIO VDDQ_ DDR VSS DDR_ DQ3 DDR_ DQ0 DDR_ DQ21 F PI7 PI5 PI15 PZ3 PH12 VSS VSS VSS PF4 PD7 PB7 PB9 PF2 PC10 PE4 VSS VDDQ_ DDR DDR_ A7 DDR_ RESET N VSS DDR_ DQ1 G PZ4 PZ0 PZ6 VSS PI6 VSS VDDQ_ DDR VSS DDR_ A13 DDR_ DQ7 DDR_ DQM0 DDR_ DQS0N DDR_ DQS0P H PI13 PI12 PZ7 PZ5 PZ1 PJ8 VDDQ_ DDR DDR_ A9 DDR_ A5 DDR_ DQ5 DDR_ DQ2 DDR_ DQ6 J PJ3 PJ0 PJ10 PG12 PI9 PI4 VSS DDR_ A2 DDR_ A3 VSS DDR_ DQ4 K PJ5 PJ4 VSS PJ2 PZ2 PJ11 VDDQ_ DDR DDR_ BA2 DDR_ A0 DDR_ BA0 DDR_ DTO1 DDR_ ZQ L PD15 PJ9 PD6 PJ7 PJ6 PJ1 VSS DDR_ CSN VSS VSS DDR_ ODT DDR_ DTO0 M PD8 PD9 PD14 VBAT VSS_ PLL VDD_ PLL VDDQ_ DDR DDR_ A1 DDR_ A15 DDR_ RASN DDR_ WEN DDR_ CASN N PI8 PC13 BOOT0 BOOT1 VDD_ ANA VREF- VSS DDR_ A10 DDR_ A12 DDR_ CLKP DDR_ CLKN DDR_ DQ8 P PC14OSC32 _IN PC15OSC32 _OUT VSS BOOT2 VSS_ ANA VREF+ VDDQ_ DDR DDR_ A14 DDR_ A11 VSS DDR_ DQ10 R NRST_ CORE NRST PA14 ANA0 VDDA VSSA VSS DDR_ BA1 DDR_ CKE DDR_ DQ13 DDR_ DQ9 DDR_ DQS1N T PH0OSC_IN PH1OSC_ OUT PI11 PA3 ANA1 VSSA VSS VDDQ_ DDR DDR_ A4 VSS DDR_ DQ11 DDR_ DQM1 DDR_ DQS1P U PWR_ LP PDR_ ON_ CORE PC3 PG3 PA5 VSSA VSS PG5 VDD PC0 PG11 VDD VSS VDD VSS VDDQ_ DDR VSS DDR_ A8 DDR_ A6 VSS DDR_ DQ14 V PWR_ ON PDR_ ON PF3 PA1 VSS PA4 PF14 PF12 PB10 PB13 PH6 PF10 PB2 PD13 OTG_ VBUS VSS VDDQ_ DDR VSS VSS DDR_ DQ12 DDR_ DQ15 DDR_ DQ24 W PI10 PH7 PA13 PG2 PG0 PF15 PF13 PF11 PA6 PE7 PE9 PD12 PB6 PE10 PG9 PA12 VSS VDDQ_ DDR VSS DDR_ DQ25 DDR_ DQ31 DDR_ DQ30 Y PC2 PE2 VSS PG1 PB11 PH3 VSS PG8 PA7 VSS PG7 PE8 VSS_ USBHS VSS_ USBHS VSS_ USBHS PA11 PA10 VSS VDDQ_ DDR VSS DDR_ DQS3P DDR_ DQS3N AA PG13 PG14 PA0 VSS PB1 PC5 PB12 PB5 PG10 PF7 PF6 BYPAS S_REG 1V8 VSS_ USBHS USB_ DM2 USB_ DP1 VSS_ USBHS USB_ RREF VSS DDR_ ATO DDR_ DQ29 DDR_ DQ28 DDR_ DQM3 AB VSS PA2 PC1 PG4 PB0 PC4 PH2 PB8 PD11 PF8 PF9 VDDA1 V8_ REG VDD 3V3_ USBHS USB_ DP2 USB_ DM1 VDD 3V3_ USBFS VDDA 1V1_ REG VSS DDR_ VREF DDR_ DQ27 DDR_ DQ26 VSS VSS VSS VDD CORE VSS VDD CORE VSS VDD CORE VSS VDD VSS VSS VDD CORE VSS VDD CORE VDD CORE VSS VDD CORE VSS VDD CORE VSS VDD CORE VDD CORE VSS VDD CORE VSS VDD CORE VSS VSS VDD CORE VSS VDD CORE VSS VDD CORE VDD VSS VDD CORE VSS VDD CORE VSS VSS VDD VSS VDD CORE VSS VDD CORE VDD VSS VDD VSS VDD CORE VSS VSS VDD VSS VDD CORE VDDQ_ DDR VDD CORE VDDQ_ DDR VDD CORE VDD CORE VDD VSS VDDQ_ DDR VDDQ_ DDR VDD CORE VDD MSv47444V2 The above figure shows the package top view. 58/245 DS12500 Rev 1 STM32MP151A Pinouts, pin description and alternate functions Table 6. Legend/abbreviations used in the pinout table Name Pin name Pin type Abbreviation Definition Unless otherwise specified, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin O Output only pin I/O Input / output pin A FT(U/D/PD) TT DDR A RST Analog or special level pin 5 V tolerant I/O (with fixed pull-up / pull-down / programmable pull-down) 3.6 V tolerant I/O directly connected to DAC 1.5 V, 1.35 V or 1.2 V I/O for DDR3, DDR3L, LPDDR2/LPDDR3 interface Analog signal Reset pin with weak pull-up resistor Option for TT or FT I/Os I/O structure _f(1) I2C FM+ option _a(2) Analog option (supplied by VDDA for the analog part of the I/O) (3) USB option (supplied by VDD3V3_USBxx for the USB part of the I/O) (4) _h High-speed output for 1.8V typ. VDD (for SPI, SDMMC, QUADSPI, TRACE) _e(5) Very-high-speed option for 1.8V typ. VDD (for ETH, SPI, SDMMC, QUADSPI, TRACE) _u Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers 1. The related I/O structures in Table 7 are: FT_f, FT_fae, FT_fh, FT_fha, FT_uf 2. The related I/O structures in Table 7 are: FT_a, TT_a, FT_ae, FT_fae, FT_fha, FT_ha, TT_ha 3. The related I/O structures in Table 7 are: FT_u, FT_uf 4. The related I/O structures in Table 7 are: FT_h, FT_fh, FT_fha, FT_ha, TT_ha 5. The related I/O structures in Table 7 are: FT_e, FT_ae, FT_fae DS12500 Rev 1 59/245 119 Pinouts, pin description and alternate functions STM32MP151A Table 7. STM32MP151A pin and ball definitions LFBGA354 TFBGA361 LFBGA448 Pin name (function after reset) Pin type I/O structure Notes Pin functions TFBGA257 Pin Number - - A2 A2 PH5 I/O FT_f - - - C2 B1 PH10 I/O FT - - - B2 F5 PH12 I/O FT_f - - - D1 D3 PH13 I/O FT - 1E2 K6 1F3 M9 VDD S - - - - A1 A1 A1 A1 VSS S - - - - - - C3 C2 PH14 I/O FT - - - B1 C1 PH15 I/O FT - - - - H6 PJ8 I/O FT_h - - - - D2 PI14 I/O FT_h - - - - F3 PI15 I/O FT - - - C1 D1 PI0 I/O FT - - - E3 E2 PI1 I/O FT_h - - - E2 E1 PI2 I/O FT_h - 1B3 E7 1A2 H9 VDDCORE S - - - - E1 E3 PI3 I/O FT_h - - - E4 J6 PI4 I/O FT - - - F3 F2 PI5 I/O FT - 60/245 Alternate functions I2C2_SDA, SPI5_NSS, SAI4_SD_B, EVENTOUT TIM5_CH1, I2C4_SMBA, I2C1_SMBA, DCMI_D1, LCD_R4, EVENTOUT HDP2, TIM5_CH3, I2C4_SDA, I2C1_SDA, DCMI_D3, LCD_R6, EVENTOUT TIM8_CH1N, UART4_TX, LCD_G2, EVENTOUT TIM8_CH2N, UART4_RX, DCMI_D4, LCD_G3, EVENTOUT TIM8_CH3N, DCMI_D11, LCD_G4, EVENTOUT TRACED14, TIM1_CH3N, TIM8_CH1, UART8_TX, LCD_G1, EVENTOUT TRACECLK, LCD_CLK, EVENTOUT LCD_G2, LCD_R0, EVENTOUT TIM5_CH4, SPI2_NSS/I2S2_WS, DCMI_D13, LCD_G5, EVENTOUT TIM8_BKIN2, SPI2_SCK/I2S2_CK, DCMI_D8, LCD_G6, EVENTOUT TIM8_CH4, SPI2_MISO/I2S2_SDI, DCMI_D9, LCD_G7, EVENTOUT TIM8_ETR, SPI2_MOSI/I2S2_SDO, DCMI_D10, EVENTOUT TIM8_BKIN, SAI2_MCLK_A, DCMI_D5, LCD_B4, EVENTOUT TIM8_CH1, SAI2_SCK_A, DCMI_VSYNC, LCD_B5, EVENTOUT DS12500 Rev 1 Additional functions - - - - - - - STM32MP151A Pinouts, pin description and alternate functions Table 7. STM32MP151A pin and ball definitions (continued) LFBGA354 TFBGA361 LFBGA448 Pin name (function after reset) Pin type I/O structure Notes Pin functions TFBGA257 Pin Number - - F4 G5 PI6 I/O FT - - - F2 F1 PI7 I/O FT - - A19 A23 A19 VSS S - - - - G1 H5 PZ1 I/O FT_fh - - - G4 F4 PZ3 I/O FT_f - - - H4 J5 PI9 I/O FT - - - G3 G2 PZ0 I/O FT_fh - - - J4 K5 PZ2 I/O FT_fh - - - G2 G1 PZ4 I/O FT_f - G1 B2 - A22 VSS S - - D1 F1 K4 J4 PG12 I/O FT_h - - - H2 H4 PZ5 I/O FT_f - - E9 - - VDDCORE S - - Alternate functions TIM8_CH2, SAI2_SD_A, DCMI_D6, LCD_B6, EVENTOUT TIM8_CH3, SAI2_FS_A, DCMI_D7, LCD_B7, EVENTOUT I2C6_SDA, I2C2_SDA, I2C5_SDA, SPI1_MISO/I2S1_SDI, I2C4_SDA, USART1_RX, SPI6_MISO, EVENTOUT I2C6_SDA, I2C2_SDA, I2C5_SDA, SPI1_NSS/I2S1_WS, I2C4_SDA, USART1_CTS/USART1_NSS, SPI6_NSS, EVENTOUT HDP1, UART4_RX, LCD_VSYNC, EVENTOUT I2C6_SCL, I2C2_SCL, SPI1_SCK/I2S1_CK, USART1_CK, SPI6_SCK, EVENTOUT I2C6_SCL, I2C2_SCL, I2C5_SMBA, SPI1_MOSI/I2S1_SDO, I2C4_SMBA, USART1_TX, SPI6_MOSI, EVENTOUT I2C6_SCL, I2C2_SCL, I2C5_SCL, I2C4_SCL, EVENTOUT LPTIM1_IN1, SPI6_MISO, SAI4_CK2, USART6_RTS/USART6_DE, SPDIFRX_IN1, LCD_B4, SAI4_SCK_A, ETH1_PHY_INTN, FMC_NE4, LCD_B1, EVENTOUT I2C6_SDA, I2C2_SDA, I2C5_SDA, I2C4_SDA, USART1_RTS/USART1_DE, EVENTOUT DS12500 Rev 1 - Additional functions - - - - - - - - - - 61/245 119 Pinouts, pin description and alternate functions STM32MP151A Pin functions Notes Pin name (function after reset) Pin type LFBGA448 TFBGA361 LFBGA354 TFBGA257 Pin Number I/O structure Table 7. STM32MP151A pin and ball definitions (continued) Alternate functions I2C6_SCL, I2C2_SCL, USART1_CK, I2S1_MCK, I2C4_SMBA, USART1_RX, EVENTOUT I2C6_SDA, I2C2_SDA, USART1_TX, EVENTOUT TRACED0, HDP0, LCD_HSYNC, EVENTOUT Additional functions - - H1 G3 PZ6 I/O FT_f - - - J3 H3 PZ7 I/O FT_f - - - - H2 PI12 I/O FT_h - - B6 C7 B2 VSS S - - - - - - - H1 PI13 I/O FT_h - TRACED1, HDP1, LCD_VSYNC, EVENTOUT - - - 1A4 H11 VDDCORE S - - - - - - - J3 PJ10 I/O FT_h - - - - K6 PJ11 I/O FT_h - - - - J2 PJ0 I/O FT_h - - - - L6 PJ1 I/O FT_h - - - - K4 PJ2 I/O FT_h - - L5 - - VDD S - - - - - - - J1 PJ3 I/O FT_h - TRACED11, LCD_R4, EVENTOUT - N1 C3 - B19 VSS S - - - - - - - K2 PJ4 I/O FT_h - TRACED12, LCD_R5, EVENTOUT - - - VDDCORE S - - - - 1D3 E11 - - - K1 PJ5 I/O FT_h - - - - L5 PJ6 I/O FT_h - - - - L4 PJ7 I/O FT_h - - C17 C12 C3 VSS S - - 62/245 TIM1_CH2N, TIM8_CH2, SPI5_MOSI, LCD_G3, EVENTOUT TIM1_CH2, TIM8_CH2N, SPI5_MISO, LCD_G4, EVENTOUT TRACED8, LCD_R7, LCD_R1, EVENTOUT TRACED9, LCD_R2, EVENTOUT TRACED10, LCD_R3, EVENTOUT TRACED2, HDP2, LCD_R6, EVENTOUT TRACED3, HDP3, TIM8_CH2, LCD_R7, EVENTOUT TRACED13, TIM8_CH2N, LCD_G0, EVENTOUT DS12500 Rev 1 - - - - - - STM32MP151A Pinouts, pin description and alternate functions Pin functions Notes Pin name (function after reset) Pin type LFBGA448 TFBGA361 LFBGA354 TFBGA257 Pin Number I/O structure Table 7. STM32MP151A pin and ball definitions (continued) Alternate functions Additional functions - 1B1 E3 D2 L3 PD6 I/O FT_ha - TIM16_CH1N, SAI1_D1, DFSDM1_CKIN4, DFSDM1_DATIN1, SPI3_MOSI/I2S3_SDO, SAI1_SD_A, USART2_RX, FMC_NWAIT, DCMI_D10, LCD_B2, EVENTOUT - E13 - H13 VDDCORE S - - - - - - - L2 PJ9 I/O FT_h - TRACED15, TIM1_CH3, TIM8_CH1N, UART8_RX, LCD_G2, EVENTOUT - - J5 - M6 VDD_PLL S - - - - - J4 - M5 VSS_PLL S - - - - TIM4_CH3, SAI3_MCLK_B, UART8_CTS, FMC_D0/FMC_DA0, EVENTOUT TIM4_CH4, SAI3_MCLK_A, UART8_CTS, FMC_D1/FMC_DA1, LCD_R1, EVENTOUT DFSDM1_CKIN3, SAI3_SCK_B, USART3_TX, SPDIFRX_IN1, FMC_D13/FMC_DA13, LCD_B7, EVENTOUT DFSDM1_DATIN3, SAI3_SD_B, USART3_RX, FMC_D14/FMC_DA14, DCMI_HSYNC, LCD_B0, EVENTOUT 1E1 F3 L3 M3 PD14 I/O FT_a - 1C2 G1 J2 L1 PD15 I/O FT_a - E1 F2 K3 M1 PD8 I/O FT_a - 1C1 G3 K1 M2 PD9 I/O FT_a - - - - N8 VDD S - - - - W1 D1 C21 C8 VSS S - - - - - - 1A6 - VDDCORE S - - - - 1D1 H3 1F1 M4 VBAT S - - - - - D4 - C11 VSS S - - - - EVENTOUT RTC_OUT2/ RTC_LSCO, TAMP_IN2/ TAMP_OUT3, WKUP4 - - L4 N1 PI8 I/O FT - DS12500 Rev 1 - - - - 63/245 119 Pinouts, pin description and alternate functions STM32MP151A Pin functions Notes Pin name (function after reset) Pin type LFBGA448 TFBGA361 LFBGA354 TFBGA257 Pin Number I/O structure Table 7. STM32MP151A pin and ball definitions (continued) Alternate functions Additional functions G3 K3 K2 N2 PC13 I/O FT - EVENTOUT RTC_OUT1/ RTC_TS/ RTC_LSCO, TAMP_IN1/ TAMP_OUT2/ TAMP_OUT3, WKUP3 F3 D5 D4 C19 VSS S - - - - F2 H2 L1 P2 PC15OSC32_OUT I/O FT - EVENTOUT OSC32_OUT - F4 - H15 VDDCORE S - - - - 1C4 F6 1B1 - VDDCORE S - - - - G2 H1 L2 P1 PC14OSC32_IN I/O FT - EVENTOUT OSC32_IN E2 J1 M3 R2 NRST I/O RST - - - J3 J2 M4 R1 NRST_CORE I RST - - - H3 K1 N1 N3 BOOT0 I FTPD - - - K3 K4 N4 N4 BOOT1 I FTPD - - - H1 L2 M2 P4 BOOT2 I FTPD - - - H2 M1 P1 T1 PH0-OSC_IN I/O FT - EVENTOUT OSC_IN - - - J8 VDDCORE S - - - - I/O FT - EVENTOUT OSC_OUT J2 M2 P2 T2 PH1OSC_OUT - D8 - C20 VSS S - - - - M2 L1 R2 V1 PWR_ON O FT - - PWR_ONLP K1 P1 N3 U1 PWR_LP O FT - - - K2 N1 T3 U2 PDR_ON_ CORE I FT - - - L3 N2 R3 V2 PDR_ON I FT - - - - L3 1G2 N5 VDD_ANA S - - - - - L4 1G1 P5 VSS_ANA S - - - - L2 P2 N2 W3 PA13 I/O FT_a - L1 R1 T2 R3 PA14 I/O FT_a - - - P4 T3 PI11 I/O FT - 64/245 DBTRGO, DBTRGI, MCO1, UART4_TX, EVENTOUT DBTRGO, DBTRGI, MCO2, EVENTOUT MCO1, I2S_CKIN, LCD_G6, EVENTOUT DS12500 Rev 1 BOOTFAILN WKUP5 STM32MP151A Pinouts, pin description and alternate functions Pin functions Notes Pin name (function after reset) Pin type LFBGA448 TFBGA361 LFBGA354 TFBGA257 Pin Number I/O structure Table 7. STM32MP151A pin and ball definitions (continued) Alternate functions Additional functions - - - T1 W1 PI10 I/O FT - HDP0, USART3_CTS/USART3_NSS, ETH1_GMII_RX_ER/ ETH1_MII_RX_ER, LCD_HSYNC, EVENTOUT - L7 1G4 - VDD S - - - - W5 E2 F21 - VSS S - - - - - F8 - - VDDCORE S - - - - 1F1 M4 1H1 R5 VDDA S - - - - 1F2 - - - VDDA S - - - - M3 N3 R4 P6 VREF+ S - - - - 1G1 N4 1H2 R6 VSSA S - - - - - P5 - T6 VSSA S - - - - - R5 - U6 VSSA S - - - - - M3 - N6 VREF- S - - - - - - W4 W2 PH7 I/O FT_fh - - - U1 V3 PF3 I/O FT_e - P3 T3 W2 U3 PC3 I/O FT_ha - - - T4 U4 PG3 I/O FT_e - P1 T1 Y1 Y2 PE2 I/O - - - N10 VDD S FT_fae - - I2C3_SCL, SPI5_MISO, ETH1_GMII_RXD3/ ETH1_MII_RXD3/ ETH1_RGMII_RXD3, MDIOS_MDC, DCMI_D9, EVENTOUT ETH1_GMII_TX_ER/ ETH1_MII_TX_ER, FMC_A3, EVENTOUT TRACECLK, DFSDM1_DATIN1, SPI2_MOSI/I2S2_SDO, ETH1_GMII_TX_CLK/ ETH1_MII_TX_CLK, EVENTOUT TRACED3, TIM8_BKIN2, DFSDM1_CKIN1, ETH1_GMII_TXD7, FMC_A13, EVENTOUT TRACECLK, SAI1_CK1, I2C4_SCL, SPI4_SCK, SAI1_MCLK_A, QUADSPI_BK1_IO2, ETH1_GMII_TXD3/ ETH1_MII_TXD3/ ETH1_RGMII_TXD3, FMC_A23, EVENTOUT - DS12500 Rev 1 - - - ADC1_INP13, ADC1_INN12 - - - 65/245 119 Pinouts, pin description and alternate functions STM32MP151A Table 7. STM32MP151A pin and ball definitions (continued) LFBGA448 E4 H3 D4 VSS Notes TFBGA361 - I/O structure LFBGA354 Pin name (function after reset) Pin functions Pin type TFBGA257 Pin Number S - - N2 P3 U2 T4 PA3 I/O FT_a - P2 T2 Y2 Y1 PC2 I/O FT_ae - - - V2 W4 PG2 I/O FT_e - R2 U1 AA1 AA2 PG14 I/O FT_e - - - W1 Y4 PG1 I/O FT_e - R3 U2 AA2 AA1 PG13 I/O FT_e - - 66/245 - U3 R4 ANA0 A A Alternate functions Additional functions - - TIM2_CH4, TIM5_CH4, LPTIM5_OUT, TIM15_CH2, USART2_RX, LCD_B2, ETH1_GMII_COL/ ETH1_MII_COL, LCD_B5, EVENTOUT DFSDM1_CKIN1, SPI2_MISO/I2S2_SDI, DFSDM1_CKOUT, ETH1_GMII_TXD2/ ETH1_MII_TXD2/ ETH1_RGMII_TXD2, DCMI_PIXCLK, EVENTOUT TRACED2, MCO2, TIM8_BKIN, ETH1_GMII_TXD6, FMC_A12, EVENTOUT TRACED1, LPTIM1_ETR, SPI6_MOSI, SAI4_D1, USART6_TX, QUADSPI_BK2_IO3, SAI4_SD_A, ETH1_GMII_TXD1/ ETH1_MII_TXD1/ ETH1_RGMII_TXD1/ ETH1_RMII_TXD1, FMC_A25, LCD_B0, EVENTOUT TRACED1, ETH1_GMII_TXD5, FMC_A11, EVENTOUT TRACED0, LPTIM1_OUT, SAI1_CK2, SAI4_CK1, SPI6_SCK, SAI1_SCK_A, USART6_CTS/USART6_NSS, SAI4_MCLK_A, ETH1_GMII_TXD0/ ETH1_MII_TXD0/ ETH1_RGMII_TXD0/ ETH1_RMII_TXD0, FMC_A24, LCD_R0, EVENTOUT - DS12500 Rev 1 - ADC1_INP15, PVD_IN ADC1_INP12, ADC1_INN11 - - - - ADC1_INP0, ADC1_INN1, ADC2_INP0, ADC2_INN1 STM32MP151A Pinouts, pin description and alternate functions Pin functions Notes Pin name (function after reset) Pin type LFBGA448 TFBGA361 LFBGA354 TFBGA257 Pin Number I/O structure Table 7. STM32MP151A pin and ball definitions (continued) Alternate functions Additional functions ADC1_INP16, WKUP1 N3 R3 AB3 AA3 PA0 I/O FT_ha - TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, TIM15_BKIN, USART2_CTS/USART2_NSS, UART4_TX, SDMMC2_CMD, SAI2_SD_B, ETH1_GMII_CRS/ ETH1_MII_CRS, EVENTOUT - E5 - E5 VSS S - - - - - - U4 T5 ANA1 A A - - ADC1_INP1, ADC2_INP1 T1 U4 AA4 V4 PA1 I/O FT_ha - 1H1 P4 V3 U5 PA5 I/O TT_ha - 1J1 R4 V4 V6 PA4 I/O TT_a - - - AC2 W5 PG0 I/O FT_e - U3 V1 AB1 Y5 PB11 I/O FT_fae - ETH_CLK, TIM2_CH2, TIM5_CH2, LPTIM3_OUT, TIM15_CH1N, USART2_RTS/USART2_DE, UART4_RX, QUADSPI_BK1_IO3, SAI2_MCLK_B, ETH1_GMII_RX_CLK/ ETH1_MII_RX_CLK/ ETH1_RGMII_RX_CLK/ ETH1_RMII_REF_CLK, LCD_R2, EVENTOUT TIM2_CH1/TIM2_ETR, TIM8_CH1N, SAI4_CK1, SPI1_SCK/I2S1_CK, SPI6_SCK, SAI4_MCLK_A, LCD_R4, EVENTOUT HDP0, TIM5_ETR, SAI4_D2, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, SPI6_NSS, SAI4_FS_A, DCMI_HSYNC, LCD_VSYNC, EVENTOUT TRACED0, DFSDM1_DATIN0, ETH1_GMII_TXD4, FMC_A10, EVENTOUT TIM2_CH4, LPTIM2_ETR, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, ETH1_GMII_TX_EN/ ETH1_MII_TX_EN/ ETH1_RGMII_TX_CTL/ ETH1_RMII_TX_EN, LCD_G5, EVENTOUT DS12500 Rev 1 ADC1_INP17, ADC1_INN16 ADC1_INP19, ADC1_INN18, ADC2_INP19, ADC2_INN18, DAC_OUT2 ADC1_INP18, ADC2_INP18, DAC_OUT1 - - 67/245 119 Pinouts, pin description and alternate functions STM32MP151A - - AB2 AB4 PG4 I/O FT_e T3 W2 AC3 AB2 PA2 I/O FT_ha 1F3 M6 - - VDD S - Pin functions Notes Pin name (function after reset) Pin type LFBGA448 TFBGA361 LFBGA354 TFBGA257 Pin Number I/O structure Table 7. STM32MP151A pin and ball definitions (continued) Alternate functions TIM1_BKIN2, ETH1_GMII_GTX_CLK/ ETH1_RGMII_GTX_CLK, FMC_A14, EVENTOUT TIM2_CH3, TIM5_CH3, LPTIM4_OUT, TIM15_CH1, USART2_TX, SAI2_SCK_B, SDMMC2_D0DIR, ETH1_MDIO, MDIOS_MDIO, LCD_R1, EVENTOUT Additional functions - ADC1_INP14, WKUP2 - - ADC1_INP11, ADC1_INN10, ADC2_INP11, ADC2_INN10, TAMP_IN3, WKUP6 T2 V2 AA6 AB3 PC1 I/O FT_ha - TRACED0, SAI1_D1, DFSDM1_DATIN0, DFSDM1_CKIN4, SPI2_MOSI/I2S2_SDO, SAI1_SD_A, SDMMC2_CK, ETH1_MDC, MDIOS_MDC, EVENTOUT A6 - K21 E19 VSS S - - - - - - Y6 U8 PG5 I/O FT - TIM1_ETR, ETH1_GMII_CLK125/ ETH1_RGMII_CLK125, FMC_A15, EVENTOUT - F10 1B3 J10 VDDCORE S - - - - - AA3 Y6 PH3 I/O FT_h U2 W3 AB6 AB5 PB0 I/O FT_a - - Y4 W6 PF15 I/O FT_fh 68/245 DFSDM1_CKIN4, QUADSPI_BK2_IO1, SAI2_MCLK_B, ETH1_GMII_COL/ ETH1_MII_COL, LCD_R1, EVENTOUT TIM1_CH2N, TIM3_CH3, TIM8_CH2N, DFSDM1_CKOUT, UART4_CTS, LCD_R3, ETH1_GMII_RXD2/ ETH1_MII_RXD2/ ETH1_RGMII_RXD2, MDIOS_MDIO, LCD_G1, EVENTOUT TRACED7, I2C4_SDA, - I2C1_SDA, ETH1_GMII_RXD7, FMC_A9, EVENTOUT DS12500 Rev 1 - ADC1_INP9, ADC1_INN5, ADC2_INP9, ADC2_INN5 - STM32MP151A Pinouts, pin description and alternate functions U1 V3 AA7 AA5 PB1 I/O FT_a - E6 - F6 VSS S - Pin functions Notes Pin name (function after reset) Pin type LFBGA448 TFBGA361 LFBGA354 TFBGA257 Pin Number I/O structure Table 7. STM32MP151A pin and ball definitions (continued) Alternate functions TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM1_DATIN1, LCD_R6, ETH1_GMII_RXD3/ ETH1_MII_RXD3/ ETH1_RGMII_RXD3, MDIOS_MDC, LCD_G0, EVENTOUT - - - AC4 V7 PF14 I/O FT_fha - - - Y5 W7 PF13 I/O FT_ha - - - AB4 AB7 PH2 I/O FT_h - TRACED6, DFSDM1_CKIN6, I2C4_SCL, I2C1_SCL, ETH1_GMII_RXD6, FMC_A8, EVENTOUT TRACED5, DFSDM1_DATIN6, I2C4_SMBA, I2C1_SMBA, DFSDM1_DATIN3, ETH1_GMII_RXD5, FMC_A7, EVENTOUT LPTIM1_IN2, QUADSPI_BK2_IO0, SAI2_SCK_B, ETH1_GMII_CRS/ ETH1_MII_CRS, LCD_R0, EVENTOUT SAI1_D3, DFSDM1_DATIN2, SAI4_D4, SAI1_D4, SPDIFRX_IN3, ETH1_GMII_RXD1/ ETH1_MII_RXD1/ ETH1_RGMII_RXD1/ ETH1_RMII_RXD1, SAI4_D3, EVENTOUT DFSDM1_CKIN2, I2S1_MCK, SPDIFRX_IN2, ETH1_GMII_RXD0/ ETH1_MII_RXD0/ ETH1_RGMII_RXD0/ ETH1_RMII_RXD0, EVENTOUT Additional functions ADC1_INP5, ADC2_INP5 ADC2_INP6, ADC2_INN2 ADC2_INP2 - ADC1_INP8, ADC1_INN4, ADC2_INP8, ADC2_INN4 V1 V4 AB7 AA6 PC5 I/O FT_a - V2 W4 AC7 AB6 PC4 I/O FT_a - - M8 - P9 VDD S - - - - 1D2 E8 P3 F7 VSS S - - - - 1J3 R7 1J2 U9 VDD S - - - - - - Y9 V8 PF12 I/O FT_ha - TRACED4, ETH1_GMII_RXD4, FMC_A6, EVENTOUT ADC1_INP6, ADC1_INN2 1E4 - - - VDDCORE S - - - - DS12500 Rev 1 ADC1_INP4, ADC2_INP4 69/245 119 Pinouts, pin description and alternate functions STM32MP151A Table 7. STM32MP151A pin and ball definitions (continued) LFBGA354 TFBGA361 LFBGA448 Pin name (function after reset) Pin type I/O structure Notes Pin functions TFBGA257 Pin Number W4 U5 Y10 W8 PF11 I/O FT_ha - SPI5_MOSI, SAI2_SD_B, DCMI_D12, LCD_G5, EVENTOUT ADC1_INP2 - E10 - F8 VSS S - - - - TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SAI4_D1, SPI1_MOSI/I2S1_SDO, SPI6_MOSI, TIM14_CH1, QUADSPI_CLK, ETH1_GMII_RX_DV/ ETH1_MII_RX_DV/ ETH1_RGMII_RX_CTL/ ETH1_RMII_CRS_DV, SAI4_SD_A, EVENTOUT ADC1_INP7, ADC1_INN3, ADC2_INP7, ADC2_INN3 Alternate functions Additional functions W2 T6 AB8 Y9 PA7 I/O FT_ha - - F12 - J12 VDDCORE S - - - - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SAI4_CK2, SPI1_MISO/I2S1_SDI, SPI6_MISO, TIM13_CH1, MDIOS_MDC, SAI4_SCK_A, DCMI_PIXCLK, LCD_G2, EVENTOUT ADC1_INP3, ADC2_INP3 W3 T5 AC8 W9 PA6 I/O FT_ha - - - 1H3 - VDD S - - - ADC1_INP10, ADC2_INP10 - U4 T7 1G2 E12 AB5 U10 PC0 I/O FT_ha - DFSDM1_CKIN0, LPTIM2_IN2, DFSDM1_DATIN4, SAI2_FS_B, QUADSPI_BK2_NCS, LCD_R5, EVENTOUT P21 F16 VSS S - - - U5 W5 Y3 V9 PB10 I/O - - 1B5 - VDDCORE S 70/245 TIM2_CH3, LPTIM2_IN1, I2C2_SCL, SPI2_SCK/I2S2_CK, DFSDM1_DATIN7, USART3_TX, FT_fha QUADSPI_BK1_NCS, ETH1_GMII_RX_ER/ ETH1_MII_RX_ER, LCD_G4, EVENTOUT - - DS12500 Rev 1 - - - STM32MP151A Pinouts, pin description and alternate functions Pin functions Notes Pin name (function after reset) Pin type LFBGA448 TFBGA361 LFBGA354 TFBGA257 Pin Number I/O structure Table 7. STM32MP151A pin and ball definitions (continued) Alternate functions Additional functions - - V3 V5 AC5 AA7 PB12 I/O FT_ae - TIM1_BKIN, I2C6_SMBA, I2C2_SMBA, SPI2_NSS/I2S2_WS, DFSDM1_DATIN1, USART3_CK, USART3_RX, ETH1_GMII_TXD0/ ETH1_MII_TXD0/ ETH1_RGMII_TXD0/ ETH1_RMII_TXD0, UART5_RX, EVENTOUT - G5 - J14 VDDCORE S - - - 1J2 T9 AA10 V10 PB13 I/O FT_e - E14 V21 F20 VSS S - TIM1_CH1N, DFSDM1_CKOUT, LPTIM2_OUT, SPI2_SCK/I2S2_CK, DFSDM1_CKIN1, USART3_CTS/USART3_NSS, ETH1_GMII_TXD1/ ETH1_MII_TXD1/ ETH1_RGMII_TXD1/ ETH1_RMII_TXD1, UART5_TX, EVENTOUT - - - ETH_CLK, TIM17_BKIN, TIM3_CH2, SAI4_D1, I2C1_SMBA, SPI1_MOSI/I2S1_SDO, I2C4_SMBA, SPI3_MOSI/I2S3_SDO, SPI6_MOSI, SAI4_SD_A, ETH1_PPS_OUT, UART5_RX, DCMI_D10, LCD_G7, EVENTOUT TRACED11, USART1_TX, UART4_TX, SPDIFRX_IN0, ETH1_GMII_TX_EN/ ETH1_MII_TX_EN/ ETH1_RGMII_TX_CTL/ ETH1_RMII_TX_EN, DCMI_D3, LCD_B3, EVENTOUT V5 T8 Y8 AA8 PB5 I/O FT_e - U6 V6 Y7 U11 PG11 I/O FT_e - 1B5 G7 1C2 - VDDCORE S - - - - - TIM12_CH1, I2C2_SMBA, SPI5_SCK, ETH1_GMII_RXD2/ ETH1_MII_RXD2/ ETH1_RGMII_RXD2, MDIOS_MDIO, DCMI_D8, EVENTOUT - - - Y11 V11 PH6 I/O FT_h DS12500 Rev 1 - - 71/245 119 Pinouts, pin description and alternate functions STM32MP151A Table 7. STM32MP151A pin and ball definitions (continued) G4 VSS Notes - I/O structure Pin name (function after reset) Pin functions Pin type LFBGA448 1H2 E16 TFBGA361 LFBGA354 TFBGA257 Pin Number S - - V4 W6 AB10 AB8 PB8 I/O - - - K9 VDDCORE S Additional functions - - HDP6, TIM16_CH1, TIM4_CH3, DFSDM1_CKIN7, I2C1_SCL, SDMMC1_CKIN, I2C4_SCL, SDMMC2_CKIN, UART4_RX, SDMMC2_D4, ETH1_GMII_TXD3/ ETH1_MII_TXD3/ ETH1_RGMII_TXD3, SDMMC1_D4, DCMI_D6, LCD_B6, EVENTOUT - - - - - - FT_fae - - Alternate functions V6 U7 AB9 Y8 PG8 I/O FT_e - TRACED15, TIM2_CH1/TIM2_ETR, ETH_CLK, TIM8_ETR, SPI6_NSS, SAI4_D2, USART6_RTS/USART6_DE, USART3_RTS/USART3_DE, SPDIFRX_IN2, SAI4_FS_A, ETH1_PPS_OUT, LCD_G7, EVENTOUT - N5 - P11 VDD S - - - U7 V7 AB11 AA9 PG10 I/O FT_h - F5 W3 - VSS S - TRACED10, UART8_CTS, LCD_G3, SAI2_SD_B, - QUADSPI_BK2_IO2, FMC_NE3, DCMI_D2, LCD_B2, EVENTOUT - - - - - 1J4 W7 AA9 W11 PE9 I/O FT_ha - TIM1_CH1, DFSDM1_CKOUT, UART7_RTS/UART7_DE, QUADSPI_BK2_IO2, FMC_D6/FMC_DA6, EVENTOUT - G9 - - VDDCORE S - - - - - - V7 T10 AA11 W10 PE7 I/O FT_h - TIM1_ETR, TIM3_ETR, DFSDM1_DATIN2, UART7_RX, QUADSPI_BK2_IO0, FMC_D4/FMC_DA4, EVENTOUT 1C3 F7 - G6 VSS S - - - 72/245 DS12500 Rev 1 STM32MP151A Pinouts, pin description and alternate functions U8 V8 1D5 G11 Pin functions Notes Pin name (function after reset) Pin type LFBGA448 TFBGA361 LFBGA354 TFBGA257 Pin Number I/O structure Table 7. STM32MP151A pin and ball definitions (continued) Alternate functions Additional functions - - AC10 AB9 PD11 I/O FT_h - LPTIM2_IN2, I2C4_SMBA, I2C1_SMBA, USART3_CTS/USART3_NSS, QUADSPI_BK1_IO0, SAI2_SD_A, FMC_CLE/FMC_A16, EVENTOUT 1C4 - VDDCORE S - - TIM17_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_TX, QUADSPI_BK1_IO2, EVENTOUT TRACED12, TIM16_CH1N, SPI5_MISO, SAI1_SCK_B, UART7_RTS/UART7_DE, TIM13_CH1, QUADSPI_BK1_IO0, EVENTOUT W7 W8 AB12 AA10 PF7 I/O FT_ha - V8 U10 AC11 AB10 PF8 I/O FT_ha - VDDCORE S - - - - TIM16_BKIN, SAI1_D3, SAI4_D4, SAI1_D4, QUADSPI_CLK, SAI4_D3, DCMI_D11, LCD_DE, EVENTOUT - - - - K11 - - 1J7 U9 Y12 V12 PF10 I/O FT_h - - F9 AA5 G8 VSS S - - - - U10 V9 - H4 U14 U11 - F11 V9 W9 - H6 AA13 AA11 - - PF6 I/O FT_ha - TIM16_CH1, SPI5_NSS, SAI1_SD_B, UART7_RX, QUADSPI_BK1_IO3, SAI4_SCK_B, EVENTOUT VDDCORE S - - - - LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1, I2C4_SCL, I2C1_SCL, USART3_RTS/USART3_DE, QUADSPI_BK1_IO1, SAI2_FS_A, FMC_ALE/FMC_A17, EVENTOUT - - - - - - Y18 W12 PD12 I/O AA8 G10 VSS S AA14 AB11 1C6 K13 FT_fha - - PF9 I/O FT_ha - TRACED13, TIM17_CH1N, SPI5_MOSI, SAI1_FS_B, UART7_CTS, TIM14_CH1, QUADSPI_BK1_IO1, EVENTOUT VDDCORE S - - - DS12500 Rev 1 73/245 119 Pinouts, pin description and alternate functions STM32MP151A Pin functions Notes Pin name (function after reset) Pin type LFBGA448 TFBGA361 LFBGA354 TFBGA257 Pin Number I/O structure Table 7. STM32MP151A pin and ball definitions (continued) Alternate functions Additional functions - V11 W10 AC14 Y11 PG7 I/O FT_h - TRACED5, SAI1_MCLK_A, USART6_CK, UART8_RTS/UART8_DE, QUADSPI_CLK, QUADSPI_BK2_IO3, DCMI_D13, LCD_CLK, EVENTOUT 1E3 F15 - G12 VSS S - - - - 1F5 - - VDDCORE S - - - - - W11 T12 U12 H8 V13 T13 - W13 PB6 I/O Y12 PE8 I/O Y15 W14 PE10 I/O 1D1 K15 VDDCORE S T11 AC13 V12 V10 - Y14 H10 TIM16_CH1N, TIM4_CH1, I2C1_SCL, CEC, I2C4_SCL, USART1_TX, FT_fha QUADSPI_BK1_NCS, DFSDM1_DATIN5, UART5_TX, DCMI_D5, EVENTOUT TIM1_CH1N, DFSDM1_CKIN2, UART7_TX, FT_h QUADSPI_BK2_IO1, FMC_D5/FMC_DA5, EVENTOUT TIM1_CH2N, DFSDM1_DATIN4, UART7_CTS, FT_ha QUADSPI_BK2_IO3, FMC_D7/FMC_DA7, EVENTOUT - - - - - - - - Y16 V13 PB2 I/O FT_ha - TRACED4, RTC_OUT2, SAI1_D1, DFSDM1_CKIN1, USART1_RX, I2S_CKIN, SAI1_SD_A, SPI3_MOSI/I2S3_SDO, UART4_RX, QUADSPI_CLK, EVENTOUT - - VDDCORE S - - - - LPTIM1_OUT, TIM4_CH2, I2C4_SDA, I2C1_SDA, I2S3_MCK, QUADSPI_BK1_IO3, SAI2_SCK_A, FMC_A18, EVENTOUT - U13 U12 AA19 V14 PD13 I/O FT_fha - - N7 - - VDD S - - - - - G2 AA12 G14 VSS S - - - - USB_RREF A A - - - 1J8 74/245 V16 AB18 AA17 DS12500 Rev 1 STM32MP151A Pinouts, pin description and alternate functions Table 7. STM32MP151A pin and ball definitions (continued) LFBGA448 TFBGA361 - - Notes - VDD3V3_ USBHS VDD3V3_ USB I/O structure 1H7 W12 AA15 AB13 Pin name (function after reset) Pin functions Pin type - LFBGA354 TFBGA257 Pin Number Alternate functions S - - - - S - - - - Additional functions USBH_HS_DP2, OTG_HS_DP USBH_HS_DM2 , OTG_HS_DM V10 W13 AC16 AB14 USB_DP2 A FT_u - - W10 V13 AB16 AA14 USB_DM2 A FT_u - - Y13 VSS_USBHS S - - - - Y14 VSS_USBHS S - - - - BYPASS_ REG1V8 I FT - - - - U11 U13 AA16 - - T15 AB13 AA12 W8 T14 Y13 W15 PG9 I/O FT_h - DBTRGO, USART6_RX, SPDIFRX_IN3, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NCE/FMC_NE2, DCMI_VSYNC, LCD_R1, EVENTOUT 1G3 - 1H5 R10 VDD S - - - - - N9 - - VDD S - - - - VDDA1V8_ REG S - - - - VSS S - - - - VDDA1V1_ REG S - - - - 1H5 V11 AB14 AB12 1H3 - - G17 1J6 W11 AB15 AB17 - G4 AA21 H7 VSS S - - - - - - - R12 VDD S - - - - - P6 - - VDD S - - - - - U14 - Y15 VSS_USBHS S - - - - - V12 - AA13 VSS_USBHS S - - - - 1D4 G6 AC1 J9 VSS S - - - - - V15 - AA16 VSS_USBHS S - - - - W14 W14 AB17 AB15 USB_DM1 A FT_u - - USBH_HS_DM1 V14 V14 AC17 AA15 USB_DP1 A FT_u - - USBH_HS_DP1 - TIM1_ETR, I2C6_SDA, I2C5_SDA, UART4_TX, USART1_RTS/USART1_DE, SAI2_FS_B, LCD_R5, EVENTOUT OTG_FS_DP V15 U16 AB19 W16 PA12 I/O FT_uf DS12500 Rev 1 75/245 119 Pinouts, pin description and alternate functions STM32MP151A Table 7. STM32MP151A pin and ball definitions (continued) LFBGA354 TFBGA361 LFBGA448 Pin name (function after reset) Pin type I/O structure Notes Pin functions TFBGA257 Pin Number Alternate functions - G8 - J11 VSS S - - - - - - - L8 VDDCORE S - - - - OTG_FS_DM U15 V17 AA18 1C6 H12 1D3 1F4 G10 AC23 - U16 T16 - Y16 PA11 I/O FT_uf - TIM1_CH4, I2C6_SCL, I2C5_SCL, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS/USART1_NSS, LCD_R4, EVENTOUT - VDDCORE S - - - - - VSS S - - - - VDD3V3_ USBFS S - - - - OTG_VBUS A FT_u - - OTG_FS_VBUS , OTG_HS_VBUS OTG_FS_ID, OTG_HS_ID W15 AA17 AB16 V16 U15 AC19 - 1B9 E15 - - - G12 - - 1H4 G14 Y17 V15 Y17 AB20 AB20 1A8 E18 AB21 AB21 - J13 AC22 AA21 1A3 Additional functions J17 I/O FT_u - DDR_DQ27 I/O DDR - - - VDDQ_DDR S - - - - DDR_DQ26 I/O DDR - - - VSS S - - - - DDR_DQ28 I/O DDR - - - VSS S - - - - DDR_DQ29 I/O DDR - - - - - - - Y22 W20 DDR_DQ25 I/O DDR - - - - - AB22 Y21 DDR_DQS3P I/O DDR - - - - H5 - J20 VSS S - - - - - - AB23 Y22 DDR_DQS3N I/O DDR - - - - - - F17 VDDQ_DDR S - - - - - - DDR_DQM3 O DDR - - - - F14 1B7 - VDDQ_DDR S - - - - - - AA22 W21 DDR_DQ31 I/O DDR - - - - H7 1A5 K3 VSS S - - - - - - AA23 W22 DDR_DQ30 I/O DDR - - - 76/245 AC21 AA20 PA10 TIM1_CH3, SPI3_NSS/I2S3_WS, USART1_RX, MDIOS_MDIO, SAI4_FS_B, DCMI_D1, LCD_B1, EVENTOUT AA20 AA22 DS12500 Rev 1 STM32MP151A Pinouts, pin description and alternate functions Table 7. STM32MP151A pin and ball definitions (continued) LFBGA354 TFBGA361 LFBGA448 Pin name (function after reset) Pin type I/O structure Notes Pin functions TFBGA257 Pin Number Alternate functions U9 H9 1A7 K7 VSS S - - - - - - Y23 V22 DDR_DQ24 I/O DDR - - - - - - G16 VDDQ_DDR S - - - - - - - L10 VDDCORE S - - - - DDR_VREF A A - - - K10 VSS S - - - - W17 W18 W23 V20 DDR_DQ12 I/O DDR - - - 1C5 H13 1B2 K12 VSS S - - - - V17 W17 Y21 V21 DDR_DQ15 I/O DDR - - - - K14 VSS S - - - - U17 V18 W22 U21 DDR_DQ14 I/O DDR - - - W18 V19 W21 T20 DDR_DQ11 I/O DDR - - - G15 1B9 H17 VDDQ_DDR S - - - - V19 U19 U22 T22 DDR_DQS1P I/O DDR - - - 1E5 1B4 L9 VSS S - - - - U18 T19 U23 R22 DDR_DQS1N I/O DDR - - - V18 U18 V22 T21 DDR_DQM1 O DDR - - - W16 W16 AC20 AB19 - - - H11 H15 - - Additional functions 1D9 - - J16 VDDQ_DDR S - - - - T18 T18 T23 R20 DDR_DQ13 I/O DDR - - - - J3 1B6 - VSS S - - - - U21 R21 DDR_DQ9 I/O DDR - - - - L11 VSS S - - - - T22 P21 DDR_DQ10 I/O DDR - - - - - VDDQ_DDR S - - - - T21 N22 DDR_DQ8 I/O DDR - - - U19 T17 1G5 J6 T19 R18 - H14 R18 P18 - J8 1B8 L13 VSS S - - - - 1J5 J10 - L17 VSS S - - - - Y19 AA19 DDR_ATO A A - - - 1F8 N19 - J7 - - VDDCORE S - - - - - - 1C8 - VDDQ_DDR S - - - - W20 U19 DDR_A6 O DDR - - - - K17 VDDQ_DDR S - - - - 1G9 N16 - - DS12500 Rev 1 77/245 119 Pinouts, pin description and alternate functions STM32MP151A Table 7. STM32MP151A pin and ball definitions (continued) Pin type I/O structure Notes Alternate functions Y20 U18 DDR_A8 O DDR - - - J12 1C1 L19 VSS S - - - - R17 P17 V20 T18 DDR_A4 O DDR - - - 1A6 J14 1C3 L20 VSS S - - - - P17 P19 T20 R19 DDR_CKE O DDR - - - P18 N17 U20 R18 DDR_BA1 O DDR - - - - L16 VDDQ_DDR S - - - - R21 P18 DDR_A14 O DDR - - - - M7 VSS S - - - - R20 P19 DDR_A11 O DDR - - - LFBGA354 Pin name (function after reset) TFBGA257 LFBGA448 Pin functions TFBGA361 Pin Number T17 R17 - - J15 N18 N18 - K2 N19 M18 Additional functions - K5 1C5 M10 VSS S - - - - 1D6 K7 - M12 VSS S - - - - R22 N18 DDR_A10 O DDR - - - M17 M19 - J9 1D5 L12 VDDCORE S - - - - - - 1D9 - VDDQ_DDR S - - - - M18 L17 P23 N19 DDR_A12 O DDR - - - M19 M17 P22 M18 DDR_A1 O DDR - - - - K9 1C7 M14 VSS S - - - - J19 K17 N20 M22 DDR_CASN O DDR - - - 1F6 K11 - N9 VSS S - - - - J18 J17 M20 M21 DDR_WEN O DDR - - - - K14 - M17 VDDQ_DDR S - - - - 1E9 L18 N21 M20 DDR_RASN O DDR - - - L17 L19 N22 N20 DDR_CLKP O DDR - - - - K13 1C9 - VSS S - - - - K18 K19 N23 N21 DDR_CLKN O DDR - - - 1F9 1E8 N16 VDDQ_DDR S - - - - 1D8 K18 K20 L22 DDR_DTO0 O DDR - - - 1C8 J19 L21 K21 DDR_DTO1 O DDR - - - L18 L16 P20 M19 DDR_A15 O DDR - - - 1H6 - 1D2 N11 VSS S - - - - 1E6 - - - VDDCORE S - - - - 78/245 - DS12500 Rev 1 STM32MP151A Pinouts, pin description and alternate functions Table 7. STM32MP151A pin and ball definitions (continued) LFBGA354 TFBGA361 LFBGA448 Pin name (function after reset) Pin type I/O structure Notes Pin functions TFBGA257 Pin Number Alternate functions - K15 - N13 VSS S - - - - J17 J18 M22 L18 DDR_CSN O DDR - - - H18 H19 L22 L21 DDR_ODT O DDR - - - H17 J16 M21 K18 DDR_BA2 O DDR - - - 1C7 L6 1D4 N17 VSS S - - - - L20 K19 DDR_A0 O DDR - - - - P17 VDDQ_DDR S - - - - G19 G19 L23 K20 DDR_BA0 O DDR - - - E17 F17 F20 G18 DDR_A13 O DDR - - - - P3 VSS S - - - - F17 G18 J20 J18 DDR_A2 O DDR - - - 1E7 L10 1D6 P7 VSS S - - - - F19 F19 K22 J19 DDR_A3 O DDR - - - - - 1F9 - VDDQ_DDR S - - - - D20 F19 DDR_ RESETN O DDR - - - - R16 VDDQ_DDR S - - - - H20 H19 DDR_A5 O DDR - - - L12 1D8 P10 VSS S - - - - 1A9 E17 E20 F18 DDR_A7 O DDR - - - - P12 VSS S - - - - 1A8 F18 K23 K22 DDR_ZQ A A - - - E18 G17 G20 H18 DDR_A9 O DDR - - - 1G7 M5 1E1 P14 VSS S - - - - - J11 1D7 L14 VDDCORE S - - - - D18 E18 J21 J21 DDR_DQ4 I/O DDR - - - - P20 VSS S - - - - D19 D17 J22 H20 DDR_DQ5 I/O DDR - - - W13 M9 1E3 - VSS S - - - - C18 D18 H21 H21 DDR_DQ2 I/O DDR - - - - T17 VDDQ_DDR S - - - - H22 H22 DDR_DQ6 I/O DDR - - - G18 H18 - - L15 L8 C16 G16 - M14 1C9 H17 - - - - L14 M7 - C19 D19 DS12500 Rev 1 Additional functions 79/245 119 Pinouts, pin description and alternate functions STM32MP151A Table 7. STM32MP151A pin and ball definitions (continued) Notes - - - G22 G22 DDR_DQS0P I/O DDR - - - - R8 VSS S - - - - G23 G21 DDR_DQS0N I/O DDR - - - - - VDDQ_DDR S - - - - H23 G20 DDR_DQM0 O DDR - - - - U16 VDDQ_DDR S - - - - B17 B18 G21 G19 DDR_DQ7 I/O DDR - - - 1B8 M13 1E5 R17 VSS S - - - - A18 A18 F22 F21 DDR_DQ1 I/O DDR - - - M15 1E7 T7 VSS S - - - - A17 A17 E22 E21 DDR_DQ0 I/O DDR - - - B16 B17 E21 E20 DDR_DQ3 I/O DDR - - - LFBGA448 - TFBGA361 S LFBGA354 Alternate functions TFBGA257 I/O structure Pin functions Pin type Pin Number Pin name (function after reset) - - 1G8 - VDDQ_DDR B19 C19 - M11 B18 B19 - N15 C17 C18 1H9 - - Additional functions - P14 1H9 V17 VDDQ_DDR S - - - - 1H8 - - T9 VSS S - - - - - J13 - - VDDCORE S - - - - - - E23 E22 DDR_DQ21 I/O DDR - - - - N6 1E9 T11 VSS S - - - - - - D21 D20 DDR_DQ22 I/O DDR - - - C14 N8 - T19 VSS S - - - - - - D22 D21 DDR_DQ17 I/O DDR - - - - - D23 D22 DDR_DQ18 I/O DDR - - - - - - W18 VDDQ_DDR S - - - - - - C22 C21 DDR_DQS2P I/O DDR - - - - N10 1F2 U7 VSS S - - - - - - B23 B22 DDR_DQS2N I/O DDR - - - - R15 1J8 - VDDQ_DDR S - - - - - - C23 C22 DDR_DQM2 O DDR - - - - - - Y19 VDDQ_DDR S - - - - - - B22 B21 DDR_DQ16 I/O DDR - - - - N12 1F4 U13 VSS S - - - - - - A22 A21 DDR_DQ23 I/O DDR - - - 80/245 DS12500 Rev 1 STM32MP151A Pinouts, pin description and alternate functions Table 7. STM32MP151A pin and ball definitions (continued) LFBGA354 TFBGA361 LFBGA448 Pin name (function after reset) Pin type I/O structure Notes Pin functions TFBGA257 Pin Number Alternate functions 1J9 N14 - U15 VSS S - - - - - - B21 B20 DDR_DQ19 I/O DDR - - - - - A21 A20 DDR_DQ20 I/O DDR - - - - - 1J4 - VDD S - - - - - P7 1F6 - VSS S - - - - - - - M11 VDDCORE S - - - - C15 D15 C20 E17 JTMS-SWDIO I/O FTU - - - A16 D16 B20 D17 JTCK-SWCLK I FTD - - - A15 D14 A19 E16 JTDOTRACESWO O FTU - - - B15 D13 A20 D16 JTDI I FTU - - - 1G6 1E2 - VDDCORE S - - - - B19 E15 NJTRST I FTU - - - VDD_PLL2 S - - - - K8 B14 D12 Additional functions - G13 - D18 - F13 - D19 VSS_PLL2 S - - - - C14 B14 VDDA1V8_Un used S - - - - 1B6 B12 - C12 C16 C14 VSS S - - - - - C13 - C15 VSS S - - - - A13 B15 B17 B17 DNU DNU - - - - B13 A15 A17 A17 DNU DNU - - - - S - - - - 1B7 A16 C17 A18 VDD1V2_Unu sed B12 A14 A16 A16 DNU DNU - - - - A12 B14 B16 B16 DNU DNU - - - - - C14 - C16 VSS S - - - - - C15 - C17 VSS S - - - - - C16 - C18 VSS S - - - - B11 B13 C15 B15 DNU DNU - - - - C12 A13 B15 A15 DNU DNU - - - - - T13 VDD S - - - - C13 A12 B18 A14 VDD_Unused S - - - - 1A7 B16 C18 B18 VDD1V2_Unu sed S - - - - - P8 DS12500 Rev 1 81/245 119 Pinouts, pin description and alternate functions STM32MP151A Table 7. STM32MP151A pin and ball definitions (continued) LFBGA448 P9 - U17 VSS S Notes TFBGA361 D17 Pin functions I/O structure LFBGA354 Pin name (function after reset) Pin type TFBGA257 Pin Number Alternate functions Additional functions - - - - - C11 A11 D16 D15 PC11 I/O FT_ha - TRACED3, DFSDM1_DATIN5, SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SAI4_SCK_B, SDMMC1_D3, DCMI_D4, EVENTOUT - K10 - - VDDCORE S - - - - TRACED1, SAI1_D2, DFSDM1_DATIN3, TIM15_CH1N, SPI4_NSS, SAI1_FS_A, SDMMC2_CKIN, SDMMC1_CKIN, SDMMC2_D4, SDMMC1_D4, FMC_A20, DCMI_D4, LCD_B0, EVENTOUT - A10 B11 - - D19 F15 PE4 I/O FT_h - - M13 VDDCORE S - - - - - A9 C11 D18 E14 PC8 I/O FT_ha - TRACED0, TIM3_CH3, TIM8_CH3, UART4_TX, USART6_CK, UART5_RTS/UART5_DE, SDMMC1_D0, DCMI_D2, EVENTOUT - P11 1F8 U20 VSS S - - - - - - B10 D11 D15 F14 PC10 I/O FT_ha - TRACED2, DFSDM1_CKIN5, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SAI4_MCLK_B, SDMMC1_D2, DCMI_D8, LCD_R2, EVENTOUT 1D7 K12 1E4 - VDDCORE S - - - B6 B9 B13 C13 PB4 I/O FT_ha - B9 A10 D17 D14 PC9 I/O FT_fh - 82/245 DS12500 Rev 1 TRACED8, TIM16_BKIN, TIM3_CH1, SAI4_CK2, SPI1_MISO/I2S1_SDI, SPI3_MISO/I2S3_SDI, SPI2_NSS/I2S2_WS, SPI6_MISO, SDMMC2_D3, SAI4_SCK_A, UART7_TX, EVENTOUT TRACED1, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, QUADSPI_BK1_IO0, SDMMC1_D1, DCMI_D3, LCD_B2, EVENTOUT - - STM32MP151A Pinouts, pin description and alternate functions Table 7. STM32MP151A pin and ball definitions (continued) V5 VSS S Notes 1G3 Pin functions I/O structure Pin name (function after reset) Pin type LFBGA448 G17 P13 TFBGA361 LFBGA354 TFBGA257 Pin Number Alternate functions Additional functions - - - - - - C10 A9 B11 D13 PC7 I/O FT_ha - HDP4, TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, I2S3_MCK, USART6_RX, SDMMC1_D123DIR, SDMMC2_D123DIR, SDMMC2_D7, SDMMC1_D7, DCMI_D1, LCD_G6, EVENTOUT - L9 - M15 VDDCORE S - - - HDP1, TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, I2S2_MCK, USART6_TX, SDMMC1_D0DIR, SDMMC2_D0DIR, SDMMC2_D6, SDMMC1_D6, DCMI_D0, LCD_HSYNC, EVENTOUT I2C2_SMBA, SDMMC2_D0DIR, SDMMC3_D0DIR, SDMMC1_D0DIR, FMC_A2, EVENTOUT TIM3_ETR, I2C5_SMBA, UART4_RX, UART5_RX, SDMMC1_CMD, DCMI_D11, EVENTOUT A4 D10 B14 E13 PC6 I/O FT_ha - - - A14 F13 PF2 I/O FT_h 1A5 B10 D12 D12 PD2 I/O FT_ha 1G4 P10 - - VDD S - - - - - - - P15 - V16 VSS S - - - - - - 1E6 - VDDCORE S - - - - B8 B8 A13 B13 PA8 I/O FT_fh - 1A4 C9 C13 A13 PB14 I/O FT_h - MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL, SPI3_MOSI/I2S3_SDO, USART1_CK, SDMMC2_CKIN, SDMMC2_D4, OTG_FS_SOF/OTG_HS_SOF, SAI4_SD_B, UART7_RX, LCD_R6, EVENTOUT TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SPI2_MISO/I2S2_SDI, DFSDM1_DATIN2, USART3_RTS/USART3_DE, SDMMC2_D0, EVENTOUT DS12500 Rev 1 - - 83/245 119 Pinouts, pin description and alternate functions STM32MP151A Pin functions Notes Pin name (function after reset) Pin type LFBGA448 TFBGA361 LFBGA354 TFBGA257 Pin Number I/O structure Table 7. STM32MP151A pin and ball definitions (continued) Alternate functions Additional functions - - 1B4 C10 D13 E12 PC12 I/O FT_h - TRACECLK, MCO2, SAI4_D3, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX, SAI4_SD_B, SDMMC1_CK, DCMI_D9, EVENTOUT K17 1G5 V18 VSS S - - - R2 C8 A8 B12 B12 PB15 I/O FT_h - L11 - N12 VDDCORE S - RTC_REFIN, TIM1_CH3N, TIM12_CH2, TIM8_CH3N, USART1_RX, SPI2_MOSI/I2S2_SDO, DFSDM1_CKIN2, SDMMC2_D1, EVENTOUT - - - - - - B7 B7 C11 C12 PE5 I/O FT_h - TRACED3, SAI1_CK2, DFSDM1_CKIN3, TIM15_CH1, SPI4_MISO, SAI1_SCK_A, SDMMC2_D0DIR, SDMMC1_D0DIR, SDMMC2_D6, SDMMC1_D6, FMC_A21, DCMI_D6, LCD_G0, EVENTOUT - - - U12 VDD S - - - TRACED9, TIM2_CH2, SAI4_CK1, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SPI6_SCK, SDMMC2_D2, SAI4_MCLK_A, UART7_RX, EVENTOUT - C7 A7 A11 A12 PB3 I/O FT_h - R6 - V19 VSS S - - - - B5 A6 A10 D11 PG6 I/O FT_h - TRACED14, TIM17_BKIN, SDMMC2_CMD, DCMI_D12, LCD_R7, EVENTOUT - 1F7 - - - VDDCORE S - - - - - HDP5, DFSDM1_CKOUT, SPI2_SCK/I2S2_CK, DFSDM1_DATIN0, USART2_CTS/USART2_NSS, SDMMC1_D123DIR, SDMMC2_D7, SDMMC2_D123DIR, SDMMC1_D7, FMC_CLK, DCMI_D5, LCD_G7, EVENTOUT - A7 84/245 C6 D14 B11 PD3 I/O FT_h DS12500 Rev 1 STM32MP151A Pinouts, pin description and alternate functions C9 D9 B10 F12 PB9 I/O FT_fh B4 C7 C19 E11 PA15 I/O FT_h N17 - 1G7 W17 VSS S - Pin functions Notes Pin name (function after reset) Pin type LFBGA448 TFBGA361 LFBGA354 TFBGA257 Pin Number I/O structure Table 7. STM32MP151A pin and ball definitions (continued) Alternate functions HDP7, TIM17_CH1, TIM4_CH4, DFSDM1_DATIN7, I2C1_SDA, SPI2_NSS/I2S2_WS, I2C4_SDA, SDMMC2_CDIR, UART4_TX, SDMMC2_D5, SDMMC1_CDIR, SDMMC1_D5, DCMI_D7, LCD_B7, EVENTOUT DBTRGI, TIM2_CH1/TIM2_ETR, SAI4_D2, SDMMC1_CDIR, CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, SPI6_NSS, UART4_RTS/UART4_DE, SDMMC2_D5, SDMMC2_CDIR, SDMMC1_D5, SAI4_FS_A, UART7_TX, LCD_R1, EVENTOUT - TIM1_CH2, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, SDMMC2_CDIR, SDMMC2_D5, DCMI_D0, LCD_R5, EVENTOUT TIM17_CH1N, TIM4_CH2, I2C1_SDA, I2C4_SDA, USART1_RX, SDMMC2_D1, DFSDM1_CKIN5, FMC_NL, DCMI_VSYNC, EVENTOUT Additional functions - - - - C6 C8 A8 A11 PA9 I/O FT_h - A3 B5 D11 F11 PB7 I/O FT_fh - - L13 1F5 N14 VDDCORE S - - - - - - A2 A4 B9 B10 PD1 I/O FT_fh - I2C6_SCL, DFSDM1_DATIN6, I2C5_SCL, SAI3_SD_A, UART4_TX, SDMMC3_D0, DFSDM1_CKIN7, FMC_D3/FMC_DA3, EVENTOUT - R9 1J6 - VDD S - - - - - - C5 A3 B8 C10 PD0 I/O FT_fh - I2C6_SDA, DFSDM1_CKIN6, I2C5_SDA, SAI3_SCK_A, UART4_RX, SDMMC3_CMD, DFSDM1_DATIN7, FMC_D2/FMC_DA2, EVENTOUT - R8 - W19 VSS S - - - DS12500 Rev 1 85/245 119 Pinouts, pin description and alternate functions STM32MP151A Table 7. STM32MP151A pin and ball definitions (continued) LFBGA354 TFBGA361 LFBGA448 Pin name (function after reset) Pin type I/O structure Notes Pin functions TFBGA257 Pin Number 1A3 A5 C9 A10 PE3 I/O FT_h - C4 D7 A7 A9 PD5 I/O FT_h - B3 B4 D10 F10 PD7 I/O FT_fh - - M10 - - VDDCORE S - - Alternate functions TRACED0, TIM15_BKIN, SAI1_SD_B, SDMMC2_CK, FMC_A19, EVENTOUT USART2_TX, SDMMC3_D2, FMC_NWE, EVENTOUT TRACED6, DFSDM1_DATIN4, I2C2_SCL, DFSDM1_CKIN1, USART2_CK, SPDIFRX_IN0, SDMMC3_D3, FMC_NE1, EVENTOUT TRACED7, SAI1_D2, I2C2_SDA, SAI1_FS_A, USART6_CTS/USART6_NSS, SDMMC3_CK, DCMI_D13, EVENTOUT TRACED2, TIM1_BKIN2, SAI1_D1, TIM15_CH2, SPI4_MOSI, SAI1_SD_A, SDMMC2_D0, SDMMC1_D2, SAI2_MCLK_B, FMC_A22, DCMI_D7, LCD_G1, EVENTOUT Additional functions - - - B1 A2 B7 D10 PG15 I/O FT_fh - B2 B3 C10 E9 PE6 I/O FT_h - - R10 1G9 Y3 VSS S - - - - - - D8 E10 PF0 I/O FT_fh - I2C2_SDA, SDMMC3_D0, SDMMC3_CKIN, FMC_A0, EVENTOUT - - - - P13 VDDCORE S - - - - - - A5 B9 PF1 I/O FT_fh - I2C2_SCL, SDMMC3_CMD, SDMMC3_CDIR, FMC_A1, EVENTOUT - 1H4 - VSS S - - - - D9 F9 PF4 I/O FT_h - USART2_RX, SDMMC3_D1, SDMMC3_D123DIR, FMC_A4, EVENTOUT - 1F7 - VDDCORE S - - - - F18 R12 - - 1E8 M12 C3 D6 B6 C9 PD4 I/O FT_h - - - U14 VDD S - - SAI3_FS_A, USART2_RTS/USART2_DE, SDMMC3_D1, DFSDM1_CKIN0, FMC_NOE, EVENTOUT - - - - - - D7 D9 PF5 I/O FT_h - USART2_TX, SDMMC3_D2, FMC_A5, EVENTOUT - R14 - Y7 VSS S - - - 86/245 - DS12500 Rev 1 STM32MP151A Pinouts, pin description and alternate functions Pin functions Notes Pin name (function after reset) Pin type LFBGA448 TFBGA361 LFBGA354 TFBGA257 Pin Number I/O structure Table 7. STM32MP151A pin and ball definitions (continued) Alternate functions Additional functions - 1A2 C5 B5 A8 PD10 I/O FT_h - RTC_REFIN, TIM16_BKIN, DFSDM1_CKOUT, I2C5_SMBA, SPI3_MISO/I2S3_SDI, SAI3_FS_B, USART3_CK, FMC_D15/FMC_DA15, LCD_B3, EVENTOUT - N11 - P15 VDDCORE S - - - - - - - B8 PJ12 I/O FT - LCD_G3, LCD_B0, EVENTOUT - - - - A7 PJ13 I/O FT - LCD_G4, LCD_B1, EVENTOUT - - - - B7 PJ14 I/O FT - LCD_B2, EVENTOUT - 1H6 Y10 VSS S - - - - A19 R16 - - - C7 PJ15 I/O FT - LCD_B3, EVENTOUT - - - 1G6 - VDDCORE S - - - - - - - D8 PK0 I/O FT_h - - - - E7 PK1 I/O FT_h - - - - E8 PK2 I/O FT_h - - R11 - - VDD S - - - - - T4 - Y18 VSS S - - - - - N13 - R14 VDDCORE S - - - - - - - B6 PK3 I/O FT - LCD_B4, EVENTOUT - - - - A6 PK4 I/O FT - LCD_B5, EVENTOUT - TIM1_CH1N, TIM8_CH3, SPI5_SCK, LCD_G5, EVENTOUT TRACED4, TIM1_CH1, HDP4, TIM8_CH3N, SPI5_NSS, LCD_G6, EVENTOUT TRACED5, TIM1_BKIN, HDP5, TIM8_BKIN, LCD_G7, EVENTOUT - - - - - - C6 PK5 I/O FT_h - TRACED6, HDP6, LCD_B6, EVENTOUT K19 U3 1H8 Y20 VSS S - - - - - - - A5 PK6 I/O FT_h - TRACED7, HDP7, LCD_B7, EVENTOUT - - - VDDCORE S - - - - - B5 PK7 I/O FT - LCD_DE, EVENTOUT - - LPTIM1_ETR, TIM4_ETR, LPTIM2_ETR, SPI3_SCK/I2S3_CK, SAI4_MCLK_B, UART8_RX, SAI2_MCLK_A, FMC_NBL0, DCMI_D2, EVENTOUT - 1G8 P12 - C2 - C4 D6 C5 PE0 I/O FT_h DS12500 Rev 1 87/245 119 Pinouts, pin description and alternate functions STM32MP151A Pin functions Notes Pin name (function after reset) Pin type LFBGA448 TFBGA361 LFBGA354 TFBGA257 Pin Number I/O structure Table 7. STM32MP151A pin and ball definitions (continued) Alternate functions Additional functions - 1A1 B1 C8 D7 PE1 I/O FT - LPTIM1_IN2, I2S2_MCK, SAI3_SD_B, UART8_TX, FMC_NBL1, DCMI_D3, EVENTOUT - U6 1J3 AA4 VSS S - - - - - - D5 D6 PH8 I/O FT_f - TIM5_ETR, I2C3_SDA, DCMI_HSYNC, LCD_R2, EVENTOUT - - - 1H7 T15 VDDCORE S - - - - - - C5 E6 PH9 I/O FT D2 C1 A4 D5 PE11 I/O FT C1 D2 B4 E4 PE12 I/O FT_h E3 C2 A3 A4 PE13 I/O FT_h - R13 - - VDDCORE S - TIM12_CH2, I2C3_SMBA, DCMI_D0, LCD_R3, EVENTOUT TIM1_CH2, DFSDM1_CKIN4, SPI4_NSS, USART6_CK, SAI2_SD_B, FMC_D8/FMC_DA8, DCMI_D4, LCD_G3, EVENTOUT TIM1_CH3N, DFSDM1_DATIN5, SPI4_SCK, SDMMC1_D0DIR, SAI2_SCK_B, FMC_D9/FMC_DA9, LCD_B4, EVENTOUT HDP2, TIM1_CH3, DFSDM1_CKIN5, SPI4_MISO, SAI2_FS_B, FMC_D10/FMC_DA10, DCMI_D6, LCD_DE, EVENTOUT - - - - - - - - - - C4 B3 PH11 I/O FT_f - TIM5_CH2, I2C4_SCL, I2C1_SCL, DCMI_D2, LCD_R5, EVENTOUT R19 U8 - AA18 VSS S - - - - - U17 1J5 AB1 VSS S - - - - - AB18 VSS S - - - - 1J7 AB22 VSS S - - - - W19 W1 - 1B2 88/245 W19 D3 C6 B4 PE14 I/O FT_h TIM1_CH4, SPI4_MOSI, UART8_RTS/UART8_DE, SAI2_MCLK_B, SDMMC1_D123DIR, FMC_D11/FMC_DA11, LCD_G0, LCD_CLK, EVENTOUT DS12500 Rev 1 - STM32MP151A Pinouts, pin description and alternate functions Pin functions Notes Pin name (function after reset) Pin type LFBGA448 TFBGA361 LFBGA354 TFBGA257 Pin Number I/O structure Table 7. STM32MP151A pin and ball definitions (continued) D3 E1 D3 C4 PE15 I/O FT - - - B3 A3 PH4 I/O FT_f - Alternate functions HDP3, TIM1_BKIN, TIM15_BKIN, USART2_CTS/USART2_NSS, UART8_CTS, FMC_NCE2, FMC_D12/FMC_DA12, LCD_R7, EVENTOUT I2C2_SCL, LCD_G5, LCD_G4, EVENTOUT DS12500 Rev 1 Additional functions - - 89/245 119 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1 SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2 TIM1/2/16/17/ LPTIM1/SYS/ RTC SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS PA0 - TIM2_CH1/ TIM2_ETR TIM5_CH1 TIM8_ETR TIM15_BKIN - - USART2_CTS/ USART2_NSS PA1 ETH_CLK TIM2_CH2 TIM5_CH2 LPTIM3_OUT TIM15_CH1N - - USART2_RTS/ USART2_DE PA2 - TIM2_CH3 TIM5_CH3 LPTIM4_OUT TIM15_CH1 - - USART2_TX PA3 - TIM2_CH4 TIM5_CH4 LPTIM5_OUT TIM15_CH2 - - USART2_RX PA4 HDP0 - TIM5_ETR - SAI4_D2 SPI1_NSS/ I2S1_WS SPI3_NSS/ I2S3_WS USART2_CK PA5 - TIM2_CH1/ TIM2_ETR - TIM8_CH1N SAI4_CK1 SPI1_SCK/I2S1 _CK - - PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN SAI4_CK2 SPI1_MISO/ I2S1_SDI - - PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N SAI4_D1 SPI1_MOSI/ I2S1_SDO - - PA8 MCO1 TIM1_CH1 - TIM8_BKIN2 I2C3_SCL SPI3_MOSI/ I2S3_SDO - USART1_CK PA9 - TIM1_CH2 - - I2C3_SMBA SPI2_SCK/ I2S2_CK - USART1_TX PA10 - TIM1_CH3 - - - SPI3_NSS/ I2S3_WS - USART1_RX PA11 - TIM1_CH4 I2C6_SCL - I2C5_SCL SPI2_NSS/ I2S2_WS UART4_RX USART1_CTS/ USART1_NSS PA12 - TIM1_ETR I2C6_SDA - I2C5_SDA - UART4_TX USART1_RTS/ USART1_DE Port DS12500 Rev 1 Port A STM32MP151A HDP/SYS/RTC SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1 Pinouts, pin description and alternate functions 90/245 Table 8. Alternate function AF0 to AF7(1) AF0 AF2 AF3 AF4 AF5 AF6 AF7 SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1 SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2 TIM1/2/16/17/ LPTIM1/SYS/ RTC SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS PA13 DBTRGO DBTRGI MCO1 - - - - - PA14 DBTRGO DBTRGI MCO2 - - - - - PA15 DBTRGI TIM2_CH1/ TIM2_ETR SAI4_D2 SDMMC1_ CDIR CEC SPI1_NSS/ I2S1_WS SPI3_NSS/ I2S3_WS SPI6_NSS PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - - DFSDM1_ CKOUT - PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - DFSDM1_ DATIN1 - PB2 TRACED4 RTC_OUT2 SAI1_D1 DFSDM1_ CKIN1 USART1_RX I2S_CKIN SAI1_SD_A SPI3_MOSI/ I2S3_SDO PB3 TRACED9 TIM2_CH2 - - SAI4_CK1 SPI1_SCK/ I2S1_CK SPI3_SCK/ I2S3_CK - PB4 TRACED8 TIM16_BKIN TIM3_CH1 - SAI4_CK2 SPI1_MISO/ I2S1_SDI SPI3_MISO/ I2S3_SDI SPI2_NSS/ I2S2_WS PB5 ETH_CLK TIM17_BKIN TIM3_CH2 SAI4_D1 I2C1_SMBA SPI1_MOSI/ I2S1_SDO I2C4_SMBA SPI3_MOSI/ I2S3_SDO PB6 - TIM16_CH1N TIM4_CH1 - I2C1_SCL CEC I2C4_SCL USART1_TX PB7 - TIM17_CH1N TIM4_CH2 - I2C1_SDA - I2C4_SDA USART1_RX PB8 HDP6 TIM16_CH1 TIM4_CH3 DFSDM1_ CKIN7 I2C1_SCL SDMMC1_ CKIN I2C4_SCL SDMMC2_ CKIN PB9 HDP7 TIM17_CH1 TIM4_CH4 DFSDM1_ DATIN7 I2C1_SDA SPI2_NSS/ I2S2_WS I2C4_SDA SDMMC2_ CDIR PB10 - TIM2_CH3 - LPTIM2_IN1 I2C2_SCL SPI2_SCK/ I2S2_CK DFSDM1_ DATIN7 USART3_TX DS12500 Rev 1 Port B 91/245 Pinouts, pin description and alternate functions HDP/SYS/RTC SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1 Port Port A AF1 STM32MP151A Table 8. Alternate function AF0 to AF7(1) (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1 SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2 TIM1/2/16/17/ LPTIM1/SYS/ RTC SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS PB11 - TIM2_CH4 - LPTIM2_ETR I2C2_SDA - DFSDM1_ CKIN7 USART3_RX PB12 - TIM1_BKIN I2C6_SMBA - I2C2_SMBA SPI2_NSS/ I2S2_WS DFSDM1_ DATIN1 USART3_CK Port B PB13 - TIM1_CH1N - DFSDM1_ CKOUT LPTIM2_OUT SPI2_SCK/ I2S2_CK DFSDM1_ CKIN1 USART3_CTS/ USART3_NSS PB14 - TIM1_CH2N TIM12_CH1 TIM8_CH2N USART1_TX SPI2_MISO/ I2S2_SDI DFSDM1_ DATIN2 USART3_RTS/ USART3_DE PB15 RTC_REFIN TIM1_CH3N TIM12_CH2 TIM8_CH3N USART1_RX SPI2_MOSI/ I2S2_SDO DFSDM1_ CKIN2 - PC0 - - - DFSDM1_ CKIN0 LPTIM2_IN2 - DFSDM1_ DATIN4 - PC1 TRACED0 - SAI1_D1 DFSDM1_ DATIN0 DFSDM1_ CKIN4 SPI2_MOSI/ I2S2_SDO SAI1_SD_A - PC2 - - - DFSDM1_ CKIN1 - SPI2_MISO/ I2S2_SDI DFSDM1_ CKOUT - PC3 TRACECLK - - DFSDM1_ DATIN1 - SPI2_MOSI/ I2S2_SDO - - PC4 - - - DFSDM1_ CKIN2 - I2S1_MCK - - PC5 - - SAI1_D3 DFSDM1_ DATIN2 SAI4_D4 - SAI1_D4 - PC6 HDP1 - TIM3_CH1 TIM8_CH1 DFSDM1_ CKIN3 I2S2_MCK - USART6_TX Port DS12500 Rev 1 Port C STM32MP151A HDP/SYS/RTC SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1 Pinouts, pin description and alternate functions 92/245 Table 8. Alternate function AF0 to AF7(1) (continued) AF0 AF3 AF4 AF5 AF6 AF7 SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1 SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2 HDP/SYS/RTC TIM1/2/16/17/ LPTIM1/SYS/ RTC SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS PC7 HDP4 - TIM3_CH2 TIM8_CH2 DFSDM1_ DATIN3 - I2S3_MCK USART6_RX PC8 TRACED0 - TIM3_CH3 TIM8_CH3 - - UART4_TX USART6_CK PC9 TRACED1 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN - - PC10 TRACED2 - - DFSDM1_ CKIN5 - - SPI3_SCK/ I2S3_CK USART3_TX PC11 TRACED3 - - DFSDM1_ DATIN5 - - SPI3_MISO/ I2S3_SDI USART3_RX PC12 TRACECLK MCO2 SAI4_D3 - - - SPI3_MOSI/ I2S3_SDO USART3_CK PC13 - - - - - - - - PC14 - - - - - - - - PC15 - - - - - - - - PD0 - - I2C6_SDA DFSDM1_ CKIN6 I2C5_SDA - SAI3_SCK_A - PD1 - - I2C6_SCL DFSDM1_ DATIN6 I2C5_SCL - SAI3_SD_A - PD2 - - TIM3_ETR - I2C5_SMBA - UART4_RX - PD3 HDP5 - - DFSDM1_ CKOUT - SPI2_SCK/ I2S2_CK DFSDM1_ DATIN0 USART2_CTS/ USART2_NSS PD4 - - - - - - SAI3_FS_A USART2_RTS/ USART2_DE PD5 - - - - - - - USART2_TX 93/245 Pinouts, pin description and alternate functions DS12500 Rev 1 Port D AF2 SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1 Port Port C AF1 STM32MP151A Table 8. Alternate function AF0 to AF7(1) (continued) AF0 AF2 AF3 AF4 AF5 AF6 AF7 SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1 SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2 TIM1/2/16/17/ LPTIM1/SYS/ RTC SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS PD6 - TIM16_CH1N SAI1_D1 DFSDM1_ CKIN4 DFSDM1_ DATIN1 SPI3_MOSI/ I2S3_SDO SAI1_SD_A USART2_RX PD7 TRACED6 - - DFSDM1_ DATIN4 I2C2_SCL - DFSDM1_ CKIN1 USART2_CK PD8 - - - DFSDM1_ CKIN3 - - SAI3_SCK_B USART3_TX PD9 - - - DFSDM1_ DATIN3 - - SAI3_SD_B USART3_RX RTC_REFIN TIM16_BKIN - DFSDM1_ CKOUT I2C5_SMBA SPI3_MISO/ I2S3_SDI SAI3_FS_B USART3_CK PD11 - - - LPTIM2_IN2 I2C4_SMBA I2C1_SMBA - USART3_CTS/ USART3_NSS PD12 - LPTIM1_IN1 TIM4_CH1 LPTIM2_IN1 I2C4_SCL I2C1_SCL - USART3_RTS/ USART3_DE PD13 - LPTIM1_OUT TIM4_CH2 - I2C4_SDA I2C1_SDA I2S3_MCK - PD14 - - TIM4_CH3 - - - SAI3_MCLK_B - PD15 - - TIM4_CH4 - - - SAI3_MCLK_A - PE0 - LPTIM1_ETR TIM4_ETR - LPTIM2_ETR SPI3_SCK/ I2S3_CK SAI4_MCLK_B - PE1 - LPTIM1_IN2 - - - I2S2_MCK SAI3_SD_B - PE2 TRACECLK - SAI1_CK1 - I2C4_SCL SPI4_SCK SAI1_MCLK_A - PE3 TRACED0 - - - TIM15_BKIN - SAI1_SD_B - DS12500 Rev 1 Port D PD10 STM32MP151A HDP/SYS/RTC SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1 Port Port E AF1 Pinouts, pin description and alternate functions 94/245 Table 8. Alternate function AF0 to AF7(1) (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1 SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2 TIM1/2/16/17/ LPTIM1/SYS/ RTC SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS PE4 TRACED1 - SAI1_D2 DFSDM1_ DATIN3 TIM15_CH1N SPI4_NSS SAI1_FS_A SDMMC2_ CKIN PE5 TRACED3 - SAI1_CK2 DFSDM1_ CKIN3 TIM15_CH1 SPI4_MISO SAI1_SCK_A SDMMC2_ D0DIR PE6 TRACED2 TIM1_BKIN2 SAI1_D1 - TIM15_CH2 SPI4_MOSI SAI1_SD_A SDMMC2_D0 PE7 - TIM1_ETR TIM3_ETR DFSDM1_ DATIN2 - - - UART7_RX PE8 - TIM1_CH1N - DFSDM1_ CKIN2 - - - UART7_TX PE9 - TIM1_CH1 - DFSDM1_ CKOUT - - - UART7_RTS/ UART7_DE PE10 - TIM1_CH2N - DFSDM1_ DATIN4 - - - UART7_CTS PE11 - TIM1_CH2 - DFSDM1_ CKIN4 - SPI4_NSS - USART6_CK PE12 - TIM1_CH3N - DFSDM1_ DATIN5 - SPI4_SCK - - PE13 HDP2 TIM1_CH3 - DFSDM1_ CKIN5 - SPI4_MISO - - PE14 - TIM1_CH4 - - - SPI4_MOSI - - PE15 HDP3 TIM1_BKIN - - TIM15_BKIN - - USART2_CTS/ USART2_NSS PF0 - - - - I2C2_SDA - - - PF1 - - - - I2C2_SCL - - - Port DS12500 Rev 1 Port E 95/245 Port F Pinouts, pin description and alternate functions HDP/SYS/RTC SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1 STM32MP151A Table 8. Alternate function AF0 to AF7(1) (continued) AF0 DS12500 Rev 1 AF3 AF4 AF5 AF6 AF7 SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1 SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2 HDP/SYS/RTC TIM1/2/16/17/ LPTIM1/SYS/ RTC SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS PF2 - - - - I2C2_SMBA - - - PF3 - - - - - - - - PF4 - - - - - - - USART2_RX PF5 - - - - - - - USART2_TX PF6 - TIM16_CH1 - - - SPI5_NSS SAI1_SD_B UART7_RX PF7 - TIM17_CH1 - - - SPI5_SCK SAI1_MCLK_B UART7_TX PF8 TRACED12 TIM16_CH1N - - - SPI5_MISO SAI1_SCK_B UART7_RTS/ UART7_DE PF9 TRACED13 TIM17_CH1N - - - SPI5_MOSI SAI1_FS_B UART7_CTS PF10 - TIM16_BKIN SAI1_D3 SAI4_D4 - - SAI1_D4 - PF11 - - - - - SPI5_MOSI - - PF12 TRACED4 - - - - - - - PF13 TRACED5 - - DFSDM1_ DATIN6 I2C4_SMBA I2C1_SMBA DFSDM1_ DATIN3 - PF14 TRACED6 - - DFSDM1_ CKIN6 I2C4_SCL I2C1_SCL - - PF15 TRACED7 - - - I2C4_SDA I2C1_SDA - - PG0 TRACED0 - - DFSDM1_ DATIN0 - - - - PG1 TRACED1 - - - - - - - PG2 TRACED2 MCO2 - TIM8_BKIN - - - - STM32MP151A Port G AF2 SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1 Port Port F AF1 Pinouts, pin description and alternate functions 96/245 Table 8. Alternate function AF0 to AF7(1) (continued) AF0 AF3 AF4 AF5 AF6 AF7 SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1 SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2 HDP/SYS/RTC TIM1/2/16/17/ LPTIM1/SYS/ RTC SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS PG3 TRACED3 - - TIM8_BKIN2 DFSDM1_ CKIN1 - - - PG4 - TIM1_BKIN2 - - - - - - PG5 - TIM1_ETR - - - - - - PG6 TRACED14 TIM17_BKIN - - - - - - PG7 TRACED5 - - - - - SAI1_MCLK_A USART6_CK PG8 TRACED15 TIM2_CH1/ TIM2_ETR ETH_CLK TIM8_ETR - SPI6_NSS SAI4_D2 USART6_RTS/ USART6_DE PG9 DBTRGO - - - - - - USART6_RX PG10 TRACED10 - - - - - - - PG11 TRACED11 - - - USART1_TX - UART4_TX - PG12 - LPTIM1_IN1 - - - SPI6_MISO SAI4_CK2 USART6_RTS/ USART6_DE PG13 TRACED0 LPTIM1_OUT SAI1_CK2 - SAI4_CK1 SPI6_SCK SAI1_SCK_A USART6_CTS/ USART6_NSS PG14 TRACED1 LPTIM1_ETR - - - SPI6_MOSI SAI4_D1 USART6_TX PG15 TRACED7 - SAI1_D2 - I2C2_SDA - SAI1_FS_A USART6_CTS/ USART6_NSS PH0 - - - - - - - - PH1 - - - - - - - - PH2 - LPTIM1_IN2 - - - - - - 97/245 Pinouts, pin description and alternate functions DS12500 Rev 1 Port H AF2 SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1 Port Port G AF1 STM32MP151A Table 8. Alternate function AF0 to AF7(1) (continued) AF0 AF2 AF3 AF4 AF5 AF6 AF7 SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1 SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2 TIM1/2/16/17/ LPTIM1/SYS/ RTC SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS PH3 - - - DFSDM1_ CKIN4 - - - - PH4 - - - - I2C2_SCL - - - PH5 - - - - I2C2_SDA SPI5_NSS - - PH6 - - TIM12_CH1 - I2C2_SMBA SPI5_SCK - - PH7 - - - - I2C3_SCL SPI5_MISO - - PH8 - - TIM5_ETR - I2C3_SDA - - - PH9 - - TIM12_CH2 - I2C3_SMBA - - - PH10 - - TIM5_CH1 - I2C4_SMBA I2C1_SMBA - - PH11 - - TIM5_CH2 - I2C4_SCL I2C1_SCL - - PH12 HDP2 - TIM5_CH3 - I2C4_SDA I2C1_SDA - - PH13 - - - TIM8_CH1N - - - - PH14 - - - TIM8_CH2N - - - - PH15 - - - TIM8_CH3N - - - - PI0 - - TIM5_CH4 - - SPI2_NSS/ I2S2_WS - - PI1 - - - TIM8_BKIN2 - SPI2_SCK/ I2S2_CK - - PI2 - - - TIM8_CH4 - SPI2_MISO/ I2S2_SDI - - PI3 - - - TIM8_ETR - SPI2_MOSI/ I2S2_SDO - - DS12500 Rev 1 Port I STM32MP151A HDP/SYS/RTC SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1 Port Port H AF1 Pinouts, pin description and alternate functions 98/245 Table 8. Alternate function AF0 to AF7(1) (continued) AF0 AF3 AF4 AF5 AF6 AF7 SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1 SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2 HDP/SYS/RTC TIM1/2/16/17/ LPTIM1/SYS/ RTC SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS PI4 - - - TIM8_BKIN - - - - PI5 - - - TIM8_CH1 - - - - PI6 - - - TIM8_CH2 - - - - PI7 - - - TIM8_CH3 - - - - PI8 - - - - - - - - PI9 HDP1 - - - - - - - PI10 HDP0 - - - - - - - PI11 MCO1 - - - - I2S_CKIN - - PI12 TRACED0 - HDP0 - - - - - PI13 TRACED1 - HDP1 - - - - - PI14 TRACECLK - - - - - - - PI15 - - - - - - - - PJ0 TRACED8 - - - - - - - PJ1 TRACED9 - - - - - - - PJ2 TRACED10 - - - - - - - PJ3 TRACED11 - - - - - - - PJ4 TRACED12 - - - - - - - PJ5 TRACED2 - HDP2 - - - - - PJ6 TRACED3 - HDP3 TIM8_CH2 - - - - PJ7 TRACED13 - - TIM8_CH2N - - - - 99/245 Pinouts, pin description and alternate functions DS12500 Rev 1 Port J AF2 SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1 Port Port I AF1 STM32MP151A Table 8. Alternate function AF0 to AF7(1) (continued) AF0 DS12500 Rev 1 Port K AF2 AF3 AF4 AF5 AF6 AF7 SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1 SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2 TIM1/2/16/17/ LPTIM1/SYS/ RTC SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS PJ8 TRACED14 TIM1_CH3N - TIM8_CH1 - - - - PJ9 TRACED15 TIM1_CH3 - TIM8_CH1N - - - - PJ10 - TIM1_CH2N - TIM8_CH2 - SPI5_MOSI - - PJ11 - TIM1_CH2 - TIM8_CH2N - SPI5_MISO - - PJ12 - - - - - - - - PJ13 - - - - - - - - PJ14 - - - - - - - - PJ15 - - - - - - - - PK0 - TIM1_CH1N - TIM8_CH3 - SPI5_SCK - - PK1 TRACED4 TIM1_CH1 HDP4 TIM8_CH3N - SPI5_NSS - - PK2 TRACED5 TIM1_BKIN HDP5 TIM8_BKIN - - - - PK3 - - - - - - - - PK4 - - - - - - - - PK5 TRACED6 - HDP6 - - - - - PK6 TRACED7 - HDP7 - - - - - PK7 - - - - - - - - PZ0 - - I2C6_SCL I2C2_SCL - SPI1_SCK/ I2S1_CK - USART1_CK PZ1 - - I2C6_SDA I2C2_SDA I2C5_SDA SPI1_MISO/ I2S1_SDI I2C4_SDA USART1_RX Port Z STM32MP151A HDP/SYS/RTC SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1 Port Port J AF1 Pinouts, pin description and alternate functions 100/245 Table 8. Alternate function AF0 to AF7(1) (continued) AF0 AF2 AF3 AF4 AF5 AF6 AF7 SAI4/ I2C1/2/3/4/5/ USART1/ TIM15/LPTIM2/ DFSDM1/CEC SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/5/6/I2C1/ SDMMC1/3/ CEC SPI3/I2S3/ SAI1/3/4/ I2C4/UART4/ DFSDM1 SPI2/I2S2/ SPI3/I2S3/ SPI6/ USART1/2/3/6/ UART7/ SDMMC2 TIM1/2/16/17/ LPTIM1/SYS/ RTC SAI1/4/I2C6/ TIM3/4/5/12/ HDP/SYS PZ2 - - I2C6_SCL I2C2_SCL I2C5_SMBA SPI1_MOSI/ I2S1_SDO I2C4_SMBA USART1_TX PZ3 - - I2C6_SDA I2C2_SDA I2C5_SDA SPI1_NSS/ I2S1_WS I2C4_SDA USART1_CTS/ USART1_NSS PZ4 - - I2C6_SCL I2C2_SCL I2C5_SCL - I2C4_SCL - PZ5 - - I2C6_SDA I2C2_SDA I2C5_SDA - I2C4_SDA USART1_RTS/ USART1_DE PZ6 - - I2C6_SCL I2C2_SCL USART1_CK I2S1_MCK I2C4_SMBA USART1_RX PZ7 - - I2C6_SDA I2C2_SDA - - - USART1_TX DS12500 Rev 1 1. Refer to Table 9 for AF8 to AF15. 101/245 Pinouts, pin description and alternate functions HDP/SYS/RTC SAI4/I2C2/ TIM8/ LPTIM2/3/4/5/ DFSDM1 /SDMMC1 Port Port Z AF1 STM32MP151A Table 8. Alternate function AF0 to AF7(1) (continued) Port PA0 DS12500 Rev 1 Port A AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS UART4_TX SDMMC2_CMD SAI2_SD_B ETH1_GMII_ CRS/ ETH1_MII_CRS - - - EVENTOUT ETH1_GMII_RX _CLK/ ETH1_MII_RX_ CLK/ SAI2_MCLK_B ETH1_RGMII_ RX_CLK/ ETH1_RMII_ REF_CLK - - LCD_R2 EVENTOUT UART4_RX QUADSPI_ BK1_IO3 PA2 SAI2_SCK_B - SDMMC2_ D0DIR ETH1_MDIO MDIOS_MDIO - LCD_R1 EVENTOUT PA3 - LCD_B2 - ETH1_GMII_ COL/ ETH1_MII_COL - - LCD_B5 EVENTOUT PA4 SPI6_NSS - - - SAI4_FS_A DCMI_HSYNC LCD_VSYNC EVENTOUT PA5 SPI6_SCK - - - SAI4_MCLK_A - LCD_R4 EVENTOUT PA6 SPI6_MISO TIM13_CH1 - MDIOS_MDC SAI4_SCK_A DCMI_PIXCLK LCD_G2 EVENTOUT SAI4_SD_A - - EVENTOUT PA7 SPI6_MOSI TIM14_CH1 ETH1_GMII_RX _DV/ ETH1_MII_RX_ DV/ QUADSPI_CLK ETH1_RGMII_ RX_CTL/ ETH1_RMII_ CRS_DV STM32MP151A PA1 Pinouts, pin description and alternate functions 102/245 Table 9. Alternate function AF8 to AF15(1) AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS PA8 SDMMC2_ CKIN SDMMC2_D4 OTG_FS_SOF/ OTG_HS_SOF - SAI4_SD_B UART7_RX LCD_R6 EVENTOUT PA9 SDMMC2_ CDIR - SDMMC2_D5 - - DCMI_D0 LCD_R5 EVENTOUT PA10 - - - MDIOS_MDIO SAI4_FS_B DCMI_D1 LCD_B1 EVENTOUT Port A PA11 - - - - - - LCD_R4 EVENTOUT PA12 SAI2_FS_B - - - - - LCD_R5 EVENTOUT PA13 UART4_TX - - - - - - EVENTOUT PA14 - - - - - - - EVENTOUT PA15 UART4_RTS/ UART4_DE SDMMC2_D5 SDMMC2_ CDIR SDMMC1_D5 SAI4_FS_A UART7_TX LCD_R1 EVENTOUT - ETH1_GMII_ RXD2/ ETH1_MII_ RXD2/ ETH1_RGMII_ RXD2 MDIOS_MDIO - LCD_G1 EVENTOUT MDIOS_MDC - LCD_G0 EVENTOUT Port DS12500 Rev 1 PB0 UART4_CTS LCD_R3 PB1 - LCD_R6 - ETH1_GMII_ RXD3/ ETH1_MII_ RXD3/ ETH1_RGMII_ RXD3 PB2 UART4_RX QUADSPI_CLK - - - - - EVENTOUT PB3 SPI6_SCK SDMMC2_D2 - - SAI4_MCLK_A UART7_RX - EVENTOUT Port B 103/245 Pinouts, pin description and alternate functions AF8 STM32MP151A Table 9. Alternate function AF8 to AF15(1) (continued) AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS PB4 SPI6_MISO SDMMC2_D3 - - SAI4_SCK_A UART7_TX - EVENTOUT PB5 SPI6_MOSI - SAI4_SD_A ETH1_PPS_ OUT UART5_RX DCMI_D10 LCD_G7 EVENTOUT PB6 - - QUADSPI_BK1 _NCS DFSDM1_ DATIN5 UART5_TX DCMI_D5 - EVENTOUT PB7 - - SDMMC2_D1 DFSDM1_ CKIN5 FMC_NL DCMI_VSYNC - EVENTOUT SDMMC1_D4 DCMI_D6 LCD_B6 EVENTOUT Port DS12500 Rev 1 UART4_RX - SDMMC2_D4 PB9 UART4_TX - SDMMC2_D5 SDMMC1_CDI R SDMMC1_D5 DCMI_D7 LCD_B7 EVENTOUT - QUADSPI_ BK1_NCS - ETH1_GMII_ RX_ER/ ETH1_MII_ RX_ER - - LCD_G4 EVENTOUT - ETH1_GMII_ TX_EN/ ETH1_MII_ TX_EN/ ETH1_RGMII_ TX_CTL/ ETH1_RMII_ TX_EN - - LCD_G5 EVENTOUT Port B PB10 PB11 - - STM32MP151A PB8 ETH1_GMII_ TXD3/ ETH1_MII_ TXD3/ ETH1_RGMII_ TXD3 Pinouts, pin description and alternate functions 104/245 Table 9. Alternate function AF8 to AF15(1) (continued) Port PB12 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS - ETH1_GMII_ TXD0/ ETH1_MII_ TXD0/ ETH1_RGMII_ TXD0/ ETH1_RMII_ TXD0 - - UART5_RX EVENTOUT - - UART5_TX EVENTOUT USART3_RX - PB13 - - - ETH1_GMII_ TXD1/ ETH1_MII_ TXD1/ ETH1_RGMII_ TXD1/ ETH1_RMII_ TXD1 PB14 - SDMMC2_D0 - - - - - EVENTOUT PB15 - SDMMC2_D1 - - - - - EVENTOUT PC0 SAI2_FS_B - QUADSPI_BK2 _NCS - - - LCD_R5 EVENTOUT PC1 - SDMMC2_CK - ETH1_MDC MDIOS_MDC - - EVENTOUT - ETH1_GMII_ TXD2/ ETH1_MII_ TXD2/ ETH1_RGMII_ TXD2 - DCMI_PIXCLK - EVENTOUT Port B Port C PC2 - - 105/245 Pinouts, pin description and alternate functions DS12500 Rev 1 AF8 STM32MP151A Table 9. Alternate function AF8 to AF15(1) (continued) Port PC3 DS12500 Rev 1 PC4 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS - ETH1_GMII_ TX_CLK/ ETH1_MII_ TX_CLK - - - EVENTOUT - ETH1_GMII_ RXD0/ ETH1_MII_ RXD0/ ETH1_RGMII_ RXD0/ ETH1_RMII_ RXD0 - - - EVENTOUT SAI4_D3 - - EVENTOUT - - - SPDIFRX_IN2 - SPDIFRX_IN3 - PC6 SDMMC1_ D0DIR SDMMC2_ D0DIR SDMMC2_D6 - SDMMC1_D6 DCMI_D0 LCD_HSYNC EVENTOUT PC7 SDMMC1_ D123DIR SDMMC2_ D123DIR SDMMC2_D7 - SDMMC1_D7 DCMI_D1 LCD_G6 EVENTOUT PC8 UART5_RTS/ UART5_DE - - - SDMMC1_D0 DCMI_D2 - EVENTOUT PC9 UART5_CTS QUADSPI_BK1 _IO0 - - SDMMC1_D1 DCMI_D3 LCD_B2 EVENTOUT Port C STM32MP151A PC5 ETH1_GMII_ RXD1/ ETH1_MII_ RXD1/ ETH1_RGMII_ RXD1/ ETH1_RMII_ RXD1 Pinouts, pin description and alternate functions 106/245 Table 9. Alternate function AF8 to AF15(1) (continued) AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS PC10 UART4_TX QUADSPI_ BK1_IO1 SAI4_MCLK_B - SDMMC1_D2 DCMI_D8 LCD_R2 EVENTOUT PC11 UART4_RX QUADSPI_ BK2_NCS SAI4_SCK_B - SDMMC1_D3 DCMI_D4 - EVENTOUT Port C PC12 UART5_TX - SAI4_SD_B - SDMMC1_CK DCMI_D9 - EVENTOUT PC13 - - - - - - - EVENTOUT PC14 - - - - - - - EVENTOUT PC15 - - - - - - - EVENTOUT Port STM32MP151A Table 9. Alternate function AF8 to AF15(1) (continued) 107/245 Pinouts, pin description and alternate functions DS12500 Rev 1 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS PD0 UART4_RX - SDMMC3_CMD DFSDM1_ DATIN7 FMC_D2/ FMC_DA2 - - EVENTOUT PD1 UART4_TX - SDMMC3_D0 DFSDM1_ CKIN7 FMC_D3/ FMC_DA3 - - EVENTOUT PD2 UART5_RX - - - SDMMC1_CMD DCMI_D11 - EVENTOUT PD3 SDMMC1_ D123DIR SDMMC2_D7 SDMMC2_ D123DIR SDMMC1_D7 FMC_CLK DCMI_D5 LCD_G7 EVENTOUT PD4 - - SDMMC3_D1 DFSDM1_ CKIN0 FMC_NOE - - EVENTOUT PD5 - - SDMMC3_D2 - FMC_NWE - - EVENTOUT PD6 - - - - FMC_NWAIT DCMI_D10 LCD_B2 EVENTOUT PD7 - SPDIFRX_IN0 SDMMC3_D3 - FMC_NE1 - - EVENTOUT PD8 - SPDIFRX_IN1 - - FMC_D13/ FMC_DA13 - LCD_B7 EVENTOUT PD9 - - - - FMC_D14/ FMC_DA14 DCMI_HSYNC LCD_B0 EVENTOUT Port DS12500 Rev 1 Port D Pinouts, pin description and alternate functions 108/245 Table 9. Alternate function AF8 to AF15(1) (continued) STM32MP151A AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS PD10 - - - - FMC_D15/ FMC_DA15 - LCD_B3 EVENTOUT PD11 - QUADSPI_ BK1_IO0 SAI2_SD_A - FMC_CLE/ FMC_A16 - - EVENTOUT PD12 - QUADSPI_ BK1_IO1 SAI2_FS_A - FMC_ALE/ FMC_A17 - - EVENTOUT PD13 - QUADSPI_ BK1_IO3 SAI2_SCK_A - FMC_A18 - - EVENTOUT PD14 UART8_CTS - - - FMC_D0/ FMC_DA0 - - EVENTOUT PD15 UART8_CTS - - - FMC_D1/ FMC_DA1 - LCD_R1 EVENTOUT Port Port D DS12500 Rev 1 109/245 Pinouts, pin description and alternate functions AF8 STM32MP151A Table 9. Alternate function AF8 to AF15(1) (continued) AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS PE0 UART8_RX - SAI2_MCLK_A - FMC_NBL0 DCMI_D2 - EVENTOUT PE1 UART8_TX - - - FMC_NBL1 DCMI_D3 - EVENTOUT FMC_A23 - - EVENTOUT Port DS12500 Rev 1 PE2 - QUADSPI_ BK1_IO2 - ETH1_GMII_ TXD3/ ETH1_MII_ TXD3/ ETH1_RGMII_ TXD3 PE3 - SDMMC2_CK - - FMC_A19 - - EVENTOUT PE4 SDMMC1_ CKIN SDMMC2_D4 - SDMMC1_D4 FMC_A20 DCMI_D4 LCD_B0 EVENTOUT PE5 SDMMC1_ D0DIR SDMMC2_D6 - SDMMC1_D6 FMC_A21 DCMI_D6 LCD_G0 EVENTOUT PE6 SDMMC1_D2 - SAI2_MCLK_B - FMC_A22 DCMI_D7 LCD_G1 EVENTOUT Port E Pinouts, pin description and alternate functions 110/245 Table 9. Alternate function AF8 to AF15(1) (continued) STM32MP151A AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS PE7 - - QUADSPI_ BK2_IO0 - FMC_D4/ FMC_DA4 - - EVENTOUT PE8 - - QUADSPI_ BK2_IO1 - FMC_D5/ FMC_DA5 - - EVENTOUT PE9 - - QUADSPI_ BK2_IO2 - FMC_D6/ FMC_DA6 - - EVENTOUT PE10 - - QUADSPI_ BK2_IO3 - FMC_D7/ FMC_DA7 - - EVENTOUT Port E PE11 - - SAI2_SD_B - FMC_D8/ FMC_DA8 DCMI_D4 LCD_G3 EVENTOUT PE12 SDMMC1_ D0DIR - SAI2_SCK_B - FMC_D9/ FMC_DA9 - LCD_B4 EVENTOUT PE13 - - SAI2_FS_B - FMC_D10/ FMC_DA10 DCMI_D6 LCD_DE EVENTOUT PE14 UART8_RTS/ UART8_DE - SAI2_MCLK_B SDMMC1_ D123DIR FMC_D11/ FMC_DA11 LCD_G0 LCD_CLK EVENTOUT PE15 UART8_CTS - FMC_NCE2 - FMC_D12/ FMC_DA12 - LCD_R7 EVENTOUT PF0 - SDMMC3_D0 SDMMC3_ CKIN - FMC_A0 - - EVENTOUT PF1 - SDMMC3_CMD SDMMC3_ CDIR - FMC_A1 - - EVENTOUT PF2 - SDMMC2_ D0DIR SDMMC3_ D0DIR SDMMC1_ D0DIR FMC_A2 - - EVENTOUT Port DS12500 Rev 1 Port F 111/245 Pinouts, pin description and alternate functions AF8 STM32MP151A Table 9. Alternate function AF8 to AF15(1) (continued) Port DS12500 Rev 1 Port F AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS FMC_A3 - - EVENTOUT - - - PF4 - SDMMC3_D1 SDMMC3_ D123DIR - FMC_A4 - - EVENTOUT PF5 - SDMMC3_D2 - - FMC_A5 - - EVENTOUT PF6 - QUADSPI_ BK1_IO3 - - SAI4_SCK_B - - EVENTOUT PF7 - QUADSPI_ BK1_IO2 - - - - - EVENTOUT PF8 - TIM13_CH1 QUADSPI_ BK1_IO0 - - - - EVENTOUT PF9 - TIM14_CH1 QUADSPI_ BK1_IO1 - - - - EVENTOUT PF10 - QUADSPI_CLK - - SAI4_D3 DCMI_D11 LCD_DE EVENTOUT PF11 - - SAI2_SD_B - - DCMI_D12 LCD_G5 EVENTOUT PF12 - - - ETH1_GMII_ RXD4 FMC_A6 - - EVENTOUT PF13 - - - ETH1_GMII_ RXD5 FMC_A7 - - EVENTOUT PF14 - - - ETH1_GMII_ RXD6 FMC_A8 - - EVENTOUT STM32MP151A PF3 ETH1_GMII_ TX_ER/ ETH1_MII_ TX_ER Pinouts, pin description and alternate functions 112/245 Table 9. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS Port F PF15 - - - ETH1_GMII_ RXD7 FMC_A9 - - EVENTOUT PG0 - - - ETH1_GMII_ TXD4 FMC_A10 - - EVENTOUT PG1 - - - ETH1_GMII_ TXD5 FMC_A11 - - EVENTOUT PG2 - - - ETH1_GMII_ TXD6 FMC_A12 - - EVENTOUT PG3 - - - ETH1_GMII_ TXD7 FMC_A13 - - EVENTOUT - ETH1_GMII_ GTX_CLK/ ETH1_RGMII_ GTX_CLK FMC_A14 - - EVENTOUT FMC_A15 - - EVENTOUT Port DS12500 Rev 1 PG4 - - Port G 113/245 PG5 - - - ETH1_GMII_ CLK125/ ETH1_RGMII_ CLK125 PG6 - - SDMMC2_CMD - - DCMI_D12 LCD_R7 EVENTOUT PG7 UART8_RTS/ UART8_DE QUADSPI_CLK - QUADSPI_ BK2_IO3 - DCMI_D13 LCD_CLK EVENTOUT PG8 USART3_RTS/ USART3_DE SPDIFRX_IN2 SAI4_FS_A ETH1_PPS_ OUT - - LCD_G7 EVENTOUT PG9 SPDIFRX_IN3 QUADSPI_ BK2_IO2 SAI2_FS_B - FMC_NCE/ FMC_NE2 DCMI_VSYNC LCD_R1 EVENTOUT Pinouts, pin description and alternate functions AF8 STM32MP151A Table 9. Alternate function AF8 to AF15(1) (continued) Port PG10 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS UART8_CTS LCD_G3 SAI2_SD_B QUADSPI_ BK2_IO2 FMC_NE3 DCMI_D2 LCD_B2 EVENTOUT - DCMI_D3 LCD_B3 EVENTOUT DS12500 Rev 1 SPDIFRX_IN0 - - PG12 SPDIFRX_IN1 LCD_B4 SAI4_SCK_A ETH1_PHY_ INTN FMC_NE4 - LCD_B1 EVENTOUT SAI4_MCLK_A ETH1_GMII_ TXD0/ ETH1_MII_ TXD0/ ETH1_RGMII_ TXD0/ ETH1_RMII_ TXD0 FMC_A24 - LCD_R0 EVENTOUT SAI4_SD_A ETH1_GMII_ TXD1/ ETH1_MII_ TXD1/ ETH1_RGMII_ TXD1/ ETH1_RMII_ TXD1 FMC_A25 - LCD_B0 EVENTOUT Port G PG13 PG14 - - - QUADSPI_ BK2_IO3 STM32MP151A PG11 ETH1_GMII_ TX_EN/ ETH1_MII_ TX_EN/ ETH1_RGMII_ TX_CTL/ ETH1_RMII_ TX_EN Pinouts, pin description and alternate functions 114/245 Table 9. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS - - SDMMC3_CK - - DCMI_D13 - EVENTOUT PH0 - - - - - - - EVENTOUT PH1 - - - - - - - EVENTOUT PH2 - QUADSPI_ BK2_IO0 SAI2_SCK_B ETH1_GMII_ CRS/ ETH1_MII_CRS - - LCD_R0 EVENTOUT PH3 - QUADSPI_ BK2_IO1 SAI2_MCLK_B ETH1_GMII_ COL/ ETH1_MII_COL - - LCD_R1 EVENTOUT PH4 - LCD_G5 - - - - LCD_G4 EVENTOUT PH5 - - - - SAI4_SD_B - - EVENTOUT - ETH1_GMII_ RXD2/ ETH1_MII_ RXD2/ ETH1_RGMII_ RXD2 MDIOS_MDIO DCMI_D8 - EVENTOUT MDIOS_MDC DCMI_D9 - EVENTOUT - DCMI_HSYNC LCD_R2 EVENTOUT Port Port G PG15 DS12500 Rev 1 Port H PH6 - - PH7 - - - ETH1_GMII_ RXD3/ ETH1_MII_ RXD3/ ETH1_RGMII_ RXD3 PH8 - - - - 115/245 Pinouts, pin description and alternate functions AF8 STM32MP151A Table 9. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS PH9 - - - - - DCMI_D0 LCD_R3 EVENTOUT PH10 - - - - - DCMI_D1 LCD_R4 EVENTOUT PH11 - - - - - DCMI_D2 LCD_R5 EVENTOUT Port H PH12 - - - - - DCMI_D3 LCD_R6 EVENTOUT PH13 UART4_TX - - - - - LCD_G2 EVENTOUT PH14 UART4_RX - - - - DCMI_D4 LCD_G3 EVENTOUT PH15 - - - - - DCMI_D11 LCD_G4 EVENTOUT PI0 - - - - - DCMI_D13 LCD_G5 EVENTOUT PI1 - - - - - DCMI_D8 LCD_G6 EVENTOUT PI2 - - - - - DCMI_D9 LCD_G7 EVENTOUT PI3 - - - - - DCMI_D10 - EVENTOUT PI4 - - SAI2_MCLK_A - - DCMI_D5 LCD_B4 EVENTOUT PI5 - - SAI2_SCK_A - - DCMI_VSYNC LCD_B5 EVENTOUT PI6 - - SAI2_SD_A - - DCMI_D6 LCD_B6 EVENTOUT PI7 - - SAI2_FS_A - - DCMI_D7 LCD_B7 EVENTOUT PI8 - - - - - - - EVENTOUT PI9 UART4_RX - - - - - LCD_VSYNC EVENTOUT PI10 USART3_CTS/ USART3_NSS - ETH1_GMII_ RX_ER/ ETH1_MII_ RX_ER - - LCD_HSYNC EVENTOUT Port DS12500 Rev 1 Port I - STM32MP151A AF8 Pinouts, pin description and alternate functions 116/245 Table 9. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS PI11 - LCD_G6 - - - - - EVENTOUT PI12 - - - - - - LCD_HSYNC EVENTOUT PI13 - - - - - - LCD_VSYNC EVENTOUT PI14 - - - - - - LCD_CLK EVENTOUT PI15 - LCD_G2 - - - - LCD_R0 EVENTOUT PJ0 - LCD_R7 - - - - LCD_R1 EVENTOUT PJ1 - - - - - - LCD_R2 EVENTOUT PJ2 - - - - - - LCD_R3 EVENTOUT PJ3 - - - - - - LCD_R4 EVENTOUT PJ4 - - - - - - LCD_R5 EVENTOUT PJ5 - - - - - - LCD_R6 EVENTOUT PJ6 - - - - - - LCD_R7 EVENTOUT PJ7 - - - - - - LCD_G0 EVENTOUT PJ8 UART8_TX - - - - - LCD_G1 EVENTOUT PJ9 UART8_RX - - - - - LCD_G2 EVENTOUT PJ10 - - - - - - LCD_G3 EVENTOUT PJ11 - - - - - - LCD_G4 EVENTOUT PJ12 - LCD_G3 - - - - LCD_B0 EVENTOUT PJ13 - LCD_G4 - - - - LCD_B1 EVENTOUT PJ14 - - - - - - LCD_B2 EVENTOUT Port Port I DS12500 Rev 1 Port J 117/245 Pinouts, pin description and alternate functions AF8 STM32MP151A Table 9. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI6/SAI2/ USART3/ UART4/5/8/ SDMMC1/2/ SPDIFRX TIM13/14/ QUADSPI/ SDMMC2/3/ LCD/SPDIFRX SAI2/4/ QUADSPI/ FMC/ SDMMC2/3/ OTG_FS/ OTG_HS DFSDM1/ QUADSPI/ SDMMC1/ MDIOS/ETH1 SAI4/UART5/ FMC/SDMMC1/ MDIOS UART7/DCMI/ LCD/RNG UART5/LCD SYS PJ15 - - - - - - LCD_B3 EVENTOUT PK0 - - - - - - LCD_G5 EVENTOUT PK1 - - - - - - LCD_G6 EVENTOUT PK2 - - - - - - LCD_G7 EVENTOUT PK3 - - - - - - LCD_B4 EVENTOUT PK4 - - - - - - LCD_B5 EVENTOUT PK5 - - - - - - LCD_B6 EVENTOUT PK6 - - - - - - LCD_B7 EVENTOUT PK7 - - - - - - LCD_DE EVENTOUT PZ0 SPI6_SCK - - - - - - EVENTOUT PZ1 SPI6_MISO - - - - - - EVENTOUT PZ2 SPI6_MOSI - - - - - - EVENTOUT PZ3 SPI6_NSS - - - - - - EVENTOUT PZ4 - - - - - - - EVENTOUT PZ5 - - - - - - - EVENTOUT PZ6 - - - - - - - EVENTOUT PZ7 - - - - - - - EVENTOUT Port Port J Port K DS12500 Rev 1 Port Z 1. Refer to Table 8 for AF0 to AF7. STM32MP151A AF8 Pinouts, pin description and alternate functions 118/245 Table 9. Alternate function AF8 to AF15(1) (continued) STM32MP151A 5 Memory mapping Memory mapping Refer to the product line reference manual for details on the memory mapping as well as the boundary addresses for all peripherals. DS12500 Rev 1 119/245 119 Electrical characteristics STM32MP151A 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of junction temperature, supply voltage and frequencies by tests in production on 100% of the devices with an junction temperature at TJ = 25 C and TJ = TJmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 6.1.2 Typical values Unless otherwise specified, typical data are based on TJ = 25 C, VDD = 3.3 V, VDDCORE = 1.2 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Figure 9. Pin loading conditions Figure 10. Pin input voltage Device pin Device pin VIN C = 50 pF MSv47493V1 120/245 DS12500 Rev 1 MSv47494V1 STM32MP151A 6.1.6 Electrical characteristics Power supply scheme USB HS PHY VSS VDD3V3_USBFS VDD VDDA1V8_REG VSS_USBHS VDD 1V1 regulator VDD3V3_USBHS VDDQ_DDR DDR PHY VSS USB FS IOs 1V8 regulator VSS VSS Core domain IOs Level shifter VDDCORE VSS IOports VDDA1V1_REG Figure 11. Power supply scheme IO logic (MPU, peripherals, RAM) (MCU, peripherals, RAM) (System logic, Peripherals) VDD (VDD_ANA) VDD IOports VBAT VDD IOs IO logic HSI, CSI, HSE, LSI, WKUP, IWDG VSW domain VSS Retention domain Retention VRET regulator Power switch VSW Power switch VDD_PLL VSS_PLL Backup domain Backup VBKP regulator PLLs VDD domain Retention RAM Backup RAM IOports VDDA BKUP IOs IO logic VSS Analog domain REF_BUF VREF+ VREFVSSA LSE, RTC, AWU, Tamper, backup registers, Reset VSS ADC, DAC VREF+ VREF- MSv46560V3 Caution: Each power supply pair (VDD/VSS, VDDCORE/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic capacitors. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. DS12500 Rev 1 121/245 228 Electrical characteristics STM32MP151A The number of needed capacitances and their values are provided in AN5031 "Getting started with STM32MP1 Series hardware development" available from the ST website www.st.com. 6.1.7 Current consumption measurement Figure 12. Current consumption measurement scheme IDD_CORE IDD_VBAT IDD VDDCORE VBAT VDD VDDA VDD_ANA VDD_PLL MSv50921V2 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 10: Voltage characteristics, Table 11: Current characteristics, and Table 12: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand. Table 10. Voltage characteristics (1) Symbols VDDX - VSS Ratings Min Max Unit -0.3 4.0 V Min(VDD, VDDA, VDD33USB, VBAT) +4.0(3)(4) V 4.0 V Input voltage on VBUS pin 6.0 V Input voltage on any other pins 4.0 V External main supply voltage (including VDD, VDDLDO, VDDA, VDD33USB, VBAT) Input voltage on FT_xxx pins VIN(2) 122/245 Input voltage on TT_xx pins VSS - 0.3 |VDDX| Variations between different VDDX power pins of the same domain - 50 mV |VSSx-VSS| Variations between all the different ground pins - 50 mV DS12500 Rev 1 STM32MP151A Electrical characteristics 1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 47 for the maximum allowed injected current values. 3. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. 4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled. Table 11. Current characteristics Symbols Ratings Max IVDD Total current into sum of all VDD power lines (source)(1) TBD IVSS (sink)(1) TBD Total current out of sum of all VSS ground lines Maximum current into each VDD power pin IVDD (source)(1) 100 (sink)(1) 100 IVSS Maximum current out of each VSS ground pin IIO Output current sunk by any I/O and control pin I(PIN) IINJ(PIN)(3)(4) IINJ(PIN) Total output current sunk by sum of all I/Os and control Unit 20 pins(2) mA 140 Total output current sourced by sum of all I/Os and control pins(2) 140 Injected current on FT_xxx, TT_xx, RST and B pins except PA4, PA5 -5/+0 Injected current on PA4, PA5 -0/0 Total injected current (sum of all I/Os and control pins)(5) 25 1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer also to Table 10: Voltage characteristics for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 12. Thermal characteristics Symbol Ratings TSTG Storage temperature range TJ Maximum junction temperature DS12500 Rev 1 Value -65 to +150 125 Unit C 123/245 228 Electrical characteristics 6.3 STM32MP151A Operating conditions Table 13. General operating conditions Symbol Parameter Operating conditions Min. Typ Max. Unit Fmpuss_ck Cortex-A7 subsystem consumer mission profile 0 - 650 Faxiss_ck, Fhclk5, Fhclk6 Internal AXI, AHB5, AHB6 clock frequency - 0 - 266 Fmcu_ck Internal MCU AHB clock frequency - 0 - 209 Fpclk1 Internal APB1 clock frequency - 0 - 100 Fpclk2 Internal APB2 clock frequency - 0 - 100 Fpclk3 Internal APB3 clock frequency - 0 - 100 Fpclk4 Internal APB4 clock frequency - 0 - 133 Fpclk5 Internal APB5 clock frequency - 0 - 133 1.71(1)(2) - 3.6 VDD I/Os and embedded SYSCFG_IOCTRLSETR = 0 regulators (REG1V1, REG1V8) supply SYSCFG_IOCTRLSETR 0 voltage 1.71 - 2.7 VDD_ANA(3) System analog supply voltage - 1.71 - 3.6 V VDD_PLL, VDD_PLL2(4) PLL supply voltage - 1.71 - 3.6 V Run, Stop mode 1.18 1.2 1.25 VDDCORE Digital core domain supply voltage LPLV-Stop mode 0.85 0.9 1.25(5) 0 0 0.75 ADC used with VREF < 2 V 1.62 - 2 ADC used with VREF > 2 V 2 - 3.6 1.8 - 3.6 - 3.6 - 2 MHz Standby mode DAC used VREFBUF with VREF = 1.5 VDDA Analog operating voltage VREFBUF with VREF = 1.5 V and ADC used 1.8 VREFBUF with VREF = 1.8 V(7) 2.1 - 3.6 VREFBUF with VREF = 2.048 V 2.35 - 3.6 VREFBUF with VREF = 2.5 V 2.8 - 3.6 0 - 3.6 ADC, DAC, VREF not used 124/245 V(6) DS12500 Rev 1 V V V STM32MP151A Electrical characteristics Table 13. General operating conditions (continued) Symbol Parameter Operating conditions Min. Typ Max. Unit - 3.6 V VBAT Backup operating voltage 64 KB retention SRAM not used 1.2 64 KB retention SRAM used 1.4 VDD3V3_USBFS(8) USB FS I/O supply voltage USB OTG FS used 3 3.3 3.6 USB OTG FS not used 0 - 3.6 VDD3V3_USBHS(8) USBH or USB OTG HS used 3 3.3 3.6 (9) USB HS I/O supply voltage USBH and USB OTG HS not used 0 - 3.6 VDD3V3_USB(8) USB I/O supply voltage USB used 3 3.3 3.6 USB not used 0 - 3.6 DDR3 memory 1.425 1.5 1.575 DDR3L memory 1.283 1.35 1.45 LPDDR2 or LPDDR3 1.14 1.2 1.3 1.65 1.8 1.95 VDDQ_DDR (10) VDDA1V8_REG VIN DDR PHY supply voltage USB HS PHY voltage supply with 1.8 V BYPASS_REG1V8 = VDD regulator in bypass mode I/O Input voltage V V V V TTxa I/O -0.3 VDD+0.3 VBUS I/O -0.3 6 DDR I/O -0.3 VDDQ_DDR -1 5.25 -0.3 See(11) -40 125 USB HS I/O All I/O except TTxa TJ V Junction temperature Suffix 3 version range V oC 1. Once nRST is released functionality is guaranteed down to VBOR falling edge max. 2. Min VDD is 2.25 V when REG1V8 is used BYPASS_REG1V8 = 0. 3. Should be connected to same power supply voltage as VDD. 4. It is recommended to connect VDD_PLL and VDD_PLL2 to same power supply as VDD. 5. 1.25 V is the max allowed voltage, however LPLV-Stop mode is only relevant for VDDCORE up to 0.95 V. In LPLV-Stop mode, if VDDQ_DDR is not shutdown, to avoid overconsumption on VDDQ_DDR, the DDR memory must be put in SelfRefresh and DDR PHY must be set in retention mode (setting bit DDRRETEN: DDR retention enable of PWR control register 3 (PWR_CR3)). 6. DAC cannot be used with VREF below 1.8 V. 7. ADC cannot be used with VREF below 2 V and VDDA above 2 V. 8. Depending on package selected, either VDD3V3_USBFS and VDD3V3_USBHS or only VDD3V3_USB are available. 9. For operation with voltage higher than Min (VDD, VDDA, VDD3V3_USBFS) +0.3 V, the internal Pull-up and Pull-Down resistors must be disabled. 10. Independent from any other supply. 11. Min(VDD, VDDA, VDD3V3_USBFS) +3.6 V < 5.5 V. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. DS12500 Rev 1 125/245 228 Electrical characteristics STM32MP151A 6.3.1 General operating conditions 6.3.2 Operating conditions at power-up / power-down Subject to general operating conditions. Table 14. Operating conditions at power-up / power-down Symbol tVDD(1) tVDDA Parameter Min Max VDD rise time rate 0 VDD fall time rate 10 VDDA rise time rate 0 VDDA fall time rate 10 0 10 tVDD3V3_USB(2) VDD3V3_USBxx rise time rate tVDD3V3_USBHS VDD3V3_USBxx fall time rate tVDD3V3_USBFS tVDDCORE VDDCORE rise time rate (from reset to RUN mode) 2000(3) VDDCORE rise time rate (from LPLV-Stop to RUN mode) 1000(4) VDDCORE fall time rate 7.33 Unit s/V 1. VDD must be present before VDDCORE . 2. VDDA1V8_REG must be present before VDD3V3_USBHS. 3. In case VDDCORE rise time is larger than 2 ms/V, user should control the NRST_CORE signal with a Power Good (PG) control signal from the external regulator to avoid dysfunction of the device due to VDDCORE potentially not yet established when internal reset signal is de-activated after tVDDCORETEMPO (cf.Table 14 and Figure 13). 4. In case VDDCORE rise time at exit of LPLV-Stop is larger than 1 ms/V, there is a risk of unwanted reset due to VDDCORE potentially not yet established after tSEL_VDDCORETEMPO (cf.Table 14 and Figure 14). In such a case, the VDDCORE supply should not be decreased during LPLV-Stop mode. 126/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Figure 13. VDDCORE rise time from reset average rise time rate should be less than tVDDCORE Max (from reset to Run mode) VDDCORE V VDDCORE should be above VDDCORE_ok Min when vddcore_ok is enabled VDDCORE_ok Min VPVDCORE_0 (rising edge) t tVDDCORETEMPO pvdcore_out Run mode vddcore_ok VDDCORE_ok Min = VPVDCORE_0 Min (rising edge) + tVDDCORETEMPO Min / tVDDCORE Max MSv47497V1 Figure 14. VDDCORE rise time from LPLV-Stop average rise time rate should be less than tVDDCORE Max (from LPLV-Stop to Run mode) VDDCORE V VDDCORE should be above VDDCORE_ok Min at the end of tSEL_VDDCORETEMPO VDDCORE_ok Min VPVDCORE_1 (falling edge) t tSEL_VDDCORETEMPO PWR_LP LPLVStop mode Wait Run mode VDDCORE_ok Min = VPVDCORE_1 Min (falling edge) + tVSEL_VDDCORETEMPO Min / tVDDCORE Max MSv47499V1 DS12500 Rev 1 127/245 228 Electrical characteristics 6.3.3 STM32MP151A Embedded reset and power control block characteristics The parameters given in Table 15 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 13: General operating conditions. Table 15. Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit - - 377 550 s Rising edge 1.62 1.67 1.71 Falling edge 1.58 1.63 1.67 Rising edge 2.055 2.1 2.145 Falling edge 1.955 2 2.045 Rising edge 2.355 2.4 2.445 Falling edge 2.255 2.3 2.345 Rising edge 2.655 2.7 2.745 Falling edge 2.555 2.6 2.645 tRSTTEMPO(1) Reset temporization. after BOR0 released VBOR0(1) Brown-out reset threshold 0 VBOR1 Brown-out reset threshold 1 VBOR2 Brown-out reset threshold 2 VBOR3 Brown-out reset threshold 3 VPVD0 Programmable Voltage Detector threshold 0 Rising edge 1.905 1.95 1.995 Falling edge 1.805 1.85 1.895 VPVD1 Programmable Voltage Detector threshold 1 Rising edge 2.055 2.1 2.145 Falling edge 1.955 2 2.045 VPVD2 Programmable Voltage Detector threshold 2 Rising edge 2.205 2.25 2.295 Falling edge 2.105 2.15 2.195 VPVD3 Programmable Voltage Detector threshold 3 Rising edge 2.355 2.4 2.445 Falling edge 2.255 2.3 2.345 VPVD4 Programmable Voltage Detector threshold 4 Rising edge 2.505 2.55 2.595 Falling edge 2.405 2.45 2.495 VPVD5 Programmable Voltage Detector threshold 5 Rising edge 2.655 2.7 2.745 Falling edge 2.555 2.6 2.645 Rising edge 2.805 2.85 2.895 VPVD6 Programmable Voltage Detector threshold 6 Falling edge in RUN mode 2.705 2.75 2.795 Vhyst_BOR0 Hysteresis voltage of BOR0 Hysteresis in RUN mode - 40 - mV Vhyst_BOR Hysteresis voltage of BOR Unless BOR0 - 100 - mV Vhyst_BOR_PVD Hysteresis voltage of BOR (unless BOR0) and PVD(2) Hysteresis in RUN mode - 100 - mV IDD_BOR_PVD(1)(3) BOR (unless BOR0) and PVD consumption from VDD 0.246 - 0.626 A 128/245 DS12500 Rev 1 V V V V V V V V V V V STM32MP151A Electrical characteristics Table 15. Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit VAVM_0 Analog voltage (VDDA) detector Rising edge threshold 0 Falling edge 1.655 1.7 1.745 1.555 1.6 1.645 VAVM_1 Analog voltage (VDDA) detector Rising edge threshold 1 Falling edge 2.055 2.1 2.145 1.955 2 2.045 VAVM_2 Analog voltage (VDDA) detector Rising edge threshold 2 Falling edge 2.455 2.5 2.545 2.355 2.4 2.445 VAVM_3 Analog voltage (VDDA) detector Rising edge threshold 3 Falling edge 2.755 2.8 2.845 2.655 2.7 2.745 Vhyst_VDDA Hysteresis of analog voltage (VDDA) detector - - 100 - mV IVDD_AVM(1) Analog Voltage Monitoring (VDDA) consumption on VDD - 0.123 - 0.248 A IVDDA_AVM(1) Analog Voltage Monitoring (VDDA) consumption on VDDA Resistor bridge 1.07 2.12 2.49 A VPVDCORE_0(4) Digital core domain supply voltage (VDDCORE) detector threshold 0 (Run) Rising edge 0.95 0.995 1.04 Falling edge 0.91 0.955 1 VPVDCORE_1(5) Digital core domain supply voltage (VDDCORE) detector threshold 1 (LPLV_Stop) Falling edge 0.71 0.755 0.8 V Vhyst_VDDCORE Hysteresis of Digital core domain supply voltage (VDDCORE) detector - - 40 - mV tVDDCORETEMPO Tempo on VPVDCORE_0 at rising edge of VDDCORE to ensure that VDDCORE is fully established - 200 340 550 s Tempo on VPVDCORE_1 at rising edge of VDDCORE to ensure that VDDCORE is fully established on exit of LPLV-Stop mode - 234 380 606 s IVDD_VDDCOREVM VDDCORE Voltage Monitoring (1) consumption on VDD - 1.7 2.6 4.2 A USB_VTH - - 1.21 - V tSEL_VDDCORETE MPO USB Threshold voltage V V V V V 1. Guaranteed by design. 2. No hysteresis when using PVD_IN pin. 3. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables. 4. During the first rising edge of VDDCORE, the slope should be less than 2 ms/V to ensure VDDCORE is fully established before the end of the tVDDCORETEMPO. 5. When exiting from LPLV-STOP mode to RUN mode the rising slope for VDDCORE should be less than 1 ms/V to ensure VDDCORE is fully established before the end of the tVDDCORETEMPO. DS12500 Rev 1 129/245 228 Electrical characteristics 6.3.4 STM32MP151A Embedded reference voltage The parameters given in Table 16, Table 17 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 13: General operating conditions. Table 16. Embedded reference voltage Symbol Parameter Conditions -40 C < TJ < 125 C Min Typ Max Unit 1.175 1.210 1.241 V VREFINT Internal reference voltages tS_vrefint(1)(2) ADC sampling time when reading the internal reference voltage - 4.3 - - tS_vbat(1) VBAT sampling time when reading the internal VBAT reference voltage - 9.8 - - tstart_vrefint Start time of reference voltage buffer when ADC is enable - 0.8 - 4.6 Irefbuf(2) Reference Buffer consumption VDDA = 3.3 V for ADC 9.1 13.6 27.7 A VREFINT(2) Internal reference voltage spread over the temperature range -40 C < TJ < 125 C - 4.3 15 mV Tcoeff_VREFINT Average temperature coefficient Average temperature coefficient - 19 67 ppm/C Acoeff Long term stability 1000 hours, T = 25 C TBD TBD TBD ppm/C VDDcoeff Average Voltage coefficient 3.0 V < VDD < 3.6 V - 10 1370 ppm/V 1. The shortest sampling time for the application can be determined by multiple iterations. 2. Guaranteed by design. s Table 17. Embedded reference voltage calibration value Symbol VREFIN_CAL Parameter Raw data acquired at temperature of 30 C, VDDA = VREF+ = 3.3 V 1. Mandatory to read in 32-bits word and do relevant mask and shift to isolate required bits. 2. These address is inside BSEC which should be enabled in RCC to allow access. 130/245 DS12500 Rev 1 Memory address 0x5C00 5250[31:16](1)(2) STM32MP151A 6.3.5 Electrical characteristics Embedded regulators characteristics The parameters given in Table 18, Table 19 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 13: General operating conditions. REG1V1 embedded regulator (USB_PHY) Table 18. REG1V1 embedded regulator (USB_PHY) characteristics Symbol Condition Min Typ Max Unit Regulated output voltage - 1.045 1.1 1.155 V CL Load Capacitor - 1.1 2.2(1) 3.3 F esr Equivalent Serial Resistor of Cload - 0.1 25 600 m - 0 - 30 mA CL=2.2uF - 93 - CL=3.3uF - VDDA1V1_ REG Parameter current(2) Iload Static load tSTART Start-up time. from PWR_CR3.REG11EN = 1 to PWR_CR3.REG11RDY = 1 IINRUSH VDD Inrush Current to load external capacitor at start IVDD(3) Regulator Current consumption on VDD - 180 - 50 60 Regulator Enabled and Iload = 0 mA - 150 205 Regulator Enabled and Iload = 30 mA - 176 242 s mA A 1. For better dynamic performances a 2.2 F typical value external capacitor is recommended. 2. Load is for internal STM32MP151A analog blocks, no additional external load is accepted unless mentioned. 3. Guaranteed by design. REG_1V8 embedded regulator (USB) Table 19. REG_1V8 embedded regulator (USB) characteristics Symbol Parameter VDD Regulator input voltage VDDA1V8_ Regulated output voltage REG CL Load Capacitor esr Equivalent Serial Resistor of Cload Condition Min Typ Max Unit - 2.25 3.3 3.6 V 1.7 1.8 1.9 V - 0.5 2.2(1) 3.3 F - 0.1 25 600 m - - - 70 mA CL=2.2uF - 81 CL=3.3uF - after trimming (2) Iload Static load current tSTART Start-up time. from PWR_CR3.REG11EN = 1 to PWR_CR3.REG11RDY = 1 IINRUSH VDD Inrush Current to load external capacitor at start - DS12500 Rev 1 - 150 80 100 s mA 131/245 228 Electrical characteristics STM32MP151A Table 19. REG_1V8 embedded regulator (USB) characteristics (continued) Symbol IVDD(3) Parameter Regulator Current consumption on VDD Condition Min Typ Max Regulator Enabled and Iload = 0 mA - 130 181 Regulator Enabled and Iload = 70 mA - Unit A 170 231 1. For better dynamic performances a 2.2 F typical value external capacitor is recommended. 2. Load is for internal STM32MP151A analog blocks, no additional external load is accepted unless mentioned. 3. Guaranteed by design. 6.3.6 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 12: Current consumption measurement scheme. All the Run mode current consumption measurements given in this section are performed with a CoreMark code unless otherwise specified. Typical and maximum current consumption The device is placed under the following conditions: * All I/O pins are in analog input mode except when explicitly mentioned. * All peripherals are disabled except when explicitly mentioned. * The maximum values are obtained for VDD/VBAT = 3.6 V and VDDCORE = 1.25 V, and the typical values for VDD/VBAT = 3.3 V and VDDCORE = 1.2 V unless otherwise specified. The parameters given in Table 21 to Table 25 are derived from tests performed under supply voltage conditions summarized in Table 13: General operating conditions. 132/245 DS12500 Rev 1 Conditions Symbol Parameter - MPU SS mode Oscillator MPU clk (MHz) MCU clk (MHz) All peripherals CRun enabled Supply IDDCORE current in Run mode All peripherals CRun enabled CRun CStop HSE+HSI+LSI+PLL HSE+HSI+LSI+PLL Tj = 25 C Tj = 55 C Tj = 85 C 330 TBD TBD TBD TBD TBD 325 TBD TBD TBD TBD TBD 400 295 TBD TBD TBD TBD TBD 648 320 TBD TBD TBD TBD TBD 310 TBD TBD TBD TBD TBD 285 TBD TBD TBD TBD TBD 600 600 209 209 400 DS12500 Rev 1 All peripherals CRun disabled CStop Max Tj = 25 C 648 Supply IDDCORE current in Run mode Supply IDDCORE current in Run mode MCU SS mode Typ Tj = Tj = 105 C 125 C 648 - 180 TBD TBD TBD TBD TBD HSE+HSI+PLL 600 - 175 TBD TBD TBD TBD TBD HSE+HSI+PLL 300 - 135 TBD TBD TBD TBD TBD HSE+HSI+PLL 150 - 92.0 TBD TBD TBD TBD TBD HSE+HSI+PLL 64 - 65.5 TBD TBD TBD TBD TBD HSE+HSI+PLL 24 - 51.5 TBD TBD TBD TBD TBD HSE+HSI 24 - 35.5 TBD TBD TBD TBD TBD HSI+PLL 64 - 65.0 - - - - - HSI+PLL 24 - 51.5 - - - - - HSI 64 - 49.0 - - - - - mA mA mA 133/245 Electrical characteristics HSE+HSI+PLL Unit STM32MP151A Table 20. Current consumption (IDDCORE) in Run mode(1) Conditions Symbol Parameter - Supply IDDCORE current in Run mode MPU in CSleep with WFI (CLK OFF). All peripherals disabled MPU SS mode CSleep MCU SS mode CStop Typ Max DS12500 Rev 1 MPU clk (MHz) MCU clk (MHz) Tj = 25 C Tj = 25 C Tj = 55 C Tj = 85 C HSE+HSI+PLL 648 - 110 TBD TBD TBD TBD TBD HSE+HSI+PLL 600 - 110 TBD TBD TBD TBD TBD HSE+HSI+PLL 300 - 100 TBD TBD TBD TBD TBD HSE+HSI+PLL 150 - 73.5 TBD TBD TBD TBD TBD HSE+HSI+PLL 64 - 57.0 TBD TBD TBD TBD TBD HSE+HSI+PLL 24 - 48.5 TBD TBD TBD TBD TBD HSE+HSI 24 - 32.5 TBD TBD TBD TBD TBD HSI+PLL 64 - 57.5 - - - - - HSI+PLL 24 - 48.5 - - - - - HSI 64 - 41.5 - - - - - Oscillator Tj = Tj = 105 C 125 C Unit Electrical characteristics 134/245 Table 20. Current consumption (IDDCORE) in Run mode(1) (continued) mA STM32MP151A Conditions Symbol Parameter - DS12500 Rev 1 Supply IDDCORE current in Run mode MPU SS mode All peripherals CStop disabled MCU SS mode CRun Typ Max MPU clk (MHz) MCU clk (MHz) Tj = 25 C Tj = 25 C Tj = 55 C Tj = 85 C HSE+HSI+PLL - 209 71.0 TBD TBD TBD TBD TBD HSE+HSI+PLL - 100 52.5 TBD TBD TBD TBD TBD HSE+HSI+PLL - 64 59.5 TBD TBD TBD TBD TBD HSE+HSI+PLL - 24 53.0 TBD TBD TBD TBD TBD HSE+HSI+PLL - 10 38.5 TBD TBD TBD TBD TBD HSE+HSI+PLL - 4 37.5 TBD TBD TBD TBD TBD HSE+HSI - 24 27.0 TBD TBD TBD TBD TBD HSI+PLL - 64 59.5 - - - - - HSI+PLL - 24 53.0 - - - - - HSI - 64 33.0 - - - - - CSI+HSI+PLL - 64 59.5 - - - - - CSI+HSI+PLL - 24 53.0 - - - - - CSI+HSI+PLL - 4 37.5 - - - - - CSI+HSI - 4 23.5 - - - - - Oscillator Tj = Tj = 105 C 125 C Unit STM32MP151A Table 20. Current consumption (IDDCORE) in Run mode(1) (continued) mA Electrical characteristics 135/245 Conditions Symbol Parameter - DS12500 Rev 1 Supply IDDCORE current in Run mode MCU in CSleep with WFI (CLK OFF). All peripherals disabled MPU SS mode CStop MCU SS mode CSleep Typ Max MPU clk (MHz) MCU clk (MHz) Tj = 25 C Tj = 25 C Tj = 55 C Tj = 85 C HSE+HSI+PLL - 209 60.0 TBD TBD TBD TBD TBD HSE+HSI+PLL - 100 47.5 TBD TBD TBD TBD TBD HSE+HSI+PLL - 64 56.0 TBD TBD TBD TBD TBD HSE+HSI+PLL - 24 52.0 TBD TBD TBD TBD TBD HSE+HSI+PLL - 10 38.0 TBD TBD TBD TBD TBD HSE+HSI+PLL - 4 37.5 TBD TBD TBD TBD TBD HSE+HSI - 24 25.5 TBD TBD TBD TBD TBD HSI+PLL - 64 56.0 - - - - - HSI+PLL - 24 51.5 - - - - - HSI - 64 30.5 - - - - - CSI+HSI+PLL - 64 56.0 - - - - - CSI+HSI+PLL - 24 51.5 - - - - - CSI+HSI+PLL - 4 37.0 - - - - - CSI+HSI - 4 23.5 - - - - - Oscillator Tj = Tj = 105 C 125 C Unit Electrical characteristics 136/245 Table 20. Current consumption (IDDCORE) in Run mode(1) (continued) mA 1. HSE = 24 MHz, AXI clk (Faxiss_ck) = Max(Fmpuss_ck, 264). Table 21. Current consumption (IDD) in Run mode(1) Conditions Parameter MPU SS mode IDD Supply current in Run mode CRun MCU SS mode CRun Max Oscillator Tj = 25 C Tj = 25 C Tj = 55 C Tj = 85 C HSE+HSI+LSI+PLL1,2,3,4 3.95 TBD TBD TBD Tj = Tj = 105 C 125 C TBD TBD Unit mA STM32MP151A Symbol Typ Conditions Symbol Parameter MPU SS mode IDD Supply current in Run mode CRun MCU SS mode CStop Typ Max Tj = 25 C Tj = 25 C Tj = 55 C Tj = 85 C HSI+PLL1,2 3.00 TBD TBD TBD TBD TBD HSE+HSI 1.75 TBD TBD TBD TBD TBD HSI 1.25 TBD TBD TBD TBD TBD Oscillator Tj = Tj = 105 C 125 C Unit STM32MP151A Table 21. Current consumption (IDD) in Run mode(1) (continued) mA 1. HSE = 24 MHz. Table 22. Current consumption in Stop mode(1) Conditions DS12500 Rev 1 Symbol Parameter - IDD Supply current in Stop mode IDDCORE MCU SS mode Max Tj = 25 C Tj = 55 C Tj = 85 C Tj = 105 C Tj = 125 C Tj = 25 C Tj = 55 C Tj = 85 C Tj = Tj = 105 C 125 C All peripherals disabled CStop CStop 980 980 985 985 995 TBD TBD TBD TBD TBD All peripherals disabled CStandby CStop 980 980 985 985 995 TBD TBD TBD TBD TBD All peripherals disabled CStop CStop 19000 42000 89500 150000 230000 TBD TBD TBD TBD TBD All peripherals disabled CStandby CStop 18500 42000 89000 150000 225000 TBD TBD TBD TBD TBD Unit A 137/245 Electrical characteristics 1. HSE = 24 MHz. MPU SS mode Typ Typ(2) Conditions Symbol Parameter - IDD Supply current in LPLV-Stop mode IDDCORE MPU SS mode MCU SS mode Tj = 25 C Tj = 55 C Tj = 85 C Max(3) Tj = Tj = 105 C 125 C Tj = 25 C Tj = 55 C Tj = 85 C Tj = Tj = 105 C 125 C All Peripheral disabled CStop CStop 980 980 985 985 995 TBD TBD TBD TBD TBD All Peripheral disabled CStandby CStop 980 980 985 985 995 TBD TBD TBD TBD TBD All Peripheral disabled CStop CStop 6950 17000 39000 67500 105000 TBD TBD TBD TBD TBD All Peripheral disabled CStandby CStop 6950 17000 39000 67500 110000 TBD TBD TBD TBD TBD Unit Electrical characteristics 138/245 Table 23. Current consumption in LPLV-Stop mode(1) A DS12500 Rev 1 1. HSE = 24 MHz. 2. VDDCORE = 0.9 V. 3. VDDCORE = 0.95 V. STM32MP151A Conditions Tj = 25 C Tj = 55 C Tj = 85 C Backup SRAM OFF, RTC Retention CStandby CStop OFF, RAM LSE OFF OFF 2.10 2.25 4.00 7.60 11.0 16.5 38.5 96.0 175 460 - IDD Max MCU SS mode Symbol Parameter Supply current in Standby mode Typ MPU SS mode DS12500 Rev 1 Backup CStandby CStop SRAM ON, RTC ON, LSE Retention CStandby CStop ON, RAM ON mediu m_high drive Tj = Tj = 105 C 125 C Tj = 25 C Tj = 55 C Tj = 85 C Tj = Tj= 105 C 125 C 16.5 - - - - - 64.5 105 - - - - - 800 1300 - - - - - Unit STM32MP151A Table 24. Current consumption in Standby mode(1) A 1. IWDG OFF, LSI OFF, VDDCORE = 0 V. Electrical characteristics 139/245 Conditions Symbol Parameter - Backup SRAM OFF, RTC OFF, LSE OFF DS12500 Rev 1 Backup SRAM Supply OFF, RTC ON,. IDDVBAT current in LSE ON, VBAT mode medium_high drive Backup SRAM ON, RTC ON,. LSE ON, high drive Retention RAM OFF Typ Max VBAT (V) Tj = 25 C Tj = 55 C Tj = 85 C Tj = Tj = 105 C 125 C Tj = 25 C Tj = 55 C Tj = 85 C 1.6 0.007 0.022 0.130 0.395 2.4 0.008 0.024 0.140 3 0.012 0.032 3.3 0.041 3.6 Tj = Tj = 105 C 125 C 1.10 - - - - - 0.420 1.15 - - - - - 0.170 0.490 1.30 - - - - - 0.100 0.520 1.45 3.90 - - - - - 0.073 0.150 0.620 1.65 4.20 - - - - - 1.6 7.80 14.0 32.5 54.5 88.5 - - - - - 2.4 8.35 14.5 33.5 55.5 89.0 - - - - - 3 8.75 15.0 34.5 57.5 92.0 - - - - - 3.3 9.15 15.5 35.5 59.5 96.0 - - - - - 3.6 9.95 16.0 36.5 61.0 98.0 - - - - - 1.6 7.90 14.5 32.0 55.5 90.0 - - - - - 2.4 8.50 15.0 33.0 57.0 91.0 - - - - - 3 9.15 16.0 34.5 58.5 93.5 - - - - - 3.3 8.85 16.5 35.5 61.0 98.0 - - - - - 3.6 10.0 17.0 36.5 62.5 100 - - - - - Unit Electrical characteristics 140/245 Table 25. Current consumption in VBAT mode A STM32MP151A Conditions Symbol Parameter - Supply IDDVBAT current in VBAT mode Backup SRAM ON, RTC ON,. LSE ON, medium_high drive Retention RAM ON DS12500 Rev 1 Backup SRAM ON, RTC ON, LSE ON, high drive Typ Max VBAT (V) Tj = 25 C Tj = 55 C Tj = 85 C Tj = Tj = 105 C 125 C Tj = 25 C Tj = 55 C Tj = 85 C 1.6 74.0 165 415 770 2.4 76.5 170 415 3 86.5 175 3.3 79.0 3.6 Tj = Tj = 105 C 125 C 1250 - - - - - 775 1250 - - - - - 425 795 1300 - - - - - 175 430 805 1300 - - - - - 84.0 175 440 820 1350 - - - - - 1.6 74.0 165 415 780 1300 - - - - - 2.4 75.5 170 420 780 1300 - - - - - 3 78.5 180 430 800 1300 - - - - - 3.3 79.5 180 440 810 1350 - - - - - 3.6 80.0 180 445 825 1350 - - - - - Unit STM32MP151A Table 25. Current consumption in VBAT mode (continued) A Electrical characteristics 141/245 Electrical characteristics STM32MP151A I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate a current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 48: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. An additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid a current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption The I/Os used by an application contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin. The theoretical formula is provided below: I SW = V DDx x f SW x C L where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDx is the MCU supply voltage fSW is the I/O switching frequency CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT 6.3.7 Wakeup time from low-power modes The wakeup times given in Table 26 are measured starting from the wakeup event trigger up to the first instruction executed by the MPU or MCU: * For SLEEP modes: - * * 142/245 the MPU or MCU goes in low-power mode after WFE (Wait For Event) instruction. For STOP modes: - MCU goes in low-power mode after WFE (Wait For Event) instruction. - MPU goes in low-power mode after WFI (Wait For Interrupt) instruction. WKUPx pin is used to wakeup from STANDBY, STOP and SLEEP modes. DS12500 Rev 1 STM32MP151A Electrical characteristics All timings are derived from tests performed under ambient temperature and VDD = 3.3 V. Table 26. Low-power mode wakeup timings Symbol Parameter Conditions (after wakeup) Typ(1) Max(1) Unit 31 TBD CPU clock cycles tWUCSLEEP_M MPU wakeup from HSE 24 MHz, SYSRAM CSleep, MCU in CSleep PU tWUCSTOP_MP U tWULPLVSTOP_MPU MPU wakeup from CStop, MCU in CStop HSI 64 MHz, SYSRAM 5.7 TBD HSE + PLL 648 MHz, SYSRAM 112 TBD MPU wakeup from CStop, MCU in CRun HSI 64 MHz, SYSRAM 0.54 TBD HSE + PLL 648 MHz, SYSRAM 0.083 TBD 410 TBD 6 TBD HSI 64 MHz, SRAM, MCTMPSKP = 1 5.3 TBD HSI 64 MHz, SRAM, MCTMPSKP = 0, PWR_LP delay = 1 ms 1.4 TBD HSI 64 MHz, SRAM 5.3 TBD MCU wakeup from CStop, HSI active HSI 64 MHz, SRAM (HSIKERON=1), MPU in CStop 0.33 TBD MCU wakeup from CStop, MPU in CRun HSI 64 MHz, SRAM 0.12 TBD MCU wakeup from STANDBY HSI 64 MHz, RETRAM 2550 TBD MPU wakeup from CStop with system in LPLV-Stop (LVDS=1), MCU in CStop tWUCSLEEP_M MCU wakeup from CSleep, MPU in CSleep CU tWULPLVSTOP_MCU tWUCSTOP_ MCU tWUCSTOP_ MCU2 tWUCSTOP_ MCU3 tWUSTANDBY_ MCU MCU wakeup from CStop with system in LPLV-Stop (LVDS=1), MPU in CStop MCU wakeup from CStop, MPU in CStop HSI 64 MHz, SYSRAM HSE 24 MHz, SRAM s CPU clock cycles s 1. Guaranteed by characterization results unless otherwise specified. Table 27. Wakeup time using USART/LPUART(1) Symbol tWUUSART tWULPUART Parameter Conditions Wakeup time needed to calculate the Stop maximum USART/LPUART baud rate allowing the wakeup from stop mode when LPLV-Stop USART/LPUART clock source is HSI. Typ Max Unit - 6.7 s - 240.7(2) s 1. Guaranteed by design. 2. Including the tSEL_VDDCORETEMPO = 234 s. DS12500 Rev 1 143/245 228 Electrical characteristics 6.3.8 STM32MP151A External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. Digital and analog bypass modes are available. The external clock signal has to respect the Table 48: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 15 for digital bypass mode and in Figure 16 for analog bypass mode. In analog bypass mode the clock can be a sinusoidal waveform. Table 28. High-speed external user clock characteristics (digital bypass)(1) Symbol fHSE_ext Parameter Min Typ Max Unit User external clock source frequency 8 25 50 MHz 0.7xVDD - VDD VSS - 0.3xVSS 7 - - VSW (VHSEH -VHSEL) OSC_IN amplitude VDC OSC_IN input voltage tW(HSE) OSC_IN high or low time V ns 1. Guaranteed by design. Figure 15. High-speed external clock source AC timing diagram (digital bypass) VHSEH 90 % 10 % VHSEL tr(HSE) tf(HSE) tW(HSE) t tW(HSE) THSE External clock source fHSE_ext IL OSC_IN STM32 ai17528b Table 29. High-speed external user clock characteristics (analog bypass)(1) Symbol fHSE_ext 144/245 Parameter Min Typ Max Unit User external clock source frequency 8 25 48 MHz duty cycle (Square wave) 45 50 55 % 20(3) % (2) duty cycle deterioration 0 10 VHSE Absolute input range 0 - VDD VPP OSC_IN peak-to-peak amplitude 0.2(4) - 0.75xVDD V tSU(5) Time to start TBD - TBD(6) s DS12500 Rev 1 STM32MP151A Electrical characteristics Table 29. High-speed external user clock characteristics (analog bypass)(1) Symbol Parameter tr/tf(HSE) Rise and Fall time (10% to 90% threshold levels of the input peak-to-peak amplitude) I(HSE) Power consumption Min Typ Max Unit TBD - TBD ns - TBD(7) TBD(8) A 1. Guaranteed by design. 2. Guaranteed by design with a square wave signal (@25 C, VDD=3.3 V /VPP = 400 mV / VDC=1 V) where VDC is the DC component of the input signal. 3. Guaranteed by design with a square wave signal (@25 C, VDD=1.6 V /VPP = 200 mV / VDC=0.8 V) where VDC is the DC component of the input signal. 4. minimum peak-to-peak amplitude (@25 C, 0.1<VDC<VDD-0.1 V) where VDC is the DC component of the input signal. 5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized analog bypass clock interface is reached. This value is measured @125 C with 200 mV peak-to-peak amplitude. 6. Maximum start-up time is obtained @125 C with 200 mV peak-to-peak amplitude. 7. with a sine wave signal (@25 C, VDD=3.3 V /VPP = 400 mV / VDC=0.4 V) where VDC is the DC component of the input signal. 8. with a sine wave signal (@125 C, VDD=3.6 V /VPP = 800 mV / VDC=1.8 V) where VDC is the DC component of the input signal. Figure 16. High-speed external clock source AC timing diagram (analog bypass) VHSE 90% VPP 10% THSE External clock source t tr(HSE) fHSE_ext OSC_IN IL STM32 MSv47498V1 Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 48: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 17. DS12500 Rev 1 145/245 228 Electrical characteristics STM32MP151A Table 30. Low-speed external user clock characteristics(1) Symbol Parameter Min Typ Max Unit kHz fLSE_ext User external clock source frequency - 32.768 1000 VLSEH OSC32_IN input pin high level voltage 0.7xVDD - VDD VLSEL OSC32_IN input pin low level voltage VSS - 0.3 VDD tw(LSEH) tw(LSEL) OSC32_IN high or low time 250 - - V ns 1. Guaranteed by design. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 17. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE External clock source fLSE_ext STM32 ai17529b High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 8 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 31. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 31. 8-48 MHz HSE oscillator characteristics(1) Symbol Parameter Operating conditions(2) Min Typ Max Unit F Oscillator frequency - 8 - 48 MHz RF Feedback resistor - - 200 - k 146/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Table 31. 8-48 MHz HSE oscillator characteristics(1) (continued) Symbol Operating conditions(2) Parameter Min Typ Max During startup - - 4 VDD = 3 V, Rm = 150 CL = 12 pF at 4 MHz - 0.35 - VDD = 3 V, Rm = 120 CL = 12 pF at 16 MHz - 0.40 - VDD = 3 V, Rm = 100 CL = 10 pF at 24 MHz - 0.45 - VDD = 3 V, Rm = 80 CL = 8 pF at 32 MHz - 0.65 - VDD = 3 V, Rm = 80 CL = 8 pF at 48 MHz - 0.95 - (3) IDD(HSE) HSE current consumption Unit mA Gmcritmax Maximum critical crystal gm Startup - - 1.5 mA/V tSU(4) Start-up time VDD is stabilized - 2 - ms 1. Guaranteed by design. 2. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 18). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. The PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 18. Typical application with a 24 MHz crystal Resonator with integrated capacitors CL1 8 MHz resonator CL2 fHSE OSC_IN REXT(1) RF OSC_OU T Bias controlled gain STM32 ai17530b 1. REXT value depends on the crystal characteristics. DS12500 Rev 1 147/245 228 Electrical characteristics STM32MP151A Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 32. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 32. Low-speed external user clock characteristics(1) Symbol F IDD Oscillator frequency LSE current consumption Maximum critical crystal Gmcritmax gm tSU(3) Operating conditions(2) Parameter Startup time Min Typ Max Unit - - 32.768 - kHz LSEDRV[1:0] = 00, Low drive capability - 290 - LSEDRV[1:0] = 01, Medium Low drive capability - 390 - LSEDRV[1:0] = 10, Medium high drive capability - 550 - LSEDRV[1:0] = 11, High drive capability - 900 - LSEDRV[1:0] = 00, Low drive capability - - 0.5 LSEDRV[1:0] = 01, Medium Low drive capability - - 0.75 LSEDRV[1:0] = 10, Medium high drive capability - - 1.7 LSEDRV[1:0] = 11, High drive capability - - 2.7 VDD is stabilized - 2 - nA A/V s 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers. 3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 k Hz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Note: 148/245 For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. DS12500 Rev 1 STM32MP151A Electrical characteristics Figure 19. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 Bias RF controlled gain 32.768 kH z resonator CL2 fLSE OSC32_IN OSC32_OU T STM32 ai17531b 1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. 6.3.9 Internal clock source characteristics The parameters given in Table 33, Table 34 and Table 35 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 13: General operating conditions. 64 MHz high-speed internal RC oscillator (HSI) Table 33. HSI oscillator characteristics(1) Symbol fHSI TRIM Parameter HSI frequency HSI user trimming step Conditions Min Typ Max Unit VDD = 3.3 V, TJ = 30 C TBD 64 TBD MHz Trimming is not a multiple of 32 TBD 0.33 TBD Trimming is 128, 256 and 384 TBD -2.43 TBD Trimming is 64, 192, 320 and 448 TBD -0.70 TBD Other trimming are a multiple of 32 (not including multiple of 64 and 128) TBD -0.30 TBD 45 - 55 % VDD = 1.71 to 3.6 V -0.12 - 0.03 % DuCy(HSI) Duty Cycle VDD (HSI) HSI oscillator frequency drift over VDD (reference is 3.3 V) HSI oscillator frequency drift over temperature (reference is 64 MHz) With Temperature Trimming TJ = -20 to 110 C TBD - TBD TEMP (HSI) TJ = -40 to 125 C -2.62 - 2.08 HSI oscillator frequency drift over temperature (reference is 64 MHz) Without Temperature Trimming TJ = -20 to 110 C TBD - TBD T J =-40 to 125 C -4 - 2.5 - - 1.47 TBD s at 1% of target frequency - 3 TBD s - - 300 TBD A TEMP_NOT RIM (HSI) tsu(HSI) HSI oscillator start-up time (Time between Enable rising and First output clock edge.) tstab(HSI) HSI oscillator stabilization time IDD(HSI) HSI oscillator power consumption - % DS12500 Rev 1 % % 149/245 228 Electrical characteristics STM32MP151A 1. Guaranteed by design unless otherwise specified. 4 MHz low-power internal RC oscillator (CSI) Table 34. CSI oscillator characteristics(1) Symbol fCSI TRIM Parameter Conditions Min Typ Max Unit VDD = 3.3 V, TJ = 30 C TBD(2) 4 TBD(2) MHz Trimming code is not a multiple of 16 - 0.85 TBD % TBD -3.5 TBD TBD 54 TBD % TBD 1.43(3) TBD % - 2 TBD s - 5 TBD cycle - 30 TBD A Min Typ Max TJ = 25 C, VDD = 3.3 V (after calibration) TBD 32 TBD TJ = 0 to 110 C, VDD = 1.71 to 3.6 V TBD 32 TBD TJ = -40 to 110 C, VDD = 1.71 to 3.6 V TBD 32 TBD TJ = -40 to 125 C, VDD = 1.71 to 3.6 V (after calibration) TBD 32 TBD - 64 TBD CSI frequency Trimming step Trimming code is a multiple of 16 DuCy(CSI) Duty Cycle - VDD (CSI) + TEMP (CSI) CSI oscillator frequency drift over VDD & drift over temperature tsu(CSI) CSI oscillator startup time tstab(CSI) CSI oscillator stabilization time (to reach 5% of fCSI) IDD(CSI) CSI oscillator power consumption VDD = 1.71 to 3.6 V TJ = 0 to 85 C TJ = 0 to 85 C - 1. Guaranteed by design. 2. Guaranteed by test in production. 3. Guaranteed by characterization results. 40 kHz low-speed internal (LSI) RC oscillator Table 35. LSI oscillator characteristics Symbol fLSI Parameter LSI frequency Conditions kHz tsu(LSI)(1) LSI oscillator startup time (Time between Enable rising and First output clock edge.) - tstab(LSI)(1) LSI oscillator stabilization time (5% of final value) - - 110 TBD IDD(LSI)(1) LSI oscillator power consumption - - 120 TBD 150/245 Unit s DS12500 Rev 1 nA STM32MP151A Electrical characteristics 1. Guaranteed by design. 6.3.10 PLL characteristics The parameters given in Table 36, Table 37, Table 38 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 13: General operating conditions. PLL1_1600, PLL2_1600 characteristics Table 36. PLL1_1600, PLL2_1600 characteristics(1) Symbol Parameter PLL input clock fPLL_IN Normal mode and Sigma delta mode Min Typ Max Unit 8 - 16 MHz PLL input clock duty cycle - 10 - 90 % PLL P,Q,R multiplier output clock - 3.125 - 800(2) MHz Division by 1 45 50 55 Even divisions (N multiple of 2) 45 50 55 fPLL_P_Q_R_ OUT Conditions PLL P,Q,R clock duty cycle [100, [100, [100, (N+1)/ (N+1)/ (N+1)/ 2N] + 2N] - 5 2N] 5 Odd divisions (N not multiple of 2) fVCO_OUT PLL VCO output tLOCK PLL lock time ALOCK Lock Accuracy (Ratio VCO frequency versus target frequency at lock) - 400 - 800 Normal mode - 50 150 Sigma-delta mode (CKIN 8 MHz) - 65 170 - - 2 - DS12500 Rev 1 % MHz s % 151/245 228 Electrical characteristics STM32MP151A Table 36. PLL1_1600, PLL2_1600 characteristics(1) (continued) Symbol Parameter RMS period jitter PLL power IVDDCORE(2) consumption on VDDCORE (Digital) Max - 18 - - 14(3) - - 12 (3) - - 20 (3) - - 18(3) - - 16(3) - - 12(3) - - 10 (3) - - 16(3) - - 15(3) - fPLL_P_Q_R_OUT division = 1 VCO = 400 MHz to 16 VCO = 533 MHz fPLL_IN = 8 MHz VCO = 800 MHz Without Fractional mode - 225(4) - - 200(4) - - 100(4) - fPLL_P_Q_R_OUT division = 1 VCO = 400 MHz to 16 VCO = 533 MHz fPLL_IN = 8 MHz VCO = 800 MHz With Fractional mode - 350(4) - - 250(4) - - 150(4) - VCO freq = 800 MHz - 930 - VCO freq = 400 MHz - 560 - VDDCORE=1.1 V - 4200 - VDDCORE=1.26 V - 5200 - VDDCORE=1.1 V - 2100 - VDDCORE=1.26 V - 2600 - Min Typ Max Normal mode 4 - 16 Sigma delta mode 8 VCO = 400 MHz fPLL_P_Q_R_OUT division = 1 to 16 VCO = 533 MHz Without Fractional mode VCO = 800 MHz fPLL_P_Q_R_OUT division = 1 VCO = 533 MHz to 16 VCO = 800 MHz With Fractional mode PLL power consumption on VDD_PLL (Analog) Typ (3) fPLL_P_Q_R_OUT division = 1 VCO = 533 MHz to 16 VCO = 800 MHz With Fractional mode Long term jitter IVDD_PLL(2) Min VCO = 400 MHz fPLL_P_Q_R_OUT division = 1 to 16 VCO = 533 MHz Without Fractional mode VCO = 800 MHz RMS cycle-tocycle jitter Jitter Conditions VCO freq = 800 MHz VCO freq = 400 MHz Unit ps ps ps A A 1. Guaranteed by design unless otherwise specified. 2. Guaranteed by characterization results. 3. Measured on DDR high speed IO. 4. Measured on DDR high speed IO for 10000 output clock cycles. PLL3_800, PLL4_800 characteristics Table 37. PLL3_800, PLL4_800 characteristics(1) Symbol Parameter PLL input clock fPLL_IN 152/245 PLL input clock duty cycle Conditions - DS12500 Rev 1 10 16 - 90 Unit MHz % STM32MP151A Electrical characteristics Table 37. PLL3_800, PLL4_800 characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit - 3.125 - 800(2) MHz 45 50 55 PLL P,Q,R multiplier output clock Even divisions (N multiple of 2) fPLL_P_Q_R_ OUT PLL P,Q,R clock duty cycle fVCO_OUT PLL VCO output tLOCK PLL lock time ALOCK Lock accuracy (Ratio VCO frequency versus target frequency at lock) RMS cycle-tocycle jitter Jitter RMS period jitter - 400 - 800 Normal mode 15 50 150 Sigma-delta mode (CKIN 8 MHz) 25 65 170 - - 2 - 80(3) - - 50 (3) - - 45(3) - VCO = 600 MHz - 65(3) - VCO = 800 MHz - 60(3) - VCO = 400 MHz - 75(3) - - 38 (3) - - 30 (3) - VCO = 600 MHz - 55(3) - VCO = 800 MHz - 50(3) - fPLL_P_Q_R_OUT division = 25 to 100 fPLL_IN = 8 MHz Without Fractional mode VCO = 400 MHz - 225(4) - VCO = 600 MHz - 150(4) - VCO = 800 MHz - 125(4) - fPLL_P_Q_R_OUT division = 25 to 100 fPLL_IN = 8 MHz With Fractional mode VCO = 400 MHz - 300(4) - VCO = 600 MHz - 200(4) - VCO = 800 MHz - 150(4) - VCO freq = 800 MHz - 600 - VCO freq = 400 MHz - 320 - - fPLL_P_Q_R_OUT division = 25 to 100 Without Fractional mode fPLL_P_Q_R_OUT division = 25 to 100 With Fractional mode fPLL_P_Q_R_OUT division = 25 to 100 Without Fractional mode fPLL_P_Q_R_OUT division = 25 to 100 With Fractional mode Long term jitter IVDD_PLL(2) [100, [100, [100, (N+1)/ (N+1)/ (N+1)/ 2N] + 2N] - 5 2N] 5 Odd divisions (N not multiple of 2) PLL power consumption on VDD_PLL (Analog) VCO = 400 MHz VCO = 600 MHz VCO = 800 MHz VCO = 600 MHz VCO = 800 MHz DS12500 Rev 1 % MHz s % ps ps ps A 153/245 228 Electrical characteristics STM32MP151A Table 37. PLL3_800, PLL4_800 characteristics(1) (continued) Symbol Parameter Conditions VCO freq = 800 MHz PLL power IVDDCORE(2) consumption on VDDCORE (Digital) VCO freq = 400 MHz Min Typ Max Unit VDDCORE = 1.1 V - 1960 - VDDCORE = 1.26 V - 2340 - VDDCORE = 1.1 V - 970 - VDDCORE = 1.26 V - 1210 - Min Typ Max Unit A 1. Guaranteed by design unless otherwise specified. 2. Guaranteed by characterization results. 3. Measured on GPIO. 4. Measured on GPIO for 10000 output clock cycles. PLL_USB (2880 MHz) characteristics Table 38. USB_PLL characteristics(1) Symbol Parameter Condition fPLL_IN PLL input clock 19.2 - 38.4 MHz fPLL_INFIN PFD input clock 19.2 - 38.4 MHz fPLL_OUT PLL multiplier output clock - 480 - MHz fVCO_OUT PLL VCO output - 2880 - MHz tLOCK PLL lock time - - 100 s tPDN PLL power down time 10 - - s IDDA1V1_R PLL power consumption on VDDA1V1_REG (internal connection) PLL in power down - TBD TBD fVCO_OUT = 2880 MHz - TBD TBD PLL power consumption on VDDA1V8_REG (internal connection) PLL in power down - - TBD fVCO_OUT = 2880 MHz - TBD TBD EG(PLL) IDDA1V8_R EG(PLL) A A 1. Guaranteed by characterization results. 6.3.11 PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows the reduction of electromagnetic interferences (see Table 44: EMI characteristics). It is available only on the PLL1_1600, PLL2_1600, PLL3_800 and PLL4_800. Table 39. SSCG parameters constraint Symbol Parameter fMod Modulation frequency md Peak modulation depth MODEPER * INCSTEP - 1. Guaranteed by design. 154/245 DS12500 Rev 1 Min Typ Max(1) Unit 20 - 60 kHz 0.25 - 2 % - - 215-1 - STM32MP151A Electrical characteristics Equation 1 The frequency modulation period (MODEPER) is given by the equation below: MODEPER = round [ f PLL_IN ( 4 x f Mod ) ] fPLL_IN and fMod must be expressed in Hz. As an example: If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation 1: 6 3 MODEPER = round [ 10 ( 4 x 10 ) ] = 250 Equation 2 Equation 2 allows the increment step (INCSTEP) calculation: INCSTEP = round [ ( ( 2 15 - 1 ) x md x PLLN ) ( 100 x 5 x MODEPER ) ] fVCO_OUT must be expressed in MHz. With a modulation depth (md) = 2% (4% peak-to-peak), and PLLN = 240 (in MHz): INCSTEP = round [ ( ( 2 15 - 1 ) x 2 x 240 ) ( 100 x 5 x 250 ) ] = 126md(quantitazed)% An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized % = ( MODEPER x INCSTEP x 100 x 5 ) ( ( 2 15 - 1 ) x PLLN ) As a result: md quantized % = ( 250 x 126 x 100 x 5 ) ( ( 2 15 - 1 ) x 240 ) = 2.002%(peak) Figure 20 and Figure 21 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. DS12500 Rev 1 155/245 228 Electrical characteristics STM32MP151A Figure 20. PLL output clock waveforms in center spread mode Frequency (PLL_OUT) md F0 md tmode Time 2xtmode ai17291 Figure 21. PLL output clock waveforms in down spread mode Frequency (PLL_OUT) F0 2xmd tmode 2xtmode Time ai17292b 6.3.12 Memory characteristics OTP characteristics The characteristics are given at TJ = -40 to 125 C unless otherwise specified. Table 40. OTP characteristics Symbol IVDDCORE Conditions Min Max Unit Programming - 450 A Reading - 490 A PowerDown - 4.2 A Programming - 10000 A Reading - 2200 A PowerDown - 1 A OTP operating Frequency - - 67 MHz Maximum number of reading cycles - - 500 Million OTP consumption on VDDCORE IVDD FOTP Parameter OTP consumption on VDD (1) NB_CYCLE (2) 1. Guaranteed by design. 2. Guaranteed by characterization results. 156/245 DS12500 Rev 1 STM32MP151A Electrical characteristics DDR characteristics DDR3L I/O DC specifications The following table provides input and output DC threshold values and on-die-termination (ODT) recommended values. The conditions for the output threshold values are unterminated outputs loaded with 1 pF capacitor load. The ODT values are measured after impedance calibration. Table 41. DC specifications - DDR3L mode(1) Symbol Parameter Min Typ Max Unit VIH(DC) DC input voltage high VREF + 0.09 - VDDQ V VIL(DC) DC input voltage low VSSQ - 0.3 - VREF - 0.09 V VOH DC output logic high 0.8 x VDDQ - - V VOL DC output logic low - - 0.2 x VDDQ V RTT Input termination resistance (ODT) to VDDQ/2 100 54 36 120 60 40 140 66 44 ILS Input leakage current, SSTL mode, unterminated - 0.01 4.8 A 1. Guaranteed by design. LPDDR2, LPDDR3 I/O DC specifications The following table provides input and output DC threshold values. The conditions for the output threshold values are un-terminated outputs loaded with 1 pF capacitor load. Table 42. DC specifications - DDR3L mode(1) Symbol Parameter Min Typ Max Unit VIH(DC) DC input voltage high VREF + 0.13 - VDDQ V VIL(DC) DC input voltage low VSSQ - VREF - 0.13 V VOH DC output logic high 0.9 x VDDQ - - V VOL DC output logic low - - 0.1 x VDDQ V ILEAK Input leakage current - 0.01 4.51 A 1. Guaranteed by design. 6.3.13 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. DS12500 Rev 1 157/245 228 Electrical characteristics STM32MP151A Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: * Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. * FTB: a burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 43. They are based on the EMS levels and classes defined in application note AN1709 available from the ST website www.st.com. Table 43. EMS characteristics Symbol Parameter VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance Conditions Level/ Class VDD = 3.3 V, VDDCORE = 1.2 V, TA = +25 C, LFBGA448, Fmpuss_ck = 648 MHz, Fmcu_ck = 209 MHz, M4 core not running, conforms to IEC 61000-42 2B 5A As a consequence, it is recommended to add a serial resistor (1 k) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm on PCB). Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: * Corrupted program counter * Unexpected reset * Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. 158/245 DS12500 Rev 1 STM32MP151A Electrical characteristics To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015 available from the ST website www.st.com.). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 44. EMI characteristics Symbol Parameter Conditions Monitored frequency band Max vs. [fHSE/fCPU] Unit 8/400 MHz SEMI 6.3.14 Peak level VDD = 3.6 V, VDDCORE = 1.2 V, TA = 25 C, LFBGA448 package, Fmpuss_ck = 648 MHz, Fmcu_ck = 209 MHz, M4 core not running, conforming to IEC61967-2 0.1 to 30 MHz 10 30 to 130 MHz -1 130 MHz to 1 GHz 18 1 GHz to 2 GHz 8 EMI Level 3.5 dBV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESDA/JEDEC JS-002 standards. Table 45. ESD absolute maximum ratings Symbol Ratings Conditions Packages Class Maximum value(1) 1C 1000 Electrostatic discharge voltage (human body model) TA = +25 C conforming to ANSI/ESDA/JEDEC JS-001 All Electrostatic discharge VESD(CDM) voltage (charge device model) TA = +25 C conforming to ANSI/ESDA/JEDEC JS-002 All VESD(HBM) Unit V C1 250 1. Guaranteed by characterization results. DS12500 Rev 1 159/245 228 Electrical characteristics STM32MP151A Static latchup Two complementary static tests are required on six parts to assess the latchup performance: * A supply overvoltage is applied to each power supply pin * A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 46. Electrical sensitivities Symbol LU Parameter Static latchup class 6.3.15 Conditions Class TA = +25 C conforming to JESD78 II level A I/O current injection characteristics As a general rule, a current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during the normal product operation. However, in order to give an indication of the robustness of the device in cases when an abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during the device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of -5 A/+0 A range), or other functional failure (for example reset, oscillator frequency deviation). The following tables are the compilation of the SIC1/SIC2 and functional ESD results. Negative induced A negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. Table 47. I/O current injection susceptibility(1) Functional susceptibility Symbol IINJ Description Negative injection Positive injection PA7, PC5, PG1, PB14, PJ7, PA11, PA12, PA13, PA14, PA15, PJ12, PB4 TBD TBD PA2, PH2, PH3, PE8, PA6, PA7, PC4, PE7, PE10, PE11 TBD TBD PA0, PA_C, PA1, PA1_C, PC2, PC2_C, PC3, PC3_C, PA4, PA5, PH4, PH5, BOOTx TBD TBD All other I/Os TBD TBD 1. Guaranteed by characterization. 160/245 DS12500 Rev 1 Unit mA STM32MP151A 6.3.16 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 48: I/O static characteristics are derived from tests performed under the conditions summarized in Table 13: General operating conditions. All I/Os are CMOS and TTL compliant. Table 48. I/O static characteristics Symbol VIL(1) Parameter I/O input low level voltage VIH(1) I/O input high level voltage VHYS(1) TT_xx, FT_xxx and NRST I/O input hysteresis FT_xx input leakage Ileak current(1) FT_u, IO Condition Min Typ Max 1.71 V < VDD < 2.7 V - - 0.35 x VDD 2.7 V < VDD < 3.6 V - - 0.3 x VDD 1.71 V < VDD < 3.6 V - - TBD 1.71 V < VDD < 3.6 V 0.7xVDD - - 1.71 V < VDD < 3.6 V TBD - - 1.71 V < VDD < 3.6 V - 0.1 x VDD - 0 < VIN Max(VDD)(6) - - TBD Max(VDD) < VIN 5.5 V (6)(2)(3) - - TBD 0 < VIN Max(VDD)(6) - - TBD Max(VDD) < VIN 5.5 V - - TBD(4) - - TBD - - TBD 25 40 55 (6)(3) TT_xx input leakage current RPU Weak pull-up equivalent resistor(5) RPD Weak pull-down equivalent resistor(5) CIO I/O pin capacitance 0 < VIN Max(VDD) (6) Max(VDD) VIN < 3.6 V VIN=VSS (6) Unit V V mV nA k VIN=VDD (6) - 25 40 55 - 5 - pF 1. Guaranteed by design. 2. All FT_xx IO except FT_uf, FT_u. 3. VIN must be less than Max(VDD) + 3.6 V. 4. To sustain a voltage higher than MIN(VDD, VDDA, VDD3V3_USBxxx) +0.3 V, the internal pull-up and pull-down resistors must be disabled. 5. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). 6. Max(VDD) is the maximum value of all the I/O supplies. All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA (with a relaxed VOL/VOH). DS12500 Rev 1 161/245 228 Electrical characteristics STM32MP151A In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 0.2. In particular: * The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run mode consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 11). * The sum of the currents sunk by all the I/Os on VSS plus the maximum Run mode consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 11). Output voltage levels Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 13: General operating conditions. All I/Os are CMOS and TTL compliant. Table 49. Output voltage characteristics(1) Symbol Conditions(3) Parameter Min Max Output low level voltage CMOS port IIO = 8 mA 2.0 V VDD 3.6 V - 0.4 Output high level voltage CMOS port(2) IIO = -8 mA 2.0 V VDD 3.6 V VDD-0.4 - Output low level voltage TTL port(2) IIO = 8 mA 2.0 V VDD 3.6 V - 0.4 Output high level voltage TTL port(2) IIO = -8 mA 2.0 V VDD 3.6 V 2.4 - VOL(3) Output low level voltage IIO = 20 mA 2.7 V VDD 3.6 V - 1.3 VOH(3) Output high level voltage IIO = -20 mA 2.7 V VDD 3.6 V VDD-1.3 - VOL(3) Output low level voltage IIO = 4 mA 1.71 V VDD 3.6 V - 0.45 VOH (3) Output high level voltage IIO = -4 mA 1.71 V VDD 3.6 V VDD-0.45 - - 0.4 - 0.4 Unit (2) VOL VOH VOL(3) VOH (3) IIO = 20 mA Output low level voltage for an FT_f 2.7 V VDD 3.6 V VOLFM+(3) IO pin in FM+ mode I = 10 mA IO 1.71 V VDD 3.6 V V 1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 10: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings IIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Guaranteed by design. 162/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Output buffer timing characteristics (HSLV option disabled) Table 50. Output timing characteristics (HSLV OFF)(1) Speed Symbol Fmax(2) Parameter Maximum frequency 00 tr/tf(3) Fmax(2) Output high to low level fall time and output low to high level rise time Maximum frequency 01 tr/tf(3) Output high to low level fall time and output low to high level rise time conditions Min Max C = 50 pF, 2.7 V VDD 3.6 V - 20 C = 30 pF, 2.7 V VDD 3.6 V - 24 C = 20 pF, 2.7 V VDD 3.6 V - 26 C = 10 pF, 2.7 V VDD 3.6 V - 30 C = 50 pF, 1.71 V VDD 2.7 V - 10 C = 30 pF, 1.71 V VDD 2.7 V - 11 C = 20 pF, 1.71 V VDD 2.7 V - 12 C = 10 pF, 1.71 V VDD 2.7 V - 13 C = 50 pF, 2.7 V VDD 3.6 V - 13.3 C = 30 pF, 2.7 V VDD 3.6 V - 11.4 C = 20 pF, 2.7 V VDD 3.6 V - 10.2 C = 10 pF, 2.7 V VDD 3.6 V - 8.8 C = 50 pF, 1.71 V VDD 2.7 V - 23 C = 30 pF, 1.71 V VDD 2.7 V - 20 C = 20 pF, 1.71 V VDD 2.7 V - 18.3 C = 10 pF, 1.71 V VDD 2.7 V - 16 C = 50 pF, 2.7 V VDD 3.6 V - 68 C = 30 pF, 2.7 V VDD 3.6 V - 83 C = 20 pF, 2.7 V VDD 3.6 V - 88 C = 10 pF, 2.7 V VDD 3.6 V - 103 C = 50 pF, 1.71 V VDD 2.7 V - 25 C = 30 pF, 1.71 V VDD 2.7 V - 28 C = 20 pF, 1.71 V VDD 2.7 V - 30 C = 10 pF, 1.71 V VDD 2.7 V - 36 C = 50 pF, 2.7 V VDD 3.6 V - 4.9 C = 30 pF, 2.7 V VDD 3.6 V - 3.9 C = 20 pF, 2.7 V VDD 3.6 V - 3.3 C = 10 pF, 2.7 V VDD 3.6 V - 2.7 C = 50 pF, 1.71 V VDD 2.7 V - 8.1 C = 30 pF, 1.71 V VDD 2.7 V - 6.5 C = 20 pF, 1.71 V VDD 2.7 V - 5.7 C = 10 pF, 1.71 V VDD 2.7 V - 4.6 DS12500 Rev 1 Unit MHz ns MHz ns 163/245 228 Electrical characteristics STM32MP151A Table 50. Output timing characteristics (HSLV OFF)(1) (continued) Speed Symbol Parameter conditions Min Max (4) C = 50 pF, 2.7 V VDD 3.6 V - 94 C = 30 pF, 2.7 V VDD 3.6 V(4) - 124 (4) - 144 (4) C = 20 pF, 2.7 V VDD 3.6 V Fmax(2) Maximum frequency C = 10 pF, 2.7 V VDD 3.6 V - 166 (4) C = 50 pF, 1.71 V VDD 2.7 V - 53 C = 30 pF, 1.71 V VDD 2.7 V(4) - 66 (4) - 72 (4) C = 20 pF, 1.71 V VDD 2.7 V C = 10 pF, 1.71 V VDD 2.7 V 10 - 81 V(4) - 3.5 C = 30 pF, 2.7 V VDD 3.6 V(4) - 2.7 C = 20 pF, 2.7 V VDD 3.6 V(4) - 2.2 C = 10 pF, 2.7 V VDD 3.6 V(4) - 1.7 C = 50 pF, 1.71 V VDD 2.7 V(4) - 6.3 C = 30 pF, 1.71 V VDD 2.7 V(4) - 4.8 C = 20 pF, 1.71 V VDD 2.7 V(4) - 4 C = 10 pF, 1.71 V VDD 2.7 V(4) - 3.2 C = 50 pF, 2.7 V VDD 3.6 V(4) - 110 C = 30 pF, 2.7 V VDD 3.6 V(4) - 150 C = 20 pF, 2.7 V VDD 3.6 V(4) - 185 C = 10 pF, 2.7 V VDD 3.6 V(4) - 210 C = 50 pF, 1.71 V VDD 2.7 V(4) - 62 C = 30 pF, 1.71 V VDD 2.7 V(4) - 70 (4) - 79 C = 10 pF, 1.71 V VDD 2.7 V(4) - 94 C = 50 pF, 2.7 V VDD 3.6 V(4) - 3 C = 30 pF, 2.7 V VDD 3.6 V(4) - 2.2 C = 20 pF, 2.7 V VDD 3.6 V(4) - 1.8 C = 10 pF, 2.7 V VDD 3.6 V(4) C = 50 pF, 2.7 V VDD 3.6 tr/tf(3) Fmax(2) Output high to low level fall time and output low to high level rise time Maximum frequency C = 20 pF, 1.71 V VDD 2.7 V 11 tr/tf(3) Output high to low level fall time and output low to high level rise time - 1.3 (4) C = 50 pF, 1.71 V VDD 2.7 V - 5.3 C = 30 pF, 1.71 V VDD 2.7 V(4) - 4 C = 20 pF, 1.71 V VDD 2.7 V(4) - 3.3 C = 10 pF, 1.71 V VDD 2.7 V(4) - 2.5 Unit MHz ns MHz ns 1. Guaranteed by design. 2. The maximum frequency is defined with the following conditions: (tr+tf) 2/3, skew 1/20 T and 45% < duty cycle < 55%. 3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively. 164/245 DS12500 Rev 1 STM32MP151A Electrical characteristics 4. Compensation system enabled. Output buffer timing characteristics (IO structure with _h, HSLV option enabled) The HSLVEN_xx bits of SYSCFG_IOCTRLSETR register (together with OTP bit PRODUCT_BELOW_2V5) can be used to optimize the I/O speed when the product voltage is below 2.5 V typ. (2.7 V max.). Table 51. Output timing characteristics (HSLV ON, _h IO structure)(1) Speed Symbol Fmax(2) Parameter Maximum frequency 00 tr/tf(3) Fmax(2) Output high to low level fall time and output low to high level rise time Maximum frequency 01 tr/tf(3) Fmax(2) Output high to low level fall time and output low to high level rise time Maximum frequency 10 tr/tf(3) Output high to low level fall time and output low to high level rise time conditions Min Max C = 50 pF, 1.71 V VDD 2.7 V - 20 C = 30 pF, 1.71 V VDD 2.7 V - 22 C = 20 pF, 1.71 V VDD 2.7 V - 24 C = 10 pF, 1.71 V VDD 2.7 V - 28 C = 50 pF, 1.71 V VDD 2.7 V - 9.9 C = 30 pF, 1.71 V VDD 2.7 V - 8.1 C = 20 pF, 1.71 V VDD 2.7 V - 7.1 C = 10 pF, 1.71 V VDD 2.7 V - 5.8 C = 50 pF, 1.71 V VDD 2.7 V - 58 C = 30 pF, 1.71 V VDD 2.7 V - 79 C = 20 pF, 1.71 V VDD 2.7 V - 90 C = 10 pF, 1.71 V VDD 2.7 V - 100 C = 50 pF, 1.71 V VDD 2.7 V - 5.7 C = 30 pF, 1.71 V VDD 2.7 V - 4.2 C = 20 pF, 1.71 V VDD 2.7 V - 3.5 C = 10 pF, 1.71 V VDD 2.7 V - 2.7 C = 50 pF, 1.71 V VDD 2.7 V(4) - 71 C = 30 pF, 1.71 V VDD 2.7 V(4) - 101 C = 20 pF, 1.71 V VDD 2.7 V(4) - 126 C = 10 pF, 1.71 V VDD 2.7 V(4) - 162 C = 50 pF, 1.71 V VDD 2.7 V(4) - 4.7 C = 30 pF, 1.71 V VDD 2.7 V(4) - 3.3 C = 20 pF, 1.71 V VDD 2.7 V(4) - 2.7 C = 10 pF, 1.71 V VDD 2.7 V(4) - 1.9 DS12500 Rev 1 Unit MHz ns MHz ns MHz ns 165/245 228 Electrical characteristics STM32MP151A Table 51. Output timing characteristics (HSLV ON, _h IO structure)(1) (continued) Speed Symbol Fmax(2) Parameter Maximum frequency 11 tr/tf(3) Output high to low level fall time and output low to high level rise time conditions Min Max (4) C = 50 pF, 1.71 V VDD 2.7 V - 77 C = 30 pF, 1.71 V VDD 2.7 V(4) - 111 (4) C = 20 pF, 1.71 V VDD 2.7 V - 145 C = 10 pF, 1.71 V VDD 2.7 V(4) - 172 (4) C = 50 pF, 1.71 V VDD 2.7 V - 4.3 C = 30 pF, 1.71 V VDD 2.7 V(4) - 3 (4) C = 20 pF, 1.71 V VDD 2.7 V - 2.3 C = 10 pF, 1.71 V VDD 2.7 V(4) - 1.6 Unit MHz ns 1. Guaranteed by design. 2. The maximum frequency is defined with the following conditions: (tr+tf) 2/3, skew 1/20 T and 45% < duty cycle < 55%. 3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively. 4. Compensation system enabled. Output buffer timing characteristics (IO structure with _e, HSLV option enabled) The HSLVEN_xx bits of SYSCFG_IOCTRLSETR register (together with OTP bit PRODUCT_BELOW_2V5) can be used to optimize the I/O speed when the product voltage is below 2.5 V typ. (2.7 V max.). Table 52. Output timing characteristics (HSLV ON, _e IO structure)(1) Speed Symbol Fmax(2) Parameter Maximum frequency 00 tr/tf(3) 166/245 Output high to low level fall time and output low to high level rise time conditions Min Max C = 50 pF, 1.71 V VDD 2.7 V - 36 C = 30 pF, 1.71 V VDD 2.7 V - 41 C = 20 pF, 1.71 V VDD 2.7 V - 46 C = 10 pF, 1.71 V VDD 2.7 V - 55 C = 50 pF, 1.71 V VDD 2.7 V - 9.2 C = 30 pF, 1.71 V VDD 2.7 V - 7.4 C = 20 pF, 1.71 V VDD 2.7 V - 6.5 C = 10 pF, 1.71 V VDD 2.7 V - 5.2 DS12500 Rev 1 Unit MHz ns STM32MP151A Electrical characteristics Table 52. Output timing characteristics (HSLV ON, _e IO structure)(1) (continued) Speed Symbol Fmax(2) Parameter Maximum frequency 01 tr/tf(3) Output high to low level fall time and output low to high level rise time conditions Min Max C = 50 pF, 1.71 V VDD 2.7 V - 55 C = 30 pF, 1.71 V VDD 2.7 V - 71 C = 20 pF, 1.71 V VDD 2.7 V - 85 C = 10 pF, 1.71 V VDD 2.7 V - 100 C = 50 pF, 1.71 V VDD 2.7 V - 6.1 C = 30 pF, 1.71 V VDD 2.7 V - 4.7 C = 20 pF, 1.71 V VDD 2.7 V - 3.9 C = 10 pF, 1.71 V VDD 2.7 V - 3 V(4) - 68 C = 30 pF, 1.71 V VDD 2.7 V(4) - 95 V(4) - 118 C = 10 pF, 1.71 V VDD 2.7 V(4) - 162 V(4) - 4.9 C = 30 pF, 1.71 V VDD 2.7 V(4) - 3.5 V(4) - 2.8 C = 10 pF, 1.71 V VDD 2.7 V(4) - 2.1 V(4) - 80 C = 30 pF, 1.71 V VDD 2.7 V(4) - 121 V(4) - 162 C = 10 pF, 1.71 V VDD 2.7 V(4) - 245 V(4) - 4.2 C = 30 pF, 1.71 V VDD 2.7 V(4) - 2.8 (4) C = 20 pF, 1.71 V VDD 2.7 V - 2.1 C = 10 pF, 1.71 V VDD 2.7 V(4) - 1.4 C = 50 pF, 1.71 V VDD 2.7 Fmax(2) Maximum frequency 10 C = 20 pF, 1.71 V VDD 2.7 C = 50 pF, 1.71 V VDD 2.7 tr/tf(3) Output high to low level fall time and output low to high level rise time C = 20 pF, 1.71 V VDD 2.7 C = 50 pF, 1.71 V VDD 2.7 Fmax(2) Maximum frequency 11 C = 20 pF, 1.71 V VDD 2.7 C = 50 pF, 1.71 V VDD 2.7 tr/tf(3) Output high to low level fall time and output low to high level rise time Unit MHz ns MHz ns MHz ns 1. Guaranteed by design. 2. The maximum frequency is defined with the following conditions: (tr+tf) 2/3, skew 1/20 T and 45% < Duty cycle < 55%. 3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively. 4. Compensation system enabled. 6.3.17 NRST and NRST_CORE pin characteristics The NRST and NRST_CORE pins input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 48: I/O static characteristics). Unless otherwise specified, the parameters given in Table 53 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 13: General operating conditions. DS12500 Rev 1 167/245 228 Electrical characteristics STM32MP151A Table 53. NRST and NRST_CORE pin characteristics Symbol Parameter Conditions Min Typ Max Unit 30 40 50 k RPU(2) Weak pull-up equivalent resistor(1) VIN = VSS VF(NRST)(2) NRST/NRST_CORE Input filtered pulse 1.71 V < VDD < 3.6 V - - 50 VNF(NRST)(2) NRST/NRST_CORE Input not filtered pulse 1.71 V < VDD < 3.6 V 350 - - ns 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Guaranteed by design. Figure 22. Recommended NRST and NRST_CORE pin protection VDD External reset circuit (1) NRST (2) RPU Internal Reset Filter 0.1 F STM32 ai14132d 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST/NRST_CORE pin can go below the VIL(NRST) max level specified in Table 53. Otherwise the reset is not taken into account by the device. 6.3.18 FMC characteristics Unless otherwise specified, the parameters given in Table 54 to Table 67 for the FMC interface are derived from tests performed under the ambient temperature, Fmc_hclk (Fhclk6) frequency and VDD supply voltage conditions summarized in Table 13: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Measurement points are done at CMOS levels: 0.5xVDD Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics. 168/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Asynchronous waveforms and timings Figure 23 through Figure 26 represent asynchronous waveforms and Table 54 through Table 61 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: * AddressSetupTime = 0x1 * AddressHoldTime = 0x1 * DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5) * DataHoldTime = 0x1 (1xTfmc_ker_ck for read operations and 2xTfmc_ker_ck for write operations) * ByteLaneSetup = 0x1 * BusTurnAroundDuration = 0x0 * Capacitive load CL = 30 pF In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period. Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms tw(NE) FMC_NE tv(NOE_NE) t w(NOE) t h(NE_NOE) FMC_NOE FMC_NWE tv(A_NE) FMC_A[25:0] t h(A_NOE) Address tv(BL_NE) t h(BL_NOE) FMC_NBL[1:0] t h(Data_NE) t su(Data_NOE) th(Data_NOE) t su(Data_NE) Data FMC_D[15:0] t v(NADV_NE) tw(NADV) FMC_NADV (1) FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32753V1 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. DS12500 Rev 1 169/245 228 Electrical characteristics STM32MP151A Table 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Parameter Min Max 3Tfmc_ker_ck-1 3Tfmc_ker_ck+0.5 0 1 tw(NE) FMC_NE low time tv(NOE_NE) FMC_NEx low to FMC_NOE low tw(NOE) FMC_NOE low time 2Tfmc_ker_ck-1 2Tfmc_ker_ck+1 th(NE_NOE) FMC_NOE high to FMC_NE high hold time Tfmc_ker_ck-1 - tv(A_NE) FMC_NEx low to FMC_A valid - 1 th(A_NOE) Address hold time after FMC_NOE high 2Tfmc_ker_ck-1 - tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck+15 - tsu(Data_NOE) Data to FMC_NOEx high setup time 16 - th(Data_NOE) Data hold time after FMC_NOE high 0 - th(Data_NE) Data hold time after FMC_NEx high 0 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0 tw(NADV) FMC_NADV low time - Tfmc_ker_ck+1 Unit ns 1. Guaranteed by characterization results. Table 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings(1)(2) Symbol Parameter Min Max tw(NE) FMC_NE low time 7Tfmc_ker_ck-0.5 7Tfmc_ker_ck+1 tw(NOE) FMC_NWE low time 6Tfmc_ker_ck-0.5 6Tfmc_ker_ck+1 tw(NWAIT) FMC_NWAIT low time Tfmc_ker_ck - tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 7Tfmc_ker_ck+2 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 5Tfmc_ker_ck - 1. Guaranteed by characterization results. 2. NWAIT pulse width is equal to 1 AHB cycle. 170/245 DS12500 Rev 1 Unit ns STM32MP151A Electrical characteristics Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FMC_NEx FMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FMC_NWE tv(A_NE) FMC_A[25:0] th(A_NWE) Address tv(BL_NE) FMC_NBL[1:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FMC_D[15:0] t v(NADV_NE) tw(NADV) FMC_NADV (1) FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32754V1 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1) Symbol Parameter Min Max tw(NE) FMC_NE low time 4Tfmc_ker_ck-0.5 4Tfmc_ker_ck+1 tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck-0.5 Tfmc_ker_ck+1 tw(NWE) FMC_NWE low time Tfmc_ker_ck-0.5 Tfmc_ker_ck+0.5 th(NE_NWE) FMC_NWE high to FMC_NE high hold time 2Tfmc_ker_ck-0.5 - tv(A_NE) FMC_NEx low to FMC_A valid - 0 th(A_NWE) Address hold time after FMC_NWE high 3Tfmc_ker_ck-1 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 th(BL_NWE) FMC_BL hold time after FMC_NWE high 3Tfmc_ker_ck-0.5 - tv(Data_NE) Data to FMC_NEx low to Data valid - 2.5 th(Data_NWE) Data hold time after FMC_NWE high 3Tfmc_ker_ck-1 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0.5 tw(NADV) FMC_NADV low time - Tfmc_ker_ck+0.5 Unit ns 1. Guaranteed by characterization results. DS12500 Rev 1 171/245 228 Electrical characteristics STM32MP151A Table 57. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 8Tfmc_ker_ck-0.5 8Tfmc_ker_ck+0.5 tw(NWE) FMC_NWE low time 5Tfmc_ker_ck-0.5 5Tfmc_ker_ck+1 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 8Tfmc_ker_ck+4 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 6Tfmc_ker_ck - ns 1. Guaranteed by characterization results. 2. NWAIT pulse width is equal to 1 AHB cycle. Figure 25. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FMC_ NE tv(NOE_NE) t h(NE_NOE) FMC_NOE t w(NOE) FMC_NWE th(A_NOE) tv(A_NE) FMC_ A[25:16] Address tv(BL_NE) th(BL_NOE) FMC_ NBL[1:0] NBL th(Data_NE) tsu(Data_NE) t v(A_NE) FMC_ AD[15:0] tsu(Data_NOE) th(Data_NOE) Data Address th(AD_NADV) t v(NADV_NE) tw(NADV) FMC_NADV FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32755V1 172/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Table 58. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol Parameter Min Max tw(NE) FMC_NE low time 4Tfmc_ker_ck-0.5 4Tfmc_ker_ck+1 tv(NOE_NE) FMC_NEx low to FMC_NOE low 2Tfmc_ker_ck-0.5 2Tfmc_ker_ck+1 ttw(NOE) FMC_NOE low time Tfmc_ker_ck-0.5 Tfmc_ker_ck+0.5 th(NE_NOE) FMC_NOE high to FMC_NE high hold time Tfmc_ker_ck-1 - tv(A_NE) FMC_NEx low to FMC_A valid - 3 tv(NADV_NE) FMC_NEx low to FMC_NADV low 0.5 1.5 tw(NADV) FMC_NADV low time Tfmc_ker_ck Tfmc_ker_ck+1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck-3 - th(A_NOE) Address hold time after FMC_NOE high Address held until next read operation - tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck+15 - tsu(Data_NOE) Data to FMC_NOE high setup time 16 - th(Data_NE) Data hold time after FMC_NEx high 0 - th(Data_NOE) Data hold time after FMC_NOE high 0 - Unit ns 1. Guaranteed by characterization results. Table 59. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1) Symbol Parameter Min Max tw(NE) FMC_NE low time 7Tfmc_ker_ck-0.5 8Tfmc_ker_ck+1 tw(NOE) FMC_NWE low time 5Tfmc_ker_ck-0.5 6Tfmc_ker_ck+1 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 7Tfmc_ker_ck+2 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 5Tfmc_ker_ck - Unit ns 1. Guaranteed by characterization results. DS12500 Rev 1 173/245 228 Electrical characteristics STM32MP151A Figure 26. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FMC_ NEx FMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FMC_NWE th(A_NWE) tv(A_NE) FMC_ A[25:16] Address tv(BL_NE) th(BL_NWE) FMC_ NBL[1:0] NBL t v(A_NE) FMC_ AD[15:0] t v(Data_NADV) Address th(Data_NWE) Data th(AD_NADV) t v(NADV_NE) tw(NADV) FMC_NADV FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32756V1 174/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Table 60. Asynchronous multiplexed PSRAM/NOR write timings(1) Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 5Tfmc_ker_ck-0.5 5Tfmc_ker_ck+1 tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck-0.5 Tfmc_ker_ck+1 tw(NWE) FMC_NWE low time 2Tfmc_ker_ck-1 2Tfmc_ker_ck+0.5 th(NE_NWE) FMC_NWE high to FMC_NE high hold time 2Tfmc_ker_ck-0.5 - tv(A_NE) FMC_NEx low to FMC_A valid - 0.5 tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1 tw(NADV) FMC_NADV low time Tfmc_ker_ck+0.5 Tfmc_ker_ck+1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck+0.5 - th(A_NWE) Address hold time after FMC_NWE high Address held until next write operation - th(BL_NWE) FMC_BL hold time after FMC_NWE high 3Tfmc_ker_ck+0.5 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 - Tfmc_ker_ck+4 3Tfmc_ker_ck+0.5 - tv(Data_NADV) FMC_NADV high to Data valid th(Data_NWE) Data hold time after FMC_NWE high ns 1. Guaranteed by characterization results. Table 61. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1) Symbol Parameter Min Max tw(NE) FMC_NE low time 9Tfmc_ker_ck-0.5 9Tfmc_ker_ck+0.5 tw(NWE) FMC_NWE low time 6Tfmc_ker_ck-0.5 6Tfmc_ker_ck+1 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 8Tfmc_ker_ck+4 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 6Tfmc_ker_ck - Unit ns 1. Guaranteed by characterization results. Synchronous waveforms and timings Figure 27 through Figure 30 represent synchronous waveforms and Table 62 through Table 65 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: * BurstAccessMode = FMC_BurstAccessMode_Enable * MemoryType = FMC_MemoryType_CRAM * WriteBurst = FMC_WriteBurst_Enable * CLKDivision = 1 * DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM DS12500 Rev 1 175/245 228 Electrical characteristics STM32MP151A In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_CLK maximum values: * For 2.7 V < VDD < 3.6 V, FMC_CLK = 130 MHz at 20 pF * For 1.71 V < VDD < 1.9 V, FMC_CLK = 95 MHz at 20 pF Figure 27. Synchronous multiplexed NOR/PSRAM read timings BUSTURN = 0 tw(CLK) tw(CLK) FMC_CLK Data latency = 0 td(CLKL-NExL) FMC_NEx t d(CLKL-NADVL) td(CLKH-NExH) td(CLKL-NADVH) FMC_NADV td(CLKL-AV) td(CLKH-AIV) FMC_A[25:16] td(CLKL-NOEL) td(CLKH-NOEH) FMC_NOE t d(CLKL-ADV) FMC_AD[15:0] td(CLKL-ADIV) tsu(ADV-CLKH) AD[15:0] th(CLKH-ADV) tsu(ADV-CLKH) D1 tsu(NWAITV-CLKH) FMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) th(CLKH-ADV) D2 th(CLKH-NWAITV) th(CLKH-NWAITV) th(CLKH-NWAITV) MS32757V1 176/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Table 62. Synchronous multiplexed NOR/PSRAM read timings(1) Symbol tw(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low td(CLKL-NADVH) FMC_CLK low to FMC_NADV high td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NOEL) td(CLKH-NOEH) FMC_CLK low to FMC_NOE low FMC_CLK high to FMC_NOE high Min Max RxTfmc_ker_ck-1(2) - - 1 RxTfmc_ker_ck/2+0.5(2) - - 1.5 1 - - 1 RxTfmc_ker_ck/2+1.5(2) - - 2 /2+0.5(2) RxTfmc_ker_ck FMC_CLK low to FMC_AD[15:0] valid - 1.5 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 1 - tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 3 - th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 1 - 3 - 1.5 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high ns - td(CLKL-ADV) tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high Unit 1. Guaranteed by characterization results. 2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period). DS12500 Rev 1 177/245 228 Electrical characteristics STM32MP151A Figure 28. Synchronous multiplexed PSRAM write timings BUSTURN = 0 tw(CLK) tw(CLK) FMC_CLK Data latency = 0 td(CLKL-NExL) td(CLKH-NExH) FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FMC_NADV td(CLKH-AIV) td(CLKL-AV) FMC_A[25:16] td(CLKH-NWEH) td(CLKL-NWEL) FMC_NWE td(CLKL-ADIV) td(CLKL-ADV) FMC_AD[15:0] td(CLKL-Data) td(CLKL-Data) AD[15:0] D1 D2 FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKH-NBLH) FMC_NBL MS32758V1 178/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Table 63. Synchronous multiplexed PSRAM write timings(1) Symbol tw(CLK) td(CLKL-NExL) Parameter FMC_CLK period, VDD range = 2.7 to 3.6 V FMC_CLK low to FMC_NEx low (x=0..2) Min Max RxTfmc_ker_ck-1(2) - - 1 td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 - FMC_CLK low to FMC_Ax valid (x=16...25) - td(CLKL-AV) td(CLKH-AIV) td(CLKL-NWEL) FMC_CLK high to FMC_Ax invalid (x=16...25) FMC_CLK low to FMC_NWE low RxTfmc_ker_ck/2+0.5 (2) RxTfmc_ker_ck/2+1.5 - 1 (2) - - 1 RxTfmc_ker_ck/2+0.5(2) - t(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 1.5 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 1 - td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 1 - RxTfmc_ker_ck/2+0.5(2) - 3 - 1.5 - td(CLKH-NBLH) FMC_CLK high to FMC_NBL high tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high Unit ns 1. Guaranteed by characterization results. 2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period). DS12500 Rev 1 179/245 228 Electrical characteristics STM32MP151A Figure 29. Synchronous non-multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK) FMC_CLK td(CLKL-NExL) td(CLKH-NExH) Data latency = 0 FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FMC_NADV td(CLKH-AIV) td(CLKL-AV) FMC_A[25:0] td(CLKL-NOEL) td(CLKH-NOEH) FMC_NOE tsu(DV-CLKH) th(CLKH-DV) tsu(DV-CLKH) FMC_D[15:0] D1 tsu(NWAITV-CLKH) FMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) D2 th(CLKH-NWAITV) tsu(NWAITV-CLKH) FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-DV) t h(CLKH-NWAITV) th(CLKH-NWAITV) MS32759V1 Table 64. Synchronous non-multiplexed NOR/PSRAM read timings(1) Symbol Parameter Min tw(CLK) FMC_CLK period RxTfmc_ker_ck t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) Max -1(2) - - 1 RxTfmc_ker_ck/2+0.5(2) - td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) - 1 RxTfmc_ker_ck/2+1.5(2) - - 2 RxTfmc_ker_ck/2+1.5(2) - td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKH-NOEH) FMC_CLK high to FMC_NOE high tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 3 - th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 1 - t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 - 1. Guaranteed by characterization results. 180/245 DS12500 Rev 1 Unit ns STM32MP151A Electrical characteristics 2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period). Figure 30. Synchronous non-multiplexed PSRAM write timings tw(CLK) tw(CLK) FMC_CLK td(CLKL-NExL) td(CLKH-NExH) Data latency = 0 FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FMC_NADV td(CLKH-AIV) td(CLKL-AV) FMC_A[25:0] td(CLKL-NWEL) td(CLKH-NWEH) FMC_NWE td(CLKL-Data) td(CLKL-Data) D1 FMC_D[15:0] D2 FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH) th(CLKH-NWAITV) FMC_NBL MS32760V1 DS12500 Rev 1 181/245 228 Electrical characteristics STM32MP151A Table 65. Synchronous non-multiplexed PSRAM write timings(1) Symbol Parameter t(CLK) FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) Min Max RxTfmc_ker_ck -1(2) - - 1 t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) - td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NWEL) FMC_CLK low to FMC_NWE low td(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-Data) RxTfmc_ker_ck/2+0.5 (2) RxTfmc_ker_ck/2+1.5 Unit - 1 (2) - - 1 RxTfmc_ker_ck/2+0.5(2) - FMC_D[15:0] valid data after FMC_CLK low - 3 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 1 - td(CLKH-NBLH) FMC_CLK high to FMC_NBL high RxTfmc_ker_ck/2+0.5(2) - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 - ns 1. Guaranteed by characterization results. 2. Clock ratio R = (FMC_CLK period / fmc_ker_ck period). NAND controller waveforms and timings Figure 31 through Figure 34 represent synchronous waveforms, and Table 66 and Table 67 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: * FMC_SetupTime = 0x01 * FMC_WaitSetupTime = 0x03 * FMC_HoldSetupTime = 0x02 * FMC_HiZSetupTime = 0x01 * Bank = FMC_Bank_NAND * MemoryDataWidth = FMC_MemoryDataWidth_16b * ECC = FMC_ECC_Enable * ECCPageSize = FMC_ECCPageSize_512Bytes * TCLRSetupTime = 0 * TARSetupTime = 0 * CL = 30 pF In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period. 182/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Figure 31. NAND controller waveforms for read access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) FMC_NWE td(ALE-NOE) th(NOE-ALE) FMC_NOE (NRE) tsu(D-NOE) th(NOE-D) FMC_D[15:0] MS32767V1 Figure 32. NAND controller waveforms for write access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) th(NWE-ALE) td(ALE-NWE) FMC_NWE FMC_NOE (NRE) tv(NWE-D) th(NWE-D) FMC_D[15:0] MS32768V1 DS12500 Rev 1 183/245 228 Electrical characteristics STM32MP151A Figure 33. NAND controller waveforms for common memory read access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) th(NOE-ALE) td(ALE-NOE) FMC_NWE tw(NOE) FMC_NOE tsu(D-NOE) th(NOE-D) FMC_D[15:0] MS32769V1 Figure 34. NAND controller waveforms for common memory write access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) td(ALE-NOE) tw(NWE) th(NOE-ALE) FMC_NWE FMC_N OE td(D-NWE) tv(NWE-D) th(NWE-D) FMC_D[15:0] MS32770V1 Table 66. Switching characteristics for NAND Flash read cycles(1) Symbol Parameter Min Max 4Tfmc_ker_ck-1 4Tfmc_ker_ck+1 tw(N0E) FMC_NOE low width tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 11 - th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 2Tfmc_ker_ck+1 th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 3Tfmc_ker_ck+0.5 - 1. Guaranteed by characterization results. 184/245 DS12500 Rev 1 Unit ns STM32MP151A Electrical characteristics Table 67. Switching characteristics for NAND Flash write cycles(1) Symbol Parameter tw(NWE) FMC_NWE low width tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid td(D-NWE) FMC_D[15-0] valid before FMC_NWE high td(ALE-NWE) FMC_ALE valid before FMC_NWE low th(NWE-ALE) FMC_NWE high to FMC_ALE invalid Min Max 4Tfmc_ker_ck-1 4Tfmc_ker_ck+1 0 - 3Tfmc_ker_ck - 4Tfmc_ker_ck-3 - - 2Tfmc_ker_ck+1 3Tfmc_ker_ck+0.5 - Unit ns 1. Guaranteed by characterization results. 6.3.19 QUADSPI interface characteristics Unless otherwise specified, the parameters given in Table 68 and Table 69 for QUADSPI are derived from tests performed under the ambient temperature, Faxiss_ck frequency and VDD supply voltage conditions summarized in Table 13: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Measurement points are done at CMOS levels: 0.5xVDD * I/O compensation cell enabled * HSLV activated when VDD 2.7 V Refer to Section 0.3.16: I/O port characteristics for more details on the input/output alternate function characteristics. Table 68. QUADSPI characteristics in SDR mode Symbol Fck1/t(CLK) tw(CLKH) Parameter QUADSPI clock frequency Conditions Min Typ Max 2.7 V VDD < 3.6 V CL = 20 pF - - 166 1.71 V < VDD <3.6 V CL = 15 pF - - 90 t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5 t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5 MHz QUADSPI clock high and low time - ts(IN) Data input setup time - 1.25 - - th(IN) Data input hold time - 2.75 - - tv(OUT) Data output valid time - - 1 1.5 th(OUT) Data output hold time - 0 - - tw(CLKL) DS12500 Rev 1 Unit ns 185/245 228 Electrical characteristics STM32MP151A Table 69. QUADSPI characteristics in DDR mode Symbol Min Typ Max 2.7 V < VDD < 3.6 V CL=20 pF - - 90 1.71 V < VDD < 3.6 V CL=15 pF - - 90 - t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5 - t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5 tsr(IN), tsf(IN) Data input setup time - 0.5 - - thr(IN), thf(IN) Data input hold time - 2.75 - - DHHC = 0 - 1 1.5 DHHC = 1 Pres = 1, 2... - t(CLK)/4+1 t(CLK)/4+1.5 DHHC = 0 0 - - t(CLK)/4 - - Fck1/t(CLK) tw(CLKH) tw(CLKL) Parameter Conditions QUADSPI clock frequency QUADSPI clock high and low time tvr(OUT), tvf(OUT) Data output valid time thr(OUT), thf(OUT) Data output hold time Unit MHz DHHC = 1 Pres = 1, 2... ns Figure 35. QUADSPI timing diagram - SDR mode tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK) Clock tv(OUT) th(OUT) Data output IO1 IO0 ts(IN) Data input IO0 IO2 th(IN) IO1 IO2 MSv36878V2 Figure 36. QUADSPI timing diagram - DDR mode tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK) Clock tvf(OUT) Data output thr(OUT) IO0 tvr(OUT) IO1 IO2 thf(OUT) IO3 tsf(IN) thf(IN) Data input IO0 IO1 IO4 IO5 tsr(IN) thr(IN) IO2 IO3 IO4 IO5 MSv36879V2 186/245 DS12500 Rev 1 STM32MP151A 6.3.20 Electrical characteristics Delay block (DLYB) characteristics Unless otherwise specified, the parameters given in Table 70 for the delay block are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 13: General operating conditions. Table 70. Dynamics characteristics: Delay block characteristics Symbol 6.3.21 Parameter Conditions Min Typ Max tinit Initial delay - 900 1200 1500 t Unit Delay - 42 46 50 Unit ps 16-bit ADC characteristics Unless otherwise specified, the parameters given in Table 71 are derived from tests performed under the ambient temperature, fpclk2 frequency and VDDA supply voltage conditions summarized in Table 13: General operating conditions. Table 71. ADC characteristics(1)(2) Symbol Parameter VDDA Analog power supply VREF+ Positive reference voltage VREF- Negative reference voltage fADC ADC clock frequency Conditions Min Typ Max - 1.62 - 3.6 2 - VDDA VDDA 2 V VDDA < 2 V VDDA - 2 V VDDA 3.3 V Unit V VSSA BOOST = 1 - - 36 BOOST = 0 - - 20 DS12500 Rev 1 MHz 187/245 228 Electrical characteristics STM32MP151A Table 71. ADC characteristics(1)(2) (continued) Symbol Parameter Min Typ Max 16-bit resolution - - 3.60 14-bit resolution - - 4.00 12-bit resolution - - 4.50 10-bit resolution - - 5.00 8-bit resolution - - 6.00 16-bit resolution - - 2.00 14-bit resolution - - 2.20 12-bit resolution - - 2.50 10-bit resolution - - 2.80 8-bit resolution - - 3.30 16-bit resolution - - 2.55 14-bit resolution - - 2.80 12-bit resolution - - 3.11 10-bit resolution - - 3.50 8-bit resolution - - 4.00 16-bit resolution - - 1.82 14-bit resolution - - 2.00 12-bit resolution - - 2.22 10-bit resolution - - 2.50 8-bit resolution - - 2.86 fADC = 36 MHz - - 3.6 MHz 16-bit resolution - - 10 1/fADC Conversion voltage range - 0 - VREF+ VCMIV Common mode input voltage - CADC Internal sample and hold capacitor - - 4 - pF tADCREG_ ADC LDO startup time - - 5 10 s Sampling rate for Fast channels, BOOST = 1, fADC = 36 MHz, sampling time = 1.5 cycles Sampling rate for Fast channels, BOOST = 0, fADC = 20 MHz, sampling time = 1.5 cycles fS Sampling rate for Slow channels, BOOST = 1, fADC = 28 MHz, sampling time = 2.5 cycles Sampling rate for Slow channels, BOOST = 0, fADC = 20 MHz, sampling time = 2.5 cycles fTRIG VAIN (3) STUP tSTAB 188/245 External trigger frequency ADC power-up time Conditions LDO already started DS12500 Rev 1 /2+ V VREF/2VREF/2 REF 10% 10% 1 Unit MSPS V 1/fADC STM32MP151A Electrical characteristics Table 71. ADC characteristics(1)(2) (continued) Symbol Parameter Conditions Min Typ tCAL Offset and linearity calibration time - 16384 tOFF_CAL Offset calibration time - 1280 tLATR Trigger conversion latency for regular and injected channels without aborting the conversion tLATRINJ Trigger conversion latency for regular and injected channels when a regular conversion is aborted tS Sampling time tCONV Total conversion time (including sampling time) IDDA(ADC) ADC consumption from VDDA supply (differential) IDDA(REF) ADC consumption from VREF+ (differential) IDDA(ADC) CKMODE = 00 1.5 2 2.5 CKMODE = 01 - - 2.5 CKMODE = 10 - - 2.5 CKMODE = 11 - - 2.25 CKMODE = 00 2.5 3 3.5 CKMODE = 01 - - 3.5 CKMODE = 10 - - 3.5 CKMODE = 11 - - 3.25 1.5 - 810.5 - - 1900 - FS = 1 Msps, BOOST = 0 - 460 - FS = 3.6 Msps, BOOST = 1 - 260 - FS = 1 Msps, BOOST = 0 - 140 - FS = 3.6 Msps, BOOST = 1 ADC consumption from VDDA supply (single-ended) F = 1 Msps, BOOST = 0 S - 1700 - - 445 - FS = 3.6 Msps, BOOST = 1 - 160 - FS = 1 Msps, BOOST = 0 - 75 - FS = 3.6 Msps - 250 - FS = 1 Msps - 50 - ADC consumption from VDD supply Unit 1/fADC ts + N/2(4) N-bit resolution FS = 3.6 Msps, BOOST = 1 ADC consumption from IDDA(REF) VREF+ supply (singleended) IDD(ADC) Max A 1. Guaranteed by design. 2. Voltage BOOSTER on ADC switches must be used for VDDA < 2.4 V (switches inside IO). 3. Depending on the package, VREF- can be internally connected to VSSA. 4. 9 to 818 cycles @ 14-bit mode. DS12500 Rev 1 189/245 228 Electrical characteristics STM32MP151A Table 72. Minimum sampling time versus RAIN with 47 pF PCB capacitor up to 125 C and VDDA = 1.6 V(1) Resolution(2) RAIN () Fast channels(3) Slow channels(4) 16 bits 47(5) 1.07E-07 1.66E-07 47 9.08E-08 1.44E-07 68 9.67E-07 1.51E-07 100 1.08E-07 1.57E-07 150 1.28E-07 1.71E-07 1.61E-07 1.92E-07 47 7.67E-08 1.25E-07 68 8.15E-08 1.27E-07 100 8.98E-08 1.34E-07 150 1.07E-07 1.46E-07 220 1.32E-07 1.69E-07 330 1.77E-07 2.05E-07 470 2.36E-07 2.64E-07 680 3.29E-07 3.45E-07 1000 4.62E-07 4.88E-07 47 6.25E-08 1.03E-07 68 6.62E-08 1.06E-07 100 7.27E-08 1.12E-07 150 8.54E-08 1.21E-07 220 1.06E-07 1.37E-07 330 1.40E-07 1.68E-07 470 1.87E-07 2.09E-07 680 2.58E-07 2.79E-07 1000 3.67E-07 3.81E-07 1500 5.37E-07 5.52E-07 2200 7.76E-07 7.86E-07 3300 1.13E-06 1.14E-06 1.60E-06 1.60E-06 14 bits 220 12 bits (5) (5) 10 bits (5) 4700 190/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Table 72. Minimum sampling time versus RAIN with 47 pF PCB capacitor up to 125 C and VDDA = 1.6 V(1) (continued) Resolution(2) 8 bits RAIN () Fast channels(3) Slow channels(4) 47 4.87E-08 8.24E-08 68 5.14E-08 8.46E-08 100 5.64E-08 8.87E-08 150 6.58E-08 9.57E-08 220 8.04E-08 1.08E-07 330 1.06E-07 1.30E-07 470 1.39E-07 1.60E-07 680 1.89E-07 2.08E-07 1000 2.69E-07 2.84E-07 1500 3.90E-07 4.05E-07 2200 5.62E-07 5.72E-07 3300 8.27E-07 8.40E-07 4700 1.17E-06 1.17E-06 6800 1.67E-06 1.67E-06 10000 2.44E-06 2.43E-06 15000 3.66E-06 3.63E-06 (5) 5.36E-06 5.31E-06 2200 1. Guaranteed by design. 2. The tolerance is 8 LSB for 16-bit, 4 LSB for 14-bit, 2 LSB for 12-bit, 10-bit and 8-bit conversions. 3. On ADC1, fast channels are PA6, PA7, PB0, PB1, PC4, PC5, PF11, PF12. On ADC2, fast channels are PA6, PA7, PB0, PB1, PC4, PC5, PF13, PF14. 4. Slow channels are all ADC inputs except the fast channels. 5. Maximum external input impedance value authorized for the given resolution. DS12500 Rev 1 191/245 228 Electrical characteristics STM32MP151A Table 73. ADC accuracy(1)(2)(3)(4)(5)(6)(7) Symbol ET(10) Conditions(8) Parameter Total unadjusted error Single ended Differential Single ended ED Differential linearity error Differential Single ended EL Integral linearity error Differential ENOB(11) SINAD(11) SNR(11) THD(11) Effective number of bits (2 MSPS) Signal-tonoise and distortion ratio (2 MSPS) Signal-tonoise ratio (2 MSPS) Total harmonic distortion Single ended Differential Single ended Differential Single ended Differential Single ended Differential Min Typ(9) Max BOOST = 1 - 5 - BOOST = 0 - 7 - BOOST = 1 - 6 - BOOST = 0 - 5 - BOOST = 1 - 3 - BOOST = 0 - 1 - BOOST = 1 - 8 - BOOST = 0 - 2 - BOOST = 1 - 6 - BOOST = 0 - 4 - BOOST = 1 - 6 - BOOST = 0 - 4 - BOOST = 1 - 12.5 - BOOST = 0 - 12.75 - BOOST = 1 - 13.3 - BOOST = 0 - 13.7 - BOOST = 1 - 77.5 - BOOST = 0 - 78.75 - BOOST = 1 - 82 - BOOST = 0 - 84.2 - BOOST = 1 - 77.6 - BOOST = 0 - 79 - BOOST = 1 - 82.4 - BOOST = 0 - 84.3 - BOOST = 1 - -85 - BOOST = 0 - -88 - BOOST = 1 - -90 - BOOST = 0 - -93 - Unit LSB bits dB 1. Guaranteed by characterization. 2. ADC DC accuracy values are measured after internal calibration. 3. ADC accuracy versus negative injection current: injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. 4. The above table gives the ADC performance in 16-bit mode. 5. Dual Simultaneous mode is limited to 12-bit. 6. Dual mode consisting in an injected conversion (reset) occurring during another (regular) conversion is forbidden. 7. Dual Interleaved 16-bit/14-bit/12-bit modes can work if the delay between the 2 ADCs is as specified in Table 74. 192/245 DS12500 Rev 1 STM32MP151A Electrical characteristics 8. ADC clock frequency 36 MHz, 2 V VDDA 3.3 V, 1.6 V VREF+ VDDA, BOOSTEN (for I/O) = 1. 9. VDDA = VREF+ = 3.3 V, 25 C. 10. ET, ED, EL are specified for [2 V VDDA 3.3 V with 2 V VREF+ VDDA] and [1.6V VDDA 2 V with 1.6V VREF+ VDDA]. 11. ENOB, SINAD, SNR and THD are specified for VDDA = VREF+ = 3.3 V. Table 74. Minimum delay for interleaved conversion versus resolution 16-bit Mode Boost Fclk (MHz) 14-bit mode 12-bit Mode Delay ADC1/ADC2 (clock cycles) Data rate (MSPS) Delay ADC1/ADC2 (clock cycles) Data rate (MSPS) Delay ADC1/ADC2 (clock cycles) Data rate (MSPS) 0 1 1.5 1.0 1.5 1.0 1.5 1.0 0 2 1.5 2.0 1.5 2.0 1.5 2.0 0 3 1.5 1.5 1.5 1.5 1.5 1.5 0 4 1.5 2.0 1.5 2.0 1.5 2.0 0 5 1.5 1.7 1.5 1.7 1.5 2.5 0 6 1.5 2.0 1.5 2.0 1.5 2.0 0 7 2.5 1.8 1.5 2.3 1.5 2.3 0 8 2.5 2.0 2.5 2.0 1.5 2.7 0 9 3.5 1.8 2.5 2.3 2.5 2.3 0 10 3.5 2.0 3.5 2.0 2.5 2.5 0 11 4.5 1.8 3.5 2.2 2.5 2.8 0 12 4.5 2.0 4.5 2.0 3.5 2.4 0 13 4.5 2.2 4.5 2.2 3.5 2.6 0 14 4.5 2.3 4.5 2.3 3.5 2.8 0 15 5.5 2.1 4.5 2.5 3.5 3.0 0 16 5.5 2.3 4.5 2.7 3.5 3.2 0 17 5.5 2.4 4.5 2.8 3.5 3.4 0 18 5.5 2.6 4.5 3.0 3.5 3.6 0 19 5.5 2.7 4.5 3.2 3.5 3.8 0 20 5.5 2.9 4.5 3.3 3.5 4.0 1 21 4.5 3.5 3.5 4.2 3.5 4.2 1 22 4.5 3.7 3.5 4.4 3.5 4.4 1 23 4.5 3.8 3.5 4.6 3.5 4.6 1 24 4.5 4.0 4.5 4.0 3.5 4.8 1 25 4.5 4.2 4.5 4.2 3.5 5.0 1 26 4.5 4.3 4.5 4.3 3.5 5.2 1 27 5.5 3.9 4.5 4.5 3.5 5.4 DS12500 Rev 1 193/245 228 Electrical characteristics STM32MP151A Table 74. Minimum delay for interleaved conversion versus resolution (continued) 16-bit Mode Boost Fclk (MHz) 14-bit mode 12-bit Mode Delay ADC1/ADC2 (clock cycles) Data rate (MSPS) Delay ADC1/ADC2 (clock cycles) Data rate (MSPS) Delay ADC1/ADC2 (clock cycles) Data rate (MSPS) 1 28 5.5 4.0 4.5 4.7 3.5 5.6 1 29 5.5 4.1 4.5 4.8 3.5 5.8 1 30 5.5 4.3 4.5 5.0 3.5 6.0 1 31 5.5 4.4 4.5 5.2 3.5 6.2 1 32 5.5 4.6 4.5 5.3 3.5 6.4 1 33 5.5 4.7 4.5 5.5 3.5 6.6 1 34 5.5 4.9 4.5 5.7 3.5 6.8 1 35 5.5 5.0 4.5 5.8 3.5 7.0 1 36 5.5 5.1 4.5 6.0 3.5 7.2 Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 0.3.16 does not affect the ADC accuracy. 194/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Figure 37. ADC accuracy characteristics [1LSB IDEAL = V REF+ 4096 (or V DDA 4096 depending on package)] EG 4095 4094 4093 (2) ET (3) 7 (1) 6 5 EO 4 EL 3 ED 2 1L SBIDEAL 1 0 1 2 3 456 7 V SSA 4093 4094 4095 4096 VDDA ai14395c 1. Example of an actual transfer curve. 2. Ideal transfer curve. 3. End point correlation line. 4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 38. Typical connection diagram using the ADC STM32 VDD RAIN(1) AINx VAIN Cparasitic Sample and hold ADC converter VT 0.6 V RADC(1) VT 0.6 V IL1 A 12-bit converter C ADC(1) ai17534b 1. Refer to Table 71 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. DS12500 Rev 1 195/245 228 Electrical characteristics STM32MP151A General PCB design guidelines PCB design guidelines are provided in AN5031 "Getting started with STM32MP1 Series hardware development." available from the ST website www.st.com. 6.3.22 DAC electrical characteristics Table 75. DAC characteristics(1) Symbol Parameter Conditions Min Typ Max VDDA Analog supply voltage - 1.8 3.3 3.6 VREF+ Positive reference voltage - 1.80 - VDDA VREF- Negative reference voltage - - VSSA - connected to VSSA 5 - - connected to VDDA 25 - - 10.3 13 16 RL Resistive Load DAC output buffer ON, Not valid in Sample & Hold mode V k RO Output Impedance Output impedance sample DAC output and hold mode, output buffer ON buffer ON VDD = 2.7 V - - 1.6 RBON VDD = 2.0 V - - 2.6 Output impedance sample DAC output and hold mode, output buffer OFF buffer OFF VDD = 2.7 V - - 17.8 RBOFF VDD = 2.0 V - - 18.7 DAC output buffer OFF - - 50 pF Sample and Hold mode - 0.1 1 F DAC output buffer ON 0.2 - VDDA -0.2(2) V DAC output buffer OFF 0 - VREF+ - TBD - - 2 - - TBD - - TBD - - TBD - - 2 - - 5 - CL CSH VDAC_OUT tSETTLING Capacitive Load Voltage on DAC_OUT output DAC output buffer OFF Unit 0.5 LSB Normal mode, Settling time (full scale: for 1 LSB DAC output a 12-bit code transition 2 LSB buffer ON, between the lowest and CL 10 pF the highest input codes 4 LSB when DAC_OUT reaches RL 5 k 8 LSB the final value of 0.5LSB, 1LSB, 2LSB, 4LSB, Normal mode, 8LSB) DAC output buffer OFF, k k s +/-1LSB, Cload 10 pF Normal mode, DAC output buffer ON, Wakeup time from off state (setting the Enx bit in CL 50 pF, RL 5 k tWAKEUP(3) the DAC Control register) Normal mode, until the 1LSB final value DAC output buffer OFF, CL 10 pF 196/245 DS12500 Rev 1 s 2 STM32MP151A Electrical characteristics Table 75. DAC characteristics(1) (continued) Symbol Parameter PSRR VDDA supply rejection ratio tSAMP Sampling time in Sample and Hold mode CSH=100nF (Code transition between the lowest input code and the highest input code when DAC_OUT reaches final value 1LSB) CIint Internal sample and hold capacitor Voffset Middle code offset for 1 trim code step Conditions Normal mode DAC output buffer ON CL 50 pF, RL = 5 k DC IDDA(DAC) 100/101 (BUFFER ON) Unit - -80 - dB - 0.7 - DACMCR.MODEx[2:0] = 111 (INTERNAL BUFFER OFF) ms 11.5 (BUFFER OFF) - 0.3 - - 2.2 - VREF+ = 3.6 V - 450 - VREF+ = 1.8 V - 213 - No load, middle code (0x800) - TBD - No load, worst code (0xF1C) - TBD - No load, middle/worst code (0x800) - TBD - - TBD - No load, middle code (0x800) - TBD - No load, worst code (0xF1C) - TBD - No load, middle/worst code (0x800) - TBD - Sample and Hold mode, Buffer ON, CSH = 100 nF (worst code) - TBD - Sample and Hold mode, Buffer OFF, CSH = 100 nF (worst code) - TBD - - DAC output buffer OFF DAC output buffer ON DAC consumption from VREF+ Max DACMCR.MODEx[2:0] = 110 Sample and Hold mode, CSH = 100 nF IDDV(DAC) Typ DACMCR.MODEx[2:0] = DAC output buffer ON DAC quiescent consumption from VDDA Min DAC output buffer OFF s V A 1. Guaranteed by design. 2. Since VREF+ must always be VDDA, maximum VDAC_OUT = minimum value between Max(VREF+) and Max(VDDA-0.2) 3. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value). DS12500 Rev 1 197/245 228 Electrical characteristics STM32MP151A Table 76. DAC accuracy Symbol Parameter DNL Differential non linearity(2) INL Integral non linearity(3) Offset Offset error at code 0x800 (3) Min Typ(1) Max DAC output buffer ON - 2 TBD DAC output buffer OFF - 2 TBD DAC output buffer ON, CL50 pF, RL5 k - 4 TBD DAC output buffer OFF, CL 50 pF, no RL - 4 TBD VREF+ = 3.6 V - 12 TBD VREF+ = 1.8 V - 25 TBD DAC output buffer OFF, CL 50 pF, no RL - 8 TBD - 5 TBD VREF+ = 3.6 V - 5 TBD VREF+ = 1.8 V - 7 TBD DAC output buffer ON, CL 50 pF, RL 5 k - 1 TBD DAC output buffer OFF, CL 50 pF, no RL - 1 TBD DAC output buffer ON, CL 50 pF, RL 5 k - 30 TBD Conditions DAC output buffer ON, CL 50 pF, RL 5 k Offset1 Offset error at code 0x001(4) DAC output buffer OFF, CL 50 pF, no RL OffsetCal Offset error at code 0x800 after factory calibration DAC output buffer ON, CL 50 pF, RL 5 k Gain TUE Gain error(5) Total unadjusted error VREF+=3.6 V TUECal SNR DAC output buffer Signal-toON,CL 50 pF, RL 5 k, (6) noise ratio 1 kHz, BW = 500 kHz THD Total harmonic distorsion(6) 198/245 DAC output buffer ON, CL 50 pF, RL 5 k LSB LSB LSB LSB LSB % LSB DAC output buffer OFF, CL 50 pF, no RL Total unadjusted error after calibration Unit - VREF+=1.8 V - DAC output buffer ON, CL 50 pF, RL 5 k, 1kHz DS12500 Rev 1 12 TBD 10 TBD 8 TBD 67.8 - -78.6 LSB dB dB STM32MP151A Electrical characteristics Table 76. DAC accuracy (continued) Symbol Parameter Conditions Min Typ(1) Max Unit SINAD Signal-tonoise and distortion ratio(6) DAC output buffer ON, CL 50 pF, RL 5 k, 1 kHz - 67.5 - dB ENOB Effective number of bits DAC output buffer ON, CL 50 pF, RL 5 k, 1 kHz - 10.9 - bits 1. Guaranteed by characterization. 2. Difference between two consecutive codes minus 1 LSB. 3. Difference between measured the value at Code i and the value measured at Code i on a line drawn between Code 0 and last Code 4095. 4. Difference between the value measured at Code (0x001) and the ideal value. 5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON. 6. Signal is -0.5dBFS with Fsampling=1 MHz. Figure 39. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) RL DAC_OUTx 12-bit digital to analog converter CL ai17157V3 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. DS12500 Rev 1 199/245 228 Electrical characteristics 6.3.23 STM32MP151A Voltage reference buffer characteristics Table 77. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA Analog supply voltage Degraded mode Normal mode VREFBUF Voltage Reference Buffer Output _OUT Degraded mode Min Typ Max VSCALE = 000 2.8 3.3 3.6 VSCALE = 001 2.4 - 3.6 VSCALE = 010 2.1 - 3.6 VSCALE = 011 1.8 - 3.6 VSCALE = 000 1.62 - 2.80 VSCALE = 001 1.62 - 2.40 VSCALE = 010 1.62 - 2.10 VSCALE = 011 1.62 - 1.80 VSCALE = 000 - 2.5 - VSCALE = 001 - 2.048 - VSCALE = 010 - 1.8 - VSCALE = 011 - 1.5 - VSCALE = 000 VDDA220 mV - 2.5 VSCALE = 001 VDDA220 mV - 2.048 VSCALE = 010 VDDA220 mV - 1.8 VSCALE = 011 VDDA220 mV - 1.5 (2) Unit V TRIM Trim step resolution - - - 0.05 - % CL Load capacitor - - 0.5 1 1.50 uF esr Equivalent Serial Resistor of CL - - - - 2 Iload Static load current - - - - 4 mA Iline_reg Line regulation 2.8 V VDDA 3.6 V Iload = 500 A - 200 - Iload = 4 mA - 100 - Iload_reg Load regulation 500 A ILOAD 4 mA Normal Mode - 50 - ppm/V ppm/ mA Tcoeff_ Tcoeff PSRR 200/245 Temperature coefficient Power supply rejection -40 C < TJ < +125 C - - VREF INT - +75 0 C < TJ < +50 C - - TBD - DC - - 60 - 100 kHz - - 40 - DS12500 Rev 1 ppm/ C dB STM32MP151A Electrical characteristics Table 77. VREFBUF characteristics(1) (continued) Symbol tSTART IINRUSH IDDA(VRE FBUF) Parameter Conditions Start-up time Typ Max CL = 0.5 F - - 300 - CL = 1 F - - 500 - CL = 1.5 F - - 650 - - 8 - Control of maximum DC current drive on VREFBUF_OUT during startup phase(3) VREFBUF consumption from VDDA Min - ILOAD = 0 A - - 15 - ILOAD = 500 A - - 16 - ILOAD = 4 mA - - 32 - Unit s mA A 1. Guaranteed by design. 2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA-drop voltage). 3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively. 6.3.24 Temperature sensor characteristics Table 78. Temperature sensor characteristics Symbol TL(1) Avg_Slope(2) V30(3) tstart_run (1) Parameter Min Typ Max VSENSE linearity with temperature (from Vsensor voltage) - - 3 VSENSE linearity with temperature (from ADC counter) - - 3 Average slope (from Vsensor voltage) - 2 - Average slope (from ADC counter) - 2 - Voltage at 30 C 5 C - 0.62 - Startup time in Run mode (buffer startup) 5.3 - 40.5 tS_temp(1) ADC sampling time when reading the temperature 9.8 - - Isens(1) Sensor consumption 0.11 0.18 0.31 Isensbuf(1) Sensor buffer consumption 2.3 3.8 6.1 Unit C mV/C V s A 1. Guaranteed by design. 2. Guaranteed by characterization. 3. Measured at VDDA = 3.3 V 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. DS12500 Rev 1 201/245 228 Electrical characteristics STM32MP151A Table 79. Temperature sensor calibration values Symbol Parameter Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 C 5 C VDDA = VREF+ = 3.3 V 10 mV 0x5C00 525C[15:0](1)(2) TS_CAL2 TS ADC raw data acquired at temperature of 130 C 2 C VDDA = VREF+ = 3.3 V 10 mV 0x5C00 525C[31:16](1)(2) 1. It is mandatory to read a 32-bit word and to do relevant masking and shifting to isolate the required bits. 2. This address is located inside the BSEC and the access is allowed after being enabled in the RCC. 6.3.25 DTS characteristics Table 80. DTS characteristics(1) Symbol Parameter fDTP TL TTOTAL_ ERROR (2) Conditions Max Unit Output Clock frequency (PTAT dependency) TBD TBD TBD kHz Linearity with temperature (from Output clock frequency). Temperature error at 1.1 V TBD TBD TBD C TBD TBD TBD C Temperature offset measurement Min Temperature: -40 to 125 C Typ CORE Additional error due to supply variation - 10 - C/V tTRIM Calibration time 2 - - ms tWAKE_UP Wake-up time from off state until DTP ready signal = 1 - 50 - s IDDCORE_DTP DTP consumption on VDDCORE - 20 TBD A TVDD 1. Guaranteed by design. 2. Guaranteed by characterization. 6.3.26 VBAT ADC monitoring characteristics and charging characteristics Table 81. VBAT ADC monitoring characteristics Symbol R Q Er (1) tS_vbat(1) Parameter Min Typ Max Unit Resistor bridge for VBAT - TBD - k Ratio on VBAT measurement - 4 - - Error on Q -10 - +10 % ADC sampling time when reading VBAT input 9.8 - - s 1. Guaranteed by design. 202/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Table 82. VBAT charging characteristics Symbol RBC 6.3.27 Parameter Condition Battery charging resistor Min Typ Max VBRS in PWR_CR3= 0 - 5 - VBRS in PWR_CR3= 1 - 1.5 - Unit k Temperature and VBAT monitoring characteristics for temper detection Table 83. Temperature and VBAT monitoring characteristics for temper detection Symbol 6.3.28 Parameter Min Typ Max TEMPhigh High temperature monitoring TBD 116 TBD TEMPlow Low temperature monitoring TBD -31 TBD VBAThigh High supply monitoring (with BKUPREGs ON) TBD 3.59 TBD VBATlow Low supply monitoring (with BKUPREGs ON) TBD 1.34 TBD VBAThigh High supply monitoring (with BKUPREGs OFF) TBD 3.59 TBD VBATlow Low supply monitoring (with BKUPREGs OFF) TBD 1.34 TBD Unit oC V V VDDCORE monitoring characteristics Table 84. VDDCORE monitoring characteristics Symbol tS_vddcore(1) Parameter Min ADC sampling time when reading VDDCORE input 100 Typ Max Unit - - ns 1. Guaranteed by design. 6.3.29 Voltage booster for analog switch Table 85. Voltage booster for analog switch characteristics Symbol VDD Parameter Condition Min - 1.71 - 3.6 V - - - TBD s 1.71 V VDD 2.7 V - - TBD 2.7 V < VDD < 3.6 V - - TBD Supply voltage tSU(BOOST) Booster startup time IDD(BOOST) Booster consumption DS12500 Rev 1 Typ Max Unit A 203/245 228 Electrical characteristics 6.3.30 STM32MP151A Digital filter for sigma-delta modulators (DFSDM) characteristics Unless otherwise specified, the parameters given in Table 86 for DFSDM are derived from tests performed under the ambient temperature, fpclkx frequency and VDD supply voltage summarized in Table 13: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5xVDD Refer to Section 0.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (DFSDMx_CKINx, DFSDMx_DATINx, DFSDMx_CKOUT for DFSDMx). Table 86. DFSDM measured timing Symbol fDFSDMCLK fCKIN (1/TCKIN) fCKOUT Parameter DFSDM clock Input clock frequency Output clock frequency Output clock DuCyCKOUT frequency duty cycle 204/245 Conditions Min Typ Max 1.71 V < VDD < 3.6 V - - fSYSCLK SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.71 V < VDD < 3.6 V - - 20 (fDFSDMCLK/4) SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 2.7 < VDD < 3.6 V - - 20 (fDFSDMCLK/4) MHz SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0]0), 1.71 < VDD < 3.6 V - - SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0]0), 2.7 < VDD < 3.6 V - - 20 (fDFSDMCLK/4) 1.71 < VDD < 3.6 V - - 20 1.71 < VDD < 3.6 V 45 50 55 DS12500 Rev 1 Unit 20 (fDFSDMCLK/4) % STM32MP151A Electrical characteristics Table 86. DFSDM measured timing (continued) Symbol Parameter Conditions Min Typ Max twh(CKIN) twl(CKIN) Input clock high and low time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.71 < VDD < 3.6 V TCKIN/2 - 0.5 TCKIN/2 - tsu Data input setup time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.71 < VDD < 3.6 V 1 - - th Data input hold time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.71 < VDD < 3.6 V TManchester Manchester mode Manchester data (SITP[1:0]=2,3), period (recovered Internal clock mode clock period) (SPICKSEL[1:0]0), 1.71 < VDD < 3.6 V Unit ns 0.5 - - (CKOUTDIV+1) xTDFSDMCLK(1) - (2xCKOUTDIV) x TDFSDMCLK(1) 1. See DFSDM section in RM0441 reference manual for definition of CKOUTDIV. DS12500 Rev 1 205/245 228 Electrical characteristics STM32MP151A DFSDM_CKINy DFSDM_DATINy DFSDM_CKOUT (SPICKSEL=0) tsu th twl twh tr tf tr tf SITP = 00 tsu th SITP = 01 SPICKSEL=3 SPICKSEL=2 SPICKSEL=1 tsu DFSDM_DATINy SPI timing : SPICKSEL = 1, 2, 3 SPI timing : SPICKSEL = 0 Figure 40. Channel transceiver timing diagrams th twl twh SITP = 0 tsu th SITP = 1 DFSDM_DATINy Manchester timing SITP = 2 SITP = 3 recovered clock recovered data 0 0 1 1 0 MS30766V2 206/245 DS12500 Rev 1 STM32MP151A 6.3.31 Electrical characteristics Camera interface (DCMI) characteristics Unless otherwise specified, the parameters given in Table 87 for DCMI are derived from tests performed under the ambient temperature, Fmcu_ck frequency and VDD supply voltage summarized in Table 13: General operating conditions, with the following configuration: * DCMI_PIXCLK polarity: falling * DCMI_VSYNC and DCMI_HSYNC polarity: high * Data formats: 14 bits * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5xVDD Table 87. DCMI characteristics(1) Symbol - Parameter Frequency ratio DCMI_PIXCLK/Fmcu_ck DCMI_PIXCLK Pixel clock input Min Max Unit - 0.4 - - 80 MHz % DPixel Pixel clock input duty cycle 30 70 tsu(DATA) Data input setup time 2 - th(DATA) Data input hold time 0.5 - tsu(HSYNC) tsu(VSYNC) DCMI_HSYNC/DCMI_VSYNC input setup time 2 - th(HSYNC) th(VSYNC) DCMI_HSYNC/DCMI_VSYNC input hold time 1 - ns 1. Guaranteed by characterization results. Figure 41. DCMI timing diagram 1/DCMI_PIXCLK DCMI_PIXCLK tsu(HSYNC) th(HSYNC) DCMI_HSYNC tsu(VSYNC) th(HSYNC) DCMI_VSYNC tsu(DATA) th(DATA) DATA[0:13] MS32414V2 DS12500 Rev 1 207/245 228 Electrical characteristics 6.3.32 STM32MP151A LCD-TFT controller (LTDC) characteristics Unless otherwise specified, the parameters given in Table 88 for LCD-TFT are derived from tests performed under the ambient temperature, Fpclk4 frequency and VDD supply voltage summarized in Table 13: General operating conditions, with the following configuration: * LCD_CLK polarity: high * LCD_DE polarity: low * LCD_VSYNC and LCD_HSYNC polarity: high * Pixel formats: 24 bits * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5xVDD * I/O compensation cell enabled Table 88. LTDC characteristics (1) Symbol fCLK Parameter LTDC clock output frequency Conditions Min Max 2.7 V < VDD < 3.6 V OSPEEDR[1:0] = 11, 10 - 90 1.71 V < VDD < 3.6 V OSPEEDR[1:0] = 11 - 45 1.71 V < VDD < 3.6 V OSPEEDR[1:0] = 10 - 38 45 55 DCLK LTDC clock output duty cycle - tw(CLKH), tw(CLKL) Clock High time, low time - tv(DATA) Data output valid time th(DATA) Data output hold time tv(HSYNC), tv(VSYNC), HSYNC/VSYNC/DE output valid time tv(DE) th(HSYNC), th(VSYNC), HSYNC/VSYNC/DE output hold time th(DE) - 3 OSPEEDR[1:0] = 10 - 4 0 - OSPEEDR[1:0] = 11 - 2.5 OSPEEDR[1:0] = 10 - 3.5 0 - - 1. Guaranteed by characterization results. 208/245 DS12500 Rev 1 MHz % tw(CLK)/2 - 0.5 tw(CLK)/2 + 0.5 OSPEEDR[1:0] = 11 - Unit ns STM32MP151A Electrical characteristics Figure 42. LCD-TFT horizontal timing diagram tCLK LCD_CLK LCD_VSYNC tv(HSYNC) tv(HSYNC) LCD_HSYNC th(DE) tv(DE) LCD_DE tv(DATA) LCD_R[0:7] LCD_G[0:7] LCD_B[0:7] Pixel Pixel 1 2 Pixel N th(DATA) HSYNC Horizontal width back porch Active width Horizontal back porch One line MS32749V1 Figure 43. LCD-TFT vertical timing diagram tCLK LCD_CLK tv(VSYNC) tv(VSYNC) LCD_VSYNC LCD_R[0:7] LCD_G[0:7] LCD_B[0:7] M lines data VSYNC Vertical width back porch Active width Vertical back porch One frame MS32750V1 DS12500 Rev 1 209/245 228 Electrical characteristics 6.3.33 STM32MP151A Timer characteristics The parameters given in Table 89 are guaranteed by design. Refer to Section 0.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 89. TIMx characteristics(1)(2) Symbol Parameter Min Max Unit tTIMxCLK tres(TIM) Timer resolution time 1 - fTIMxCLK Timer kernel clock 0 209 fEXT Timer external clock frequency on CH1 to CH4 0 fTIMxCLK/2 ResTIM Timer resolution - 16/32 Maximum possible count with 16-bit counters tMAX_COUNT Maximum possible count with 32-bit counter (TIM2, TIM5) MHz bit 65536 - 65536 x 65536 tTIMxCLK 1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers. 2. Guaranteed by design. Table 90. LPTIMx characteristics(1)(2) Symbol Parameter Min Max Unit tTIMxCLK tres(TIM) Timer resolution time 1 - fLPTIMxCLK Timer kernel clock 0 104.5 fEXT Timer external clock frequency on Input1 and Input2 0 fLPTIMxCLK/ 2 MHz ResTIM Timer resolution - 16 bit tMAX_COUNT Maximum possible count - 65536 tTIMxCLK 1. LPTIMx is used as a general term to refer to the LPTIM1 to LPTIM5 timers. 2. Guaranteed by design. 6.3.34 Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: * Standard-mode (Sm): with a bit rate up to 100 kbit/s * Fast-mode (Fm): with a bit rate up to 400 kbit/s. * Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured and when the i2c_ker_ck frequency is greater than the minimum shown in the table below: 210/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Table 91. Minimum i2c_ker_ck frequency in all I2C modes Symbol Parameter Condition Standard-mode Fast-mode I2CCLK frequency f(I2CCLK) Fast-mode Plus Min - 2 Analog filter ON DNF=0 8 Analog filter OFF DNF=1 9 Analog filter ON DNF=0 19 Analog filter OFF DNF=1 16 Unit MHz The SDA and SCL I/O requirements are met with the following restrictions: * The SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. * The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the maximum load Cload supported in Fm+, which is given by these formulas: tr(SDA/SCL) = 0.8473 x Rp x Cload Rp(min) = (VDD-VOL(max))/IOL(max) Where Rp is the I2C lines pull-up. Refer to Section 0.3.16: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 92 for the analog filter characteristics: Table 92. I2C analog filter characteristics(1) Symbol tAF Parameter Min Max Unit Maximum pulse width of spikes that are suppressed by the analog filter 70(2) 120(3) ns 1. Guaranteed by design. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered. The I2C pins can be set in FM+ mode in SYSCFG_PMCR register. Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 13: General operating conditions. DS12500 Rev 1 211/245 228 Electrical characteristics STM32MP151A Table 93. I2C FM+ pin characteristics Symbol Parameter Conditions Fmax(1) Maximum frequency Tf(2) Output high to low level fall time C = 50 pF 1.71 VDD 3.6 V Min Max Unit - 1 MHz - 5 ns 1. The maximum frequency is defined with the following conditions: - (Tr + Tf) T - 45% < duty cycle < 55%. 2. The fall time is defined between 70% and 30% of the output waveform accordingl to I2C specification NXP UM10204 rev- Oct 2012. SPI interface characteristics Unless otherwise specified, the parameters given in Table 94 for the SPI interface are derived from tests performed under the ambient temperature, fpclkx frequency and VDD supply voltage conditions summarized in Table 13: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5xVDD * I/O compensation cell enabled * HSLV activated when VDD 2.7 V Refer to Section 0.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). 212/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Table 94. SPI dynamic characteristics(1) Symbol fSCK Parameter SPI clock frequency tsu(NSS) NSS setup time th(NSS) NSS hold time tw(SCKH), SCK high and low time tw(SCKL) Conditions Min Typ Max Master mode 1.71 V VDD 3.6 V SPI1 70 Master mode 2.7 V VDD 3.6 V SPI1 80 Master mode 1.71 V VDD 3.6 V SPI2, SPI3 80 Master mode 2.7 V VDD 3.6 V SPI2, SPI3 100 Master mode 1.71 V VDD 3.6 V SPI4, SPI5, SPI6 - - MHz 66 Slave receiver mode 1.71 V VDD 3.6 V SPI1, SPI2, SPI3 100 Slave receiver mode 1.71 V VDD 3.6 V SPI4, SPI5, SPI6 66 Slave mode transmitter/full duplex 2.7 V VDD 3.6 V 38(2) Slave mode transmitter/full duplex 1.71 V VDD 3.6 V 35(2) Slave mode Master mode DS12500 Rev 1 Unit 2 - - 1 - - Tpclk - 1 Tpclk Tpclk + 1 ns 213/245 228 Electrical characteristics STM32MP151A Table 94. SPI dynamic characteristics(1) (continued) Symbol tsu(MI) Parameter Conditions Data input setup time tsu(SI) th(MI) Data input hold time th(SI) Min Typ Max Master mode 1 - - Slave mode 2 - - Master mode 3 - - Slave mode 1 - - ta(SO) Data output access time Slave mode 9 11 16 tdis(SO) Data output disable time Slave mode 3 5 7.5 Slave mode 2.7 V VDD 3.6 V - 11 13 Slave mode 1.71 V VDD 3.6 V - 11 14 tv(MO) Master mode - 1.5 2.5 th(SO) Slave mode 1.71 V VDD 3.6 V 8 - - Master mode 1 - - tv(SO) Data output valid time Data output hold time th(MO) Unit ns 1. Guaranteed by characterization results. 2. Maximum frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%. Figure 44. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) tsu(NSS) th(NSS) tw(SCKH) tr(SCK) SCK input CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) First bit OUT MISO output th(SO) Next bits OUT tf(SCK) tdis(SO) Last bit OUT th(SI) tsu(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V1 214/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Figure 45. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK input tc(SCK) tsu(NSS) tw(SCKH) ta(SO) tw(SCKL) tf(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tv(SO) th(SO) First bit OUT MISO output tsu(SI) MOSI input tr(SCK) Next bits OUT tdis(SO) Last bit OUT th(SI) First bit IN Next bits IN Last bit IN MSv41659V1 1. Measurement points are done at 0.5xVDD and with external CL = 30 pF. Figure 46. SPI timing diagram - master mode(1) High NSS input SCK Output CPHA= 0 CPOL=0 SCK Output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MSB IN tr(SCK) tf(SCK) BIT6 IN LSB IN th(MI) MOSI OUTPUT MSB OUT tv(MO) B I T1 OUT LSB OUT th(MO) ai14136c 1. Measurement points are done at 0.5xVDD and with external CL = 30 pF. I2S interface characteristics Unless otherwise specified, the parameters given in Table 95 for the I2S interface are derived from tests performed under the ambient temperature, fpclkx frequency and VDD DS12500 Rev 1 215/245 228 Electrical characteristics STM32MP151A supply voltage conditions summarized in Table 13: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5xVDD * I/O compensation cell enabled Refer to Section 0.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Table 95. I2S dynamic characteristics(1) Symbol Parameter Conditions Min Max Unit 256x8K 256xFs MHz Master data - 64xFs Slave data - 64xFs fMCK I2S Main clock output fCK I2S clock frequency tv(WS) WS valid time Master mode - 6.5 th(WS) WS hold time Master mode 0.5 - tsu(WS) WS setup time Slave mode 1 - th(WS) WS hold time Slave mode 0 - Master receiver 2 - Slave receiver 1.5 - Master receiver 2 - Slave receiver 0.5 - Slave transmitter (after enable edge) - 15 Master transmitter (after enable edge) - 1 Slave transmitter (after enable edge) 8.5 - Master transmitter (after enable edge) 0 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) tv(SD_MT) th(SD_ST) th(SD_MT) Data input setup time Data input hold time Data output valid time Data output hold time - 1. Guaranteed by characterization results. 216/245 DS12500 Rev 1 MHz ns STM32MP151A Electrical characteristics Figure 47. I2S slave timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 48. I2S master timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. SAI characteristics Unless otherwise specified, the parameters given in Table 96 for SAI are derived from tests performed under the ambient temperature, Fpclk2 frequency and VDD supply voltage DS12500 Rev 1 217/245 228 Electrical characteristics STM32MP151A conditions summarized in Table 13: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF * Measurement points are performed at CMOS levels: 0.5xVDD Refer to Section 0.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS). Table 96. SAI characteristics(1) Symbol fMCK FCK tv(FS) Parameter SAI bit clock frequency(2) FS valid time FS setup time th(FS) FS hold time tsu(SD_B_SR) th(SD_A_MR) th(SD_B_SR) 218/245 Min Max Unit - - 50 MHz Master transmitter 2.7 V VDD 3.6 V - 45 Master transmitter 1.71 V VDD 3.6 V - 27 Master receiver 1.71 V VDD 3.6 V - 27 Slave transmitter 2.7 V VDD 3.6 V - 45 Slave transmitter 1.71 V VDD 3.6 V - 31 Slave receiver 1.71 VDD 3.6 V - 50 Master mode 2.7 V VDD 3.6 V - 11 Master mode 1.71 V VDD 3.6 V - 18 Slave mode 7 - Master mode 2 - Slave mode 2.5 - Master receiver 2 - Slave receiver 1.5 - Master receiver 3 - Slave receiver 0.5 - SAI Main clock output tsu(FS) tsu(SD_A_MR) Conditions Data input setup time Data input hold time DS12500 Rev 1 MHz ns STM32MP151A Electrical characteristics Table 96. SAI characteristics(1) (continued) Symbol tv(SD_B_ST) th(SD_B_ST) tv(SD_A_MT) th(SD_A_MT) Parameter Conditions Data output valid time Data output hold time Data output valid time Data output hold time Min Max Slave transmitter (after enable edge) 2.7 V VDD 3.6 V - 11 Slave transmitter (after enable edge) 1.71 V VDD 3.6 V - 16 Slave transmitter (after enable edge) 8.5 - Master transmitter (after enable edge) 2.7 V VDD 3.6 V - 10 Master transmitter (after enable edge) 1.71 V VDD 3.6 V - 18 Master transmitter (after enable edge) 7 - Unit ns 1. Guaranteed by characterization results. 2. APB clock frequency must be at least twice SAI clock frequency. Figure 49. SAI master timing waveforms 1/fSCK SAI_SCK_X th(FS) SAI_FS_X (output) tv(FS) th(SD_MT) tv(SD_MT) SAI_SD_X (transmit) Slot n tsu(SD_MR) SAI_SD_X (receive) Slot n+2 th(SD_MR) Slot n MS32771V1 Figure 50. SAI slave timing waveforms SAI_SCK_X tw(CKH_X) SAI_FS_X (input) tw(CKL_X) tsu(FS) th(FS) th(SD_ST) tv(SD_ST) SAI_SD_X (transmit) Slot n tsu(SD_SR) SAI_SD_X (receive) Slot n+2 th(SD_SR) Slot n MS32772V1 DS12500 Rev 1 219/245 228 Electrical characteristics STM32MP151A MDIOS characteristics Table 97. MDIOS timing parameters Symbol Parameter Min Typ Max Unit - - 30 MHz 6.5 8 19 FMDC Management data clock td(MDIOS) Management data input/output output valid time tsu(MDIOS) Management data input/output setup time 1 - - th(MDIOS) Management data input/output hold time 0.5 - - ns The MDIOS controller is mapped on APB1 domain. The frequency of the APB bus should at least 1.5 times the MDC frequency: Fpclk1 1.5 * FMDC. Figure 51. MDIOS timing diagram TMDC MDIOS_MDC td(MDIOS) MDIOS_MDIO(O) tsu(MDIOS) th(MDIOS) MDIOS_MDIO(I) MSv50900V1 SD/SDIO MMC card host interface (SDMMC) characteristics Unless otherwise specified, the parameters given in Table 98 for the SDIO/MMC interface are derived from tests performed under the ambient temperature, Fhclk6 frequency and VDD supply voltage conditions summarized in Table 13: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5xVDD * I/O compensation cell enabled * HSLV activated when VDD 2.7 V * Delay block disabled Refer to Section 0.3.16: I/O port characteristics for more details on the input/output characteristics. 220/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Table 98. Dynamic characteristics: SD / MMC / e*MMC characteristics, VDD = 2.7 V to 3.6 V(1)(2) Symbol fPP - Parameter Conditions Min Typ Max Unit Clock frequency in data transfer mode - 0 - 130 MHz SDIO_CK/fpclk2 frequency ratio - - - 8/3 - 8.5 9.5 - 8.5 9.5 - 1.5 - - 1.5 - - 2.5 - - - 5 6.5 2.5 - - 1.5 - - 1.5 - - - 0.5 1.5 0 - - tW(CKL) Clock low time tW(CKH) Clock high time fPP = 52 MHz ns CMD, D inputs (referenced to CK) in MMC and SD HS/SDR(3)/DDR(3) mode tISU Input setup time HS tIH Input hold time HS tIDW(4) Input valid window (variable window) - CMD, D outputs (referenced to CK) in MMC and SD HS/SDR tOV Output valid time HS tOH Output hold time HS (3)/DDR(3) - ns mode ns CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD tIHD Input hold time SD - ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD tOHD Output hold default time SD - ns 1. Guaranteed by characterization results. 2. Above 100 MHz, CL = 20 pF. 3. For SD 1.8 V support, an external voltage converter is required. 4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. Table 99. Dynamic characteristics: SD / MMC / e*MMC characteristics VDD = 1.71 V to 1.9 V(1)(2) Symbol fPP - Parameter Conditions Min Typ Max Unit Clock frequency in data transfer mode - 0 - 105 MHz SDIO_CK/fpclk2 frequency ratio - - - 8/3 - 8.5 9.5 - 8.5 9.5 - 1.5 - - 2.5 - - 3 - - tW(CKL) Clock low time tW(CKH) Clock high time fPP = 52 MHz ns CMD, D inputs (referenced to CK) in e*MMC mode tISU Input setup time HS tIH Input hold time HS tIDW(3) Input valid window (variable window) - ns CMD, D outputs (referenced to CK) in e*MMC mode DS12500 Rev 1 221/245 228 Electrical characteristics STM32MP151A Table 99. Dynamic characteristics: SD / MMC / e*MMC characteristics VDD = 1.71 V to 1.9 V(1)(2) (continued) Symbol Parameter tOV Output valid time HS tOH Output hold time HS Conditions - Min Typ Max - 5 6 4 - - Unit ns 1. Guaranteed by characterization results. 2. CL = 20 pF. 3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. Figure 52. SDIO high-speed mode Figure 53. SD default mode CK tOVD tOHD D, CMD (output) ai14 222/245 DS12500 Rev 1 STM32MP151A Electrical characteristics Figure 54. DDR mode tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK) Clock tvf(OUT) Data output thr(OUT) D0 tvr(OUT) D1 D2 thf(OUT) D3 D4 tsf(IN) thf(IN) Data input D0 D1 D5 tsr(IN) thr(IN) D3 D2 D4 D5 MSv36879V1 USB OTG_FS characteristics The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation). Table 100. USB OTG_FS electrical characteristics Symbol Parameter Condition Min Typ Max Unit V VDD33USB USB transceiver operating voltage - 3.0(1) - 3.6 RPUI Embedded USB_DP pull-up value during idle - 900 1250 1600 RPUR Embedded USB_DP pull-up value during reception - 1400 2300 3200 ZDRV Output driver impedance(2) Driver high and low 28 36 44 1. The USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7 to 3.0 V voltage range. 2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is already included in the embedded driver. Ethernet (ETH) characteristics Unless otherwise specified, the parameters given in Table 101, Table 102, Table 103, Table 104 and Table 105 for MDIO/SMA, RMII, GMII, RGMII and MII are derived from tests performed under the ambient temperature, Faxiss_ck frequency summarized in Table 13: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 20 pF * Measurement points are done at CMOS levels: 0.5xVDD. Refer to Section 0.3.16: I/O port characteristics for more details on the input/output characteristics. Table 101 gives the list of Ethernet MAC timings for the MDIO/SMA and Figure 55 shows the corresponding timing diagram. DS12500 Rev 1 223/245 228 Electrical characteristics STM32MP151A Table 101. Dynamics characteristics: Ethernet MAC timings for MDIO/SMA(1) Symbol Parameter Min Typ Max tMDC MDC cycle time(2.5 MHz) 399 400 401 Td(MDIO) Write data valid time 0.5 1 3 tsu(MDIO) Read data setup time 13.5 - - th(MDIO) Read data hold time 0 - - Unit ns 1. Guaranteed by characterization results. Figure 55. Ethernet MDIO/SMA timing diagram tMDC ETH_MDC td(MDIO) ETH_MDIO(O) tsu(MDIO) th(MDIO) ETH_MDIO(I) MS31384V1 Table 102 gives the list of Ethernet MAC timings for the RMII and Figure 56 shows the corresponding timing diagram. Table 102. Dynamics characteristics: Ethernet MAC timings for RMII(1) Symbol Parameter Typ Max tsu(RXD) Receive data setup time 2 - - tih(RXD) Receive data hold time 1.5 - - tsu(CRS) Carrier sense setup time 1.5 - - tih(CRS) Carrier sense hold time 1.5 - - td(TXEN) Transmit enable valid delay time 5.5 6.5 9.5 td(TXD) Transmit data valid delay time 6 6.5 10 1. Guaranteed by characterization results. 224/245 Min DS12500 Rev 1 Unit ns STM32MP151A Electrical characteristics Figure 56. Ethernet RMII timing diagram RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tsu(CRS) tih(RXD) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667b Table 103 gives the list of Ethernet MAC timings for MII and Figure 57 shows the corresponding timing diagram. Table 103. Dynamics characteristics: Ethernet MAC timings for MII(1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 2 - - tih(RXD) Receive data hold time 1 - - tsu(DV) Data valid setup time 1 - - tih(DV) Data valid hold time 0.5 - - tsu(ER) Error setup time 1 - - tih(ER) Error hold time 0.5 - - td(TXEN) Transmit enable valid delay time 6 7.5 10.5 td(TXD) Transmit data valid delay time 7 8 11 Unit ns 1. Guaranteed by characterization results. DS12500 Rev 1 225/245 228 Electrical characteristics STM32MP151A Figure 57. Ethernet MII timing diagram MII_RX_CLK tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) MII_RXD[3:0] MII_RX_DV MII_RX_ER MII_TX_CLK td(TXEN) td(TXD) MII_TX_EN MII_TXD[3:0] ai15668b Table 104. Dynamics characteristics: Ethernet MAC signals for GMII (1) Symbol Parameter Typ Max tsu(RXD) Receive data setup time 1 - - tih(RXD) Receive data hold time 0.5 - - tsu(DV) Data valid setup time 1 - - tih(DV) Data valid hold time 0.5 - - tsu(ER) Error setup time 1 - - tih(ER) Error hold time 0.5 - - td(TXEN) Transmit enable valid delay time 1 1.5 2 td(TXD) Transmit data valid delay time 1 2 3 1. Guaranteed by characterization results. 226/245 Min DS12500 Rev 1 Unit ns STM32MP151A Electrical characteristics Figure 58. Ethernet GMII timing diagram GMII_RX_CLK GMII_RXD[7:0] GMII_RX_DV GMII_RX_ER tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) GTX_CLK td(TXEN) td(TXD) GMII_TX_EN GMII_TXD[7:0] MSv50970V1 Table 105. Dynamics characteristics: Ethernet MAC signals for RGMII (1) Symbol tsu(RXD) Rating Receive data setup time Min Typ Max 1.12(2) - - (2) tih(RXD) Receive data hold time 0.83 - - tsu(DV) Data valid setup time 1.12(2) - - tih(DV) Data valid hold time 0.83(2) - - TskewT(TXEN) Transmit enable valid delay time -0.25 0.25 0.5 TskewT(TXD) Transmit data valid delay time -0.25 2 0.5 Unit ns 1. Guaranteed by characterization results. 2. Guaranteed by design. Figure 59. Ethernet RGMII timing diagram tskewT RGMII_GTX_CLK RGMII_TXD[3:0] RGMII_TX_EN tsu tih RGMII_RX_CLK RGMII_RXD[3:0] RGMII_RX_DV MSv50971V1 DS12500 Rev 1 227/245 228 Electrical characteristics 6.3.35 STM32MP151A USART interface characteristics Unless otherwise specified, the parameters given in Table 106 for USART are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 106, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5xVDD Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, CK, TX, RX for USART). Table 106. USART characteristics(1) Symbol Parameter Conditions Master mode USART2,3,6 fCK USART clock frequency Master mode USART1 Min Typ Max Unit 12.5 - 16.5 Slave mode - - 27 MHz tsu(NSS) NSS setup time Slave mode tker+2 - - ns th(NSS) NSS hold time Slave mode 2 - - ns tw(CKH), tw(CKL) CK high and low time Master mode 1/fCK/2 - 1 1/fck/2 1/fCK/2 + 1 ns tsu(RX) Data input setup time Master mode tker+3 - - Slave mode 2 - - thRX) Data input hold time Master mode 1 - - Slave mode 1 - - tv(TX) Data output valid time Slave mode - 10 18 Master mode - 0.5 1 th(TX) Data output hold time Slave mode 8 - - Master mode 0 - - 1. 1.Guaranteed by characterization results. 228/245 DS12500 Rev 1 ns ns ns ns STM32MP151A 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 TFBGA 257 package information Figure 60. TFBGA - 257 balls, 10x10 mm, 0.5/0.65 mm pitch, low profile fine pitch ball grid array package outline b (257 balls) eee M C A B fff M C F2 Peripheral ball matrix pitch 0.5 mm 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 e1 e2 D A B C D E F G H J K L M N P R T U V W 1A 1B 1C 1D 1E 1F 1G 1H 1J F1 8 F1 9 6 7 4 5 B E e1 2 3 Peripheral ball matrix pitch 0.5 mm Central ball matrix pitch 0.65 mm E1 E2 A1 ball pad corner 1 Central ball matrix pitch 0.65 mm A F2 e2 D2 D1 SEATING PLANE BOTTOM VIEW TOP VIEW C ddd C A2 A1 A SIDE VIEW B02Y_ME_V1 1. Drawing is not to scale. DS12500 Rev 1 229/245 242 Package information STM32MP151A Table 107. TFBGA - 257 balls, 10x10 mm, 0.5/0.65 mm pitch, low profile fine pitch ball grid array mechanical data inches(1) millimeters Symbol A (2) A1 A2 Min Typ Max Min Typ Max - - 1.200 - - 0.0472 0.150 - - 0.0059 - - - 0.810 - - 0.0319 - (3) 0.300 0.350 0.400 0.0118 0.0138 0.0157 D 9.850 10.000 10.150 0.3878 0.3937 0.3996 D1 - 9.000 - - 0.3543 - E 9.850 10.000 10.150 0.3878 0.3937 0.3996 E1 - 9.000 - - 0.3543 - D2 - 5.200 - - 0.2047 - E2 - 5.200 - - 0.2047 - e1 - 0.500 - - 0.0197 - e2 - 0.650 - - 0.0256 - F1 - 0.500 - - 0.0197 - F2 - 2.400 - - 0.0945 - ddd - - 0.100 - - 0.0039 - - 0.150 - - 0.0059 - - 0.050 - - 0.0020 b eee fff (4) (5) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. - The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other feature of package body or integral heat slug. - A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional. 3. Initial ball equal 0.300 mm. 4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. 5. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball must lie simultaneously in both tolerance zones. 230/245 DS12500 Rev 1 STM32MP151A Package information Figure 61. TFBGA - 257 balls, 10x10 mm, 0.5/0.65 mm pitch, low profile fine pitch ball grid array recommended footprint Dpad Dsm B02Y_FP_V1 1. Dimensions are expressed in millimeters. Table 108. TFBGA - 257 balls, recommended PCB design rules (0.5/0.65 mm pitch, BGA) Dimension Recommended values Pitch 0.5/0.65 mm Dpad 0.350 mm Dsm 0.480 mm typ. Stencil opening 0.350 mm Stencil thickness 0.125 mm to 0.100 mm DS12500 Rev 1 231/245 242 Package information STM32MP151A Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 62. TFBGA257 marking (package top view) Product identification STM32MP15x xADxx Revision R Y WW MSv60330V1 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 232/245 DS12500 Rev 1 STM32MP151A 7.2 Package information LFBGA354 package information Figure 63. LFBGA - 354balls, 16x16 mm, 0.8 mm pitch, low profile fine pitch ball grid array package outline b (354 balls) A1 ball pad corner eee M C A B fff M C e 18 19 16 17 14 15 12 13 8 10 11 9 6 7 4 5 2 3 1 A C D E F G H J K L M N P R T U V W D1 F F D e E1 A B E BOTTOM VIEW SEATING PLANE TOP VIEW C ddd C A1 A2 A SIDE VIEW B02Z_ME_V1 1. Drawing is not to scale. 2. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones. Table 109. LFBGA - 354balls, 16x16 mm, 0.8 mm pitch, low profile fine pitch ball grid array mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max - - 1.290 - - 0.0508 0.250 - - 0.0098 - - A2 - 0.900 - - 0.0354 - b(4) 0.350 0.400 0.450 0.0138 0.0157 0.0177 D 15.850 16.000 16.150 0.6240 0.6299 0.6358 D1 - 14.400 - - 0.5669 - A(2) (3) A1 DS12500 Rev 1 233/245 242 Package information STM32MP151A Table 109. LFBGA - 354balls, 16x16 mm, 0.8 mm pitch, low profile fine pitch ball grid array mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E 15.850 16.000 16.150 0.6240 0.6299 0.6358 E1 - 14.400 - - 0.5669 - e - 0.800 - - 0.0315 - F - 0.800 - - 0.0315 - - - 0.100 - - 0.0039 - - 0.150 - - 0.0059 - - 0.080 - - 0.0031 ddd eee fff (5) (6) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. LFBGA stands for Low profile Fine pitch Ball Grid Array package. Low profile: 1.20mm < A 1.70mm / Fine pitch: e < 1.00mm pitch. The total profile height (Dim A) is measured from the seating plane to the top of the component The maximum total package height is calculated by the RSS method (Root Sum Square). A Max = A1 Typ + A2 Typ + A4 Typ + (A1 + A2 + A4 tolerance values). 3. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other feature of package body or integral heat slug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional. 4. Initial ball equal 0.400 mm. 5. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. 6. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball must lie simultaneously in both tolerance zones. Figure 64. LFBGA - 354balls, 16x16 mm, 0.8 mm pitch, low profile fine pitch ball grid array recommended footprint Dpad Dsm B02Z_FP_V1 1. Dimensions are expressed in millimeters. 234/245 DS12500 Rev 1 STM32MP151A Package information Table 110. LFBGA - 354 balls, recommended PCB design rules (0.8 mm pitch, BGA) Dimension Recommended values Pitch 0.8 mm Dpad 0.400 mm Dsm 0.550 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.400 mm Stencil thickness 0.125 mm to 0.100 mm Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 65. LFBGA354 marking (package top view) Product identification STM32MP15xxABx Revision R Y WW MSv60332V1 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS12500 Rev 1 235/245 242 Package information 7.3 STM32MP151A TFBA361 package information Figure 66. TFBGA - 361 ball, 12x12 mm, 0.5/0.65 mm pitch, thin profile fine pitch ball grid array package outline eee M C A B fff M C b (361 balls) A1 ball pad corner Peripheral ball matrix pitch 0.5 mm e1 F2 A B C D E F G H J K L M N P R T U V W Y AA AB AC 1A 1B 1C 1D 1E 1F 1G 1H 1J 8 9 F1 F1 6 7 4 5 Peripheral ball matrix pitch 0.5 mm E2 e2 Central ball matrix pitch 0.65 mm E1 22 20 18 16 14 12 10 8 6 4 2 23 21 19 17 15 13 11 9 7 5 3 1 E e1 A 2 3 1 Central ball matrix pitch 0.65 mm e2 B F2 D2 D D1 BOTTOM VIEW SEATING PLANE TOP VIEW C ddd C A1 A2 A SIDE VIEW B031_ME_V1 1. Drawing is not to scale. 2. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other feature of package body or integral heat slug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional. 236/245 DS12500 Rev 1 STM32MP151A Package information Table 111. TFBGA - 361 ball, 12x12 mm, 0.5/0.65 mm pitch, thin profile fine pitch ball grid array mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A(2) - - 1.200 - - 0.0472 A1 0.150 - - 0.0059 - - A2 - 0.810 - - 0.0319 - 0.300 0.350 0.400 0.0118 0.0138 0.0157 D 11.850 12.000 12.150 0.4665 0.4724 0.4783 D1 - 11.000 - - 0.4331 - E 11.850 12.000 12.150 0.4665 0.4724 0.4783 E1 - 11.000 - - 0.4331 - D2 - 5.200 - - 0.2047 - E2 - 5.200 - - 0.2047 - e1 - 0.500 - - 0.0197 - e2 - 0.650 - - 0.0256 - F1 - 0.500 - - 0.0197 - F2 - 3.400 - - 0.1339 - ddd - - 0.080 - - 0.0031 - - 0.150 - - 0.0059 - - 0.080 - - 0.0031 b (3) eee fff (4) (5) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. TFBGA stands for Thin Profile Fine Pitch Ball Grid Array. The total profile height (dim A) is measured from the seating plane to the top of the component. 3. Initial ball equal to 0.300 mm. 4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. 5. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball must lie simultaneously in both tolerance zones. DS12500 Rev 1 237/245 242 Package information STM32MP151A Figure 67. TFBGA - 361 ball, 12x12 mm, 0.5/0.65 mm pitch, thin profile fine pitch ball grid array recommended footprint Dpad Dsm B031_FP_V2 Table 112. TFBGA - 361 ball, recommended PCB design rules (0.5/0.65 mm pitch BGA) Dimension 238/245 Recommended values Pitch 0.5/0.65 mm Dpad 0.350 mm Dsm 0.480 mm typ. Stencil opening 0.350 mm Stencil thickness 0.125 mm to 0.100 mm DS12500 Rev 1 STM32MP151A Package information Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 68. TFBGA361 marking (package top view) Product identification STM32MP15x xACxx Revision R Y WW MSv60331V1 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS12500 Rev 1 239/245 242 Package information 7.4 STM32MP151A LFBGA448 package information Figure 69. LFBGA - 448 balls, 18x18 mm, 0.8 mm pitch, low profile fine pitch ball grid array package outline eee fff C A B A1 corner index area C B b (448 Balls) e 8 20 18 16 14 12 10 6 4 2 21 19 17 15 13 11 9 7 5 3 1 D1 F A A B C D E F G H J K L M N P R T U V W Y AA AB F D e E1 BOTTOM VIEW A2 A TOP VIEW ddd C 22 E C A4 A3 SEATING PLANE A1 SIDE VIEW B032_LFBGA448_ME_V1 1. Drawing is not to scale. 2. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones. Table 113. LFBGA - 448 balls, 18x18 mm, 0.8 mm pitch, low profile fine pitch ball grid array mechanical data inches(1) millimeters Symbol 240/245 Min Typ Max Min Typ Max A - - 1.270 - - 0.0500 A1 0.250 0.290 0.330 0.0098 0.0114 0.0130 A2 0.790 0.880 0.970 0.0311 0.0346 0.0382 A3 0.240 0.28 0.320 0.0094 0.0110 0.0126 A4 0.550 0.600 0.650 0.0217 0.0236 0.0256 b(2) 0.350 0.400 0.450 0.0138 0.0157 0.0177 DS12500 Rev 1 STM32MP151A Package information Table 113. LFBGA - 448 balls, 18x18 mm, 0.8 mm pitch, low profile fine pitch ball grid array mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D 17.900 18.000 18.100 0.7047 0.7087 0.7126 D1 - 16.800 - - 0.6614 - E 17.900 18.000 18.100 0.7047 0.7087 0.7126 E1 - 16.800 - - 0.6614 - e - 0.800 - - 0.0315 - F - 0.600 - - 0.0236 - - 0.120 - - 0.0047 - - 0.150 - - 0.0059 - - 0.080 - - 0.0031 - ddd eee (3) fff(4) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Low profile: 1.20 mm < A 1.70 mm / Fine pitch: e < 1.00 mm pitch. The total profile height (Dim.A) is measured from the seating plane "C" to the top of the component. The maximum total package height is calculated by the RSS method (Root Sum Square). A Max = A1 Typ + A2 Typ + A4 Typ + (A1 + A2 + A4 tolerance values). 3. The typical ball diameter before mounting is 0.40 mm 4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Figure 70. LFBGA - 448 balls, 18x18 mm, 0.8 mm pitch, low profile fine pitch ball grid array recommended footprint Dpad Dsm B032_LFBGA448_FP_V1 1. Dimensions are expressed in millimeters. Table 114. LFBGA - 448 balls, recommended PCB design rules (0.8 mm pitch, BGA) Dimension Recommended values Pitch 0.8 mm Dpad 0.400 mm DS12500 Rev 1 241/245 242 Package information STM32MP151A Table 114. LFBGA - 448 balls, recommended PCB design rules (0.8 mm pitch, BGA) Dimension Recommended values Dsm 0.550 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.400 mm Stencil thickness 0.125 mm to 0.100 mm Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 71. LFBGA448 marking (package top view) Product identification STM32MP15xxAAx Revision R Y WW MSv60333V1 1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 242/245 DS12500 Rev 1 STM32MP151A 8 Ordering information Ordering information Table 115. STM32MP151A ordering information scheme Example: STM32 MP 151 A AA 3 T Device family STM32 = Arm-based 32-bit processor Product type MP = MPU product Device subfamily 151 = STM32MP151 Line Security option A = Basic security Package and pin count AD = TFBGA257 10x10, 257 balls pitch 0.5 mm AB = LFBGA354 16x16, 354 balls pitch 0.8 mm AC = TFBGA361 12x12, 361 balls pitch 0.5 mm AA = LFBGA448 18x18, 448 balls pitch 0.8 mm Junction temperature range 3 = -40C < TJ < +125C Packing T = tape and reel No character = tray or tube For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. DS12500 Rev 1 243/245 243 Revision history 9 STM32MP151A Revision history Table 116. Document revision history 244/245 Date Revision 08-Feb-2019 1 Changes Initial release. DS12500 Rev 1 STM32MP151A IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2019 STMicroelectronics - All rights reserved DS12500 Rev 1 245/245 245