CY2292
Three PLL General Purpose
EPROM Programmable Clock Generator
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-07449 Rev. *I Revised December 21, 2012
Three PLL Gene ral Purpose EPR OM Programmable C lock Generator
Features
■Three integrated phase locked loops (PLLs)
■Erasable programmable read only memory (EPROM)
programmability
■Factory programmable (CY2292) or field programmable
(CY2292F) device options
■Low-skew, low-jitter, high accuracy outputs
■Power management options (shutdown, OE, suspend)
■Frequency select option
■Smooth slewing on CPUCLK
■Configurable 3.3 V or 5 V operation
■16-pin small-outline integrated circuit (SOIC) package
(CY2292F also in TSSOP)
Benefits
■Generates up to three custom frequencies from one external
source
■Easy customization and fast turnaround
■Programming support available for all opportunities
■Supports low power applications
■Eight user selectable frequencies on CPU PLL
■Allows downstream PLLs to stay locked on CPUCLK output
■Industry standard packaging saves on board space
Selector Guide
Part Number Input Frequency Range Output Frequency Range Specifics
CY2292SC, SL, SXC, SXL 10 MHz to 25 MHz (external crystal)
1 MHz to 30 MHz (reference clock)
76.923 kHz to 100 MHz (5 V)
76.923 kHz to 80 MHz (3.3 V)
Factory programmable
Commercial temperature
CY2292SI, SXI 10 MHz to 25 MHz (external crystal)
1 MHz to 30 MHz (reference clock)
76.923 kHz to 90 MHz (5 V)
76.923 kHz to 66.6 MHz (3.3 V)
Factory programmable
Industrial temperature
CY2292F, FXC, FZX 10 MHz to 25 MHz (external crystal)
1 MHz to 30 MHz (reference clock)
76.923 kHz to 90 MHz (5 V)
76.923 kHz to 66.6 MHz (3.3 V)
Field programmable
Commercial temperature
CY2292FXI, FZXI 10 MHz to 25 MHz (external crystal)
1 MHz to 30 MHz (reference clock)
76.923 kHz to 80 MHz (5 V)
76.923 kHz to 60.0 MHz (3.3 V)
Field programmable
Industrial temperature
Logic Block Diagram
XTALIN
XTALOUT
S2 / SUSPEND
S1
S0
SHUTDOWN /
CONFIG
EPROM
OSC. XBUF
CPLL
SPLL
UPLL
CPUCLK
CLKA
CLKB
CLKC
CLKD
MUX
OE
/1,2,4
/1,2,3,4,5,6
/8,10,12,13
/20,24,26,40
/48,52,96, 104
/1,2,4,8
(8 BIT)
(8 BIT)
( 10 BIT)
CY2292
Document Number: 38-07449 Rev. *I Page 2 of 16
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Operation ........................................................................... 4
Output Configuration .......................................................4
Power Saving Features ....................................................4
CyClocks Software ........................................................... 4
Cypress FTG Programmer ............................................... 4
Custom Configuration Request Procedure .................... 4
Maximum Ratings .............................................................5
Operating Conditions ....................................................... 5
Electrical Characteristics, Commercial 5.0 V .................5
Electrical Characteristics, Commercial 3.3 V .................5
Electrical Characteristics, Industrial 5.0 V .....................6
Electrical Characteristics, Industrial 3.3 V .....................6
Switching Characteristics, Commercial 5.0 V ................7
Switching Characteristics, Commercial 3.3 V ................7
Switching Characteristics, Industrial 5.0 V .................... 8
Switching Characteristics, Industrial 3.3 V .................... 9
Switching Waveforms .................................................... 10
Test Circuit ...................................................................... 11
Ordering Information ...................................................... 11
Possible Configurations ............................................. 11
Ordering Code Definition ............................................... 12
Package Characteristics ................................................ 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................ 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC® Solutions ....................................................... 16
CY2292
Document Number: 38-07449 Rev. *I Page 3 of 16
Pinouts
Figure 1. CY2292 – 16-Pin SOIC and TSSOP
Pin Definitions
Name Pin Number
CY2292 Description
CLKC 1 Configurable clock output C.
VDD 2, 14 Voltage supply.
GND 3, 11 Ground.
XTALIN[1] 4 Reference crystal input or external reference clock input.
XTALOUT[1, 2] 5 Reference crystal feedback.
XBUF 6 Buffered reference clock output.
CLKD 7 Configurable clock output D.
CPUCLK 8 CPU frequency clock output.
CLKB 9 Configurable clock output B.
CLKA 10 Configurable clock output A.
S0 12 CPU clock select input, bit 0.
S1 13 CPU clock select input, bit 1.
S2/SUSPEND 15 CPU clock select input, bit 2. Optionally enables suspend feature when LOW.
SHUTDOWN/OE 16 Places outputs in tristate[3] condition and shuts down chip when LOW. Optionally, only
places outputs in tristate[3] condition and does not shut down chip when LOW.
1
2
3
4
5
6
7
89
10
CLKC
VDD
GND
XTALIN
XTALOUT
XBUF
CLKD
CPUCLK
SHUTDOWN/OE
S2/SUSPEND
VDD
S1
S0
GND
CLKA
CLKB
11
12
13
14
15
16
Notes
1. For best accuracy, use a parallel-resonant crystal, CLOAD 17 pF or 18 pF.
2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal).
3. The CY2292 has weak pull downs on all outputs. Hence, when a tristate condition is forced on the outputs, the output pins are pulled low.
CY2292
Document Number: 38-07449 Rev. *I Page 4 of 16
Operation
The CY2292 is a third-generation family of clock generators. The
CY2292 is upwardly compatible with the industry standard
ICD2023 and ICD2028 and continues their tradition by providing
a high level of customizable features to meet the diverse clock
generation needs of modern motherboards and other
synchronous systems.
All parts provide a highly configurable set of clocks for PC
motherboard applications. Each of the four configurable clock
outputs (CLKA–CLKD) can be assigned 1 of 30 frequencies in
any combination. Multiple outputs configured for the same or
related frequencies have low (less than 500 ps) skew, in effect
providing on-chip buffering for heavily loaded signals.
The CY2292 can be configured for either 5 V or 3.3 V operation.
The internal ROM tables use EPROM technology, allowing full
customization of output frequencies. The reference oscillator is
designed for 10 MHz to 25 MHz crystals, providing additional
flexibility. No external components are required with this crystal.
Alternatively, an external reference clock of frequency between
1 MHz and 30 MHz can be used.
Output Configuration
The CY2292 has four independent frequency sources on-chip.
These are the reference oscillator and three PLLs. Each PLL has
a specific function. The system PLL (SPLL) provides fixed output
frequencies on the configurable outputs. The SPLL offers the
most output frequency divider options. The CPU PLL (CPLL) is
controlled by the select inputs (S0–S2) to provide eight
user-selectable frequencies with smooth slewing between
frequencies. The utility PLL (UPLL) provides the most accurate
clock. It is often used for miscellaneous frequencies not provided
by the other frequency sources.
All configurations are EPROM programmable, providing short
sample and production lead times.
Power Saving Features
The SHUTDOWN/OE input tristates the outputs when pulled
LOW. If system shutdown is enabled, a LOW on this pin also
shuts off the PLLs, counters, the reference oscillator, and all
other active components. The resulting current on the VDD pins
is less than 50 µA (for commercial temperature or 100 µA for
industrial temperature). After leaving shutdown mode, the PLLs
have to relock. All outputs have a weak pull down so that the
outputs do not float when tristated.[4]
The S2/SUSPEND input can be configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs can be shut off in nearly any combination.
The only limitation is that if a PLL is shut off, all outputs derived
from it must also be shut off. Suspending a PLL shuts off all
associated logic, while suspending an output simply forces a
tristate condition.
The CPUCLK can slew (transition) smoothly between 20 MHz
and the maximum output frequency (100 MHz at 5 V / 80 MHz at
3.3 V for commercial temperature parts or 90 MHz at
5 V / 66.6 MHz at 3.3 V for industrial temperature and for
field-programmed parts). This feature is extremely useful in
green applications, where reducing the frequency of operation
can result in considerable power savings.
CyClocks Software
CyClocks is an easy-to-use application that allows you to
configure any one of the EPROM-programmable clocks offered
by Cypress. Specify the input frequency, PLL and output
frequencies, and different functional options. Note the output
frequency ranges in this datasheet when specifying them in
CyClocks to ensure that you stay within the limits. CyClocks also
has a power calculation feature that allows you to see the power
consumption of your specific configuration. CyClocks is a sub
application located within the CyberClocks software. You can
download a copy of CyberClocks for free on the Cypress web site
at http://www.cypress.com.
Cypress FTG Programmer
The Cypress frequency timing generator (FTG) programmer is a
portable programmer designed to custom program our family of
EPROM field programmable clock devices. The FTG
programmer connects to a PC serial port and allow users of
CyClocks software to quickly and easily program any of the
CY2291F, CY2292F and CY2907F devices. The ordering code
for the Cypress FTG Programmer is CY3670. An adapter, the
CY3095, connects to the CY3670 and is required for
programming the CY2292F.
Custom Configuration Request Procedure
The CY229x are EPROM-programmable devices that may be
configured in the factory or in the field by a Cypress field
application engineer (FAE). The output frequencies requested is
matched as closely as the internal PLL divider and multiplier
options allow. All custom requests must be submitted to your
local Cypress FAE or sales representative. The method to use to
request custom configurations is:
Use CyClocks software. This software automatically calculates
the output frequencies that can be generated by the CY229x
devices and provides a print-out of final pinout which can be
submitted (in electronic or print format) to your local FAE or sales
representative.
When the custom request is processed, you receive a part
number with a 3-digit extension (for example, CY2292SC-128)
specific to the frequencies and pinout of your device. This is the
part number used for samples requests and production orders.
Note
4. The CY2292 has weak pull downs on all outputs. Hence, when a tristate condition is forced on the outputs, the output pins are pulled low.
CY2292
Document Number: 38-07449 Rev. *I Page 5 of 16
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage ..............................................–0.5 V to +7.0 V
DC input voltage ...........................................–0.5 V to +7.0 V
Storage temperature ................................ –65 C to +150 C
Maximum soldering temperature (10 sec).................. 260 C
Junction temperature.................................................. 150 C
Package power dissipation....................................... 750 mW
Static discharge voltage.............................................2000 V
(per MIL-STD-883, method 3015)
Operating Conditions[5]
Parameter Description Part Numbers Min Max Unit
VDD Supply voltage, 5.0 V operation All 4.5 5.5 V
VDD Supply voltage, 3.3 V operation All 3.0 3.6 V
TACommercial operating temperature, ambient CY2292 / CY2292F 0 70 C
Industrial operating temperature, ambient CY2292I / CY2292FI 40 85 C
CLOAD Maximum load capacitance 5.0 V operation All – 25 pF
CLOAD Maximum load capacitance 3.3 V operation All – 15 pF
fREF External reference crystal All 10.0 25.0 MHz
External reference clock[6, 7, 8] All 1 30 MHz
Electrical Characteristics, Commercial 5.0 V
Parameter Description Conditions Min Typ Max Unit
VOH High level output voltage IOH = 4.0 mA 2.4 – – V
VOL Low level output voltage IOL = 4.0 mA – – 0.4 V
VIH High level input voltage[9] Except crystal pins 2.0 – – V
VIL Low level input voltage[9] Except crystal pins – – 0.8 V
IIH Input high current VIN = VDD – 0.5 V – < 1 10 µA
IIL Input low current VIN = +0.5 V – < 1 10 µA
IOZ Output leakage current Tristate outputs – – 250 µA
IDD VDD supply current[10] commercial VDD = VDD max, 5 V operation – 75 100 mA
IDDS VDD power supply current in shutdown mode[10] Shutdown active – 10 50 µA
Notes
5. Electrical parameters are guaranteed by design with these operating conditions, unless otherwise noted.
6. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD / 2.
7. Refer to white paper “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock.
8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up to 20 MHz. For external reference clocks above 20 MHz, it is recommended
that a 150 pull up resistor to VDD be connected to the Xout pin.
9. Xtal inputs have CMOS thresholds.
10. Load = Max, VIN = 0 V or VDD, Typical (–104) configuration, CPUCLK = 66 MHz. Other configurations vary. Power can be approximated by the following formula
(multiply by 0.65 for 3 V operation): IDD = 10 + 0.06•(FCPLL + FUPLL + 2•FSPLL) + 0.27•(FCLKA + FCLKB + FCLKC + FCLKD + FCPUCLK + FXBUF).
Electrical Characteristics, Commercial 3.3 V
Parameter Description Conditions Min Typ Max Unit
VOH High level output voltage IOH = 4.0 mA 2.4 – – V
VOL Low level output voltage IOL = 4.0 mA – – 0.4 V
VIH High level input voltage[9] Except crystal pins 2.0 – – V
VIL Low level input voltage[9] Except crystal pins – – 0.8 V
IIH Input high current VIN = VDD – 0.5 V – < 1 10 µA
IIL Input low current VIN = +0.5 V – < 1 10 µA
IOZ Output leakage current Tristate outputs – – 250 µA
IDD VDD supply current[10] commercial VDD = VDD max, 3.3 V operation – 50 65 mA
IDDS VDD power supply current in shutdown mode[10] Shutdown active – 10 50 µA
CY2292
Document Number: 38-07449 Rev. *I Page 6 of 16
Electrical Characteristics, Industrial 5.0 V
Parameter Description Conditions Min Typ Max Unit
VOH High level output voltage IOH = 4.0 mA 2.4 – – V
VOL Low level output voltage IOL = 4.0 mA – – 0.4 V
VIH High level input voltage[11] Except crystal pins 2.0 – – V
VIL Low level input voltage[11] Except crystal pins – – 0.8 V
IIH Input high current VIN = VDD – 0.5 V – < 1 10 µA
IIL Input low current VIN = +0.5 V – < 1 10 µA
IOZ Output leakage current Tristate outputs – – 250 µA
IDD VDD supply current[12] industrial VDD = VDD max, 5 V operation – 75 110 mA
IDDS VDD power supply current in shutdown mode[12] Shutdown active – 10 100 µA
Electrical Characteristics, Industrial 3.3 V
Parameter Description Conditions Min Typ Max Unit
VOH High level output voltage IOH = 4.0 mA 2.4 – – V
VOL Low level output voltage IOL = 4.0 mA – – 0.4 V
VIH High level input voltage[11] Except crystal pins 2.0 – – V
VIL Low level input voltage[11] Except crystal pins – – 0.8 V
IIH Input high current VIN = VDD – 0.5 V – < 1 10 µA
IIL Input low current VIN = +0.5 V – < 1 10 µA
IOZ Output leakage current Tristate outputs – – 250 µA
IDD VDD supply current[12] industrial VDD = VDD max, 3.3 V operation – 50 70 mA
IDDS VDD power supply current in shutdown mode[12] Shutdown active – 10 100 µA
Notes
11. Xtal inputs have CMOS thresholds.
12. Load = Max, VIN = 0 V or VDD, Typical (–104) configuration, CPUCLK = 66 MHz. Other configurations vary. Power can be approximated by the following formula (multiply
by 0.65 for 3 V operation): IDD = 10 + 0.06•(FCPLL + FUPLL + 2•FSPLL) + 0.27•(FCLKA + FCLKB + FCLKC + FCLKD + FCPUCLK + FXBUF).
CY2292
Document Number: 38-07449 Rev. *I Page 7 of 16
Switching Characteristics, Commercial 5.0 V
Parameter Name Description Min Typ Max Unit
t1Output period Clock output range, 5 V
operation
CY2292SC, SXC 10
(100 MHz)
– 13000
(76.923 kHz)
ns
CY2292F, FXC, FZX 11.1
(90 MHz)
– 13000
(76.923 kHz)
ns
Output duty cycle[13] Duty cycle for outputs, defined as t2 t1[14]
fOUT > 66 MHz
40 50 60 %
Duty cycle for outputs, defined as t2 t1[14]
fOUT < 66 MHz
45 50 55 %
t3Rise time Output clock rise time[15] –3 5 ns
t4Fall time Output clock fall time[15] –2.5 4 ns
t5Output disable time Time for output to enter tristate mode after
SHUTDOWN/OE goes LOW
–10 15 ns
t6Output enable time Time for output to leave tristate mode after
SHUTDOWN/OE goes HIGH
–10 15 ns
t7Skew Skew delay between any identical or related
outputs[14, 16] – < 0.25 0.5 ns
t8CPUCLK slew Frequency transition rate 1.0 – 20.0 MHz /
ms
t9A Clock jitter[16] Peak-to-peak period jitter (t9A max – t9A min),
percentage of clock period (fOUT < 4 MHz)
–< 0.5 1 %
t9B Clock jitter[16] Peak-to-peak period jitter (t9B max – t9B min)
(4 MHz < fOUT < 16 MHz)
– < 0.7 1 ns
t9C Clock jitter[16] Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) – < 400 500 ps
t9D Clock jitter[16] Peak-to-peak period jitter (fOUT > 50 MHz) – < 250 350 ps
t10A Lock time for CPLL Lock time from power-up – < 25 50 ms
t10B Lock time for UPLL and
SPLL
Lock time from power-up – < 0.25 1 ms
Slew limits CPU PLL slew limits CY2292SC, SXC 20 – 100 MHz
CY2292F, FXC, FZX 20 – 90 MHz
Switching Characteristics, Commercial 3.3 V
Parameter Name Description Min Typ Max Unit
t1Output period Clock output range, 3.3 V
operation
CY2292SL, SXL 12.5
(80 MHz)
– 13000
(76.923 kHz)
ns
CY2292F, FXC, FZX 15
(66.6 MHz)
– 13000
(76.923 kHz)
ns
Output duty cycle[13] Duty cycle for outputs, defined as t2 t1[14]
fOUT > 66 MHz
40 50 60 %
Duty cycle for outputs, defined as t2 t1[14]
fOUT < 66 MHz
45 50 55 %
t3Rise time Output clock rise time[15] –3 5 ns
t4Fall time Output clock fall time[15] –2.5 4 ns
Notes
13. XBUF duty cycle depends on XTALIN duty cycle.
14. Measured at 1.4 V.
15. Measured between 0.4 V and 2.4 V.
16. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit.
CY2292
Document Number: 38-07449 Rev. *I Page 8 of 16
t5Output disable time Time for output to enter tristate mode after
SHUTDOWN/OE goes LOW
–10 15 ns
t6Output enable time Time for output to leave tristate mode after
SHUTDOWN/OE goes HIGH
–10 15 ns
t7Skew Skew delay between any identical or related
outputs[18, 20] – < 0.25 0.5 ns
t8CPUCLK slew Frequency transition rate 1.0 – 20.0 MHz /
ms
t9A Clock jitter[20] Peak-to-peak period jitter (t9A max – t9A min),
percentage of clock period (fOUT < 4 MHz)
–< 0.5 1 %
t9B Clock jitter[20] Peak-to-peak period jitter (t9B max – t9B min)
(4 MHz < fOUT < 16 MHz)
–< 0.7 1 ns
t9C Clock jitter[20] Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) – < 400 500 ps
t9D Clock jitter[20] Peak-to-peak period jitter (fOUT > 50 MHz) – < 250 350 ps
t10A Lock time for CPLL Lock time from power-up – < 25 50 ms
t10B Lock time for UPLL and
SPLL
Lock time from power-up – < 0.25 1 ms
Slew limits CPU PLL slew limits CY2292SL, SXL 20 – 80 MHz
CY2292F, FXC, FZX 20 – 66.6 MHz
Switching Characteristics, Industrial 5.0 V
Parameter Name Description Min Typ Max Unit
t1Output period Clock output range, 5 V
operation
CY2292SI, SXI 11.1
(90 MHz)
– 13000
(76.923 kHz)
ns
CY2292FXI, FZXI 12.5
(80 MHz)
– 13000
(76.923 kHz)
ns
Output duty cycle[17] Duty cycle for outputs, defined as t2 t1[18]
fOUT > 66 MHz
40 50 60 %
Duty cycle for outputs, defined as t2 t1[18]
fOUT < 66 MHz
45 50 55 %
t3Rise time Output clock rise time[19] –3 5 ns
t4Fall time Output clock fall time[19] –2.5 4 ns
t5Output disable time Time for output to enter tristate mode after
SHUTDOWN/OE goes LOW
–10 15 ns
t6Output enable time Time for output to leave tristate mode after
SHUTDOWN/OE goes HIGH
–10 15 ns
t7Skew Skew delay between any identical or related
outputs[18, 20] – < 0.25 0.5 ns
t8CPUCLK slew Frequency transition rate 1.0 – 20.0 MHz /
ms
t9A Clock jitter[20] Peak-to-peak period jitter (t9A max – t9A min),
percentage of clock period (fOUT < 4 MHz)
–< 0.5 1 %
t9B Clock jitter[20] Peak-to-peak period jitter (t9B max – t9B min)
(4 MHz < fOUT < 16 MHz)
–< 0.7 1 ns
Switching Characteristics, Commercial 3.3 V (continued)
Parameter Name Description Min Typ Max Unit
Notes
17. XBUF duty cycle depends on XTALIN duty cycle.
18. Measured at 1.4 V.
19. Measured between 0.4 V and 2.4 V.
20. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit.
CY2292
Document Number: 38-07449 Rev. *I Page 9 of 16
t9C Clock jitter[24] Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) – < 400 500 ps
t9D Clock jitter[24] Peak-to-peak period jitter (fOUT > 50 MHz) – < 250 350 ps
t10A Lock time for CPLL Lock time from power-up – < 25 50 ms
t10B Lock time for UPLL and
SPLL
Lock time from power-up – < 0.25 1 ms
Slew limits CPU PLL slew limits CY2292SI, SXI 20 – 90 MHz
CY2292FXI, FZXI 20 – 80 MHz
Switching Characteristics, Industrial 3.3 V
Parameter Name Description Min Typ Max Unit
t1Output period Clock output range, 3.3 V
operation
CY2292SI, SXI 15
(66.6 MHz)
– 13000
(76.923 kHz)
ns
CY2292FXI, FZXI 16.66
(60 MHz)
– 13000
(76.923 kHz)
ns
Output duty cycle[21] Duty cycle for outputs, defined as t2 t1[22]
fOUT > 66 MHz
40 50 60 %
Duty cycle for outputs, defined as t2 t1[22]
fOUT < 66 MHz
45 50 55 %
t3Rise time Output clock rise time[23] –3 5 ns
t4Fall time Output clock fall time[23] –2.5 4 ns
t5Output disable time Time for output to enter tristate mode after
SHUTDOWN/OE goes LOW
–1015 ns
t6Output enable time Time for output to leave tristate mode after
SHUTDOWN/OE goes HIGH
–1015 ns
t7Skew Skew delay between any identical or related
outputs[22, 24] – < 0.25 0.5 ns
t8CPUCLK slew Frequency transition rate 1.0 – 20.0 MHz /
ms
t9A Clock jitter[24] Peak-to-peak period jitter (t9A max – t9A min),
percentage of clock period (fOUT < 4 MHz)
–< 0.5 1 %
t9B Clock jitter[24] Peak-to-peak period jitter (t9B max – t9B min)
(4 MHz < fOUT < 16 MHz)
– < 0.7 1 ns
t9C Clock jitter[24] Peak-to-peak period jitter
(16 MHz < fOUT < 50 MHz)
– < 400 500 ps
t9D Clock jitter[24] Peak-to-peak period jitter
(fOUT > 50 MHz)
– < 250 350 ps
t10A Lock time for CPLL Lock time from power-up – < 25 50 ms
t10B Lock time for UPLL and
SPLL
Lock time from power-up – < 0.25 1 ms
Slew limits CPU PLL slew limits CY2292SI, SXI 20 – 66.6 MHz
CY2292FXI, FZXI 20 – 60 MHz
Switching Characteristics, Industrial 5.0 V (continued)
Parameter Name Description Min Typ Max Unit
Notes
21. XBUF duty cycle depends on XTALIN duty cycle.
22. Measured at 1.4 V.
23. Measured between 0.4 V and 2.4 V.
24. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit.
CY2292
Document Number: 38-07449 Rev. *I Page 10 of 16
Switching Waveforms
Figure 2. All Outputs, Duty Cycle and Rise / Fall Time
t1
Output
t2
t3t4
Figure 3. Output Tristate Timing[30]
Figure 4. CLK Outputs Jitter and Skew
t7
CLK
Output
Related CLK
t9A
Figure 5. CPU Frequency Change
Note
30. The CY2292 has weak pull downs on all outputs. Hence, when a tristate condition is forced on the outputs, the output pins are pulled low.
Select
CPU
Old Select New Select Stable
F
old Fnew
t8&t10
CY2292
Document Number: 38-07449 Rev. *I Page 11 of 16
Possible Configurations
Some product offerings are factory programmed customer specific devices with customized part numbers. This table shows the
available device types, but not complete part numbers. Contact your local Cypress FAE or Sales Representative for more information
Test Circuit
Ordering Information
Ordering Code Package Type Operating Range Operating Voltage
Pb-free
CY2292FXC 16-pin SOIC Commercial, 0 C to 70 C 3.3 V or 5.0 V
CY2292FXCT 16-pin SOIC – Tape and Reel Commercial, 0 C to 70 C 3.3 V or 5.0 V
CY2292FXI 16-pin SOIC Industrial, –40 C to 85 C 3.3 V or 5.0 V
CY2292FXIT 16-pin SOIC – Tape and Reel Industrial, –40 C to 85 C 3.3 V or 5.0 V
CY2292FZX 16-pin TSSOP Commercial, 0 C to 70 C 3.3 V or 5.0 V
CY2292FZXT 16-pin TSSOP – Tape and Reel Commercial, 0 C to 70 C 3.3 V or 5.0 V
CY2292FZXI 16-pin TSSOP Industrial, –40 C to 85 C 3.3 V or 5.0 V
CY2292FZXIT 16-pin TSSOP – Tape and Reel Industrial, –40 C to 85 C 3.3 V or 5.0 V
Programmer
CY3670 FTG Clock Programmer
CY3095 Adapter for programming the CY2292F on the CY3670
0.1 F
VDD
0.1 F
VDD
CLKout
CLOAD
GND
Outputs
Ordering Code Package Type Operating Range Operating Voltage
Pb-free
CY2292SXC–XXX 16-pin SOIC Commercial, 0 C to 70 C5.0V
CY2292SXC–XXXT 16-pin SOIC – Tape and Reel Commercial, 0 C to 70 C5.0V
CY2292SXL–XXX 16-pin SOIC Commercial, 0 C to 70 C3.3V
CY2292SXI–XXX 16-pin SOIC Industrial, –40 C to 85 C 3.3 V or 5.0 V
CY2292SXI–XXXT 16-pin SOIC – Tape and Reel Industrial, –40 C to 85 C 3.3 V or 5.0 V
CY2292
Document Number: 38-07449 Rev. *I Page 12 of 16
Ordering Code Definition
Package Characteristics
Package JA (C/W) JC (C/W) Transistor Count
16-pin SOIC 83 19 9271
T = Tape and Reel; blank = Tube
Custom configuration code (factory programmed device only)
Temperature: C or L or blank = commercial; I = industrial
X = Pb-free package
Package: Z = TSSOP; S or blank = SOIC
Programming: F = field programmable; blank = factory programmed
Device part number
Company ID: CY = Cypress
2292CY (S) X (T)
(F) (C) (–xxx)
CY2292
Document Number: 38-07449 Rev. *I Page 13 of 16
Package Diagrams
Figure 6. 16-Pin (150-Mil) SOIC S16.15
51-85068 *E
51-85091 *D
Figure 7. 16-Pin TSSOP 4.40 mm Body Z16.173
CY2292
Document Number: 38-07449 Rev. *I Page 14 of 16
Acronyms
Document Conventions
Units of Measure
Acronym Description
CPU central processing unit
CMOS complementary metal oxide semiconductor
DC direct current
EPROM erasable programmable read only memory
FAE field application engineer
FTG frequency Timing Group
OE output enable
OSC oscillator
PD power down
PLL phase locked loop
ROM read only memory
SOIC small outline integrated circuit
TSSOP thin shrunk small outline package
Symbol Unit of Measure
°C degree Celsius
kkilohms
MHz megahertz
µA microamperes
mA milliamperes
ms milliseconds
mW milliwatts
ns nanoseconds
ohms
% percent
pF picofarads
ppm parts per million
ps picoseconds
Vvolts
CY2292
Document Number: 38-07449 Rev. *I Page 15 of 16
Document History Page
Document Title: CY2292 Three PLL General Purpose EPROM Programmable Clock Generator
Document Number: 38-07449
Revision ECN Orig. of
Change
Submission
Date Description of Change
** 116993 DSG 07/01/02 Changed from Spec number: 38-00946 to 38-07449
*A 119639 CKN 12/05/02 Changed 8 MHz to 20 MHz in Power-saving Features
*B 277130 RGL 10/26/04 Added Lead-free Devices
*C 395808 RGL 09/07/05 Minor Change: fixed the typo in the ordering code
*D 2565316 AESA/KVM 09/16/08 Updated template. Added Note “Not recommended for new designs.”
Removed parts: CY2292FI, CY2292FIT, CY2292FZ, and CY2292FZT.
Changed Lead-Free to Pb-Free. Changed CyClock reference to include Cyber-
Clock
*E 2761988 KVM 09/10/09 Corrected operating range attribute for CY2292FZXI and CY2292FZXI in
Ordering Information table.
Revised Selector Guide (p. 1): removed Outputs column, updated part number
suffixes, and consolidated two rows
Updated part number suffixes in Switching Characteristics tables
*F 2897775 KVM 03/23/10 Removed inactive parts from the ordering information table. Moved xxx parts
to Possible Configurations table.Updated package diagrams.
*G 2948137 KVM 06/09/10 Updated Figure 1 title (to include both SOIC and TSSOP)
Added table of contents. Added Acronyms
*H 3010397 KVM 08/18/2010 Added ordering code definition.
Added programmer and adapter to ordering information table.
Added CY3095 adapter to programmer text description.
Removed reference to obsolete CY2071F.
*I 3849272 PURU 12/21/2012 Removed “Understanding the CY2291 and CY2292” application note related
information in all instances across the document.
Updated Package Diagrams:
spec 51-85068 – Changed revision from *C to *E.
spec 51-85091 – Changed revision from *C to *D.
Document Number: 38-07449 Rev. *I Revised December 21, 2012 Page 16 of 16
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY2292
© Cypress Semiconductor Corporation, 2002-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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