DATA SH EET
Product specification
Supersedes data of 2001 Mar 27 2001 Jun 29
INTEGRATED CIRCUITS
UDA1344TS
Low-voltage low-power stereo
audio CODEC with DSP features
2001 Jun 29 2
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
FEATURES
General
•Low power cons umption
•3.0 V power supply
•System clock of 256fs, 384fsand 512fs
•Supports sampling frequencies from 8 to 55 kHz
•Non-inverting ADC plus integra ted high-pass filter to
cancel DC offset
•ADC supports 2 V (RMS) input s ignals
•Overload detector for easy record level control
•Separate power control for ADC and DAC
•Integrated digital in terpolation filter plus non-inverting
DAC
•Functions controllable either via L3 microcontroller
interface or via static pins
•UDA1344TS is pin and function compatible with
UDA1340M
•Small package size (SSOP28)
•Easy application .
Multiple format input interface
•I2S-bus, MSB-justified or LSB-justified
16, 18 and 20 bits format compatible
•Three combined data formats with MSB-justified output
and LSB-jus tified 16, 18 and 20 bits input
•1fsinput and output format data rate.
DAC digital sound processing
The sound processing features of the UDA1344TS can be
used in the L3 mode only:
•Digital tone control, bass boost a nd treble
•Digital dB-linear volume control (low microcontroller
load) via L3 microcontroller
•Digital de-emphasis for 32, 44.1 and 48 kHz
•Soft mute.
Advanced audio configuration
•Stereo single-ended input configuration
•Stereo line output (under microcontroller volume
control), no post filter required
•High linearity, dynamic ra nge and low distortion.
GENERAL DESCRIPTION
The UDA1344TS is a single-chip stereo Analog-to -Digital
Converter (ADC) and Digital-to- Analog Converter (DAC)
with signal processing features employing bitstream
conversion tech niques. The low power co nsumption and
low voltage requirements mak e the device eminently
suitable for use in low-voltage low-power portable digital
audio equip ment which incorporates re co rding and
playback functions.
The UDA1344TS supports the I2S-bus data format with
word lengths of up to 20 bits, the MSB-justified data format
with word lengths of up to 20 bits and the LSB-justified
data format with word lengths of 16, 18 and 20 bits. The
UDA1344TS also supports three co mbined data formats
with MSB-justified data ou tp ut an d LSB-justified
16, 18 and 20 bits data input.
The UDA1344TS can be controlled either via static pins or
via the L3 interface. In the L3 mode the UDA1344TS has
special Digital Sound Processin g (D SP) features in
playback mode such as de-e mphasis, volume control,
bass boost, treble and soft mute.
ORDERING INFORMATION
TYPE
NUMBER PACKAGE
NAME DESCRIPTION VERSION
UDA1344TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1
2001 Jun 29 3
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
QUICK REFERENCE DATA
Notes
1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately
1 mA by using a series resistor.
2. The input volta ge to the ADC is inversely proportional to the supply voltage.
3. The output voltage of the UDA1344TS differs from the output voltage of the UDA1340M.
4. The output of the DAC scales proportionally with the supply vo ltage.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VDDA(ADC) ADC analog supply voltage 2.7 3.0 3.6 V
VDDA(DAC) DAC analog supply voltage 2.7 3.0 3.6 V
VDDO operational amplifier supply voltage 2.7 3.0 3.6 V
VDDD digital supply voltage 2.7 3.0 3.6 V
IDDA(ADC) ADC analog su pply current operating −9.0 11.0 mA
ADC power-dow n −3.5 5.0 mA
IDDA(DAC) DAC analog supply current operating −4.0 6.0 mA
DAC power-down −25 75 μA
IDDO operational amplifier su pply current operating −4.0 6.0 mA
DAC power-down −250 350 μA
IDDD digit al supply current operating −6.0 9.0 mA
DAC power-down −2.5 4.0 mA
ADC power-dow n −3.5 5.0 mA
Tamb ambient temperature −40 −+85 °C
Analog-to-digit al converter
Vi(rms) input voltage (RMS value) notes 1 and 2 −1.0 −V
(THD + N) /S total harmonic distortion-p lus-noise to
signal ratio at 0 dB −−85 −80 dB
at −60 dB; A-weighted −−35 −30 dB
S/N signal-to-noise ratio Vi= 0 V; A-weighted −95 −dB
αcs channel separation −100 −dB
Digital-to-analog converter
Vo(rms) output voltage (RMS value) notes 3 and 4 −900 −mV
(THD + N) /S total harmonic distortion-p lus-noise to
signal ratio at 0 dB −−90 −85 dB
at −60 dB; A-weighted −−37 −dB
S/N signal-to-noise r atio c ode = 0; A-weighted −100 −dB
αcs channel separation −100 −dB
Power performance
PADDA power cons umption in record and
playback mod e −69 −mW
PDA power consump t ion in playback mode −42 −mW
PAD power consumption in record mode −37.5 −mW
PPD power consump t ion in power-down mode −17 −mW
2001 Jun 29 4
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
MGL441
ADC
0 dB/6 dB
SWITCH 0 dB/6 dB
SWITCH
35
10
11
18
16
17
19
25 27 23 22
12
15
14
13
20
21
8
VINL
VDDD
VSSD
DATAO
BCK
WS
DATAI
MP1
VOUTL
28
24
9
26 VOUTR
SYSCLK
MP4
MP3
MP2
MP5
MC2
MC1
VINR
21 76 4
DECIMATION FILTER
DC-CANCELLATION FILTER
DIGITAL INTERFACE L3-BUS
INTERFACE
ADC
DAC
Vref(D)
VDDO VSSO
DAC
INTERPOLATION FILTER
NOISE SHAPER
DSP FEATURES
VDDA(ADC) VSSA(ADC) VADCP VADCN Vref(A)
UDA1344TS
VDDA(DAC) VSSA(DAC)
2001 Jun 29 5
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
PINNING
SYMBOL PIN DESCRIPTION
VSSA(ADC) 1 ADC analog ground
VDDA(ADC) 2 ADC analog supply voltage
VINL 3 ADC input left
Vref(A) 4 ADC reference vo ltage
VINR 5 ADC input right
VADCN 6 ADC negative reference voltage
VADCP 7 ADC positive reference voltage
MC1 8 mode control 1 input (pull-down)
MP1 9 multi-purpose pin 1 output
VDDD 10 digital supply voltage
VSSD 11 digit al ground
SYSCLK 12 system clock input:
256fs,384f
sor 512fs
MP2 13 multi-purpose pin 2 input
MP3 14 multi-purpose pin 3 input
MP4 15 multi-purpose pin 4 input
BCK 16 bit clock input
WS 17 word select inpu t
DATAO 18 data output
DATAI 19 data input
MP5 20 multi-purpose pin 5 output
(pull-down)
MC2 21 mode control 2 input (pull-down)
VSSA(DAC) 22 DAC analog gro und
VDDA(DAC) 23 DAC analog supply voltage
VOUTR 24 DAC output right
VDDO 25 operational amplifier supply voltage
VOUTL 26 DAC output left
VSSO 27 operational amplifier ground
Vref(D) 28 DAC reference voltage Fig.2 Pin configuration.
handbook, halfpage
VSSA(ADC)
VDDA(ADC)
VINL
Vref(A)
VINR
VADCN
VADCP
MC1
MP1
VDDD
VSSD
SYSCLK
MP2
MP3
Vref(D)
VSSO
VOUTL
VDDO
VDDA(DAC)
VSSA(DAC)
VOUTR
MC2
MP5
DATAI
DATAO
WS
BCK
MP4
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
UDA1344TS
MGL442
2001 Jun 29 6
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
FUNCTIONAL DESCRIPTION
The UDA1344TS acc ommodates slave mode only, th is
means that in all applicat ions the system de vices must
provide the system clock. The system clock must be
locked in frequency to the digital interface input signals.
The BCK clock can be up to 128fs, or in other words the
BCK frequency is 128 times the Word Select (WS)
frequency or less: fBCK =<128×fWS.
Remarks:
1. The WS edge MUST fall on the neg ative edg e of the
BCK clock at all times for proper operation of the digital
I/O data interface
2. The sampling frequency range is from 8 to 55 kHz
3. For MSB- and LSB-justified formats it is important to
have a WS signal with a duty factor of 50%.
Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1344 TS consists of two
3rd-order Sigma-Delta modula tors. They have a modified
Ritchie-coder architecture in a differential switched
capacitor impleme ntation. The oversampling ra tio is 128.
In contrast to the UDA1340M, the UDA1344TS supports
1 V (RMS) input signals and can be set, via an external
resistor, to su pport 2 V (RMS) input s i gnals.
Analog front-end
The analog front-end is equipped with a selectable 0 dB or
6 dB gain block. The pin to select the gain switch is given
in Section “L3 mode”. This block ca n be used in
applications in which both 1 V (RMS) and 2 V (RMS) input
signals are available.
In applications in which a 2 V (RMS) input signal is used ,
a 12 kΩ resistor must be connected in series with the input
of the ADC. This makes a voltage divider with the internal
ADC resistor and ma kes sure only 1 V (RMS) maximum is
input to the IC. Using this application for a 2 V (RMS) input
signal, the gain switch must be set to 0 dB. When a
1 V (RMS) input signal is input to the ADC in the same
application, the gain switch must be set to 6 dB.
An overview of the maximum input voltages allowed
against the presence of an external resistor and the setting
of the gain switch is giv en in Table 1.
Table 1 Application modes using input gain stage
Decimation filter (ADC)
The decimati on from 128fsto 1fs is pe rformed in 2 stages.
The first stage realizes 3rd-order characteristic. This
filter decreases the sa mple rate by 16.
The second st age, a Finite Imp ulse Resp onse (FI R) filt er,
consists of 3 half-band filters, each dec imating by a factor
of 2.
Table 2 Decimation filter characteristics
DC-cancellation filter (ADC)
An optional Infinite Impulse-Response (IIR) high-pass filter
is provided to remove unwanted DC components.
The operation is selected by the microcontroller via the
L3 interface. The filter characteristics are given in Table 3.
Table 3 DC-cancellation filter c haracteristics
RESISTOR
(12 kΩ)INPUT GAIN
SWITCH
MAXIMUM
INPUT
VOLTAGE
Present 0 dB 2 V (RMS)
Present 6 dB 1 V (RMS)
Absent 0 dB 1 V (RMS)
Absent 6 dB 0.5 V (RMS)
ITEM CONDITIONS VALUE (dB)
Pass-band ripple 0 −0.45fs±0.05
Stop band >0.55fs−60
Dynamic range 0 −0.45fs108
Overall gain with
0 dB input to the
ADC
DC −1.16
ITEM CONDITIONS VALUE (dB)
Pass-band ripple −none
Pass-band gain −0
Droop at 0.00045fs0.031
Attenuation at DC at 0.00000036fs>40
Dynamic range 0 −0.45fs>110
sin x
x
------------
2001 Jun 29 7
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
Mute (ADC)
On recovery from po wer-down or switching on of the
system clock, the serial data output on pin DATAO is held
at LOW level until valid data is available from the
decimation filter. This time depends on whether th e
DC-cancellation filter is selected:
•DC cancel off:
; t = 23.2 ms at fs=44.1kHz
•DC cancel on:
; t = 279 ms at fs=44.1kHz.
Interpolation filter (DAC)
The digital filter interpolates from 1fsto 128fs by means of
a cascade of a recursive filter and an FIR filter.
Table 4 Interpolation filter characteristics
Noise shaper (DAC)
The 3rd-order no ise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise sh aping technique enab les high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a Filter
Stream Digital-to-Analog Converter (FSD AC).
Filter stream DAC
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output vo ltage. The filter coeffici ents are
implemented as current sources and are summed at virtual
ground of th e output opera tional amplifier. In t his way very
high signal-to-noise performance and low clock jitter
sensitivity is achieved . A post-filter is not needed due to
the inherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
The output voltage of the FSDAC scales proportionally
with the power su pply voltage.
Multiple format input/output interface
The UDA1344TS supports the following data input/output
formats:
•I2S-bus format with data word length of up to 20 bits
•MSB-justified serial format with data word length of up to
20 bits
•LSB-justified serial format with data word lengths of
16, 18 or 20 bits (in L3 mode o nly )
•Combined data formats:
– L3 mode: MSB-justified data output and
LSB-justified 16, 18 and20bits data input
– Static pin mode: MSB-justified data output and
LSB-justified 16 and 20 bits data input.
The formats are illustrated in Fig.3. Left and right
data-channel words are time multiplexed.
Control mode selection
The UDA1344TS can be used under L3 microcontroller
interface control or static pin control. The mode can be set
via the mode control pins MC1 an d MC2 (see Table 5).
Table 5 Mode control pins
Important: in the L3 mode the UDA1344TS is complet ely
pin and function compatible with the UDA1340M.
ITEM CONDITIONS VALUE (dB)
Pass-band rip p l e 0 −0.45fs±0.03
St op band >0.55fs−50
Dynamic range 0 −0.45fs108
Gain DC −3.5
t1024
fs
-------------
=
t12288
fs
----------------
=
PINMC2 PINMC1 MODE
LOW LOW L3 mode
LOW HIGH Test mode
HIGH LOW
HIGH HIGH Static pin mode
2001 Jun 29 8
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
ndb
ook, full pagewidth
16
MSB B2 B3 B4 B5 B6
LEFT
LSB-JUSTIFIED FORMAT 20 BITS
W
S
B
CK
D
ATA
RIGHT
1518 1720 19 2 1
B19 LSB
16
MSB B2 B3 B4 B5 B6
1518 1720 19 2 1
B19 LSB
MSB MSBB2
21> = 812 3
LEFT
I2S-BUS FORMAT
WS
BCK
D
ATA
RIGHT
3> = 8
MSB B2
MBL14
0
16
MSB B2
LEFT
LSB-JUSTIFIED FORMAT 16 BITS
W
S
B
CK
D
ATA
RIGHT
15 2 1
B15 LSB
16
MSB B2
15 2 1
B15 LSB
16
MSB B2 B3 B4
LEFT
LSB-JUSTIFIED FORMAT 18 BITS
W
S
B
CK
D
ATA
RIGHT
1518 17 2 1
MSB B2 B3 B4
B17 LSB
16 1518 17 2 1
B17 LSB
MSB-JUSTIFIED FORMAT
W
SLEFT RIGHT
321321
MSB B2 MSBLSB LSB MSB B2B2
> = 8 > = 8
B
CK
D
ATA
Fig.3 Serial interface formats.
2001 Jun 29 9
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
Static pin mode
The UDA1344TS is set to static pin mode by settin g both
pins MC1 and MC2 to HIGH level.
The controllable features in this mode are:
•System clock frequency selection
•Data input/output format selection
•De-emphasis a nd mute control
•Power-down an d ADC input level selection.
PINNING DEFINITION
The pinning definitio n in the stat ic pin mode is given in
Table 6.
Table 6 Pinning definition in static pin model
SYSTEM CLOCK
In the static pin mode the options are 256fs and 384fs as
given in Table 7.
Table 7 System clock selection
MUTE AND DE-EMPHASIS
The level definition of pin MP2 pin is given in Tab le 8.
Table 8 Levels for pin MP2
INPUT/OUTPUT DATA FORMAT SELECTION
The input/output data format can be selected using
pins MP1 and MP5 as given in Table 9.
Table 9 Data format selection
ADC INPUT VOLTAGE SELECTION AND POWER-DOWN
In the static pin mode the three- lev el pin MP4 is used to
select 0 or 6 dB ga in and power-dow n.
Table 10 Levels for pin MP4
PIN DESCRIPTION
MP1 data input/output setting
MP2 three-level pin to select no
de-emphasis, de -emphasis or mute
MP3 256fsor 384fs system clock sele ction
MP4 three-level pin to select
ADC po we r- down, ADC input
1 V (RMS) or ADC input 2 V (RMS)
MP5 data input/output setting
PIN MP3 SELECTION
LOW 256fs clock frequency
HIGH 384fs clock frequency
PIN MP2 SELECTION
LOW no de-emphasi s and mute
0.5VDDD de-emphasis 44 .1 kHz
HIGH mute
PIN MP1 PIN MP5 SELECTION
LOW LOW input: MSB-justified
LOW HIGH input: I2S-bus
HIGH LOW input: LSB-justified 20 bits;
output: MSB-justified
HIGH HIGH input: LSB-justified 16 bits;
output: MSB-justified
PIN MP4 SELECTION
LOW ADC power-down
0.5VDDD 6dB gain
HIGH 0 dB gain
2001 Jun 29 10
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
L3 mode
The UDA1344TS is set to the L3 mode by setting both
pins MC1 and MC2 to LOW level.
The static pins in this mode are used for:
•ADC output overload detection
•L3 interface signal input
•ADC input voltage selection.
The controllable features via the L3 interface and the
definition of the control registers are given in
Section “L3 interface”.
PINNING DEFINITION
The pinning definition in the L3 mode is given in Table 11.
Table 11 Pinning definition in L3 mode
ADC OUTPUT OVERLOAD DETECTION
In practice the output is us ed to indicate whenever the
output data, in either the left or right channel, is greater
than −1 dB (actual figure is −1.16 dB) of the maximum
possible digital swing. When this condition is detected
pin MP1 is forced to HIGH level for at least 512fscycles
(11.6 ms at fs= 44.1 kHz). This time-o ut is re set for each
infringement.
ADC INPUT VOLTAGE SELECTION
In the L3 mode pin MP5 is used to select 0 or 6 dB gain.
Table 12 Levels for pin MP5
PIN FUNCTION
MP1 ADC output overload detection
MP2 L3MODE input
MP3 L3CLOCK input
MP4 L3DATA input
MP5 ADC inpu t voltage selection:
1 V (RMS) or 2 V (RMS)
PIN MP4 SELECTION
LOW 0 dB gain
HIGH 6 dB gain
2001 Jun 29 11
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
L3 INTERFACE
The UDA1344TS has a microcontroller input mode. In the
microcontroller control mode, all the digital sound
processing features and the system controlling features
can be controlled by the mic rocontroller. The cont rollable
features are:
•System clock frequency
•Data input format
•Power control
•DC filtering
•De-emphasis
•Volume
•Flat/min./max. switch
•Bass boost
•Treble
•Mute.
The exchange of data and control information between the
microcontroller and the UDA1344TS is accomplished
through a serial hardware interface comprising the
following lines:
L3DATA: microcontroller interface data line
L3MODE: microcontroller interface mode line
L3CLOCK: microcontroller interface clock line.
Information transfer via the microcontroller bu s is LSB first
and is organized in accordance with the so called
‘L3’ format, in which two different modes of operation can
be distinguished: ad dress mode and data transfer mode.
The address mode is required to select a device
communicating via the L3 interface and to define the
destination registers for the data transfer mode. Data
transfer for the UDA134 4TS can only be in one direc tio n:
input to the UDA1344TS to program its sound processing
and other functional features.
Address mode
The address mode is used to sele ct a device for
subsequent data transf er and to define the destination
registers. The address mode is characterized by L3MODE
being LOW and a burst of 8 pulses on L3CLOCK,
accompanied by 8 data bits.
The fundamental timing is shown in Fig.4.
Data bits 7 to 2 represent a 6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The address of the
UDA1344TS is 000101 (bits 7 to 2).
Data bits 1 and 0 indicate the typ e of subsequent data
transfer as given in Table 13.
Table 13 Selection of data transfer
In the event that the UDA1344TS receives a different
address, it will deselect its microcontroller interface logic.
Data transfer mode
The selection prefo rmed in the address mode remains
active during subsequent data transfers, until the
UDA1344TS receives a new address command.
The fundamental t iming of data transf ers is essentially th e
same as in the address mode and is shown in Fig.5.
The maximum input clock and data rate is 64fs.
All transfers are byte wise, i.e. they are based on groups of
8 bits. Data will be stored in the UDA1344TS after the
eighth bit of a byte has been received.
A multibyte data transfer is illustrated in Fig.6.
Programming the sound processing and other
features
The sound processing and other feature values are stored
in independent registers.
The first selection of the registers is achieved by the choice
of data type that is transferred. This is performed in the
address mode by bit 1 and bit 0 (see Table 13).
The second selection is perfo rmed by the 2 MSBs of the
data byte (bit 7 and bit 6 ).
The other bits in the data byte (bits 5 to 0) is the value that
is placed in th e selected registers.
BIT 1 BIT 0 TRANSFER
0 0 data (volume, bass boost, treble,
de-emphasis, mute , mode and
power contro l)
0 1 not used
1 0 status (system clock frequency,
data input/output format and
DC filter)
1 1 not used
2001 Jun 29 12
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
handbook, full pagewidth
th(L3)A
th(L3)DA
tsu(L3)DA
Tcy(CLK)(L3)
BIT 0
L3MODE
L3CLOCK
L3DATA BIT 7
MGL723
tCLK(L3)H
tCLK(L3)L
tsu(L3)A
tsu(L3)A
th(L3)A
Fig.4 Timing in address mode.
handbook, full pagewidth tstp(L3) tstp(L3)
tsu(L3)D
tsu(L3)DA th(L3)DA
th(L3)D
MGL882
Tcy(CLK)L3
L3MODE
L3CLOCK
tCLK(L3)H
tCLK(L3)L
BIT 0
L3DATA
WRITE BIT 7
Fig.5 Timing in data transfer mode.
2001 Jun 29 13
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
handbook, full pagewidth tstp(L3)
address
L3DATA
L3CLOCK
L3MODE
addressdata byte #1 data byte #2 MGL725
Fig.6 Multibyte data transfer.
L3 interface registers
When the data transfer of type ‘status’ is selected, the features system clock frequency, data input format and DC filter
can be controlled.
Table 14 Data transfer of type ‘status’
When the data transfer of type ‘data’ is selected, the features volume, bass boost, treble, de-emphasis, mute, mode and
power control ca n be controlled.
Table 15 Data transfer of type ‘data’
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 REGISTER SELECTED
0 0 SC1 SC0 IF2 IF1 IF0 DC SC = s ystem clock freque ncy (2 bits); see Table 16
IF = data input forma t (3 bits); see Table 17
DC = DC filter (1 bit); see Table 18
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 REGISTER SELECTED
0 0 VC5 VC4 VC3 VC2 VC1 VC0 VC = volume control (6 bits); see Table 19
0 1 BB3 BB2 BB1 BB0 TR1 TR0 BB = bass boost (4 bits); see Table 20
TR = treble (2 bits); see Table 21
1 0 0 DE1 DE0 MT M1 M0 D E = de-emphas is (2 bits); see Table 22
MT=mute(1bit); seeTable23
M = filter mode (2 bits); see Table 24
1 1 0 0 0 0 PC1 PC0 PC = power control (2 bits); see Table 25
2001 Jun 29 14
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
SYSTEM CLOCK FREQUENCY
A 2-bit value to select the used external clock frequency.
Table 16 System clock frequency set tings
DATA INPUT FORMAT
A 3-bit value to select the used data format.
Table 17 Data format settings
DC FILTER
A 1-bit value to enable the digital DC filter.
Table 18 DC filtering
VOLUME CONTROL
A 6-bit value to prog ram the lef t and ri ght chan nel volume
attenuation. The range is from 0 to −∞ dB in steps of 1 dB.
Table 19 Volume settings
BASS BOOST
A 4-bit value to prog ram the ba ss boost setting. The used
set depends on the mode bits M1 and M0.
Table 20 Bass boost settings
SC1 SC0 SELECTION
0 0 512fs
0 1 384fs
1 0 256fs
1 1 not used
IF2 IF1 IF0 FORMAT
000I
2S-bus
0 0 1 LSB-justified 16 bits
0 1 0 LSB-justified 18 bits
0 1 1 LSB-justified 20 bits
1 0 0 MSB-justified
1 0 1 input: LSB-justified 16 bits;
output: MSB-justified
1 1 0 input: LSB-justified 18 bits;
output: MSB-justified
1 1 1 input: LSB-justified 20 bits;
output: MSB-justified
DC SELECTION
0 no DC filtering
1DCfiltering
VC5VC4VC3VC2VC1VC0 VOLUME(dB)
000000 0
000001 0
000010 −1
000011 −2
:::::: :
111011 −58
111100 −59
111101 −60
111110 −∞
111111 −∞
BB3 BB2 BB1 BB0 BASS BOOST SETTING
FLAT
(dB) MIN.
(dB) MAX.
(dB)
0000 0 0 0
0001 0 2 2
0010 0 4 4
0011 0 6 6
0100 0 8 8
0101 0 10 10
0110 0 12 12
0111 0 14 14
1000 0 16 16
1001 0 18 18
1010 0 18 20
1011 0 18 22
1100 0 18 24
1101 0 18 24
1110 0 18 24
1111 0 18 24
2001 Jun 29 15
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
TREBLE
A 2-bit value to program the treble setting. The used set
depends on the mode bits M1 and M0.
Table 21 Treble settings
DE-EMPHASIS
A 2-bit value to enable the digital de-emphasis filter.
Table 22 De-emphasis settings
MUTE
A 1-bit value to enable the digital mute.
Table 23 Mute
MODE
A 2-bit value to program the mode of the sound processing
filters of bass boost and treble.
Table 24 Flat/min./max. switch
POWER CONTROL
A 2-bit value to disable the ADC and/or DAC to reduce
power consumption.
Table 25 Power control settings
TR1 TR0 TREBLE SETTING
FLAT (dB) MIN. (dB) MAX. (dB)
00 0 0 0
01 0 2 2
10 0 4 4
11 0 6 6
DE1 DE0 SELECTION
0 0 no de-emphasis
0 1 de-emphasis 32 kHz
1 0 de-emphasis 44.1 kHz
1 1 de-emphasis 48 kHz
MT SELECTION
0no muting
1muting
M1 M0 SELECTION
00flat
01min.
10min.
11max.
PC1 PC0 SELECTION
ADC DAC
00offoff
01offon
10onoff
1 1 on on
2001 Jun 29 16
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
LIMITING VALUES
In accordance with the Absolute Max i mum Rating System (IEC 60134).
Notes
1. Equivalent to discha rging a 100 pF capacitor via a 1.5 kΩ series resistor.
2. Equivalent to discha rging a 200 pF capacitor via a 2.5 μH series inductor.
3. DAC oper ation cannot be guarantee d after a short-circuit has oc c urred.
THERMAL CHARACTE RISTICS
DC CHARACTERISTICS
VDDD =V
DDA =V
DDO = 3.0 V; Tamb =25°C; RL=5kΩ; all voltages referenced to grou nd; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDDD digital supply voltage −5.0 V
Txtal(max) maximum crystal temperature −150 °C
Tstg storage temperature −65 +125 °C
Tamb ambient temperature −40 +85 °C
Ves electrostatic handling voltage note 1 −3000 +3000 V
note 2 −300 +300 V
Ilu(prot) latch-up protection curre nt Tamb =25°C; VDD =3.6V −200 mA
Isc(DAC) DAC short- circuit current: Tamb =0°C; VDDA = 3.0 V; note 3
output short-circuited to VSSA(DAC) −482 mA
output short-circuited to VDDA(DAC) −346 mA
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to ambient in free air 90 K/W
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies; note 1
VDDA(ADC) ADC analog supply voltage 2.7 3.0 3.6 V
VDDA(DAC) DAC analog supply voltage 2.7 3.0 3.6 V
VDDO operational amplifier supply voltage 2.7 3.0 3.6 V
VDDD digital supply voltage 2.7 3.0 3.6 V
IDDA(ADC) ADC analog su pply current operating −9.0 11.0 mA
ADC power-dow n −3.5 5.0 mA
IDDA(DAC) DAC analog supply current operating −4.0 6.0 mA
DAC power-down −25 75 μA
IDDO operational amplifier supply current operating −4.0 6.0 mA
DAC power-down −250 300 μA
IDDD digital supply current operating −6.0 9.0 mA
DAC power-down −2.5 4.0 mA
ADC power-dow n −3.5 5.0 mA
2001 Jun 29 17
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
Notes
1. All power su pply pins (VDD and VSS) must be connected to the same exte rnal power supply unit.
2. When higher capacitive loads must be driven, a 100 Ω resistor must be connected in series with the DAC output in
order to prevent os cillations in the output o perational amplifier.
Digital inputs
VIH HIGH-level input voltage 0.8VDDD −VDDD +0.5 V
VIL LOW-level input voltage −0.5 −0.2VDDD V
⎪ILI⎪input leakage current −−10 μA
Ciinput capacitance −−10 pF
Digital outputs
VOH HIGH-level output voltage IOH =−2mA 0.85V
DDD −− V
VOL LOW-level output voltage IOL =2mA −−0.4 V
Three-level inputs: pins MP2 and MP4
VIH HIGH-level input voltage 0.9VDDD −VDDD +0.5 V
VIM MIDDLE-level input voltage 0.4VDDD −0.6VDDD V
VIL LOW-level input voltage −0.5 −0.1VDDD V
Analog-to-digit al converter
Vref(A) reference voltage refererred to
VSSA(ADC)
0.45VDDA 0.5VDDA 0.55VDDA V
Ro(refA) output resistance on pin Vref(A) −24 −kΩ
Riinput resistance fi=1kHz −9.8 −kΩ
Ciinput capacitance −20 −pF
Digital-to-analog converter
Vref(D) reference voltage refererred to
VSSA(DAC)
0.45VDDA 0.5VDDA 0.55VDDA V
Ro(refD) output resistance on pin Vref(D) −28 −kΩ
Rooutput resistance of DAC −0.13 3.0 Ω
Io(max) maximum output current (THD + N)/S < 0.1
%; RL=5kΩ
−0.22 −mA
RLload resistance 3 −− kΩ
CLload capacitance note 2 −−200 pF
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2001 Jun 29 18
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
AC CHARACTERISTICS
VDDD =V
DDA =V
DDO = 3.0 V; fi= 1 kHz; Tamb =25°C; RL=5kΩ; all voltages referenced to ground; unless otherwise
specified.
Notes
1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately
1 mA by using a series resistor.
2. The input voltage to the ADC is inversely proportional with the supply voltage.
3. The output voltage of the UDA1344TS differs from the output voltage of the UDA1340M.
4. The output of the DAC scales proportionally with the supply vo ltage.
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
Analog-to-digit al converter
Vi(rms) input voltage (RMS value) notes 1 and 2 1.0 −V
ΔViunbalance between channels 0.1 −dB
(THD + N) /S total harmonic distortion-plus-noise to signal ratio at 0 dB −85 −80 dB
at −60 dB; A-weighted −35 −30 dB
S/N signal-to-noise ratio Vi= 0 V; A-weighted 95 −dB
αcs channel separation 100 −dB
PSRR power supply rejection ra tio fripple =1kHz;
Vripple =300mV(p-p) 30 −dB
Digital-to-analog converter
Vo(rms) output voltage (RMS value) notes 3 and 4 900 −mV
ΔVounbalance between channels 0.1 −dB
(THD + N) /S total harmonic distortion-plus-noise to signal ratio at 0 dB −90 −85 dB
at −60 dB; A-weighted −37 −dB
S/N signal-to-noise r atio c ode = 0; A-we ighted 100 −dB
αcs channel separation 100 −dB
PSRR power supply rejection ra tio fripple =1kHz;
Vripple =300mV(p-p) 50 −dB
2001 Jun 29 19
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
TIMING
VDDD =V
DDA =V
DDO = 2.7 to 3.6 V; Tamb =−40 to +85 °C; RL=5kΩ; all voltages referenced to ground; unless
otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
System clock input (see Fig.7)
Tsys system clock cycle time fsys = 256fs78 88 −ns
fsys = 384fs52 59 −ns
fsys = 512fs39 44 −ns
tCWH system clock HIGH time fsys < 19.2 MHz 0.30Tsys −0.70Tsys ns
fsys ≥19.2 MHz 0.40Tsys −0.60Tsys ns
tCWL system clock LOW time fsys < 19.2 MHz 0.30Tsys −0.70Tsys ns
fsys ≥19.2 MHz 0.40Tsys −0.60Tsys ns
Serial interface input/output data (see Fig.8)
fBCK bit clock frequency −−64fsHz
Tcy(BCK) bit clock cycle time Tcy(s) = cycle time of
sample frequency −− ns
tBCKH bit clock HIGH time 100 −− ns
tBCKL bit clock LOW time 100 −− ns
trrise time −−20 ns
tffall time −−20 ns
tsu(WS) word select set-up time 20 −− ns
th(WS) word select hold time 10 −− ns
tsu(DATAI) data input set-up time 20 −− ns
th(DATAI) da ta input hold time 0 −− ns
th(DATAO) data output hold time 0 −− ns
td(DATAO−BCK) data output to bit clock delay from BCK falling edge −−80 ns
td(DATAO−WS) data output to word select delay from WS edge for
MSB-justified format −−80 ns
L3 interface input (see Figs 4 and 5)
Tcy(CLK)L3 L3CLOCK cycle time 500 −− ns
tCLK(L3)H L3CLOCK HIGH time 250 −− ns
tCLK(L3)L L3CLOCK LOW time 250 −− ns
tsu(L3)A L3MODE set-up time for address mode 190 −− ns
th(L3)A L3MODE ho ld time for ad dr ess mode 190 −− ns
tsu(L3)D L3MODE set-up time for data transfer
mode 190 −− ns
th(L3)D L3MODE h old time for dat a transfer mode 190 −− ns
tstp(L3) L3MODE stop time 190 −− ns
tsu(L3)DA L3DATA set-up time in data transfer and
address mode 190 −− ns
th(L3)DA L3DATA hold time in data transfer and
address mode 30 −− ns
Tcy(s)
64
-------------
2001 Jun 29 20
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
Fig.7 System clock timing.
handbook, full pagewidth
MGL443
tCWH
tCWL
Tsys
handbook, full pagewidth
MGS756
WS
BCK
DATAO
DATAI
tf
trth(WS) tsu(WS)
tBCKH
tBCKL
Tcy(BCK) th(DATAO)
tsu(DATAI) th(DATAI)
td(DATAO-BCK)
td(DATAO-WS)
Fig.8 Serial interface timing.
2001 Jun 29 21
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
APPLICATION INFORMATION
handbook, full pagewidth
MGL444
47 Ω
R30
C11
100 μF
(16 V)
C12
100 μF
(16 V)
VDD1
VDD2
L1
BLM32A07
BLM32A07
L2
3 V
g
round
1
VSSA(ADC)
UDA1344TS
12
4
SYSCLK
Vref(A)
10
26711
VDDD
VDDA(ADC) VADCN VADCP VSSD
s
ystem
clock
18
DATAO
16
BCK
17
WS
o
verload
flag 9
MP1
C1
47 μF
(16 V)
3
VINL
26 VOUTL R23
100 Ω
R22
10 kΩ
24 VOUTR R26
100 Ω
R27
10 kΩ
C6
47 μF
(16 V)
5
VINR
19
DATAI
13
MP2
14
MP3
15
MP4
100 nF
(63 V)
R21
1 Ω
10 Ω
R24
C2
100 μF
(16 V)
C25
100 nF
(63 V)
C21
VDD1
C3
47 μF
(16 V)
C8
47 μF
(16 V)
C5
47 μF
(16 V)
C22
100 nF
(63 V)
28 Vref(D)
C4
47 μF
(16 V)
C23
100 nF
(63 V)
100 nF
(63 V)
R28
1 Ω
C9
100 μF
(16 V)
C29
VDD2
VSSO
27 VDDO
25
R25
1 Ω
C7
100 μF
(16 V)
C26
100 nF
(63 V)
VDD1
VDDA(DAC)
VSSA(DAC)
23
22
R29
1 Ω
C10
100 μF
(16 V)
C27
100 nF
(63 V)
VDD1
left
outp
ut
righ
t
outp
ut
left
input
right
input
X5
X4
X2
X3
Fig.9 Application diagra m.
2001 Jun 29 22
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
PACKAGE OUTLINE
UNIT A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 10.4
10.0 5.4
5.2 0.65 1.25
7.9
7.6 0.9
0.7 1.1
0.7 8
0
o
o
0.13 0.10.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT341-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
114
28 15
0.25
y
pin 1 index
0 2.5 5 mm
scale
S
SOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341
-1
A
max.
2
2001 Jun 29 23
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth acco un t of sold er ing ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packag es”
(document order number 9398 652 90011).
There is no soldering method tha t is idea l for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-s yringe dispensing before package placement.
Several methods exist for reflowing; for example,
convection or convection/infrare d heating in a conveyor
type oven. Through put times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatur es range from
215to250°C. The top-surface temperature of the
packages sh ould preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Wave soldering
Conventional single wave solder ing is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wa ve soldering me thod comprising a
turbulent wave with high up ward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitc h (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axi s is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footp rint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board .
The footprint must incorporate solder thieves at the
downstream end.
•For packages with leads on four sides, the footprint must
be plac ed at a 45° angle to the transp ort direction of the
printed-circuit board. The footprint must incor porate
solder thieves downstream and at th e side corners.
During placement and before soldering, the package must
be fixed with a droplet of adh esive. The adhesive c an be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will elim inate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one ope ration within 2 t o 5 seconds between
270 and 320 °C.
2001 Jun 29 24
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with res pect to time) and body size of the package, there is a risk that internal or extern al package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Package s ; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top ve rsion).
3. If wave soldering is con sid ered, then the package mus t be placed at a 45° angle to the solder wave direc tion.
The package footprint must incorporate so lder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE SOLDERING METHOD
WAVE REFLOW(1)
BGA, HBGA, LFBGA, SQFP, TFBGA not suitable suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS not suitable(2) suitable
PLCC(3), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(3)(4) suitable
SSOP, TSSOP, VSO not recommended(5) suitable
2001 Jun 29 25
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
DATA SHEET STATUS
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The prod uct status of dev i ce(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on th e Internet at
URL http://www.nxp.com.
DOCUMENT
STATUS(1) PRODUCT
STATUS(2) DEFINITION
Objective data sheet Dev elopment This document co ntains data from the objective specification for pro duc t
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This doc ument contains the product spe cific ation.
DISCLAIMERS
Limited warranty and liability ⎯ Information in this
document is believed to be accurate and re liable.
However, NXP Semiconduc tors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or cons equential
damages (including - without limitation - lost profits, lost
savings, busin es s interru ption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cu mulative liability towa rds customer for
the products described herein shall be limited in
accordance with the Terms and conditions of comme rcial
sale of NXP Semiconductors.
Right to make changes ⎯ NXP Semiconductors
reserves the right to make changes to information
published in this doc ument, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use ⎯ NXP Semiconduct ors pr oduc ts are
not designed, au thorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reas onably be
expected to result in pe rs onal injury, death or severe
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductor s pr oducts in such equipment or
application s and therefore such inc lusion and/or use is at
the customer’s own risk.
Applications ⎯ Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors pro du ct is su itable and fit for the
customer’s applications and products planned, as well as
for the planned a pplication and use of custo m er’s third
party customer(s). Customers should provide appropriate
design and opera t ing saf eg ua rd s to minimize the risks
associated with their applications an d products.
NXP Semiconduc tors does n ot a ccept any liabil ity rela ted
to any default, damage, costs or problem which is based
on any weakne ss or default in t he customer’s applic ations
or products, or the application or use by customer’s third
party customer( s) . C us to m er is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors produc ts in order to
avoid a default of the applic ations and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
2001 Jun 29 26
NXP Semiconductors Product specification
Low-voltage low-power stereo audio
CODEC with DSP features UDA1344TS
Limiting values ⎯ Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions abo ve those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Terms and conditions of commercial sale ⎯ NXP
Semiconductors products are sold s ubject to the general
terms and conditio ns of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written ind i vidual agreement. In case an
individual agreeme nt is co nc luded only the terms and
conditions of the resp ective agreement shall app ly. NXP
Semiconductors hereby expressly objects to a pplying the
customer’s general terms and conditions with regard to the
purchase of NXP Semicon ductors products by cust omer.
No offer to sell or license ⎯ Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual proper ty rights.
Export control ⎯ This document as well as the item(s)
described he re in may be subject to export contro l
regulations. Export might require a prior authorization from
national auth or itie s.
Quick refer ence data ⎯ The Quick reference data is an
extract of th e product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaus tive or legally binding.
Non-automotive qualified products ⎯ Unless this data
sheet expressly states that this specific NXP
Semiconductors product is au tomotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor te sted in accordanc e with automot ive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified prod ucts in automotive equipment or
applications.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such au t omo tive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be so lely at
customer’s own ris k, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product clai ms r esult ing fr om custo mer desi gn an d us e o f
the product for automotive ap plic ations beyond NXP
Semiconductors ’ st andard warran ty and NXP
Semiconductors’ product specifications.
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Contact information
For additional information p lease visit: http://www.nxp.com
For sales offices addresses send e-mail to: salesaddresses@nxp.com
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information pr e sent ed in this document does not fo rm p art of any quotation or cont ra ct, is b elieve d to be accurate and reli a ble and may be chan ged
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimer s. No changes were made to the technical content, exc ept for package outline
drawings which were updated to the latest version.
Printed in The Netherlands 753503/05/pp27 Date of r el eas e : 2001 Jun 29 Document order number: 9397 750 08498
