3.0 System Description (Continued)
3.2 AT Interface Block
The function of the AT Interface Block is to interface the
Link Card with the AT host. This block features a full 24-bit
address bus for flexible Link Card memory map placement.
The data bus is 8 bits wide which is adequate for this demo
platform. Bits 8 through 15 are not used on the base Link
Card, but they have been tapped to test points on the board.
The test points are included in the event that an application
requires a 16-bit data bus. In addition to the address and
data buses, seven AT bus interrupts and the necessary con-
trol signals are included. All address and data signal lines
are buffered with independent parity generation supplied for
the data bus.
The AT bus block is the
sole
power supply for the Link Card.
The address decoding scheme is accomplished with gener-
ic array logic devices (GALs). Equations for each of the four
GAL devices are included in Appendix G of the DP83290EB
FDDI Physical Layer Evaluation Board User’s Guide.
Beyond these basic functions, the AT Interface offers a
number of modes such as autoconfiguration, base register
area select, and memory map configuration.
3.3 Clock Bus Block
The Clock Bus Block is included in the Link Card design to
provide a physical bus among all Link and MAC Cards that
form a station. The construction of the bus is a twenty pin
ribbon cable capable of supporting 9 signals. Each signal is
surrounded on either side by a ground line to reduce cross-
talk.
3.4 CDD Device Block
The Clock Distribution Device is a clock generation and dis-
tribution device intended for use in FDDI networks. The de-
vice provides the complete set of clocks required to convert
byte wide data to serial format for fiber medium transmis-
sion and to move byte wide data between the PLAYER and
BMAC devices in various station configurations. 12.5 MHz
and 125 MHz differential ECL clocks are generated for the
conversion of data to serial format and 12.5 MHz and 125
MHz TTL clocks are generated for the byte wide data trans-
fers.
3.5 CRD Device Block
The Clock Recovery Device has been designed for used in
this FDDI implementation. The device receives serial data
from a Fiber Optic Receiver (FORX) in differential ECL NRZI
4B/5B group code format and outputs resynchronized NRZI
received data and a 125 MHz received clock in differential
ECL format for use by the PLAYER device.
3.6 Link Bus Block
The function of the Link Bus is to provide a data path be-
tween the Link and MAC Cards that form an FDDI station.
Each connection contains two 10-bit data buses (Indicate
and Request) and station configuration signals. The pinout
of the Link Bus has been designed to allow the user to build
Single Attachment and Dual Attachment/Single MAC con-
figurations. To build one of these configurations, the user
must simply connect the cabling in the manner shown in
Appendix E of the User’s Guide.
Every other wire in the Link Bus is grounded to insure data
integrity. This cabling scheme has been tested for resist-
ance to data corruption induced by crosstalk.
3.7 Player Device Block
The Physical Layer Controller is a part of National Semicon-
ductor’s FDDI Chip Set. It implements one Physical Layer
entity as defined by the ANSI X3T9.5 PHY standard. The
PLAYER device performs the 4B/5B encoding and decod-
ing, serialization and deserialization of data, repeat filter,
and line state control and detection. It also contains a con-
figuration switch. The PLAYER device supports many types
of station configurations as allowed by the standard.
Although tailored to the FDDI specification, the PLAYER de-
vice is also well suited for use in high speed point-to-point
communication links over optical fibers and coaxial cable.
3.8 Transceiver Block
The transceiver block consists of two parts: fiber optic re-
ceiver and fiber optic transmitter. The Link Card supports
the following FDDI optical transceiver modules:
AT&T ODL 125 Lightwave Data Links
Sumitomo DM-742 1300nm Data Link
Any transceiver pair which supports the AT&T footprint
2.1.8.1.1 pin format composed of 2 independent
16-pin DIP (footprints)
See Appendix A. of the User’s Guide for a detailed footprint
description.
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