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FEATURES APPLICATIONS
DESCRIPTION
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
24-Bit, 192-kHz Sampling, Enhanced Multilevel, Delta-Sigma,Audio Digital-to-Analog Converter
•A/V Receivers•24-Bit Resolution
•DVD Movie Players•Analog Performance (V
CC
= 5 V):
•DVD Add-On Cards For High-End PCs– Dynamic Range: 106 dB
•DVD Audio Players– SNR: 106 dB, Typical
•HDTV Receivers– THD+N: 0.002%, Typical
•Car Audio Systems– Full-Scale Output: 3.9 Vp-p, Typical
•Other Applications Requiring 24-Bit Audio•4×/8× Oversampling Digital Filter:– Stop-Band Attenuation: –50 dB– Pass-Band Ripple: ±0.04 dB
The PCM1780/81/82 is a CMOS, monolithic,•Sampling Frequency: 5 kHz to 200 kHz
integrated circuit, which includes stereodigital-to-analog converters and support circuitry in a•System Clock: 128 f
S
, 192 f
S
, 256 f
S
, 384 f
S
,
small 16-lead SSOP package. The data converters512 f
S
, 768 f
S
, 1152 f
S
With Autodetect
use TI’s enhanced multilevel delta-sigma architecture•Software Control (PCM1780, PCM1782):
to achieve excellent dynamic performance and– Accepts 16-, 18-, 20-, and 24-Bit Audio Data
improved tolerance to clock jitter. ThePCM1780/81/82 accepts industry standard audio– Formats: Right-Justified, I
2
S, and
data formats with 16- to 24-bit data, providing easyLeft-Justified
interfacing to audio DSP and decoder chips.– Digital Attenuation: Mode Selectable
Sampling rates up to 200 kHz are supported. The•0 dB to –63 dB, 0.5 dB/step
PCM1780/82 provides a full set ofuser-programmable functions through a three-wire•0 dB to –100 dB, 1 dB/step
serial control port, which supports register write– Digital De-Emphasis
functions. The PCM1781 provides a subset of– Digital Filter Rolloff: Sharp or Slow
user-programmable functions through four controlpins.– Soft Mute– Zero Flags for Each Output
The PCM1780 is pin-compatible with the PCM1680(8-channel DAC).– Open-Drain Output Zero Flag (PCM1782)•Hardware Control (PCM1781):– I
2
S and 16-Bit Word, Right-Justified– Digital De-Emphasis
– Soft Mute– Zero Flag for L-, R-Channel CommonOutput
•Power Supply: 5-V Single Supply•Small, 16-Lead SSOP Package (150 mil)•Pin-Compatible with PCM1680
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.System Two, Audio Precision are trademarks of Audio Precision, Inc.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage canrange from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible todamage because very small parametric changes could cause the device not to meet its published specifications.
over operating free-air temperature range (unless otherwise noted)
(1)
PCM1780, PCM1781, PCM1782
Supply voltage V
CC
–0.3 V to 6.5 VInput voltage –0.3 V to V
CC
+ 0.3 V, < 6.5 VInput current (any pins except supplies) ±10 mAAmbient temperature under bias – 40°C to 125°CStorage temperature – 55°C to 150°CJunction temperature 150°CLead temperature (soldering) 260°C, 5 sPackage temperature (IR reflow, peak) 260°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
over operating free-air temperature range
MIN NOM MAX UNIT
Digital and analog supply voltage, V
CC
4.5 5 5.5 VDigital input logic family TTLSystem clock 8.192 36.864 MHzDigital input clock frequency
Sampling clock 32 192 kHzAnalog output load resistance 5 k ΩAnalog output load capacitance 50 pFDigital output load capacitance 20 pFOperating free-air temperature, T
A
–25 85 °C
All specifications at T
A
= 25°C, V
CC
= 5 V, f
S
= 48 kHz, system clock = 512 f
S
, and 24-bit data (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 24 Bits
DATA FORMAT
PCM1780, Right-justified, I
2
S,PCM1782 left-justifiedAudio data interface format
PCM1781 I
2
S, right-justifiedPCM1780, 16-, 18-, 20-, 24-bitPCM1782 selectableAudio data bit length
16–24-bit I
2
S, 16-bitPCM1781
right-justifiedAudio data format MSB-first, 2s complementf
S
Sampling frequency 5 200 kHz128 f
S
, 192 f
S
, 256 f
S
, 384 f
S
,System clock frequency
512 f
S
, 768 f
S
, 1152 f
S
2
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PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25°C, V
CC
= 5 V, f
S
= 48 kHz, system clock = 512 f
S
, and 24-bit data (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUT/OUTPUT
Logic family TTL compatibleV
IH
2Input logic level VdcV
IL
0.8I
IH
(1)
V
IN
= V
CC
10I
IL
(1)
V
IN
= 0 V –10Input logic current µAI
IH
(2)
V
IN
= V
CC
65 100I
IL
(2)
V
IN
= 0 V –10V
OH
(3)
I
OH
= –1 mA 2.4Output logic level VdcV
OL
(4)
I
OL
= 1 mA 0.4
DYNAMIC PERFORMANCE
(5)
V
OUT
= 0 dB, f
S
= 48 kHz 0.002% 0.006%V
OUT
= 0 dB, f
S
= 96 kHz, system
0.003%THD+N Total harmonic distortion + noise clock = 256 f
S
V
OUT
= 0 dB, f
S
= 192 kHz, system
0.004%clock = 128 f
S
EIAJ, A-weighted, f
S
= 48 kHz 100 106A-weighted, f
S
= 96 kHz, system
104Dynamic range clock = 256 f
S
dBA-weighted, f
S
= 192 kHz, system
102clock = 128 f
S
EIAJ, A-weighted, f
S
= 48 kHz 100 106A-weighted, f
S
= 96 kHz, system
104SNR Signal-to-noise ratio clock = 256 f
S
dBA-weighted, f
S
= 192 kHz, system
102clock = 128 f
S
f
S
= 48 kHz 97 103Channel separation f
S
= 96 kHz, system clock = 256 f
S
101 dBf
S
= 192 kHz, system clock = 128 f
S
100
DC ACCURACY
% ofGain error ±1 ±6
FSR
% ofGain mismatch, channel-to-channel ±1 ±6
FSRBipolar zero error V
OUT
= 49% of V
CC
at BPZ input ±30 ±80 mV
ANALOG OUTPUT
Output voltage Full scale (–0 dB) 0.78 V
CC
Vp-pBipolar zero voltage 0.49 V
CC
VdcLoad impedance AC-coupled load 5 k Ω
DIGITAL FILTER PERFORMANCE
Filter Characteristics (Sharp Rolloff)
Pass band ±0.04 dB 0.454 f
S
Stop band 0.546 f
S
Pass-band ripple 0.04 dBStop-band attenuation Stop band = 0.546 f
S
–50 dB
(1) Pins 5, 6, 7, 8: SCK, DATA, BCK, LRCK(2) Pins 2, 3, 4: MS, MC, MD (PCM1780/PCM1782). Pins 1, 2, 3, 4: FMT, DEMP0, DEMP1, MUTE (PCM1781)(3) Pins 1, 16: ZEROL, ZEROR (PCM1780). Pin 16: ZEROA (PCM1781)(4) Pins 1, 16: ZEROL, ZEROR (PCM1780/PCM1782). Pin 16: ZEROA (PCM1781)(5) Analog performance specifications are measured using the System Two™ Cascade audio measurement system by Audio Precision™.
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DEVICE INFORMATION
PIN ASSIGNMENTS
ZEROR/ZEROA
VOUTL
VOUTR
VCOM
AGND
VCC
NC
NC
16
15
14
13
12
11
10
9
ZEROL/NA
MS
MC
MD
SCK
DATA
BCK
LRCK
PCM1780/PCM1782
(TOP VIEW)
1
2
3
4
5
6
7
8
ZEROA
VOUTL
VOUTR
VCOM
AGND
VCC
NC
TEST
16
15
14
13
12
11
10
9
FMT
DEMP0
DEMP1
MUTE
SCK
DATA
BCK
LRCK
PCM1781
(TOP VIEW)
1
2
3
4
5
6
7
8
P0014-01
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25°C, V
CC
= 5 V, f
S
= 48 kHz, system clock = 512 f
S
, and 24-bit data (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Filter Characteristics (Slow Rolloff, PCM1780/PCM1782)
Pass band ±0.5 dB 0.198 f
S
Stop band 0.884 f
S
Pass-band ripple ±0.5 dBStop-band attenuation Stop band = 0.884 f
S
–35 dBDelay time 20/f
S
sDe-emphasis error ±0.1 dB
ANALOG FILTER PERFORMANCE
at 20 kHz –0.02Frequency response dBat 44 kHz –0.07
POWER SUPPLY REQUIREMENTS
V
CC
Voltage range 4.5 5 5.5 Vdcf
S
= 48 kHz 25 40I
CC
Supply current f
S
= 96 kHz, system clock = 256 f
S
30 mAf
S
= 192 kHz, system clock = 128 f
S
30f
S
= 48 kHz 125 200Power dissipation f
S
= 96 kHz, system clock = 256 f
S
150 mWf
S
= 192 kHz, system clock = 128 f
S
150
TEMPERATURE RANGE
T
A
Operation temperature –25 85 °Cθ
JA
Thermal resistance 115 °C/W
4
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PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
DEVICE INFORMATION (continued)TERMINAL FUNCTIONS—PCM1780/PCM1782
TERMINAL
I/O DESCRIPTIONNAME NO.
AGND 12 – GroundBCK 7 I Audio data bit clock input
(1)
DATA 6 I Audio data digital input
(1)
LRCK 8 I Audio data left and right clock input
(1)
MC 3 I Mode control clock input
(1) (2)
MD 4 I Mode control data input
(1) (2)
MS 2 I Mode control select input
(1) (2)
NC 9, 10 – No connectionSCK 5 I System clock input
(1)
V
CC
11 – Power supply, 5-VV
COM
13 – Common voltage decouplingV
OUT
L 15 O Analog output for L-channelV
OUT
R 14 O Analog output for R-channelZEROL/NA 1 O Zero flag output for L-channel / No assign
(3)
ZEROR/ZEROA 16 O Zero flag output for R-channel / Zero flag output for L- and R-channels
(3)
(1) Schmitt-trigger input(2) Pulldown
(3) Open-drain output (PCM1782)
TERMINAL FUNCTIONS—PCM1781
TERMINAL
I/O DESCRIPTIONNAME NO.
AGND 12 – GroundBCK 7 I Audio data bit clock input
(1)
DATA 6 I Audio data digital input
(1)
DEMP0 2 I De-emphasis control
(1) (2)
DEMP1 3 I De-emphasis control
(1) (2)
FMT 1 I Data format select
(1) (2)
LRCK 8 I Audio data left and right clock input
(1)
MUTE 4 I Soft mute control
(1) (2)
NC 10 – No connectionSCK 5 I System clock input
(1)
TEST 9 – Test pin for factory use. Must be LOW or open
(1) (2)
V
CC
11 – Power supply, 5-VV
COM
13 – Common voltage decouplingV
OUT
L 15 O Analog output for L-channelV
OUT
R 14 O Analog output for R-channelZEROA 16 O Zero flag output for L- and R-channels
(1) Schmitt-trigger input(2) Pulldown
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Power Supply
Enhanced
Multilevel
Delta-Sigma
Modulator
VOUTL
4y/8y
Oversampling
Digital
Filter
With
Function
Control
Audio
Serial
Port
BCK
LRCK
DATA
Serial
Control
Port
Zero Detect
(TEST)
SCK System
Clock
Manager
MC (DEMP1)
MS (DEMP0)
Output Amp
and
Low-Pass Filter
MD (MUTE)
DAC
VCOM
System Clock
AGND
VCC
ZEROR/ZEROA(1)
(ZEROA)
ZEROL/NA(1)
Output Amp
and
Low-Pass Filter
DAC VOUTR
B0030-01
(FMT)
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
Functional Block Diagram
(1) Open-drain output for the PCM1782NOTE: Signal names in parentheses ( ) are for the PCM1781.
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TYPICAL PERFORMANCE CURVES
Digital Filter (De-Emphasis Off)
Frequency [× fS]
−0.05
−0.04
−0.03
−0.02
−0.01
0.00
0.01
0.02
0.03
0.04
0.05
0.0 0.1 0.2 0.3 0.4 0.5
Amplitude – dB
G002
Frequency [× fS]
−140
−120
−100
−80
−60
−40
−20
0
0 1 2 3 4
Amplitude – dB
G001
Frequency [× fS]
−140
−120
−100
−80
−60
−40
−20
0
0 1 2 3 4
Amplitude – dB
G003
Frequency [× fS]
−5
−4
−3
−2
−1
0
1
2
3
4
5
0.0 0.1 0.2 0.3 0.4 0.5
Amplitude – dB
G004
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
All specifications at T
A
= 25°C, V
CC
= 5 V, f
S
= 48 kHz, system clock = 512 f
S
, and 24-bit data, unless otherwise noted
FREQUENCY RESPONSE PASS-BAND FREQUENCY RESPONSE(SHARP ROLLOFF) (SHARP ROLLOFF)
Figure 1. Figure 2.
FREQUENCY RESPONSE TRANSITION CHARACTERISTICS(SLOW ROLLOFF) (SLOW ROLLOFF)
Figure 3. Figure 4.
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TYPICAL PERFORMANCE CURVES (Continued)
De-Emphasis Filter
f – Frequency – kHz
−0.5
−0.4
−0.3
−0.2
−0.1
0.0
0.1
0.2
0.3
0.4
0.5
0 2 4 6 8 10 12 14
De-Emphasis Error – dB
fS = 32 kHz
G006
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0 2 4 6 8 10 12 14
f – Frequency – kHz
De-Emphasis Level – dB
fS = 32 kHz
G005
f – Frequency – kHz
−0.5
−0.4
−0.3
−0.2
−0.1
0.0
0.1
0.2
0.3
0.4
0.5
0 2 4 6 8 10 12 14 16 18 20
De-Emphasis Error – dB
fS = 44.1 kHz
G008
f – Frequency – kHz
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0 2 4 6 8 10 12 14 16 18 20
De-Emphasis Level – dB
fS = 44.1 kHz
G007
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
All specifications at T
A
= 25°C, V
CC
= 5 V, f
S
= 48 kHz, system clock = 512 f
S
, and 24-bit data, unless otherwise noted
DE-EMPHASIS DE-EMPHASIS ERROR
Figure 5. Figure 6.
DE-EMPHASIS DE-EMPHASIS ERROR
Figure 7. Figure 8.
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TYPICAL PERFORMANCE CURVES (Continued)
f – Frequency – kHz
−0.5
−0.4
−0.3
−0.2
−0.1
0.0
0.1
0.2
0.3
0.4
0.5
0 2 4 6 8 10 12 14 16 18 20 22
De-Emphasis Error – dB
fS = 48 kHz
G010
f – Frequency – kHz
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0 2 4 6 8 10 12 14 16 18 20 22
De-Emphasis Level – dB
fS = 48 kHz
G009
Analog Filter
−70
−60
−50
−40
−30
−20
−10
0
10
f − Frequency − kHz
Amplitude − dB
1 100 1k 10k
G011
10
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
All specifications at T
A
= 25°C, V
CC
= 5 V, f
S
= 48 kHz, system clock = 512 f
S
, and 24-bit data, unless otherwise noted
DE-EMPHASIS DE-EMPHASIS ERROR
Figure 9. Figure 10.
ANALOG FILTER PERFORMANCE
Figure 11.
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TYPICAL PERFORMANCE CURVES (Continued)
Analog Dynamic Performance
Supply Voltage Characteristics
VCC − Supply V oltage − V
4.50 4.75 5.00 5.25 5.50
THD+N − Total Harmonic Distortion + Noise − %
G012
0.001
0.01
VCC – Supply V oltage – V
96
98
100
102
104
106
108
110
4.50 4.75 5.00 5.25 5.50
Dynamic Range – dB
G013
VCC – Supply V oltage – V
96
98
100
102
104
106
108
110
4.50 4.75 5.00 5.25 5.50
SNR − Signal-to-Noise Ratio – dB
G014
VCC – Supply V oltage – V
96
98
100
102
104
106
108
110
4.50 4.75 5.00 5.25 5.50
Channel Separation – dB
G015
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
All specifications at T
A
= 25°C, V
CC
= 5 V, f
S
= 48 kHz, system clock = 512 f
S
, and 24-bit data, unless otherwise noted
THD+N DYNAMIC RANGEvs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 12. Figure 13.
SIGNAL-TO-NOISE RATIO CHANNEL SEPARATIONvs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 14. Figure 15.
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TYPICAL PERFORMANCE CURVES (Continued)
Temperature Characteristics
TA − Free-Air Temperature − °C
−25 0 25 50 75
THD+N − Total Harmonic Distortion + Noise − %
G016
0.001
0.01
TA − Free-Air Temperature − °C
96
98
100
102
104
106
108
110
−25 0 25 50 75
Dynamic Range – dB
G017
TA − Free-Air Temperature − °C
96
98
100
102
104
106
108
110
−25 0 25 50 75
SNR − Signal-to-Noise Ratio – dB
G018
TA − Free-Air Temperature − °C
96
98
100
102
104
106
108
110
−25 0 25 50 75
Channel Separation – dB
G019
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
All specifications at T
A
= 25°C, V
CC
= 5 V, f
S
= 48 kHz, system clock = 512 f
S
, and 24-bit data, unless otherwise noted
THD+N DYNAMIC RANGEvs vsTEMPERATURE TEMPERATURE
Figure 16. Figure 17.
SIGNAL-TO-NOISE RATIO CHANNEL SEPARATIONvs vsTEMPERATURE TEMPERATURE
Figure 18. Figure 19.
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SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
tw(SCKH)
System Clock
tw(SCKL)
2 V
0.8 V
H
LSystem Clock
Pulse Cycle
Time(1)
T0005A08
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
The PCM1780/81/82 requires a system clock for operating the digital interpolation filters and multileveldelta-sigma modulators. The system clock is applied at the SCK input (pin 5). Table 1 shows examples ofsystem clock frequencies for common audio sampling rates.
Figure 20 shows the timing requirements for the system clock input. For optimal performance, it is important touse a clock source with low phase jitter and noise. TI’s PLL170x family of multiclock generators is an excellentchoice for providing the PCM1780/81/82 system clock.
Table 1. System Clock Frequencies for Common Audio Sampling Frequencies
SAMPLING SYSTEM CLOCK FREQUENCY (f
SCK
), MHzFREQUENCY
128 f
S
192 f
S
256 f
S
384 f
S
512 f
S
768 f
S
1152 f
S
8 kHz 1.024 1.536 2.048 3.072 4.096 6.144 9.21616 kHz 2.048 3.072 4.096 6.144 8.192 12.288 18.43232 kHz 4.096 6.144 8.192 12.288 16.384 24.576 36.86444.1 kHz 5.6448 8.4672 11.2896 16.9344 22.5792 33.8688 –
(1)
48 kHz 6.144 9.216 12.288 18.432 24.576 36.864 –
(1)
88.2 kHz 11.2896 16.9344 22.5792 33.8688 –
(1)
–
(1)
–
(1)
96 kHz 12.288 18.432 24.576 36.864 –
(1)
–
(1)
–
(1)
192 kHz 24.576 36.864 –
(1)
–
(1)
–
(1)
–
(1)
–
(1)
(1) This system clock frequency is not supported for the given sampling frequency.
(1) 1/128 f
S
, 1/192 f
S
, 1/256 f
S
, 1/384 f
S
, 1/512 f
S
, 1/768 f
S
, or 1/1152 f
S
PARAMETER MIN TYP MAX UNIT
t
w(SCKH)
System clock pulse duration, HIGH 7 nst
w(SCKL)
System clock pulse duration, LOW 7 ns
Figure 20. System Clock Input Timing
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Power-On-Reset Functions
Reset Reset Release
VCC
3.7 V
3 V
2.2 V
Internal Reset
System Clock
T0014-06
0 V
Don’t Care 3072 System Clocks
Audio Serial Interface
Audio Data Formats and Timing
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
The PCM1780/81/82 includes a power-on-reset function. Figure 21 shows the operation of this function. With thesystem clock active and V
CC
> 3 V (typical, 2.2 V to 3.7 V), the power-on-reset function is enabled. Theinitialization sequence requires 3072 system clocks from the time V
CC
> 3 V (typical, 2.2 V to 3.7 V). After theinitialization period, the PCM1780/82 is set to its reset default state, as described in the Mode Control Registersection of this data sheet.
During the reset period (3072 system clocks), the analog output is forced to the common voltage (V
COM
), orV
CC
/2. After the reset period, the internal register is initialized in the next 1/f
S
period and if SCK, BCK, and LRCKare provided continuously, the PCM1780/81/82 provides the proper analog output with a group delaycorresponding to the input data.
Figure 21. Power-On-Reset Timing
The audio serial interface for the PCM1780/81/82 consists of a three-wire synchronous serial port. It includesLRCK (pin 8), BCK (pin 7), and DATA (pin 6). BCK is the serial audio bit clock, and it is used to clock the serialdata present on DATA into the serial shift register of the audio interface. Serial data is clocked into thePCM1780/81/82 on the rising edge of BCK. LRCK is the serial audio left/right word clock. It is used to latchserial data into the internal registers of the serial audio interface.
Both LRCK and BCK should be synchronous with the system clock. Ideally, it is recommended that LRCK andBCK be derived from the system clock input, SCK. LRCK is operated at the sampling frequency, f
S
. BCK can beoperated at 32, 48, or 64 times the sampling frequency.
Internal operation of the PCM1780/81/82 is synchronized with LRCK. Accordingly, internal operation of thedevice is suspended when the sampling rate clock, LRCK, is changed or SCK and/or BCK is interrupted at leastfor three bit-clock cycles. If SCK, BCK, and LRCK are provided continuously after this suspended condition, theinternal operation is resynchronized automatically within a period of less than 3/f
S
. External resetting is notrequired.
The PCM1780/82 supports industry-standard audio data formats, including right-justified, I
2
S, and left-justified.The PCM1781 supports I
2
S and 16-bit-word, right-justified. The data formats are shown in Figure 22 . Dataformats are selected for the PCM1780/82 using the format bits, FMT[2:0], located in control register 20, and areselected for the PCM1781 using the FMT pin. The default data format is 24-bit, left-justified. All formats requirebinary 2s complement, MSB-first audio data. Figure 23 shows a detailed timing diagram for the serial audiointerface.
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PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
Figure 22. Audio Data Input Formats
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t(BCH)
DATA
t(BCL) t(LS)
t(BCY) t(LH)
t(DH)
t(DS)
LRCK
BCK
T0010-03
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
PARAMETER MIN UNIT
t
(BCY)
BCK pulse cycle time 1/(32 f
S
), 1/(48 f
S
), 1/(64 f
S
)
(1)
t
(BCH)
BCK pulse duration, HIGH 35 nst
(BCL)
BCK pulse duration, LOW 35 nst
(LS)
LRCK setup time to BCK rising edge 10 nst
(LH)
LRCK hold time to BCK rising edge 10 nst
(DS)
DATA setup time 10 nst
(DH)
DATA hold time 10 ns
(1) f
S
is the sampling frequency (e.g., 44.1 kHz, 48 kHz, 96 kHz, etc.).
Figure 23. Audio Interface Timing
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OVERSAMPLING RATE CONTROL
ZERO FLAGS (PCM1780/82)
Zero-Detect Condition
Zero-Flag Outputs
ZERO FLAG (PCM1781)
HARDWARE CONTROL (PCM1781)
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
The PCM1780/81/82 automatically controls the oversampling rate of the delta-sigma D/A converters with thesystem clock frequency. The oversampling rate is set to 64× oversampling with an 1152-f
S
, 768-f
S
, or 512-f
Ssystem clock, to 32× oversampling with a 384-f
S
or 256-f
S
system clock, or to 16× oversampling with a 192-f
S
or128-f
S
system clock.
Zero detection for each output channel is independent from the other. If the data for a given channel remains ata 0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that channel.
Each channel has a corresponding zero-flag pin, ZEROL (pin 1) or ZEROR (pin 16). Given that a zero-detectcondition exists for one or more channels, the zero-flag pins for those channels are set to a logic-1 state. Thezero-flag pins can be used to operate external mute circuits, or used as status indicators for a microcontroller,audio signal processor, or other digitally controlled function.
The active polarity of the zero-flag outputs can be inverted by setting the ZREV bit of control register 22 to 1.The reset default is active-high output, or ZREV = 0.
The L-channel and R-channel common zero flag can be selected by setting the AZRO bit of control register 22to 1. The reset default is for independent L-channel and R-channel zero flags, or AZRO = 0.
On the PCM1782, ZEROL and ZEROR are open-drain outputs.
The PCM1781 has a zero-flag pin, ZEROA (pin 16). ZEROA is the L-channel and R-channel common zero-flagpin. If the data for L-channel and R-channel remains at a 0 level for 1024 sampling periods (or LRCK clockperiods), ZEROA is set to a logic-1 state.
The digital functions of the PCM1781 are capable of hardware control. Table 2 shows selectable formats,Table 3 shows de-emphasis control, and Table 4 shows muting control.
Table 2. Data Format Selection
FMT (PIN 1) DATA FORMAT
LOW 16- to 24-bit, I
2
S formatHIGH 16-bit right-justified
Table 3. De-Emphasis Control
DEMP1 (PIN 3) DEMP0 (PIN 2) DE-EMPHASIS FUNCTION
LOW LOW OFFLOW HIGH 48-kHz de-emphasis ONHIGH LOW 44.1-kHz de-emphasis ONHIGH HIGH 32-kHz de-emphasis ON
Table 4. Mute Control
MUTE (PIN 4) MUTE STATUS
LOW Mute OFFHIGH Mute ON
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SOFTWARE CONTROL (PCM1780/82)
Register Write Operation
MSB
0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D000
LSB
Register Index (or Address) Register Data
R0001-01
IDX0 D7 D6 D4D5 D3 D2 D1 D00
MS
MC
MD X 0 IDX6
X
IDX1IDX2IDX3IDX4IDX5IDX6
X
T0048-01
Control Interface Timing Requirements
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
The PCM1780/82 has many programmable functions that can be controlled in the software control mode; thefunctions are controlled by programming the internal registers using MS, MC, and MD.
The serial control interface is a 3-wire serial port which operates asynchronously to the audio serial interface.The serial control interface is used to program the on-chip mode registers. The control interface includes MD(pin 4), MC (pin 3), and MS (pin 2). MD is the serial data input, used to program the mode registers. MC is theserial bit clock, used to shift data into the control port. MS is the select input, used to enable the mode controlport.
All write operations for the serial control port use 16-bit data words. Figure 24 shows the control data wordformat. The most significant bit must be a 0. Seven bits, labeled IDX[6:0], set the register index (or address) forthe write operation. The least significant eight bits, D[7:0], contain the data to be written to the register specifiedby IDX[6:0].
Figure 25 shows the functional timing diagram for writing to the serial control port. MS is held at a logic-1 stateuntil a register needs to be written. To start the register write cycle, MS is set to logic 0. Sixteen clocks are thenprovided on MC, corresponding to the 16 bits of the control data word on MD. After the sixteenth clock cycle hascompleted, MS is set to logic 1 to latch the data into the indexed mode control register.
Figure 24. Control Data Word Format for MD
Figure 25. Register Write Operation
Figure 26 shows a detailed timing diagram for the serial control interface. These timing parameters are criticalfor proper control port operation.
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t(MCH)
MS
t(MSS)
LSB
t(MCL)
t(MHH)
t(MSH)
t(MCY)
t(MDH)
t(MDS)
MC
MD
T0013-03
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
PARAMETER MIN UNIT
t
(MCY)
MC pulse cycle time 100 nst
(MCL)
MC low-level time 50 nst
(MCH)
MC high-level time 50 nst
(MHH)
MS high-level time 3/(256 × f
S
)
(2)
nst
(MSS)
MS falling edge to MC rising edge 20 nst
(MSH)
MS hold time
(1)
20 nst
(MDH)
MD hold time 15 nst
(MDS)
MD setup time 20 ns
(1) MC rising edge for LSB to MS rising edge(2) f
S
: sampling rate
Figure 26. Control Interface Timing
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MODE CONTROL REGISTERS (PCM1780/82)
User-Programmable Mode Controls
Register Map
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
The PCM1780/82 includes a number of user-programmable functions, which are accessed via control registers.The registers are programmed using the serial control interface, which was previously discussed in the SoftwareControl section of this data sheet. Table 5 lists the available mode control functions, along with their resetdefault conditions and associated register index.
The mode control register map is shown in Table 6 . Each register includes an index (or address) indicated bythe IDX[6:0] bits.
Table 5. User-Programmable Mode Controls
FUNCTION RESET DEFAULT REGISTER BIT(S)
Digital attenuation control, 0 dB to –63 dB in 0.5-dB 0 dB, no attenuation 16 and 17 AT1[7:0], AT2[7:0]steps
Soft mute control Mute disabled 18 MUT[2:0]Oversampling rate control ×64, ×32, ×16 18 OVERSoft reset control Reset disabled 18 SRSTDAC operation control DAC1 and DAC2 enabled 19 DAC[2:1]De-emphasis function control De-emphasis disabled 19 DM12De-emphasis sample rate selection 44.1 kHz 19 DMF[1:0]Audio data format control 24-bit, left-justified 20 FMT[2:0]Digital filter rolloff control Sharp rolloff 20 FLTDigital attenuation mode select 0 to –63 dB, 0.5 dB/step 21 DAMSOutput phase select Normal Phase 22 DREVZero-flag polarity select High 22 ZREVZero-flag function select L-, R-channels independent 22 AZRO
Table 6. Mode Control Register MapIDX REGIST
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(B8–B14) ER
10h 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10
11h 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20
12h 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 SRST OVER RSV RSV RSV RSV MUT2 MUT1
13h 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV DMF1 DMF0 DM12 RSV RSV DAC2 DAC1
14h 20 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV FLT RSV RSV FMT2 FMT1 FMT0
15h 21 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV RSV RSV DAMS
16h 22 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV 0 AZRO ZREV DREV
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Register Definitions
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0REGISTER 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0REGISTER 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20
ATx[7:0]: Digital Attenuation Level Setting
Where x = 1 or 2, corresponding to the DAC output V
OUT
L (x = 1) and V
OUT
R (x = 2)
Default value: 1111 1111bATx[7:0] DECIMAL VALUE ATTENUATION LEVEL SETTING
DAMS = 0 DAMS = 1
1111 1111b 255 0 dB, no attenuation (default) 0 dB, no attenuation (default)1111 1110b 254 –0.5 dB –1 dB1111 1101b 253 –1 dB –2 dB: : : :1001 1100b 156 –49.5 dB –99 dB1001 1011b 155 –50 dB –100 dB1001 1010b 154 –50.5 dB Mute: : :1000 0010b 130 –62.5 dB Mute1000 0001b 129 –63 dB Mute1000 0000b 128 Mute Mute: : : :0000 0000b 0 Mute Mute
Each DAC channel (V
OUT
L or V
OUT
R) includes a digital attenuation function. The attenuation level can be setfrom 0 dB to R dB, in S-dB steps. Changes in attenuator levels are made by incrementing or decrementing byone step (S dB) every 8/f
S
time internal until the programmed attenuator setting is reached. Alternatively, theattenuation level can be set to infinite attenuation (or mute).
R (range) and S (step) are –63 and 0.5 for DAMS = 0 and –100 and 1 for DAMS = 1, respectively. The DAMSbit is defined in register 21.
The attenuation data for each channel can be set individually. The attenuation level can be calculated using thefollowing formula:
Attenuation level (dB) = S •(ATx[7:0]
DEC
– 255)
where ATx[7:0]
DEC
= 0 through 255. For ATx[7:0]
DEC
= 0 through 128 with DAMS = 0, or for ATx[7:0]
DEC
= 0through 154 with DAMS = 1, the attenuation level is set to infinite attenuation (mute).
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PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0REGISTER 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 SRST OVER RSV RSV RSV RSV MUT2 MUT1NOTE: RSV indicates a reserved bit that should be set to 0.
MUTx: Soft Mute Control
Where x = 1 or 2, corresponding to the DAC output V
OUT
L (x = 1) and V
OUT
R (x = 2).
Default value: 0MUTx = 0 Mute disabled (default)MUTx = 1 Mute enabled
The mute bits, MUT1 and MUT2, are used to enable or disable the soft mute function for the corresponding DACoutputs, V
OUT
L and V
OUT
R. The soft mute function is incorporated into the digital attenuators. When mute isdisabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, thedigital attenuator for the corresponding output is decreased from the current setting to infinite attenuation, oneattenuator step (S dB) for every 8/fS seconds. This provides pop-free muting of the DAC output. The step size,S, is 0.5 dB for DAMS = 0 and 1 dB for DAMS = 1.
By setting MUTx = 0, the attenuator is increased one step for every 8/f
S
seconds to the previously programmedattenuation level.
OVER: Oversampling Rate Control
Default value: 0
System clock frequency = 512 f
S
, 768 f
S
, or 1152 f
S
OVER = 0 ×64 oversampling (default)OVER = 1 ×128 oversampling (applicable only if sampling clock frequency ≤24 kHz)
System clock frequency = 256 f
S
or 384 f
S
OVER = 0 ×32 oversampling (default)OVER = 1 ×64 oversampling (applicable only if sampling clock frequency ≤48 kHz)
System clock frequency = 128 f
S
, 192 f
S
OVER = 0 ×16 oversampling (default)OVER = 1 ×32 oversampling (applicable only if sampling clock frequency ≤96 kHz)
The OVER bit is used to control the oversampling rate of the delta-sigma D/A converters.
Setting OVER = 1 is recommended under the following conditions:•System clock frequency = 512 f
S
, 768 f
S
, or 1152 f
S
, and sampling clock frequency ≤24 kHz•System clock frequency = 256 f
S
or 384 f
S
and sampling clock frequency ≤48 kHz•System clock frequency = 128 f
S
or 192 f
S
and sampling clock frequency ≤96 kHz
SRST: Reset
Default value: 0SRST = 0 Reset disabled (default)SRST = 1 Reset enabled
The SRST bit is used to enable or disable the soft reset function. The operation is the same as for thepower-on-reset function with the exception of the reset period, which is 1024 system clocks for the SRSTfunction. All registers are initialized.
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PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0REGISTER 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV DMF1 DMF0 DM12 RSV RSV DAC2 DAC1NOTE: RSV indicates a reserved bit that should be set to 0.
DACx: DAC Operation Control
Where x = 1 or 2, corresponding to the DAC output V
OUT
L (x = 1) or V
OUT
R (x = 2).
Default value: 0DACx = 0 DAC operation enabled (default)DACx = 1 DAC operation disabled
The DAC operation controls are used to enable and disable the DAC outputs, V
OUT
L and V
OUT
R. WhenDACx = 0, the corresponding output generates the audio waveform dictated by the data present on the DATApin. When DACx = 1, the corresponding output is set to the dc common voltage (V
COM
), equal to V
CC
/2.
DM12: Digital De-Emphasis Function Control
Default value: 0DM12 = 0 De-emphasis disabled (default)DM12 = 1 De-emphasis enabled
The DM12 bit is used to enable or disable the digital de-emphasis function. Refer to the plots shown in theTypical Performance Curves section of this data sheet.
DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
Default value: 00DMF[1:0] De-Emphasis Sample Rate Selection
00 44.1 kHz (default)01 48 kHz10 32 kHz11 Reserved
The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when it isenabled.
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PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0REGISTER 20 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV FLT RSV RSV FMT2 FMT1 FMT0NOTE: RSV indicates a reserved bit that should be set to 0.
FMT[2:0]: Audio Interface Data Format
Default value: 101FMT[2:0] Audio Data Format Selection
000 24-bit right-justified format, standard data001 20-bit right-justified format, standard data010 18-bit right-justified format, standard data011 16-bit right-justified format, standard data100 I
2
S format, 16 to 24 bits101 Left-justified format, 16 to 24 bits (default)110 Reserved111 Reserved
The FMT[2:0] bits are used to select the data format for the serial audio interface. The preceding table showsthe available format options.
FLT: Digital Filter Rolloff Control
Default value: 0FLT = 0 Sharp rolloff (default)FLT = 1 Slow rolloff
The FLT bit allows users to select the digital filter rolloff that is best suited to their application. Two filter rolloffselections are available: sharp and slow. The filter responses for these selections are shown in the TypicalPerformance Curves section of this data sheetB15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0REGISTER 21 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV RSV RSV DAMSNOTE: RSV indicates a reserved bit that should be set to 0.
DAMS: Digital Attenuation Mode Select
Default value: 0DAMS = 0 Fine step, 0.5 dB/step for 0 to –63 dB range (default)DAMS = 1 Wide range, 1 dB/step for 0 to –100 dB range
The DAMS bit is used to select the digital attenuation mode.
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PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0REGISTER 22 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV 0 AZRO ZREV DREVNOTE: RSV indicates a reserved bit that should be set to 0.
DREV: Output Phase Select
Default value: 0DREV = 0 Normal output (default)DREV = 1 Inverted output
The DREV bit allows the user to control the phase of the analog output signal.
ZREV: Zero-Flag Polarity Select
Default value: 0ZREV = 0 Zero-flag pins HIGH at a zero detect (default)ZREV = 1 Zero-flag pins LOW at a zero detect
The ZREV bit allows the user to select the polarity of the zero-flag pins.
AZRO: Zero Flag Function Select
Default value: 0AZRO = 0 Pin 1: ZEROL; zero-flag output for L-channelPin 16: ZEROR; zero-flag output for R-channelAZRO = 1 Pin 1: NA; not assignedPin 16: ZEROA; zero-flag output for L-/R-channel
The AZRO bit allows the user to select the function of zero-flag pins.
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ANALOG OUTPUTS
V
COM
Output
–
–
VCOM
OPA337
+
10 µF
+
PCM1780/81/82
Buffered VCOM
VCC
VOUTX†
+
PCM1780/81/82
AV+ *1, where AV+ * R2
R1
VCOM
†X = L or R
1/2
OPA2353
+
VCC
2
31
C1
R3
R2
C2
R1
10 µF
+
(a) Using VCOM to Bias a Single-Supply Filter Stage
(b) Using a Voltage Follower to Buffer VCOM When Biasing Multiple Nodes
S0054-01
R4
R5
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
The PCM1780/81/82 includes two independent output channels, V
OUT
L and V
OUT
R. These are unbalancedoutputs, each capable of driving 3.9 Vp-p typical into a 5-k Ωac-coupled load. The internal output amplifiers forV
OUT
L and V
OUT
R are biased to the dc common voltage, equal to 0.5 V
CC
.
The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energypresent at the DAC outputs due to the noise-shaping characteristics of the PCM1780/81/82 delta-sigma D/Aconverters. The frequency response of this filter is shown as ANALOG FILTER in the Typical PerformanceCurves section. By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level formany applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Furtherdiscussion of DAC post-filter circuits is provided in the Application Information section of this data sheet.
One unbuffered common voltage output pin, V
COM
(pin 13), is brought out for decoupling purposes. This pin isnominally biased to the dc common voltage, equal to V
CC
/2. This pin can be used to bias external circuits.Figure 27 shows an example of using the V
COM
pin for external biasing applications.
Figure 27. Biasing External Circuits Using the V
COM
Pin
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APPLICATION INFORMATION
Connection Diagrams
ZEROL/NA 16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
MS
MC
MD
SCK
DATA
BCK
LRCK
ZEROR/ZEROA
NC
VOUTL
VOUTR
VCOM
AGND
NC
VCC
PCM1780
PCM1782
Mode Control
L-Ch OUT
R4
R3
R2
R1
PCM Audio Data
System Clock
Zero Mute Control
+
Post LPF
C4
R-Ch OUT
+
Post LPF
C3
+
C20 V
5 V
+
C1
FMT 16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
DEMP0
DEMP1
MUTE
SCK
DATA
BCK
LRCK
ZEROA
TEST
VOUTL
VOUTR
VCOM
AGND
NC
VCC
PCM1781
De-Emphasis L-Ch OUT
R4
R3
R2
R1
PCM Audio Data
System Clock
Zero Mute Control
+
Post LPF
C4
R-Ch OUT
+
Post LPF
C3
+
C20 V
5 V
+
C1
S0055-01
Format
Mute
C1: 0.1-µF Ceramic and 10-µF Electrolytic
C2: 10-µF Electrolytic
C3, C4: 4.7-µF to 10-µF Electrolytic
R1−R4: 22 Ω to 100 Ω
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
A basic connection diagram is shown in Figure 28 , with the necessary power supply bypassing and decouplingcomponents. TI recommends using the component values shown in Figure 28 for all designs.
The use of series resistors (22 Ωto 100 Ω) is recommended for the SCK, LRCK, BCK, and DATA inputs. Theseries resistor combines with the stray PCB and device input capacitance to form a low-pass filter which reduceshigh-frequency noise emissions and helps to dampen glitches and ringing present on clock and data lines.
Figure 28. Basic Connection Diagram
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Power Supplies and Grounding
D/A Output Filter Circuits
–
2
31
OPA2134
+VOUT
R4
C2
C1
R3
R2
R1
VIN
AV+ * R2
R1S0053-01
PCB LAYOUT GUIDELINES
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
APPLICATION INFORMATION (continued)
The PCM1780/81/82 requires a 5-V supply for V
CC
.
Proper power supply bypassing is shown in Figure 28 . The 0.1- µF ceramic capacitor and the 10- µF electrolyticcapacitor are recommended.
Delta-sigma D/A converters use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR)performance at the expense of generating increased out-of-band noise above the Nyquist frequency, or f
S
/2. Theout-of-band noise must be low-pass filtered in order to provide optimal converter performance. This isaccomplished by a combination of on-chip and external low-pass filtering.
Figure 27 (a) and Figure 29 show the recommended external low-pass active filter circuits for single- anddual-supply applications. These circuits are second-order Butterworth filters using the multiple feedback (MFB)circuit arrangement, which reduces sensitivity to passive component variations over frequency and temperature.For more information regarding MFB active filter design, see Dynamic Performance Testing of Digital Audio D/AConverters (SBAA055 ), available from the TI Web site at http://www.ti.com.
Figure 29. Dual-Supply Filter Circuit
A typical PCB floor plan for the PCM1780/81/82 is shown in Figure 30 . A ground plane is recommended, withthe analog and digital sections being isolated from one another using a split or cut in the circuit board. ThePCM1780/81/82 should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short,direct connections to the digital audio interface and control signals originating from the digital section of theboard.
Separate power supplies are recommended for the digital and analog sections of the board. This prevents theswitching noise present on the digital supply from contaminating the analog power supply and degrading thedynamic performance of the PCM1780/81/82. In cases where a common 5-V supply must be used for theanalog and digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog anddigital 5-V supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 31shows the recommended approach for single-supply applications.
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Digital Logic
and
Audio
Processor
Digital Power
+VDDGND
Digital Section Analog Section
Return Path for Digital Signals
Analog Power
+VS
AGND –VS
+5VA
Digital
Ground
Analog
Ground
Output
Circuits
PCM1780/81/82
AGND
VCC
B0031-01
VDD
Digital Section Analog Section
RF Choke or Ferrite Bead Power Supplies
Common
Ground
Output
Circuits
AGND
VCC
+VS
+5V –VS
AGND
PCM1780/81/82
B0032-01
Digital Logic
and
Audio
Processor
PCM1780 , PCM1781 , PCM1782
SLES132B – MARCH 2005 – REVISED AUGUST 2006
APPLICATION INFORMATION (continued)
Figure 30. Recommended PCB Layout
Figure 31. Single-Supply PCB Layout
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PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCM1780DBQ ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1780DBQG4 ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1780DBQR ACTIVE SSOP DBQ 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1780DBQRG4 ACTIVE SSOP DBQ 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1781DBQ ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1781DBQG4 ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1781DBQR ACTIVE SSOP DBQ 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1781DBQRG4 ACTIVE SSOP DBQ 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1782DBQ ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1782DBQG4 ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1782DBQR ACTIVE SSOP DBQ 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1782DBQRG4 ACTIVE SSOP DBQ 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PCM1780DBQR SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PCM1781DBQR SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PCM1782DBQR SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM1780DBQR SSOP DBQ 16 2000 367.0 367.0 35.0
PCM1781DBQR SSOP DBQ 16 2000 367.0 367.0 35.0
PCM1782DBQR SSOP DBQ 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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