081747/081747P PRELIMINARY DALLAS DS1747/DS1747P SEMICONDUCTOR Y2KC Nonvolatile Timekeeping RAM FEATURES PIN ASSIGNMEN Integrated NV SRAM, real time clock, crystal, power- Aiea: fail control circuit and lithium energy source Ale Be Clock registers are accessed identical to the static ae a RAM. These registers are resident in the eight top avs RAM locations. ache Century byte register, ie., Y2K compliant na 1 Totally nonvolatile with over 10 years of operation in AaB the absence of power ADE A1B BCD coded century, year, month, date, day, hours, ao8 minutes, and seconds with automatic leap year com- ono B pensation valid up to the year 2100 oat g Battery voltage level indicator flag own Powerfail write protection allows for +10% Voc SIaK XB power supply tolerance 32-PIN ENCAPSULATED PACKAGE Lithium energy source is electrically disconnected to No aa CO Ata retain freshness until poweris applied for the first time AIS 2 aa _] at7 AiG 3a a2 Ald DIP Module only RST 4 ai CJ aia v 430 Az - Standard JEDEG Byte-wide 512K x 8 static we . 9) att RAM pinout vd 7 2a] AIO CE B a7 L_] aa PowerGap Module Board only bay 3 a6 Fa] AB Surface mountable package for direct connec- pas 10 25 (__] a7 tion to PowerGap containing battery and crystal pas 11 a4 [| A6 Dad 12 24 AS - Replaceable battery (PowerGap) pas 13 a2 (Tad Dae 14 Pal Ag - Power-On Reset Output pot ey xo mee - Pin for pin compatible with other densities of Bao 16 BAT 9 At DS174XP Timekeeping RAM GND 7 ] E] LE] ] G4 34-PIN POWERCAP MODULE BOARD ORDERING INFORMATION (USES DSe0sPCx POWERGAP DS1747P-XXX (5 Volt} T -70 70ns access PIN DESCRIPTION -100 100 ns access AQ-A18 Address Input GE - Chip Enable blank 32-pin DIP Module OE - Output Enable P 34-pin PowerGap Module board* WE - Write Enable DS1747WP-XXX (3.3 Volt) ace, - ewer Supply Input | le -120 120 ns access ~ &roun i -150 150 ns access DOQ0-BQ7 - Data Input/Cutput blank 32-pin DIP Module NG_ - No Connection P 34-pin PowerCap Module RST Power-on Reset Output{Power- board* Gap Module board only) *DS9034P CX Freier be on Required: X1, X2 - Crystal Connection must be ordered separately) VaAT - Battery Connection opoene 1117031747/051747P DESCRIPTION The DS1747 is a full function, year 2000 compliant (2KC}, real-time clock/calendar (RTG} and 512K x 8 non-volatile static RAM. User access to all registers within the DS1747 is accomplished with a bytewide interface as shown in Figure 1. The Real Time Glock (RTG} information and control bits reside in the eight up- permost RAM locations. The RIC registers contain century, year, month, date, day, hours, minutes, and se- conds data in 24 hour BCD format. Corrections for the date of each month and leap year are made automati- cally. The ATG clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. The double buffered system also prevents time loss as the timekeeping countdown con- tinues unabated by access to time register data. The DS1747 also contains its own power-fail circuitry which deselects the device when the Voc supplyisin an out of tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low Voc 45 errant access and update cycles are avoided. PACKAGES The DS1747 is available in two packages (32-pin DIP and 34-pin PowerGap module). The 32-pin DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin PowerGap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX} that contains the crystal and battery. This design allows the Power- Gap to be mounted on top of the D$1747P after the DS1747 BLOCK DIAGRAM Figure 1 | g2.768KHz [_] TT CHAIN a OSCILLATOR AND CLOCK COUNTDOWN | N V completion of the surface mount process. Mounting the PowerGap after the surface mount process prevents dam age to the crystal and battery due to the high tem- peratures required for solder reflow. The PowerGap is keyed to prevent reverse insertion. The PowerGap Module Board and PowerGap are ordered separately and shipped in separate containers. The part number for the PowerCap is DS9034PCX. CLOCK OPERATIONS-READING THE CLOCK Whilethe double buffered register structure reduces the chance of reading incorrect data, intemal updates tothe DS1747 clock registers should be halted before clack data is read to prevent reading of data in transition. However, halting the intemal clock register updating process does not affect dock accuracy. Updating is halted when a oneis written into the read bit, bit 6 of the century register, see Table 2. Aslong as a one remains in that position, updatingis halted. After ahaltis issued, the registers reflect the count, thatis day, date, andtime that was current at the moment the halt command was issued. However, the internal clock registers of the double buffered system continue to update so that the clock accuracy is not affected by the access of data. All of the DS1 747 registers are updated simultaneously af- tertheintem al dock register updating process hasbeen re-enabled. Updating is within a second after the read bitis written to zero. RST {PowerCap < Maule only) POWER MONITOR, v, SWITCHING, AND cc ., WRITE PROTECTION Vaar +O = CLOCK REGISTERS - cE WE 512K xB NV SRAM A0-A18 <_@$ $+ OE GO0208 27DS1747/051747P DS1747 TRUTH TABLE Table 1 Vee CE OE WE MODE DQ POWER Vin x x DESELECT HIGH=2 STANDBY VIL x VIL WRITE DATA IN ACTIVE Voc > Vpr VIL Vit Vin READ DATA OUT ACTIVE VIL Vin Vin READ HIGH-Z ACTIVE Vso < Voc < Ver x x x DESELECT HIGH=Z CMOS STANDBY Voc< Vso x x x DESELECT HIGH=2 DATA RETENTION MODE SETTING THE CLOCK As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a one, like the read bit, halts updates to the DS1747 registers. The user can then load them with the correct day, date and time data in 24hourBCD format. Resetting the write bit to a zero then transfers those values to the actual dock counters and allows normal operation to resume. STOPPING AND STARTING THE CLOCK OSCILLATOR The dock oscillator may be stopped at any time. Toin- crease the shelf life, the oscillator can be tumed aff to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see Table 2. Setting it to a one stops the oscillator. FREQUENCY TEST BIT As shown in Table 2, bit6 of the day byteis the frequency test bit. When thefrequency test bitissettologic1 and the oscillatoris running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is be- ingread, the DQOline will toggle atthe 512 Hz frequency as long as conditions for access remain valid {i.e., GE low, OE low, WE high, and address for seconds register remain valid and stable}. CLOCK ACCURACY (DIP MODULE) The DS1747 is guaranteed to keep time accuracy to within +1 minute per month at 25C. The clock is cali- brated at the factory by Dallas Semiconductor using spedal calibration nonvolatile tuning elements. The DS1 747 does not require additional calibration andtem- perature deviations will have anegligible effect in most applications. Forthis reason, methods of field clock cal- ibration are not available and not necessary. CLOCK ACCURACY (POWERCAP MODULE) The DS1747P and DS 9034PCX are each individually tested for accuracy. Once mounted together, the mod- ule is guaranteed to keep time accuracy to within +1.53 minutes per month (35 ppm} at 25C. op0ene8 447031747/051747P DS1747 REGISTER MAP Table 2 DATA ADDRESS FUNCTION/RANGE By Bs Bs By Bs B> By Bo 7EFFF 10 YEAR YEAR YEAR 00-99 7FFFE x x | 10MO MONTH MONTH 01-12 7FFFD x x | 10 DATE DATE DATE 01-31 7FFFG BF FT x x x DAY DAY 01-07 7FFFB x x | 10 HOUR HOUR HOUR 0-28 7EFFA x 10 MINUTES MINUTES MINUTES 00-59 7FFF9 =| OSG 10 SEGONDS SECONDS SECONDS 00-59 7FFF8 Ww R | 10 GENTURY GENTURY GENTURY 00-39 OSC = STOP BIT R = READBIT FT = FREQUENCY TEST Ws = WRITE BIT X = SEENOTEBELOW BF = BATTERY FLAG NOTE: All indicated X bits are not dedicated to any particular function and can be used as normal RAM bits. RETRIEVING DATA FROM RAM OR CLOCK The DS1747 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE (chip enable) is low. The device architecture allows ripple- through access to any of the addresslocationsin the NV SRAM. Valid data will be available atthe DQ pins within taa after the last address input is stable, providing that the CE and OE access times and states are satisfied. If GE or OE access times and states are not met, valid data will be available at the latter of chip enable access {toe a) or at output enable access time (toca). The state of the data input/output pins (DQ) is controlled by CE and OE. Ifthe outputs are activatedbefore ta, the data lines are driven to an intermediate state until tag. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (toy) but will then go indeterminate until the next address access. WRITING DATA TO RAM OR CLOCK TheDS1747isin the write mode whenever WE, and CE arein their active state. The start of a writeis referenced to the latter occurring transition of WE or CE. The ad- dresses must beheld valid throughout the cycle. CE or WE must retum inactive for a minimum of twp prior to theinitiation of another read or write cycle. Datain must be valid tps prior to the end of write and remain valid for tpy afterward. In atypical application, the OE signal will behigh during awrite cycle. However, OE can be active provided that careistaken with the data busto avoid bus contention. If OE is low prior to WE transitioninglow the data bus can become active with read data defined by the address inputs. Alowtransition on WE will then dis- able the outputs tye alter WE goes active. Gooeo8 417DS1747/051747P DATA RETENTION MODE The 5 volt device isfully accessible and data can be writ- ten or read only when Vocis greater than Vpp. However, when Voc is below the power fail point, Vpp, (point at which write protection occurs) the intemal clock regis- ters and SRAM are blocked from any access. At this time the power fail reset output signal (RST) is driven active and will remain active until Voc retu ms to nominal levels. When Vcc falls below the battery switch point Vso (battery supply level}, device power is switched from the Voc pin to the backup battery. RTC operation and SRAM data are maintained from the battery until Vecis returned to nominal levels. The 3.3 volt device is fully accessible and data can be written or read only when Vogis greater than Vpp. When Vec falls below the power fail point, Vpr, access to the deviceis inhibited. At this time the power fail reset out- put signal (RST) is driven active and will remain active until Veg returns to nominal levels. If Vpe is less than Vaart, the device power is switched from Vcc to the backup supply (VaaT) when Vcc drops below Vpr. If Vpr is greater than Vgaz the device power is switched from Veg tothe backup supply (VgatT} when Veg drops below Vaart. RTC operation and SRAM data are main- tained from the battery until Voc is retumed to nominal levels. The RST signal is an open drain output and requires a pull up. Except for the RST, all control, data, and address signals must be powered down when Vcocis powered down. BATTERY LONGEVITY The DS1747 has a lithium power source that is de- signedto provide energy for dock activity, andclock and RAM data retention when the Voc supply isnot present. The capability of this internal power supply is sufficient to power the DS1747 continuously for the life of the equipment in which itis installed. For specification pur- poses, the life expectancy is 10 years at 25C with the intemal clock oscillator running in the absence of Voc power, Each DS 1747 is shipped from Dallas Semicon- ductor with its lithium energy source disconnected, guaranteeing full energy capacity. When Vc is first applied at a level greater than Vpr, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the DS1 747 will be much longer than 10 years since no lithium battery energy is consumed when Voc is present. BATTERY MONITOR The DS1747 constantly monitors the battery voltage of theintemal battery. The Battery Flag bit (bit 7) of the day register is used to indicate the voltage level range of the battery. This bitis not writable and should always be a one when read. If a zerois ever present, an exhausted lithium energy source is indicated andboth the contents of the RTG and RAM are questionable. opoene 5117031747/051747P ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -0.3V to +6.0V Operating Temperature OC to 70G Storage Temperature -20G to +70G Soldering Temperature 260C for 10 seconds (See Note 7} * Thisis astress rating only and functional operation of the device atthese orany other conditions abovethose indicated in the operation sections of this specification is notimplied. Exposureto absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0C to 70C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Lagic 1 Voltage All Inputs Voc = 5V 410% Vin 22 Voect+0.3V Vv 1 Voc = 4.3V 110% Vin 2.0 Vect+0.3V Vv 1 Logic 0 Voltage All Inputs Voc = SV 410% VIL -0.3 0.8 Vv 1 Voc = 3.3V 410% VIL -0.3 0.6 Vv 1 DC ELECTRICAL CHARACTERISTICS (0C to 70C; Veo = 5.0V+ 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Active Supply Current loc x 95 mA 2,3 TTL Standby Current leci X 6 mA 2,3 (GE = Vin GMOS Standby Current loce X 4 mA 2,3 (GE > Veg-0.2V} Input Leakage Gurrent (any input) li -1 + pA Output Leakage Current lot -1 +1 pA (any output) Output Logic 1 Voltage Vou 24 1 (Iqu7 =-1.0 mA} Output Logic 0 Voltage VoL 0.4 1 (lout =+2.1 mA) Write Protection Voltage Vpr 4.25 4.37 4.50 Vv 1 Battery Switch Over Voltage Vso VeaT 1,4 Gooeoe G17DS1747/051747P DC ELECTRICAL CHARACTERISTICS (0C to 70C; Veo = 3.3V + 10%} PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Active Supply Current lec Xx 30 mA 2,3 TTL Standby Current lect x 2 mA 2,3 (CE = Vin} GMOS Standby Current loca x 2 mA 2,3 (CE 2 VCC -0.2V} Input Leakage Current (any input) iL -1 +1 uA Output Leakage Gurrent lot -1 +1 pA (any output} Output Logic 1 Voltage Vou 24 1 (lout =-1.0 mA) Output Logic 0 Voltage VoL 0.4 1 (lout = 2.1 mA} Write Protection Voltage Ver 2.80 2.88 2.97 Vv 1 Battery Switch Over Voltage Vso Vaart or Vv 1,4 Vpr READ CYCLE, AC CHARACTERISTICS (OC to 70C; Voc = 5.0V + 10%) 70 ns access | 100 ns access PARAMETER SYMBOL | MIN | MAX] MIN | MAX | UNITS | NOTES Read Cycle Time tac 70 100 ns Address Access Time taa 70 100 ns GE to DQ Low-Z toEL 5 5 ns CE Access Time tcEA 70 100 ns GE Data Off Time tcEz 25 35 ns OE to DQ Low-Z toEL 5 5 ns OE Access Time toEA 35 55 ns OE Data Off Time toez 25 35 ns Output Hold from Address tou 5 5 ns opoene8 717031747/051747P READ CYCLE, AC CHARACTERISTICS (0C to 70C; Veco = 3.3V + 10%) 120 ns access | 150ns access PARAMETER SYMBOL | MIN MAX MIN MAX UNITS NOTES Read Cycle Time trac 120 160 ns Address Access Time TAA 120 150 ns GE Low to DQ Low-Z teeL 5 5 ns GE Access Time tcEA 120 150 ns CE Data Off Time toez 40 50 ns OE Low to DO Low-2 toEeL 5 5 ns OE Access Time toEA 100 130 ns OE Data Off Time toez 35 35 ns Output Hold from Address tou 5 5 ns READ CYCLE TIMING DIAGRAM < tro - AG-A18 } tag _______m t wm! tH tce2 be - Pe tcea 1#] -_ CE et toe, t 'OEA Lee ~ tbez_ OF foeL * Basa? {4 VALID Go0e08 B17DS1747/051747P WRITE CYCLE, AC CHARACTERISTICS (OC to 70C; Veco = 5.0V + 10%) 70 ns access | 100 ns access PARAMETER SYMBOL | MIN | MAX | MIN MAX UNITS NOTES Write Cycle Time twe 70 100 ns Address Setup Time tas 0 0 ns WE Pulse Width twew 50 70 ns GE Pulse Width tcEW 60 75 ns Data Setup Time tos 30 40 ns Address Hold Time taH4 5 5 ns 8 Address Hold Time taHe x x ns 9 Data Hold Time tpH4 0 0 ns 8 Data Hold Time tpHe xX xX ns 9 WE Data Cff Time twez 25 35 ns Write Recovery Time twr 5 5 ns WRITE CYCLE, AC CHARACTERISTICS (0C to 70C; Veco = 3.3V + 10%) 120 ns access | 150 ns access PARAMETER SYMBOL |} MIN | MAX | MIN | MAX UNITS NOTES Write Cycle Time two 120 150 ns Address Setup Time tas 0 0 ns WE Pulse Width twew 100 130 ns CE Pulse Width toew 110 140 ns Data Setup Time tos 80 90 ns Address Hold Time TAHA 0 0 ns 8 Address Hold Time taH2 xX x ns 9 Data Hold Time tpu4 0 0 ns 8 Data Hold Time tpH2 xX xX ns 9 WE Data Cff Time twez 40 50 ns Write Recovery Time twr 10 10 ns opoene O17031747/051747P WRITE CYCLE TIMING DIAGRAM, WRITE ENABLE CONTROLLED a two a AG-AIB VALID VALID pbgQe-DaQ7 DATA QUTPUT DATA INPUT DATA INPUT | tos | WRITE CYCLE TIMING DIAGRAM, CHIP ENABLE CONTROLLED a two - AG-A1B VALID VALID: wm tas tana ~ a toew er] twr DAdae, Aa DATA INPUT | < DATA INPUT |-<__ tos Gooene 10/17DS1747/051747P POWER-UP/DOWN AC CHARACTERISTICS (0C to 70C; Veo = 5.0V + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CE or WE at Vin Before ipo 0 ps Power-down Voc Fall Time: Vpp(MAX} to tr 300 ys Vpr (Min} Vec Fall Time: Vpr {MIN} to Vso tra 10 Hs Voc Rise Time: Vpr(MIN) to tr 0 Hs Vpr{(MAX} Power-up Recover Time lpec 35 ms Expected Data Retention Time lpr 10 years 5, 6 (Oscillator On} POWER-UP/POWER-DOWN TIMING 5 VOLT DEVICE Voc Var (MAX) weurs \ _/ RECOGNIZED DON'T CARE HIGH-Z RECOGNIZED OUTPUTS VALID O90e88 1117031747/051747P POWER-UP/DOWN CHARACTERISTICS (0G to 70C: Veg = 3.3 +10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CE or WE at Vin, Before tpp 0 ys PowerDown Voc Fall Time: VPF(MAX) to te 300 us VPFiMin) Vec Rise Time: VPF(MIN) to tp 0 Us VPFIMAX} Ver to RST High tREG 35 ms Expected Data Retention Time lpr 10 years 5,6 (Oscillator On} POWER-UP/DOWN WAVEFORM TIMING 3.3 VOLT DEVICE RECOGNIZED weurs _/ DON'T CARE HIGH-Z OUTPUTS VALID CAPACITANCE RECOGNIZED VALID (ta = 25C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Capacitance on allinput pins Cin pF Capacitance on all output pins Co 10 pF epoene 12/17DS1747/051747P AC TEST CONDITIONS Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0.0 to 3.0 Volts Timing Measurement Reference Levels: Input: 1.5 Output: 1.5V Input Pulse Rise and Fall Times: 5ns NOTES: 1. Voltages are referenced to ground. 2. Typical values are at 25C and nominal supplies. 3. Outputs are open. 4. Battery switch over occurs at the lower of either the battery terminal voltage or Vpp. . Data retention time is at 26C. 5 6. Each DS1747 has a built-in switch that disconnects the lithium source until Veg is first applied by the user. The expected tpr is defined for DIP modules and assembled PowerCap Module as a cumulative time in the absence of Voc starting from the time power is first applied by the user. 7. Real-Time Clock Modules (DIP) can be successfully processed through conventional wavesoldering tech- niques as long as temperatures as long as temperature exposure to the lithium energy source contained within does not exceed +85C. Post solder cleaning with water washing techniques is acceptable, provided that ultra- sonic vibration is not used. In addition, for the PowerGap: a. Dallas Semiconductor recommends that PowerGap Module bases experience one pass through solder reflow oriented with the label side up (ive bug). b. Hand Soldering and touch-up: Donottouch orapply the solderin giron toleads for more than 3 (three) seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder. 8. tani, tp are measured from WE going high. 9. tana, tpye are measured from GE going high. 090208 14/17031747/051747P DS1747 32-PIN PACKAGE |e A | - Cc H, . be ele lal PKG 32-PIN DIM MIN MAX 4 IN, 1.676 1.690 MM 342 38.99 BIN. Os 0740 MM 18.16 18.80 c IN. O3a5 0.365 MM 451 O27 D IN. G.075 0.165 MM 1.91 O67 E IN. 015 0.680 MM O38 O76 F IN. o146 0.180 MM 3.56 457 G IN. 6.080 o110 MM an) 279 H_ IN. 6590 6.630 MM 14.99 16.60 JIN. o016 0.018 MM G25 045 K IN, 6015 0.025 MM O38 O64 Gooene 14/17DS1747/051747P TOP VIEW 0.015 0.620 6.025 DS1747P 'B Da | Ia S PKG INCHES Semiconductor DIM MIN NOM MAX DSXXXX A 0.920 0.925 0.930 YYWwWwemn B 0.980 0.985 0.990 XAKKAX c = = 8.080 D 0.052 0.055 0.058 E 0.048 0.050 0.052 F G 6.025 0.027 6.036 BOTTOM VIEW COMPONENTS AND PLACEMENT MAY VARY FRGM EACH DEVICE TYPE NOTE: Dallas Semiconductor recommends that PowerGap Module bases experience one pass through solder reflow ori- ented with the label side up (live - bug). Hand Soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3 (three) seconds. To solder, apply flux tothe pad, heat the lead frame pad and apply solder. To remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder. 690208 15/17031747/051747P DS1747P WITH DS9034PCX ATTACHED samnnaenncinene CUA AHA AAA ATA B TOP VIEW SIDE VEW Donon) VONNDACDNNAN COVOODONNOCKE BOTTOM VIEW COMPONENTS AND PLACEMENT MAY an 1. VARY FROM EACH DEVICE TYPE PKG INCHES DIM MIN NOM MAX A 0.220 o925 6.990 B 0.955 a960 6.965. c 0.240 0.245 6.250 DB 0.052 6.055 6.058 E 0.048 6.050 6.05 F O.015 o.e2o G025 G 0.620 O.g25 6.030 Gooene 16/17DS1747/051747P RECOMMENDED POWERCAP MODULE LAND PATTERN TL Tt TC | to f 16 PL ny | PKG DIM INCHES MIN NOM MAX 1.060 0.26 0.660 0.630 mm) ol) a|] @ 0.112 690208 17117