ANALOG Fast, Complete 8-/10-Bit A/D Converters DEVICES with Microprocessor Interface AD573/AD673 REV. B 1.1 Scope. This specification covers the detail requirements for complete 8-bit and 10-bit resolution A/D converters with full microprocessor interface. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows: Device Part Number -1 AD673SD/883B 2 AD573SD/883B 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-M-1000: package outline: D-20. 1.3 Absolute Maximum Ratings. (T, = + 25C unless otherwise noted) Vec to Digital Common. . 2. 0. ee es +7V Veg to Digital Common... . 2... ee 16.5V Analog Common to Digital Common ... 1.2... 2 ee ee +1V Analog Input to Analog Common... . 1... 1. ee +15V ControlInputs 2... 1. ee 0 to Vec Digital Outputs (High Impedance State) ... 2... ee 0 to Vec Power Dissipation... 2... ee 800mW Storage Temperature Range... 2... 65C to + 150C Lead Temperature Range (Soldering 10sec)... 2... 2 ee ee 300C 1.5 Thermal Characteristics. Thermal Resistance 6; = 25C/W Oya = 85C/W ANALOG-TO-DIGITAL CONVERTERS 6-15 ANALOG-TO-DIGITAL CONVERTERS =AD573/AD673SPECIFICATIONS Table 1. Design Sub Sub | Sub Limit Group| Group} Group Test Symbol | Device?} @ + 25C | 1 2,3 14 Test Condition! Units Relative Accuracy RA -1 0.195 0.195 | 0.195 Unipolar and Bipolar +%of FS max -2 [0.098 | 0.195 | 0.098 | 0.098 | Major Transitions +3 Codes Differential Nonlinearity? DNL -1 8 8 8 All codes test Bits min 2 10 8 10 10 Unipolar and Bipolar Full-Scale Error* Ag -1,2 | 40 40 Unipolar +mV max -1,2 | 20 20 Bipolar +mvV max Full-Scale Temperature TCAg | -1 0.781 0.781 + % of FS max Drift -2 | 0.488 0.488 Offset Error Vos -1 20 20 First Transition +mV max -2 10 20 10 Offset Temperature Drift TCVos | -1 0.391 0.391 + % of FS max ~2 0.195 0.195 Bipolar Zero Error Bpze -1 20 20 Low Side MSB Transition +mV max ~2 {10 20 10 _| Bipolar Bipolar Zero Temperature TCBpze| 1 0.391 0.391 Low Side MSB Transition + %of FS max Drift -2 [0.195 0.195 Bipolar Input Resistance Rin -1,2 [3 3 3 kN min 7 7 7 kQ max Conversion Time tc -1,2 | 10 10 10 psmin 30 30 30 ps max Three-State Leakage Current | loi -1 40 40 40 Von =5.0V Vor =0.0V, DBO-DB7 + pA max =. | 40 [40 Vou=5.0V Vo. =0.0V, DBO-DB9 Power Supply Rejection Ratio] PSRR_ | 1 78.1 78.1 | 78.1 Vec= 5V, ~15.75VSVegs 14.25V| +mV max Voc=5V, -12.6VSVep 11.4V -2 19,5 78.1 | 78.1 | 19.5 | Vep=15V,4.5VsVocs5.5V Power Supply Current Ice -1,2 | 15 1s DR LOW +mA max 15 15 DR HIGH (During Conversion) lee -1,2 | 15 15 mA max Digital Input High Voltage | Vin -1,2 |2.0 20 | 2.0 Convert, HBE, LBE, DE +Vmin Digital Input Low Voltage | Vi. -1,2 [0.8 08 | 0.8 Convert, HBE, LBE, DE + Vmax Digital Input HighCurrent | Ip -1,2 | 100 100 | 100 Convert, HBE, LBE, DE + pA max Vin=5.0V Digital Input LowCurrent = | Ip. -1,2 | 100 100 | 100 Convert, HBE, LBE, DE +pA max Vit =0.0V Digital Output Low Voltage | Vo. ~1 0.4 0.4 | 0.4 lo. = +3.2mA, DR, DBO-DB7 +V max -2 0.4 0.4 | 0.4 Io. = + 3.2mA DR, DBO-DB9 Digital Output High Voltage | Voy -1 2.4 2.4 2.4 lox = ~ 0.5mA, DBO-DB7 +Vmin -2 2.4 2.4 2.4 Ion = 0.5mA, DBO-DB9 6-16 ANALOG-TO-DIGITAL CONVERTERS REV.ADS73/AD673 Design Sub Sub Sub Limit Group | Group | Group Test Symbol | Device |@ + 25C | 1 2,3 4 | Test Condition Units Convert Pulse Width? tes |-1,2 | 500 500 500 ns min DR Delay Convert* tose |-1,2 | 15 1.5 jus max Data Valid After DE, HBE | tun or LBE High -1,2 | 50 ns min Output Float Delay ta |-1,2 | 200 200 ns max Data Access Time tpp |-1,2 | 250 250 Ds max NOTES "Voc = +5V, Van= 15V, analog input through 151 resistor to Pin 13, Unipol fi Ta = 25C unless otherwise indicated Unipolar configuration Pin 16 (Bipolar Offeet Control) is grounded. Bipolar configuration Pin 16 is not connected. ;Fot = 1 (@-Bit resolution Device), 0.391% of full sale = 1 LSB (least significant bit). For 2(10-Bit resolution device), 0.098% of full scale = 1 LSB. 2Minimum lution for which no missing + deviefullacaleeror guaranteed trimmable with S00 potentiometer. ~ 2. device full scale error d tri ble with 2002 p ; . 5See Figure 1. See Figures 2 and 3. 3.2.1 Functional Block Diagram and Terminal Assignments. ANALOG ANALOG iN HIGH SYTE orrser " CONTROL CONTAGL - Low BYTE BURIED ZENER REF BURIED ZENEA REF DATA, ATA READY READY J a ts ner[7] @ PING 20) DATA ENABLE Bopo[a] @ PIN rein [20] Hee ca IDENTIFIER et (2 [13] CBE ne [2] 3] Ne op? [3] me tse oeo [3] 16] DATA READY DB3 tC Tz] bic com pei (4 17] DIGITAL COMMON oes (5 (15) B1e OFF oe2 (5 [16] BIPOLAR OFFSET ADS73 AD673 pes[e] (TOP VIEW) 7s] ANALOG COM oes [6 (roP view) = [75] ANALOG COMMON pas (7 | 14} ANALOG IN oes (7 [ia] anatos iw a7 Ce ra] Vee pas [ 8 13] Vee pee [3 [12] CONVERT oss [3] 1z] CONVERT mss pas [70 [3] Voc mse 087 [10 [at] Voc *PINS 1 & 2 ARE INTERNALLY CONNECTED TO TEST POINTS AND SHOULD BE LEFT FLOATING REV. B ANALOG-TO-DIGITAL CONVERTERS 6-17 ANALOG-TO-DIGITAL CONVERTERS aAD573/AD673 Vint Wo + te___ Lo. CONVERT $f tose V - { F mz _____ J Von+ Vou oe oe Figure 1. AD573 and AD673 CONVERT Timing TBE oR ABE Vent Ve ee pw tro DBO_DB7 Figure 2. AD573 READ Timing HIGH too HIGH DR IMPEDANCE Vou DATA IMPEDANCE DBe-DB9 Vo. ___VALIO_ | tee 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (57). 4.2.1 Life Test/Burn-In Circuit. bE Vat Va Yaw Me jaat thao HIGH too HIGH IMPEDANCE Von DATA IMPEDANCE peo- fig CATA | DB7 Vou - VAUD be tn Figure 3. AD673 READ Timing Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). o_9_ 4 tbe eee-6 10] OBS e Ne DBo tee [20 H__ oat fu} os fs} t 6k +5% DBs com [17+_ 3 Yaw > CARBON Des BIP ne] Nc. comp. ras 1 o pes acom [1s } tI 1 pes an[t} t p87 Ver ra} -$_0 - 15 sa. DBs CONVERT | 727 + o_[1L Wave Th} 0 +8V 6-18 ANALOG-TO-DIGITAL CONVERTERS REV. B