DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
Final 1
V ersi on: D M 93 01 - DS -F02
May 8, 20 00
General Description
The DM9301 is a physic al-layer, single-chip, low-
power media converter for 100BASE-TX/FX full
duplex repeater applications. On the TX medi a side,
it provides a dire ct interface to Unshielded Twisted
Pair Cable 5 (UTP5) for 100BASE-TX Fast Ethernet.
On the FX medi a side, it provi des a direct interface to
a Pseudo Emitter Coupled Logic level interface
(PECL).
The DM9301 uses a low power and high
performance CMOS process. It contains the entire
physic al layer functions of 100BASE-TX as defi ned
by IEEE802.3u, including the Physical Coding
Sublayer (PCS), Physical Medium Attachment
(PMA), Twisted Pair Physical Medium Dependent
Sublayer (TP-PMD) and a PECL compliant interface
for a fiber opti c modul e, c om pliant with ANSI X3.166.
The DM9301 provides two independent clock
recover y circ ui ts to minimi ze bit delay thr ough the
converter (no FIFO are used to buffer data between
the FX and TX interfaces). Furthermore, due to the
excellent rise/fall time control by a built-in w ave-
shaping filter, the DM9301 needs no external filter to
transport signals to the media on the 100Base-TX
interface.
Patent-Pen di ng C ircu its
• Smar t adaptiv e receiv er equal iz er
• Digital algorithm for high frequency clock/data
recovery circuit
• High speed wa ve-shaping circuit
Block Diagram
TX Code-
group
Alignment
Monitor
Descrambler Serial to
Parallel
NRZI
to
NRZ RX
CRM
MLT-3 to
NRZI Adaptive
EQ
CGM
125M TPRXCLK
25M TPRXCLK
25M
OSC/XTAL
TPRXI+/-
Parallel
to Serial
FX Code-
group
Alignment
Monitor
Serial to
Parallel
RX
CRM
Scrambler Parallel
to Serial
NRZ
to
NRZI
NRZI to
MLT-3 MLT-3
Driver TPTXO+/-
Rise/Fall
Time
CTL
25M FXRXCLK
125M FXRXCLK
PECL
TXMT
PECL
RCVR
PECLRXI +/-
PECLTXO +/-
FXSD
RCVR
Link Status
Monitor &
LED Driver
PECLSD
NRZ
to
NRZI
NRZI
to
NRZ
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
2Final
Version: DM9301-DS-F02
May 8, 20 00
Table of Contents
General Descripti on................................................1
Block Diagram........................................................1
Tab le of con te nts....................................................2
Features.................................................................3
Pin Configuration: DM9301 QFP.............................4
Pin D escrip tion .......................................................5
Functional Descripti on ..........................................10
100Base-FX to T X Oper ation................................10
T
FX PECL Receiver............................................10
T
FX Receiver Cloc k Recover y Module ................10
T
FX NRZI to NRZ Converter ...............................10
T
FX Serial to Parallel Converter ..........................11
T
FX Code Group Alignment Monitor....................11
T
TX Scrambler....................................................11
T
TX Parallel to Serial Converter..........................11
T
TX NRZ to NRZI Converter ...............................11
T
TX NRZI to MLT-3 Converter.............................11
T
TX MLT-3 Driver ...............................................11
100Base-TX to FX Operation................................12
T
TX Signal Detect...............................................12
T
TX Digital Adaptive Equalization........................12
T
TX MLT- 3 to NRZI Decoder...............................13
T
TX Cloc k Recover y Module...............................13
T
TX NRZI to NRZ Decoder..................................13
T
TX Serial to Parallel Converter ..........................13
T
TX Code Group Monitor ....................................13
T
TX Descrambler................................................13
T
FX Parallel to Serial Converter..........................13
T
FX NRZ to NRZI Encoder .................................13
T
Link Monitor and LED Driver.............................13
Absolute Maximum Ratings..................................14
DC Electrical Characteristics ................................15
AC Electri cal Characteristics.................................16
Timin g Wave for ms ...............................................17
T
100BASE-TX to F X Transmit Timing Diagram...17
T
100BASE-FX to T X Transmit Timing Diagram...17
T
5-Bit S ymbol 100Base-TX/F X Tr ansmit Timing
Diagram ............................................................17
T
5-Bit S ymbol 100Base-TX/F X Receive Timing
Diagram ............................................................18
Application Cir c uit (For R eferen c e Only)...............19
Package Information.............................................21
Ordering Informa tio n.............................................22
Disclaimer............................................................22
Company Overview..............................................22
Products...............................................................22
Contact Windows..................................................22
Warning ...............................................................22
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
Final 3
V ersi on: D M 93 01 - DS -F02
May 8, 20 00
Features
• 100BASE-TX/FX sing le-chip media converter
• Total bit delay from FX to TX i nterface is 20 bit
times (10 bit times each direction).
• Optional propagate HAL T on no Link condition
• Comp liant with IEEE802.3u 100BASE-TX standard
• Compliant with ANSI X3T12 TP-PMD 1995
standard
• Compliant with ANSI X3.166 FDDI-PMD
• Supports Half and Full Duplex operation 100Mbps,
the DM9301 operates in Full Duplex mode at all
times
• High performance 100Mbps clock generator and
data recovery circuit
• Controlled output edge rates in the 100Base-TX
transmit ter wi thout th e need for an external fil te r
• LED support for FX Link, T X li nk , FX receive data,
TX receive data, FX code group error and TX code
group error.
• Built in LED test, a ll LED will light during a reset
condition on the DM9301
• Digital clock recovery and regeneration circuit
usin g a n ad v an ced di g ital al gorith m to mini mi z e
jitter
• Supports diagnost ic T X to TX anal og loopback and
FX to FX analog loopback (Loopback at the NRZI
interface)
• Supports diagnost ic T X to TX di gi tal loopback and
FX to FX digital l oopbac k (Loopbac k at the 5B
symbol interface)
• Low- power, high-perform anc e CMOS process
• Available in a 100 QFP package
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
4Final
Version: DM9301-DS-F02
May 8, 20 00
Pin Configur ation: DM9301 F QFP
AVCC
PECLSD-
PECLRXI-
PECLRXI+
AGND
AVCC
PECLTXO-
PECLTXO+
AGND
TPRXI-
AGND
AVCC
AVCC
AGND
AGND
AGND
TPTXO-
TPTXO+
AVCC
OSC/X1
X2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
30
27
29
80
79
78
77
76
75
74
72
73
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
TPO1
TPO2
TPO3
TPO4
TPO5
TPO6
DVCC
DGND
TRIDRV
FXERRLED#
FXRCVLED#
DGND
TXALPBK
TXERRLED#
TXRCVLED#
TXLNKLED#
TPI0
TPI1
TPI2
TPI3
DGND
TPMUX
50
49
48
47
46
45
44
43
42
40
41
39
38
37
36
35
34
33
32
31
TPEN
DVCC
TXD0
TXD1
TXD2
FRCFXSD
TXD3
TXD4
TXCLK
HLTNOLNK
DVCC
DGND
DGND
BGRET
BGREF
OSC/XTL#
AGND
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
AGND
AGND
RXD4
DVCC
DVCC
TPO0
DGND
DM9301F
TPRXI+
RESET#
RXD0
DGND
DVCC
RXD2
RXD3
DGND
RXCLK
CONFIGA
CONFIGB
FXDLPBK
TXDLPBK
DVCC
FXLNKLED#
FXALPBK
DGND
MUXCTL1
MUXCTL0
BPSCRAM
RXD1
AVCC
AVCC
AGND
AVCC
AGND
PECLSD+
TESTMODE
DGND
DVCC
DVCC
DGND
DGND
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
Final 5
V ersi on: D M 93 01 - DS -F02
May 8, 20 00
Pin Description
Pin No. Pin Name I/O Description
Media Interface
1, 2 TPR XI+,
TPRXI- I100Mbps-TX Differential Input Pair:
These pins are differential receive input for 100BASE-
TX. They are capable of receivi ng 100BASE-TX MLT-3
data.
13, 14 TPTXO-,
TPTXO+ O100BASE-TX Differential Output P a ir:
The se outputs drive MLT -3 encoded dat a over 100Mbps
twisted pair cable and provide controlled rise and fall
times designed to filter the transmitter output,
reducing any associated EMI.
24, 25 PECLRXI- ,
PECLRXI+ I100BASE-FX PECL Receive Data Differential Pair:
These pins are differential receive input for 100BASE-
FX PECL. They are capab le of receiving PECL
100BASE-FX NRZI data.
18, 19 PECLTXO-,
PECLTXO+ O100BASE-F X Transmi t Dif f erential Ou t pu t Pair:
The se outputs drive NRZI encoded data for PECL FX
interface.
22, 23 PECLSD-,
PECLSD+ I100BASE-FX PECL Signal detect:
These pins are differential signals that indicate to the
DM9301 that the Optica l Module interface is detecting
valid optical energy.
Clock and Misc. Interface
27 OSCI/X1 I Cr ystal or Oscilla tor In put:
This pin should connect to one side of a 25MHz, 50ppm
c rystal if OSC/X TL #=0 . This pin is th e 2 5MHz, 50ppm
ex ternal TT L oscillator input, if OSC/XTLB=1.
28 X2 O Crystal Osci ll at or Output :
The o the r sid e of a 25MHz , 50ppm crystal should
connect to this pin if OSC/XTL #=0. Leave this pin open
if O S C/XTL#=1.
30 OSC/XTL# I Cry stal or Osc illator S elec t or P in:
OSC/XTL#= 0: An external 25MHz, 50ppm crystal
should connect to X1 and X2 pins.
OSC/XTL#= 1: An external 25MHz, 50ppm oscill ator
should connect to X1 and left X2 pin
open.
8BGREFI
Ba ndgap Voltage Refer ence R esis tor:
It connect s to a 6.49KΩ, 1% error tolerance resistor
between this pin and BGRET pin 9 to provide an
accurate current reference for the chip.
9BGRETI
Bandgap Return
Return pin for 6.49K Ω resistor connection, DO NOT
CONNECT TO GROUND.
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
6Final
Version: DM9301-DS-F02
May 8, 20 00
Clock and Misc. Interface (Continued)
84 TRIDRV I Tris t ate Digita l Outp u t Pins:
When set high, all digital output pins ar e set to high
impedance.
85 RESET# I Reset: Active Lo w input that initializes the DM9301,
must be asserted low for 30msecs after VCC is stable.
34 HLTNOLNK I Send Halt on no Link Conditi on:
Causes the DM9301 to Send out a Halt symbol to the
TX interface if no FX link active or send out a H alt
symbol to the FX interface if no TX link active.
Propagates a no-link condition to the Link P artner if 1,
Idle sy mbol if 0. Active high
93 CONFIGA I Config A : Must be connected to GND
95 CONFIGB I Config B: Must be connected to GND
LED Interface
67 FXLNKLED# OD FX Link LED:
Indicates Good Li nk stat us for 100M bps FX operat ion.
Active low (Open Drain Output)
64 TXLNKLED# OD TX Link LED:
Indicates Good Li nk stat us for 100M bps TX operat ion.
Active low (Open Drain Output)
69 FXRCVLED# OD FX Receive LED:
Indicates the presence of receive activity for 100Mbps
FX operat ion. A c tive l ow (Open Drain Output)
The DM9301 incorporates a "monostable" function on
the FXRCVLED output. This ensure s that even
minimum size packets generate adequate LED ON to
insure visibility.
62 TXRCVLED# OD TX Receive LED:
Indicates the presence of receive activity for 100Mbps
TX operat ion. A c tive l ow (Open Drain Output)
The DM9301 incorporates a "monostable" function on
the TXRCVLED output. This ensure s that even
minimum size packets generate adequate LED ON to
insure visibility.
80 FXERRLED# OD FX Error LED:
Indicates an error was detected by the FX Code Group
Alignment Monitor function on the FX rece iver. Active
low (Open Drain Output)
The DM9301 incorporates a "monostable" function on
the FXERRLED output. Thi s ensures that even
minimum size errors generate adequate LED ON to
insure visibility.
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
Final 7
V ersi on: D M 93 01 - DS -F02
May 8, 20 00
LED Interface(Continued)
52 TXERRLED# OD TX Error LED:
Indicates an error was detected by the TX Code Group
Alignment Monitor function on the TX rece iver. Active
low (Open Drain Output)
The DM9301 incorporates a "monostable" function on
the TXERRLED output. Thi s ensures that even
minimum size errors generate adequate LED ON to
insure visibility.
Diagnostic Port Interface
36 FXALPBK I FX Interface Analog Loop Back:
Loops the FX NRZI analog transmit data path to the FX
NRZI analog receive path.
Initiated at a H/W reset. Active high.
35 TXALPBK I TX Interface Analog Loop Back:
Loops the TX NRZI analog transmit data path to the TX
NRZI analog receive path.
Initiated at a H/W reset. Active high.
96 FXDLPBK I FX Interface Digital Loop Back:
Loops the FX 5-bit symbol digital transmit dat a path to
the FX 5-bit symbol digi tal receive path.
Initi ated at a H/W r eset. Activ e high.
97 TXDLPBK I TX Interface Digital Loop Back:
Loops the TX 5-bit symbol digital transmit dat a path to
the TX 5-bit symbol digi tal receive path.
Initiated at a H/W reset. Active high.
79, 77,
76, 74,
73
RXD0, RXD1,
RXD2, RXD3,
RXD4
0Receive Data 4 through 0:
The receive data 5- bit symbol interface. Data is clocked
out on the falling edge of RXCLK.
70 RXCLK O Receive Clock:
25 Mhz recovered clock, clock source is selected by the
MUXCTL1 and MUXCTL0.
48, 47,
45, 44,
43
TXD0, TXD1,
TXD2, TXD3,
TXD4
ITransmit Data 4 through 0:
The transmit data 5-bit symbol interface. Data is clocked
in on the rising edge of TXCLK.
71 TXCLK O Transmit Clock:
25 Mhz recovered clock, clock source is selected by the
MUXCTL1 and MUXCTL0.
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
8Final
Version: DM9301-DS-F02
May 8, 20 00
Diagnostic Port Interface (Continued)
39, 40 MUXCTL1,
MUXCTL0 IMux. Control 1 and 0:
Used for testing the DM9301 Data Paths. Set to zero for
normal operati on.
Initiated at a H/W reset. Active high.
MUXCTL1 MUXCTL0 DATA PATH
0 0 Normal, FX to TX and T X to FX
1 0 TX Transmit from TXD[4:0]
TXCLK from TX PLL
TX Receive to RXD[4:0]
RXCLK from TX receive clock
0 1 FX Transmit fro m TXD[4:0]
TXCLK from FX PLL
FX Receive to RXD[4:0]
RXCLK from FX receive clock
1 1 TX Transmit fro m TXD[4:0]
TXCLK from TX PLL
FX Receive to RXD[4:0]
RXCLK from FX receive clock
65, 54,
55, 57,
58, 60,
61
TPO6, TPO5,
TPO4, TPO3,
TPO2, TPO1,
TPO0
OTest Port Output :
Reflects the DM9301 internal status. Selection of status
indica tors is made by using TPEN and TPMUX.
Initiated at a H/W reset. Active high.
92, 91, 89,
88 TPI3, TPI2 , TPI1 ,
TPI0, ITest Port Input :
Controls the DM9301 internal test features. Selection of
input control is made by u sing TPEN and TPMUX.
TPEN must be true (one) for this signal to take effect.
Initiated at a H/W reset. Active high.
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
Final 9
V ersi on: D M 93 01 - DS -F02
May 8, 20 00
Diagnostic Port Interface (Continued)
49 FRCFXSD I Force FX Signal Detect
Forces the DM9301 FX interface Signal Detect true
Initiated at a H/W reset. Active high.
38 TPEN I Test Port Enabl e:
Enables the DM9301 Test Port features.
Initiated at a H/W reset. Active high.
87 TPMUX I Test Port Mux:
Controls the DM9301 T est P ort Input and Out put bits.
A value of zero indi cates the TX interface and a value of
one indicates the FX interface. TPEN must be true (one)
for this signal to take effect.
Initiated at a H/W reset. Active high.
41 BPSCRAM I Bypass Scrambler:
Controls the DM9301 T X i nterface Scrambler/De-
scrambler function. A value of zero indicates to
scramble and de-scramble the TX interface 5-bit
symbol data to and from the FX interface. A value of one
bypasse s the scrambl er/ de- scrambler functi on.
Initiated at a H/W reset. Active high.
Power and Ground Pins :
The power (VCC) and ground (GND) pins of the DM9301 are grouped in pairs of two categories - Digital
Circuitry Power/Ground Pairs and Analog Circuitry Power/Ground Pair.
Group A - Digital Supply Pairs
33, 42, 50, 53,
63, 68, 82, 90,
98
DGND P Digital Logic Ground.
37, 46, 51, 66,
81, 94 DVCC P Digital Logic power supply
Group B - Analog Circuit Supply Pairs
5, 6, 11, 12, 20,
29, 32, 99, 100, AGND P Analog circuit ground
3, 4, 7, 15, 21,
26, 31 AVCC P Analog circuit power supply
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
10 Final
Version: DM9301-DS-F02
May 8, 20 00
Functional Description
The DM9301 Fast Ethernet single-chip TX/FX media
converter, provides the functionality as s pecified in
IEEE802 .3, integra tes the co mp lete 100BASE -TX and a
PE CL op ti c mo d ule i nte rfac e for 100Base-FX. The
DM9301 implements the PCS, PMA, and TP-PMD
sublayer functions, as de fined by specification. The te rm
“X” will be used to describe the sections used in the fiber
PHY layer interface. The term “X” w ill be us ed to de scribe
the sections used in the twisted-pair PMD layer interface.
100BASE-FX to TX Operation
The block diagra m in figure 1 provides an o verview o f the
functional blocks contained in the FX to TX media
con ver ter in ter fa ce .
The FX to TX interface includes the following functional
blocks:
• FX PECL Receiver
• FX Receiver Clock Recovery Module
• FX NRZI to N RZ Converter
• FX Ser ial to Pa ra lle l Con ver te r
• FX Code Group Alignment Monitor
• TX Scrambler
• TX Para lle l to Ser ia l Con ver te r
• TX NRZ to N R ZI C on ver ter
• TX NRZI to MLT-3 Converter
• TX MLT-3 Driver
FX PECL Receiver
The PECL receiver receives NRZI encoded, differential
Pseudo Emitter Coupled Logic level signal. The receiver
converts the receive signal into a single-ended NRZI
signal and p resents this signa l to the FX C lock Recovery
Module.
FX Receiver Clock Recovery M odule
The FX Cloc k Recovery Module accepts NRZI data from
the PECL receiver. The FX C lock Recovery Module locks
onto the data stream, using a Phase Lock Loop (PLL) and
extracts the 125Mh z reference cloc k. The extracted and
synchronized clock and data are presented to the FX
NRZI to NRZ Decoder.
FX NRZI to NRZ C onverter
The receive data stream is required to be NR ZI encoded
for co mpatibility w ith the standards for 100Base- FX. This
conversion process must be reversed on the tr ansmit end.
The FX NRZ I to NRZ decoder, receives the NRZ I
data stream from the FX Clock Reco very Module
and con verts it to a N RZ data stream to be
presented to the FX Serial to Parallel conversion
block.
CGM
25M
OSC/XTAL
FX Code-
group
Alignment
Monitor
FX Serial
to
Parallel
FX
RX
CRM
TX
Scrambler
TX
Parallel
to Serial
TX
NRZ
to
NRZI
TX
NRZI to
MLT-3
MLT-3
Driver TPTXO+/-
Rise/Fall
Time
CTL
25M FXRXCLK
125M FXRXCLK
FX
PECL
RCVR
PECLRXI +/-
FXSD
RCVR
FX Link
Status
Monitor
PECLSD
FX
NRZI
to
NRZ
FX to TX B lock Dia gr am
Figur e 1
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
Final 11
V ersi on: D M 93 01 - DS -F02
May 8, 20 00
FX Se ria l to P arallel Con ver ter
The Serial to Parallel converter receives a serial
data stream from the NRZI to NRZ converter, and
converts the data str eam to parallel data to be
presented to the scrambler. The parallel data format
presented to the TX scrambler is 5B coded.
FX Code Group Alignment Monitor
The FX Code Group Alignment block receives non-
ali gned 5B data from the FX Serial to Paral lel
converter and monitors it for 5B code group
v i olations. FX Code Group Alignment occur s after
the J/K is detected, and subsequent data is
mon itored on a fixed boundary. I f a v iolation is
detected, the FX Code Gr oup Alignment Monit or
block signals the error t o the Link Status Monit or
block. In turn, the Link Status Monitor block flashes
the FX error LED (FXERRLED#).
TX Scrambler
The scrambler also receives data from the FX Serial
to Paralle l converter. Data from the serial to parallel
conversion block is 5B symbol encoded. The
scrambl er i s required to control the radiated
emissions (EMI ) by spreadi ng the tr ansmit energy
across the frequency spectrum at the media
connector and on the twisted pair cable in 100Base-
TX tr ansmit oper ation.
By scramb ling the data, the total energy presented
to the cable is randomly distributed over a wide
frequency range. Without the scrambler , energy
levels on the cable could peak beyond FCC
limitations at frequencies related to repeated 5B
sequences l ike conti nuous transmission of IDLE
symbols. The scrambler output is combined with the
NRZ 5B data from the FX Seria l to Parallel
conv erter via an XOR logic function. The result is a
scra mbled dat a stream with sufficient randomization
to decrease radiated emissions at critical
frequencies.
TX Parallel to Serial Converter
The TX Parallel to Serial conv erter receives parallel
5B scrambled data from the scrambler and
serializes i t (converts it from a parallel to a s erial
data stream). The serialized data stre am is then
presented to the NRZ to NRZI converter block
TX NRZ to NRZI Converter
After t he tr ansmit data str eam has been scrambl ed
and serialized, the data must be NRZI encoded for
compatib ility with the TP-PMD standard for
100Base-TX transmission over Category- 5
unshielded twisted pair cable.
TX MLT-3 Converter
The MLT-3 conversion is accomplished by
con verting the data stream output from the NRZI
encoder into two binary data streams with
alternately phased logic one events.
TX MLT-3 Driver
The two binary data streams created at the MLT-3
converter are fed to the twisted pair output driver
which converts these s treams to current sources
and alternately drives either side of the transmit
transformer primary winding resulting in a minimal
curr ent MLT-3 signal .
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
12 Final
Version: DM9301-DS-F02
May 8, 20 00
100Base-TX to FX Operation
The block diagra m in figure 2 provides an o verview o f the
functional blocks contained in the TX to FX media
con ver ter in ter fa ce .
The TX to FX interface contains the following functional
blocks:
• TX Digital Adaptive Equa lization
• TX MLT -3 to NR ZI
• TX Clock Recovery Module
• TX NR ZI to N RZ Dec oder
• TX Serial to Parallel Conversion
• TX Descrambler
• TX Code Group Alignment Monitor
• FX Para lle l to Ser ia l Con ver sio n
• FX NRZ to NRZI
• FX PECL Transmitter
TX Sig nal Detect
The signa l detect function meets the s pecifications
mandated by the ANSI XT12 TP-PMD100Base-TX
standards for both voltage thresholds and timing
parameters.
TX D igit al A dap tive Eq ualiz at ion
When transmitting data at high speeds over copper
twisted pair cable, attenuation based on frequency
becomes a concern. In high speed twisted pair signaling,
the frequency content of the tran smit te d signal can vary
greatly during normal operation based on the randomness
of th e s c ramb le d d at a st ream . T his va ri a tion in si gnal
attenuation caused by frequency variations must be
compensated for to ensure the integrity of the received
data. In order to ensure quality transmiss ion when
employing MLT-3 encoding, the compensation must be
able to adapt to various cable lengths and ca ble types
depending on the installed environment. The selection of
long cable lengths for a given implementation, requires
significant compensation which will be over-kill in a
situation that includes s horter, less attenuating cable
lengths. Conversely, the s election o f short or intermediate
cable lengths requiring less compensation will cause
serious under-compensation for longer leng th cables.
TX Code-
group
Alignment
Monitor
TX
Descrambler
TX
Serial to
Parallel
TX
NRZI
to
NRZ TX
CRM
TX
MLT-3 to
NRZI
TX
Adaptive
EQ
CGM
125M TPRXCLK
25M TPRXCLK
25M
OSC/XTAL
TPRXI+/-
FX
Parallel
to Serial
TX
PECL
TXMT
PECLTXO +/-
TX Link
Status
Monitor
TX
NRZ
to
NRZI
TX to FX Block Diagram
Figur e 2
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
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V ersi on: D M 93 01 - DS -F02
May 8, 20 00
There fore, the compensation or equali z ation m ust be
adaptive to ensure proper con ditio ni n g of t he re ceiv ed
signal independent of the ca ble le ngth.
TX ML T-3 to NR ZI De co der
The DM9301 decodes the MLT-3 information from the TX
Digital Adaptive Equalizer into NRZ I da ta.
TX Clock Recovery Module
The TX Clock Recovery Module accepts NRZI data
from the MLT-3 to NRZI decoder. The TX Clock
Recovery Module locks onto the data stream and
ex tr ac ts the 125Mhz refer enc e clock . The ext r ac ted
and synchronized clock and data are presented to
the NRZI to NRZ Decoder.
TX NRZI to NRZ Decoder
The TX tr ansmit data st r eam is required to be NRZI
encoded in for compatibility with the TP-PMD
standard for 100Base-TX transmission over
Category-5 unshielded twi sted pair cable. This
conversion process mu st be reversed on the
receive end. The NRZI to NRZ decoder, receives
the NRZI data stream from the TX Clock Recovery
Module and converts it to a NRZ data stream to be
presented to the TX Serial to Parallel conversion
block.
TX Serial to Parallel Co nv er te r
The TX Serial to Parallel c onv er ter receives a serial
data stream fro m the TX NRZI to NRZ d e c oder, a n d
converts the data str eam to parallel data to be
presented to the TX descrambler. The parallel data
format presented to the TX descrambler is 5B
coded.
TX Code Group Monitor
The TX Code Group Alignment block receives non-
ali gned 5B data from the TX descra mbler and
m oni tors it for 5B code gr oup violations. TX Code
Group Alignment occurs aft er t he J/K i s detec ted,
and subsequent data is monitored on a fixed
boundary. If a violation is detec ted, t he TX Code
Group Monit or block signal s the error to the L ink
Status Moni tor block. In turn, the Link Statu s
Monitor bl oc k flashes the TX error LED
(TXERRLED#).
TX Descrambl er
Because of the scrambling process required to
control the radiated emissions of transmit data
streams, the receiver must de scram ble the receive
data streams. The TX Descrambler rec eives
scrambled parallel dat a stream s from the Serial to
Parallel converter, des crambles the data streams,
and presents the data streams to the Code Group
alignment block.
FX Parallel to Serial Converter
The FX Parallel to Serial Converter receives parallel
5B data from the TX de-scrambler and serializes it
(converts i t f r om a parallel to a serial data st ream).
The serialized data stream is then presented to the
FX NRZ t o NRZI Encoder block
FX NRZ to NRZI Encoder
After t he tr ansmit data str eam has been serialized,
the data must be NRZI encoded for compatibility
with the standard for 100Base-FX.
Link Monitor a nd LED Driver
The Link Monitor block monitors both the TX and
FX interfaces for l ink active, receive data and erring
5-bit str eam.
The Link Monitor has the ability to detect each
interfaces l ink status. The TX wi ll tr ansmit either an
Idle symbol or a Ha lt symbol if the FX link is not
establ ished. Conversely the FX will transmit either
an Idle sym bol or a Hal t symbol if t he TX li nk i s not
established. When an o Link” conditio n e xi sts, th e
interface pin called LTNOLNK” will c ause Halt
symbols to be transmitted instead of Idle symbols.
Th e link ac tive LED i s a static indication of the TX
and FX links. It will be true to indicate the presence
of a link. The receive data and error LED are
generated through a ne-Shot” so that even the
smallest rec eive or error conditi on will be indic ated.
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
14 Final
Version: DM9301-DS-F02
May 8, 20 00
A bsolute Maxim um Ratin gs*
Absolute Max imum Rat ings ( 25°
°°
°C )
Symbol Parameter Min. Max. Unit Conditions
VCC Max. Supply Vo ltage -- 7.0 V Non-operating
VIN DC Input Voltage (VIN)-0.55.5V
VOUT DC Output Voltage(VOUT)-0.55.5V
T stg Storage Temperature Rang (Tstg) -65 + 150 °C
PD Power Dissipation (PD) --- 1 W
LT Lead Temp. (TL, Soldering, 10 sec.) -- - 24 0 °C
ESD ESD rating (Rzap=1.5K,Czap=100pF) --- 4000 V
Oper at ing C o nd itio ns
Symbol Parameter Min. Max. Unit Conditions
DVCC,AVCC Supply Voltage 4.75 --- 5.25
Tc Case Temperature 0 85 °C
PD
(Power Dissipation) 100BASE-TX --- 200 mA 5V
*Comments
Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only. Functional
operation of this device at these or any other
conditions above those indicated in the operational
sections of this specifi c ation is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect devic e reliability .
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
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V ersi on: D M 93 01 - DS -F02
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DC Electrical Characteristics (VCC = 5V)
Symbol Parameter Min. Typ. Max. Unit Conditions
TTL Inputs
(DPLXSEL, RESET# )
VIL Input Low Voltage 0.8 V IIL = -400uA
VIH Input High Voltage 2.0 V IIH = 100uA
IIL Input Low Current -200 uA VIN = 0.4V
IIH Input High Current 100 uA VIN = 2.7V
LED Drive r Outp u ts
(FXLINK LE D#, T XLINK LE D#, FXRXD#,RXR XD#)
VOL Out put Low Voltage 0.4 V IOL = 8mA
VOH Out put High Voltage 2.4 V IOH = -0.1mA
TPTX Receiver
VICM RXI+/RXI- Input Common-Mode
Voltage 1.5 2.0 2.5 V 100 Ω Termination
Across
TPTX Transmitter
ITD100 100TXO+/- 100BASE-TX Mode
Differential Output Current
ǔ
mA
PECL FX Transmitter
IFD100 PECLTX+/- 100BASE-FX Mode
Differential Output Current
mA
VOH PECL Output Voltage – High VCC-
1.05 VCC-
0.88 V
VOL PECL Output Voltage – Low VCC-
1.81 VCC-
1.62 V
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
16 Preliminary
Version: DM9301-DS-F02
May 8, 2000
AC Electrical Characteristics (Over full range of operating conditio n u n l e ss spec ifie d ot her w is e)
Symbol Parameter Min. Typ. Max. Unit Conditions
Transmitter
tTR/F 100TXO+/- Differential Rise/Fall Time 3.0 5.0 ns
tTM 100TXO+/- Differential Rise/Fall Time
Mismatch -0.5 0.5 ns
tTDC 100TXO+/- Differential Output Duty Cycle
Distortion -0.5 0.5 ns
tT/T 100TXO+/- Differential Output Peak-to-
Peak Jitter 300 ps
XOST 100TXO+/- Differential Voltage Overshoot 5 %
PECL Transmitter (FX Transmit Interface)
ptTR/F 100FXTD+/- Differential Rise/Fall Time 1.0 2.0 ns
ptTM 100FXTD+/- Differential Rise/Fall Time
Mismatch -0.5 0.5 ns
ptTDC 100FXTD+/- Differential Output Duty Cycle
Distortion -0.5 0.5 ns
ptPPJ 100FXTD+/- Differential Output Peak-to-
Peak Jitter 300 ps
ptDDJ 100FXTD+/- Differential Output Data
Dependent Jitter 2.0 ns
Clock Specifications
XNTOL TX Input Clock Fr equenc y T olerance
(Oscillator or Crystal input frequency) -50 +50 ppm 25MHz Frequency
XBTOL TX Output Clock Frequenc y T oler anc e -100 +100 ppm 25MHz F r equenc y
tPWH OSC Pulse Width High 14 ns
tPWL OSC Pulse Width Low 14 ns
tRPWH RX_CLK Pulse Wid th High 14 ns
tRPWL RX_CLK Pulse Width Low 14 ns
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
Final 17
V ersi on: D M 93 01 - DS -F02
May 8, 20 00
Ti mi ng Wa vefo rms
100BASE-TX to FX Transmit Timing Diagram
TPRXI+/-
t
FX
pd
PECLTX+/-
100BASE-TX to FX Transmit Timing Parameters
Symbol Parameter Min. Typ1.Max. Unit Conditions
tFXpd TPRXI+/- to PECLTX+/- Out (FX Latency) - - 10 BT
100BASE-FX to TX Transmit Timing Diagram
TPRXI+/-
t
TX
pd
PECLTX+/-
100BASE-FX to TX Transmit Timing Parameters
Symbol Parameter Min. Typ1.Max. Unit Conditions
tTXpd PECLRX+/- to TPTXo+/- Out (TX
Latency) --10BT
5-Bit Symbol 100Base-TX/FX Transmit Timing Diagram
TXCLK
t
TX
h
t
TX
S
t
TXD
pdtpo
TXD [4:0]
100TX+/- t
TX
rft
t
TXD
pdfxo
100FX+/-
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
18 Preliminary
Version: DM9301-DS-F02
May 8, 2000
5-Bit Symbol 100Base-TX/FX Transmit Tim ing Parameters
Symbol Parameter Min. Typ.1 Max. Unit Conditions
tTXsTXD[4:0] Setup To TX_CLK High 11 - - ns
tTXhTXD[4:0] Hold From TX_CLK
High 0--ns
tTXDpdtpo TXD[4:0] Sampled To TPTXO
(TXD to TP Latency) --6BT
tTXDpdfxo TXD[4:0] Sampled To PECL TXO
(TXD to FX Latency) --4BT
tTXr/f 100T X Driver Rise/F all Time 3 4 5 ns 90% To 10%, I nt o
100ohm Diff er ential
1. Typical values are at 25and are for design a id only; not guaranteed and not subject to production testing.
5-Bit Symbol 100Base-TX/FX Receive Timing Diagram
RXCLK
RXD [4:0]
TX RXI+/-
t
RX
S
t
RX
h
FX RXI+/-
t
RXD
pdtxi
t
RXD
pdfxi
5-Bit Symbol 100Base-TX/FX Receive Timing Parameter
Symbol Parameter Min. Typ1.Max. Unit Conditions
tRXsRXD[4:0) Setup To RX_CLK
High 10 - - ns
tRXhRXD[4:0]Hold From RX_CLK
High 10 - - ns
tRXDpdtxi TXRXI In To RXD[0:3] Out (Rx
Latency) --6BT
tRXDpdfxi P E CLRDI In To RXD[4:0] Out
(Rx Latency) --4BT
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
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V ersi on: D M 93 01 - DS -F02
May 8, 20 00
MII Application Circuit: DM9301 QFP (For Reference Only)
CUT AWAY POW ER PLANE IN
THIS AREA (See Schema tic )
THIS IS A ISOLATION BARRIER
.350
.125
100 PIN QFP U1
PIN 1
J2
RJ45
J1
Power
Jack .120
PIN 1
PIN 1
Fiber LEDs Twisted LEDs
Footprints for either
Optical module
PE68551 LAN Xformer
.080 holes with Plating
.120 Ho les
.018 holes
0. 80 inch
0. 25 in
.80
SOT-223 3.3v REG
DM9301 Sample, suggested placement
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
20 Preliminary
Version: DM9301-DS-F02
May 8, 2000
MII Application Circuit: DM9301 QFP (Continued, For Reference Only)
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
Final 21
V ersi on: D M 93 01 - DS -F02
May 8, 20 00
Packag e In form ation
QFP 100 L Ou tline Dim e nsions Unit: Inche s/mm
b
e
A
1
A
2
A
Seating Plane
1
30
31 50
51
80
81100
H
D
D
F
E
H
E
G
E
G
D
See Detail F
D
yL
G
D
~
~~
L
1
Detail F
c
Symbol Dimensions In Inches D imensions In mm
A 0.130 Max. 3.30 Max.
A10.004 Min. 0.10 Min.
A20.1120.005 2.850.13
b 0.012 +0.004 0.31 +0.10
-0.002 -0.05
c 0.006 +0.004 0.15 +0.10
-0.002 -0.05
D 0.5510.005 14.00+/-0.13
E 0.7870.005 20.00+/-0.13
e0.026 0.006 0.650.15
F 0.742 NOM. 18.85 NOM.
GD0.693 NOM. 17.60 NOM.
GE0.929 NOM. 23.60 NOM.
HD0.7400.012 18.800.31
HE0.9760.012 24.790.31
L 0.0470.008 1.190.20
L10.0950.008 2.410.20
y 0.006 Max. 0.15 Max.
θ0° ~ 12°0° ~ 12°
Note:
1. Dimension D & E do not include resin fins.
2. Dimension GD & GE are for PC Boa rd surface mount pad pitch design re ference only.
3. All dimensions are based on metric system.
DM9301
100Mbps E thern et Fi ber/Twi sted Pai r Si ngle Chi p Media Co nvert er
22 Preliminary
Version: DM9301-DS-F02
May 8, 2000
Ordering Information
Part Number Pin C ount Package
DM9301F 100 QFP
Disclaimer
The information appearing i n t his publication i s b e li ev e d to
be accurate. Integrated circuits sold by DAVICOM
Semiconductor are covered by the warranty and patent
ind e mnific ation pr ovisio n s stip ulated in the t e rms of sale
only. DAVICOM makes no warranty, express, statutory,
implied or by description regarding the information in this
publication or regarding the information i n thi s publication or
regarding the freedom of the described chip(s) from patent
infringement. FURTHER, DAVICOM MAKES NO
WAR RAN TY OF MERC HAN TABIL ITY OR FI TNESS F OR
ANY PURPOSE. D AVICOM reserves the right to halt
production or alter the specifications and prices at any time
without notice. Accordingly, the reader is cautioned to verify
tha t th e da t a sheets and othe r information in this publication
are current before placing order s. Products described
herein are intended for use in norma l commercial
applications. Applications involving unusual environmental
or r eli a bili ty r e qui rem e nts, e.g. m ilitar y equi pme nt or me dic al
life s upport equipment, are specifically not recommended
without additional processing by DAVICOM f or such
applications. Please note th at ap plication circuits illustrated
in this document are for reference purposes only.
DAVICOM ‘s terms and conditions pr inted on the ord er
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will not be bound by any terms inconsisten t with these
unless DAVICOM agrees otherwise in w riting. Acceptance
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integrated circuits for integration into data communication
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that are the industry’s best value for Data, Audio, V ideo, and
Internet/Intranet applications. To a chie ve this goa l, w e h ave
built an orga nization that is able to devel op chipsets in
response to the e vo lving technology requ irements o f our
cus tomers wh ile s till de liver ing p roducts th at me et th eir cost
requirements.
Products
We o ffer only products that satis fy high p erformance
requirements and which are c ompatible with major
hardware and software standards. Our currently av ailable
and soon to be released product s a re based on our
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Contact Windows
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WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the
limits of the operating ranges will stress a nd may temporarily (and permanently) affect and damage structure, performance and/or function.
