1
®
FN4805.21
ICL3221, ICL3222, ICL3223,
ICL3232, ICL3241, ICL3243
One Microamp Supply-Current, +3V to +5.5V,
250kbps, RS-232 Transmitters/Receivers
The Intersil ICL32XX devices are 3.0V to 5.5V powered
RS-232 transmitters/receivers which meet ElA/TIA-232 and
V.28/V.24 specifications, even at VCC = 3.0V. Targeted
applications are PDAs, Palmtops, and notebook and laptop
computers where the low operational, and even lower
standby, power consumption is critical. Efficient on-chip
charge pumps, coupled with manual and automatic
powerdown functions (except for the ICL3232), reduce the
standby supply current to a 1µA trickle. Small footprint
packaging, and the use of small, low value capacitors ensure
board space savings as well. Data rates greater than
250kbps are guaranteed at worst case load conditions. This
family is fully compatible with 3.3V only systems, mixed 3.3V
and 5.0V systems, and 5.0V only systems.
The ICL324X are 3-driver, 5-receiver devices that provide a
complete serial port suitable for laptop or notebook
computers. Both devices also include noninverting always-
active receivers for “wake-up” capability.
The ICL3221, ICL3223 and ICL3243, feature an
automatic powerdown function which powers down the
on-chip power-supply and driver circuits. This occurs when
an attached peripheral device is shut off or the RS-232
cable is removed, conserving system power automatically
without changes to the hardware or operating system.
These devices power up again when a valid RS-232
voltage is applied to any receiver input.
Table 1 summarizes the features of the devices represented
by this data sheet, while Application Note AN9863
summarizes the features of each device comprising the
ICL32XX 3V family.
Features
• Pb-Free Plus Anneal Available as an Option
(RoHS Compliant) (See Ordering Info)
• 15kV ESD Protected (Human Body Model)
• Drop in Replacements for MAX3221, MAX3222,
MAX3223, MAX3232, MAX3241, MAX3243, SP3243
• ICL3221 is Low Power, Pin Compatible Upgrade for 5V
MAX221
• ICL3222 is Low Power, Pin Compatible Upgrade for 5V
MAX242, and SP312A
• ICL3232 is Low Power Upgrade for HIN232/ICL232 and
Pin Compatible Competitor Devices
• RS-232 Compatible with VCC = 2.7V
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• Latch-Up Free
• On-Chip Voltage Converters Require Only Four External
0.1µF Capacitors
• Manual and Automatic Powerdown Features (Except
ICL3232)
• Guaranteed Mouse Driveability (ICL324X Only)
• Receiver Hysteresis For Improved Noise Immunity
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps
• Guaranteed Minimum Slew Rate . . . . . . . . . . . . . . . 6V/µs
• Wide Power Supply Range . . . . . . . Single +3V to +5.5V
• Low Supply Current in Powerdown State. . . . . . . . . . .1µA
Applications
• Any System Requiring RS-232 Communication Ports
- Battery Powered, Hand-Held, and Portable Equipment
- Laptop Computers, Notebooks, Palmtops
- Modems, Printers and other Peripherals
- Digital Cameras
- Cellular/Mobile Phones
TABLE 1. SUMMARY OF FEATURES
PART NUMBER
NO. OF
Tx.
NO. OF
Rx.
NO. OF
MONITOR Rx.
(ROUTB)
DATA
RATE
(kbps)
Rx. ENABLE
FUNCTION?
READY
OUTPUT?
MANUAL
POWER-
DOWN?
AUTOMATIC
POWERDOWN
FUNCTION?
ICL3221 1 1 0 250 Yes No Yes Yes
ICL3222 2 2 0 250 Yes No Yes No
ICL3223 2 2 0 250 Yes No Yes Yes
ICL3232 2 2 0 250 No No No No
ICL3241 3 5 2 250 Yes No Yes No
ICL3243 3 5 1 250 No No Yes Yes
Data Sheet March 1, 2006
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1999-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN4805.21
March 1, 2006
Ordering Information
PART NUMBER (NOTE 1) PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. #
ICL3221CA ICL3221CA 0 to 70 16 Ld SSOP M16.209
ICL3221CAZ (Note 2) ICL3221CAZ 0 to 70 16 Ld SSOP (Pb-free) M16.209
ICL3221CV ICL3221CV 0 to 70 16 Ld TSSOP M16.173
ICL3221CVZ (Note 2) 3221CVZ 0 to 70 16 Ld TSSOP (Pb-free) M16.173
ICL3221IA ICL3221IA -40 to 85 16 Ld SSOP M16.209
ICL3221IAZ (Note 2) ICL3221IAZ -40 to 85 16 Ld SSOP (Pb-free) M16.209
ICL3222CA ICL3222CA 0 to 70 20 Ld SSOP M20.209
ICL3222CAZ (Note 2) ICL3222CAZ 0 to 70 20 Ld SSOP (Pb-free) M20.209
ICL3222CB ICL3222CB 0 to 70 18 Ld SOIC M18.3
ICL3222CBZ (Note 2) 3222CBZ 0 to 70 18 Ld SOIC (Pb-free) M18.3
ICL3222CP ICL3222CP 0 to 70 18 Ld PDIP E18.3
ICL3222CPZ (Note 2) ICL3222CPZ 0 to 70 18 Ld PDIP* (Pb-free) E18.3
ICL3222CV ICL3222CV 0 to 70 20 Ld TSSOP M20.173
ICL3222CVZ (Note 2) ICL3222CVZ 0 to 70 20 Ld TSSOP (Pb-free) M20.173
ICL3222IA ICL3222IA -40 to 85 20 Ld SSOP M20.209
ICL3222IAZ (Note 2) ICL3222IAZ -40 to 85 20 Ld SSOP (Pb-free) M20.209
ICL3222IB ICL3222IB -40 to 85 18 Ld SOIC M18.3
ICL3222IV ICL3222IV -40 to 85 20 Ld TSSOP M20.173
ICL3222IVZ (Note 2) ICL3222IVZ -40 to 85 20 Ld TSSOP (Pb-free) M20.173
ICL3223CA ICL3223CA 0 to 70 20 Ld SSOP M20.209
ICL3223CAZ (Note 2) ICL3223CAZ 0 to 70 20 Ld SSOP (Pb-free) M20.209
ICL3223CP ICL3223CP 0 to 70 20 Ld PDIP E20.3
ICL3223CPZ (Note 2) ICL3223CPZ 0 to 70 20 Ld PDIP* (Pb-free) E20.3
ICL3223CV ICL3223CV 0 to 70 20 Ld TSSOP M20.173
ICL3223IA ICL3223IA -40 to 85 20 Ld SSOP M20.209
ICL3223IAZ (Note 2) ICL3223IAZ -40 to 85 20 Ld SSOP (Pb-free) M20.209
ICL3223IV ICL3223IV -40 to 85 20 Ld TSSOP M20.173
ICL3223IVZ (Note 2) ICL3223IVZ -40 to 85 20 Ld TSSOP (Pb-free) M20.173
ICL3232CA ICL3232CA 0 to 70 16 Ld SSOP M16.209
ICL3232CAZ (Note 2) 3232CAZ 0 to 70 16 Ld SSOP (Pb-free) M16.209
ICL3232CB ICL3232CB 0 to 70 16 Ld SOIC M16.3
ICL3232CBZ (Note 2) 3232CBZ 0 to 70 16 Ld SOIC (Pb-free) M16.3
ICL3232CBN 3232CBN 0 to 70 16 Ld SOIC (N) M16.15
ICL3232CBNZ (Note 2) 3232CBNZ 0 to 70 16 Ld SOIC (N) (Pb-free) M16.15
ICL3232CP ICL3232CP 0 to 70 16 Ld PDIP E16.3
ICL3232CPZ (Note 2) ICL3232CPZ 0 to 70 16 Ld PDIP* (Pb-free) E16.3
ICL3232CV ICL3232CV 0 to 70 16 Ld TSSOP M16.173
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
3FN4805.21
March 1, 2006
ICL3232CVZ (Note 2) 3232CVZ 0 to 70 16 Ld TSSOP (Pb-free) M16.173
ICL3232IA ICL3232IA -40 to 85 16 Ld SSOP M16.209
ICL3232IAZ (Note 2) 3232IAZ -40 to 85 16 Ld SSOP (Pb-free) M16.209
ICL3232IB ICL3232IB -40 to 85 16 Ld SOIC M16.3
ICL3232IBZ (Note 2) 3232IBZ -40 to 85 16 Ld SOIC (Pb-free) M16.3
ICL3232IBN 3232IBN -40 to 85 16 Ld SOIC (N) M16.15
ICL3232IBNZ (Note 2) 3232IBNZ -40 to 85 16 Ld SOIC (N) (Pb-free) M16.15
ICL3232IV ICL3232IV -40 to 85 16 Ld TSSOP M16.173
ICL3232IVZ (Note 2) 3232IVZ -40 to 85 16 Ld TSSOP (Pb-free) M16.173
ICL3241CA ICL3241CA 0 to 70 28 Ld SSOP M28.209
ICL3241CAZ (Note 2) ICL3241CAZ 0 to 70 28 Ld SSOP (Pb-free) M28.209
ICL3241CB ICL3241CB 0 to 70 28 Ld SOIC M28.3
ICL3241CBZ (Note 2) ICL3241CBZ 0 to 70 28 Ld SOIC (Pb-free) M28.3
ICL3241CV ICL3241CV 0 to 70 28 Ld TSSOP M28.173
ICL3241CVZ (Note 2) ICL3241CVZ 0 to 70 28 Ld TSSOP (Pb-free) M28.173
ICL3241IA ICL3241IA -40 to 85 28 Ld SSOP M28.209
ICL3241IAZ (Note 2) ICL3241IAZ -40 to 85 28 Ld SSOP (Pb-free) M28.209
ICL3241IB ICL3241IB -40 to 85 28 Ld SOIC M28.3
ICL3241IBZ (Note 2) ICL3241IBZ -40 to 85 28 Ld SOIC (Pb-free) M28.3
ICL3241IV ICL3241IV -40 to 85 28 Ld TSSOP M28.173
ICL3241IVZ (Note 2) ICL3241IVZ -40 to 85 28 Ld TSSOP (Pb-free) M28.173
ICL3243CA ICL3243CA 0 to 70 28 Ld SSOP M28.209
ICL3243CAZ (Note 2) ICL3243CAZ 0 to 70 28 Ld SSOP (Pb-free) M28.209
ICL3243CB ICL3243CB 0 to 70 28 Ld SOIC M28.3
ICL3243CBZ (Note 2) ICL3243CBZ 0 to 70 28 Ld SOIC (Pb-free) M28.3
ICL3243CV ICL3243CV 0 to 70 28 Ld TSSOP M28.173
ICL3243CVZ (Note 2) ICL3243CVZ 0 to 70 28 Ld TSSOP (Pb-free) M28.173
ICL3243IA ICL3243IA -40 to 85 28 Ld SSOP M28.209
ICL3243IAZ (Note 2) ICL3243IAZ -40 to 85 28 Ld SSOP (Pb-free) M28.209
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTES:
1. Most surface mount devices are available on tape and reel; add “-T” to suffix.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Ordering Information (Continued)
PART NUMBER (NOTE 1) PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. #
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
4FN4805.21
March 1, 2006
Pinouts
ICL3221 (SSOP, TSSOP)
TOP VIEW
ICL3222 (PDIP, SOIC)
TOP VIEW
ICL3222 (SSOP, TSSOP)
TOP VIEW
ICL3223 (PDIP, SSOP, TSSOP)
TOP VIEW
ICL3232 (PDIP, SOIC, SSOP, TSSOP)
TOP VIEW
ICL3241 (SOIC, SSOP, TSSOP)
TOP VIEW
EN
C1+
V+
C1-
C2+
C2-
V-
R1IN
FORCEOFF
GND
T1OUT
FORCEON
T1IN
R1OUT
VCC
INVALID
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
EN
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
SHDN
GND
T1OUT
R1IN
R1OUT
T2IN
VCC
T1IN
R2OUT
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
EN
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
SHDN
GND
T1OUT
R1IN
R1OUT
T1IN
NC
VCC
NC
T2IN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
R2OUT
EN
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
FORCEOFF
GND
T1OUT
R1IN
R1OUT
T1IN
INVALID
VCC
FORCEON
T2IN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
R2OUT
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
VCC
T1OUT
R1IN
R1OUT
T1IN
R2OUT
GND
T2IN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C2+
C2-
V-
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T3OUT
T3IN
T2IN
T1IN
C1+
VCC
GND
C1-
EN
R1OUTB
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
V+
SHDN
R2OUTB
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T2OUT
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
5FN4805.21
March 1, 2006
ICL3243 (SOIC, SSOP, TSSOP)
TOP VIEW
Pinouts (Continued)
C2+
C2-
V-
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T3OUT
T3IN
T2IN
T1IN
C1+
VCC
GND
C1-
FORCEON
INVALID
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
V+
FORCEOFF
R2OUTB
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T2OUT
Pin Descriptions
PIN FUNCTION
VCC System power supply input (3.0V to 5.5V).
V+ Internally generated positive transmitter supply (+5.5V).
V- Internally generated negative transmitter supply (-5.5V).
GND Ground connection.
C1+ External capacitor (voltage doubler) is connected to this lead.
C1- External capacitor (voltage doubler) is connected to this lead.
C2+ External capacitor (voltage inverter) is connected to this lead.
C2- External capacitor (voltage inverter) is connected to this lead.
TIN TTL/CMOS compatible transmitter Inputs.
TOUT RS-232 level (nominally ±5.5V) transmitter outputs.
RIN RS-232 compatible receiver inputs.
ROUT TTL/CMOS level receiver outputs.
ROUTB TTL/CMOS level, noninverting, always enabled receiver outputs.
INVALID Active low output that indicates if no valid RS-232 levels are present on any receiver input.
EN Active low receiver enable control; doesn’t disable ROUTB outputs.
SHDN Active low input to shut down transmitters and on-board power supply, to place device in low power mode.
FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (See Table 2).
FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF must be high).
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
6FN4805.21
March 1, 2006
Typical Operating Circuits
ICL3221 ICL3222
ICL3223 ICL3232
15
VCC
T1OUT
T1IN
T1
0.1µF
+0.1µF
+
0.1µF
11 13
2
4
3
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
5
6
R1OUT R1IN
R1
89
5kΩ
C1
C2
+C3
C4
EN
1
GND
+3.3V +0.1µF
14
TTL/CMOS
LOGIC LEVELS
RS-232
LEVELS
FORCEON
FORCEOFF
12
16 VCC
10
INVALID TO POWER
CONTROL
LOGIC
+
C3 (OPTIONAL CONNECTION, NOTE)
NOTE: The negative terminal of C3 can be
connected to either VCC or GND
17
VCC
T1OUT
T2OUT
T1IN
T2IN
T1
T2
0.1µF
+0.1µF
+
0.1µF
12
11
15
8
2
4
3
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
5
6
R1OUT R1IN
14
5kΩ
R2OUT R2IN
9
10
5kΩ
13
C1
C2
+C3
C4
EN
SHDN
1
GND
18
+3.3V +0.1µF
16
VCC
TTL/CMOS
LOGIC LEVELS
RS-232
LEVELS
R1
R2
+
C3 (OPTIONAL CONNECTION, NOTE)
NOTE: The negative terminal of C3 can be
connected to either VCC or GND
19
VCC
T1OUT
T2OUT
T1IN
T2IN
T1
T2
0.1µF
+
0.1µF
+
0.1µF
13
12
17
8
2
4
3
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
5
6
R1OUT R1IN
16
5kΩ
R2OUT R2IN
910
5kΩ
15
C1
C2
+C3
C4
EN
1
GND
+3.3V +0.1µF
18
TTL/CMOS
LOGIC LEVELS
RS-232
LEVELS
R1
R2
FORCEON
FORCEOFF
14
20 VCC
11
INVALID TO POWER
CONTROL LOGIC
16
VCC
T1OUT
T2OUT
T1IN
T2IN
T1
T2
0.1µF
+
0.1µF
+
0.1µF
11
10
14
7
1
3
2
6
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
4
5
R1OUT R1IN
13
5kΩ
R2OUT R2IN
8
9
5kΩ
12
C1
C2
+C3
C4
GND
+3.3V +0.1µF
15
TTL/CMOS
LOGIC LEVELS
RS-232
LEVELS
R1
R2
+
C3 (OPTIONAL CONNECTION, NOTE)
NOTE: The negative terminal of C3 can be
connected to either VCC or GND
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
7FN4805.21
March 1, 2006
ICL3241 ICL3243
Typical Operating Circuits (Continued)
26
VCC
T1OUT
T2OUT
T3OUT
T1IN
T2IN
T3IN
T1
T2
T3
0.1µF
+0.1µF
+
0.1µF
14
13
9
10
12 11
28
24
27
3
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
1
2
R1OUT R1IN
4
5kΩ
R2OUT R2IN
518
5kΩ
R3OUT R3IN
617
5kΩ
R4OUT R4IN
716
5kΩ
R5OUT R5IN
R5
815
5kΩ
19
R2OUTB
C1
C2
+C3
C4
EN
SHDN
23
GND
22
+3.3V +0.1µF
20
25
VCC
TTL/CMOS
LOGIC LEVELS
RS-232
LEVELS
RS-232
LEVELS
R1OUTB
21
R1
R2
R3
R4
26
VCC
T1OUT
T2OUT
T3OUT
T1IN
T2IN
T3IN
T1
T2
T3
0.1µF
+0.1µF
+
0.1µF
14
13
9
10
12 11
28
24
27
3
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
1
2
R1OUT R1IN
4
5kΩ
R2OUT R2IN
518
5kΩ
R3OUT R3IN
617
5kΩ
R4OUT R4IN
716
5kΩ
R5OUT R5IN
R5
815
5kΩ
19
R2OUTB
C1
C2
+C3
C4
FORCEON
FORCEOFF
23
GND
22
+3.3V +0.1µF
20
25
VCC
TTL/CMOS
LOGIC LEVELS
RS-232
LEVELS
RS-232
LEVELS
R1
R2
R3
R4
21
INVALID
TO POWER
CONTROL LOGIC
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
8FN4805.21
March 1, 2006
Absolute Maximum Ratings Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
TIN, FORCEOFF, FORCEON, EN, SHDN . . . . . . . . . -0.3V to 6V
RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
Output Voltages
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
ROUT
, INVALID. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Short Circuit Duration
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Operating Conditions
Temperature Range
ICL32XXCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
ICL32XXIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Thermal Resistance (Typical, Note 3) θJA (°C/W)
16 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 90
18 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 80
20 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 77
16 Ld Wide SOIC Package . . . . . . . . . . . . . . . . . . . 100
16 Ld Narrow SOIC Package. . . . . . . . . . . . . . . . . . 115
18 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 75
28 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 75
16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 135
20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 122
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 145
20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 140
28 Ld SSOP and TSSOP Packages . . . . . . . . . . . . 100
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC, SSOP, TSSOP - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
Typicals are at TA = 25°C
PARAMETER TEST CONDITIONS
TEMP
(°C) MIN TYP MAX UNITS
DC CHARACTERISTICS
Supply Current, Automatic
Powerdown
All RIN Open, FORCEON = GND, FORCEOFF =V
CC
(ICL3221, ICL3223, ICL3243 Only)
25 - 1.0 10 µA
Supply Current, Powerdown FORCEOFF = SHDN = GND (Except ICL3232) 25 - 1.0 10 µA
Supply Current,
Automatic Powerdown Disabled
All Outputs Unloaded,
FORCEON = FORCEOFF =
SHDN =V
CC
VCC = 3.15V,
ICL3221-32
25 - 0.3 1.0 mA
VCC = 3.0V, ICL3241-43 25 - 0.3 1.0 mA
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low TIN, FORCEON, FORCEOFF, EN, SHDN Full - - 0.8 V
Input Logic Threshold High TIN, FORCEON, FORCEOFF, EN,
SHDN
VCC = 3.3V Full 2.0 - - V
VCC = 5.0V Full 2.4 - - V
Input Leakage Current TIN, FORCEON, FORCEOFF, EN, SHDN Full - ±0.01 ±1.0 µA
Output Leakage Current
(Except ICL3232)
FORCEOFF =GND or EN=V
CC Full - ±0.05 ±10 µA
Output Voltage Low IOUT = 1.6mA Full - - 0.4 V
Output Voltage High IOUT = -1.0mA Full VCC -0.6 VCC -0.1 - V
AUTOMATIC POWERDOWN (ICL3221, ICL3223, ICL3243 Only, FORCEON = GND, FORCEOFF = VCC)
Receiver Input Thresholds to
Enable Transmitters
ICL32XX Powers Up (See Figure 6) Full -2.7 - 2.7 V
Receiver Input Thresholds to
Disable Transmitters
ICL32XX Powers Down (See Figure 6) Full -0.3 - 0.3 V
INVALID Output Voltage Low IOUT = 1.6mA Full - - 0.4 V
INVALID Output Voltage High IOUT = -1.0mA Full VCC-0.6 - - V
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
9FN4805.21
March 1, 2006
Receiver Threshold to
Transmitters Enabled Delay (tWU)
25 - 100 - µs
Receiver Positive or Negative
Threshold to INVALID High Delay
(tINVH)
25 - 1 - µs
Receiver Positive or Negative
Threshold to INVALID Low Delay
(tINVL)
25 - 30 - µs
RECEIVER INPUTS
Input Voltage Range Full -25 - 25 V
Input Threshold Low VCC = 3.3V 25 0.6 1.2 - V
VCC = 5.0V 25 0.8 1.5 - V
Input Threshold High VCC = 3.3V 25 - 1.5 2.4 V
VCC = 5.0V 25 - 1.8 2.4 V
Input Hysteresis 25 - 0.3 - V
Input Resistance 25 3 5 7 kΩ
TRANSMITTER OUTPUTS
Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 - V
Output Resistance VCC = V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - Ω
Output Short-Circuit Current Full - ±35 ±60 mA
Output Leakage Current VOUT =±12V, VCC = 0V or 3V to 5.5V
Automatic Powerdown or FORCEOFF = SHDN =GND
Full - - ±25 µA
MOUSE DRIVEABILITY (ICL324X Only)
Transmitter Output Voltage
(See Figure 9)
T1IN =T2
IN = GND, T3IN =V
CC, T3OUT Loaded with 3kΩ to
GND, T1OUT and T2OUT Loaded with 2.5mA Each
Full ±5- -V
TIMING CHARACTERISTICS
Maximum Data Rate RL=3kΩ, CL= 1000pF, One Transmitter Switching Full 250 500 - kbps
Receiver Propagation Delay Receiver Input to Receiver
Output, CL= 150pF
tPHL 25 - 0.3 - µs
tPLH 25 - 0.3 - µs
Receiver Output Enable Time Normal Operation (Except ICL3232) 25 - 200 - ns
Receiver Output Disable Time Normal Operation (Except ICL3232) 25 - 200 - ns
Transmitter Skew tPHL - tPLH Full - 200 1000 ns
Receiver Skew tPHL - tPLH Full - 100 500 ns
Transition Region Slew Rate VCC =3.3V,
RL=3kΩ to 7kΩ,
Measured From 3V to -3V or -3V
to 3V
CL = 200pF to 2500pF 25 4 8.0 30 V/µs
CL = 200pF to 1000pF 25 6 - 30 V/µs
ESD PERFORMANCE
RS-232 Pins (TOUT
, RIN) Human Body Model ICL3221 - ICL3243 25 - ±15 - kV
IEC61000-4-2 Contact Discharge ICL3221 - ICL3243 25 - ±8-kV
IEC61000-4-2 Air Gap Discharge ICL3221 - ICL3232 25 - ±8-kV
ICL3241 - ICL3243 25 - ±6-kV
All Other Pins Human Body Model ICL3221 - ICL3243 25 - ±2-kV
Electrical Specifications Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
Typicals are at TA = 25°C (Continued)
PARAMETER TEST CONDITIONS
TEMP
(°C) MIN TYP MAX UNITS
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
10 FN4805.21
March 1, 2006
Detailed Description
ICL32XX interface ICs operate from a single +3V to +5.5V
supply, guarantee a 250kbps minimum data rate, require
only four small external 0.1µF capacitors, feature low power
consumption, and meet all ElA RS-232C and V.28
specifications. The circuit is divided into three sections:
charge pump, transmitters and receivers.
Charge-Pump
Intersil’s new ICL32XX family utilizes regulated on-chip dual
charge pumps as voltage doublers, and voltage inverters to
generate ±5.5V transmitter supplies from a VCC supply as
low as 3.0V. This allows these devices to maintain RS-232
compliant output levels over the ±10% tolerance range of
3.3V powered systems. The efficient on-chip power supplies
require only four small, external 0.1µF capacitors for the
voltage doubler and inverter functions at VCC = 3.3V. See
the Capacitor Selection section, and Table 3 for capacitor
recommendations for other operating conditions. The charge
pumps operate discontinuously (i.e., they turn off as soon as
the V+ and V- supplies are pumped up to the nominal
values), resulting in significant power savings.
Transmitters
The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. Coupled with the on-chip ±5.5V supplies,
these transmitters deliver true RS-232 levels over a wide
range of single supply system voltages.
Except for the ICL3232, all transmitter outputs disable and
assume a high impedance state when the device enters the
powerdown mode (See Table 2). These outputs may be
driven to ±12V when disabled.
All devices guarantee a 250kbps data rate for full load
conditions (3kΩ and 1000pF), VCC ≥ 3.0V, with one
transmitter operating at full speed. Under more typical
conditions of VCC ≥3.3V, RL=3kΩ, and CL= 250pF, one
transmitter easily operates at 900kbps.
Transmitter inputs float if left unconnected, and may cause
ICC increases. Connect unused inputs to GND for the best
performance.
Receivers
All the ICL32XX devices contain standard inverting receivers
that three-state (except for the ICL3232) via the EN or
FORCEOFF control lines. Additionally, the two ICL324X
products include noninverting (monitor) receivers (denoted
by the ROUTB label) that are always active, regardless of the
state of any control lines. All the receivers convert RS-232
signals to CMOS output levels and accept inputs up to ±25V
while presenting the required 3kΩ to 7kΩ input impedance
(See Figure 1) even if the power is off (VCC = 0V). The
receivers’ Schmitt trigger input stage uses hysteresis to
increase noise immunity and decrease errors due to slow
input signal transitions.
The ICL3221/22/23/41 inverting receivers disable only when
EN is driven high. ICL3243 receivers disable during forced
(manual) powerdown, but not during automatic powerdown
(See Table 2).
ICL324X monitor receivers remain active even during
manual powerdown and forced receiver disable, making
them extremely useful for Ring Indicator monitoring.
Standard receivers driving powered down peripherals must
be disabled to prevent current flow through the peripheral’s
protection diodes (See Figures 2 and 3). This renders them
useless for wake up functions, but the corresponding
monitor receiver can be dedicated to this task as shown in
Figure 3.
Low Power Operation
These 3V devices require a nominal supply current of
0.3mA, even at VCC = 5.5V, during normal operation (not in
powerdown mode). This is considerably less than the 5mA
to 11mA current required by comparable 5V RS-232 devices,
allowing users to reduce system power simply by switching
to this new family.
Pin Compatible Replacements For 5V Devices
The ICL3221/22/32 are pin compatible with existing 5V
RS-232 transceivers - see the Features section on the front
page for details.
This pin compatibility coupled with the low Icc and wide
operating supply range, make the ICL32XX potential lower
power, higher performance drop-in replacements for existing
5V applications. As long as the ±5V RS-232 output swings
are acceptable, and transmitter input pull-up resistors aren’t
required, the ICL32XX should work in most 5V applications.
When replacing a device in an existing 5V application, it is
acceptable to terminate C3 to VCC as shown on the Typical
Operating Circuit. Nevertheless, terminate C3 to GND if
possible, as slightly better performance results from this
configuration.
Powerdown Functionality (Except ICL3232)
The already low current requirement drops significantly
when the device enters powerdown mode. In powerdown,
supply current drops to 1µA, because the on-chip charge
pump turns off (V+ collapses to VCC, V- collapses to GND),
and the transmitter outputs three-state. Inverting receiver
outputs may or may not disable in powerdown; refer to
Table 2 for details. This micro-power mode makes these
devices ideal for battery powered and portable applications.
RXOUT
GND ≤ VROUT ≤ VCC
5kΩ
RXIN
-25V ≤ VRIN ≤ +25V
GND
VCC
FIGURE 1. INVERTING RECEIVER CONNECTIONS
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
11 FN4805.21
March 1, 2006
Software Controlled (Manual) Powerdown
Most devices in the ICL32XX family provide pins that allow
the user to force the IC into the low power, standby state.
On the ICL3222 and ICL3241, the powerdown control is via
a simple shutdown (SHDN) pin. Driving this pin high enables
normal operation, while driving it low forces the IC into its
powerdown state. Connect SHDN to VCC if the powerdown
function isn’t needed. Note that all the receiver outputs
remain enabled during shutdown (See Table 2). For the
lowest power consumption during powerdown, the receivers
should also be disabled by driving the EN input high (See
next section, and Figures 2 and 3).
The ICL3221, ICL3223, and ICL3243 utilize a two pin
approach where the FORCEON and FORCEOFF inputs
determine the IC’s mode. For always enabled operation,
FORCEON and FORCEOFF are both strapped high. To
switch between active and powerdown modes, under logic
or software control, only the FORCEOFF input need be
driven. The FORCEON state isn’t critical, as FORCEOFF
dominates over FORCEON. Nevertheless, if strictly manual
control over powerdown is desired, the user must strap
FORCEON high to disable the automatic powerdown
circuitry. ICL3243 inverting (standard) receiver outputs also
disable when the device is in manual powerdown, thereby
eliminating the possible current path through a shutdown
peripheral’s input protection diode (See Figures 2 and 3).
TABLE 2. POWERDOWN AND ENABLE LOGIC TRUTH TABLE
RS-232
SIGNAL
PRESENT
AT
RECEIVER
INPUT?
FORCEOFF
OR SHDN
INPUT
FORCEON
INPUT
EN
INPUT
TRANSMITTER
OUTPUTS
RECEIVER
OUTPUTS
(NOTE 4)
ROUTB
OUTPUTS
INVALID
OUTPUT MODE OF OPERATION
ICL3222, ICL3241
N.A. L N.A. L High-Z Active Active N.A. Manual Powerdown
N.A. L N.A. H High-Z High-Z Active N.A. Manual Powerdown w/Rcvr. Disabled
N.A. H N.A. L Active Active Active N.A. Normal Operation
N.A. H N.A. H Active High-Z Active N.A. Normal Operation w/Rcvr. Disabled
ICL3221, ICL3223
No H H L Active Active N.A. L Normal Operation
(Auto Powerdown Disabled)
No H H H Active High-Z N.A. L
Yes H L L Active Active N.A. H Normal Operation
(Auto Powerdown Enabled)
Yes H L H Active High-Z N.A. H
No H L L High-Z Active N.A. L Powerdown Due to Auto Powerdown
Logic
No H L H High-Z High-Z N.A. L
Yes L X L High-Z Active N.A. H Manual Powerdown
Yes L X H High-Z High-Z N.A. H Manual Powerdown w/Rcvr. Disabled
No L X L High-Z Active N.A. L Manual Powerdown
No L X H High-Z High-Z N.A. L Manual Powerdown w/Rcvr. Disabled
ICL3243
No H H N.A. Active Active Active L Normal Operation
(Auto Powerdown Disabled)
Yes H L N.A. Active Active Active H Normal Operation
(Auto Powerdown Enabled)
No H L N.A. High-Z Active Active L Powerdown Due to Auto Powerdown
Logic
Yes L X N.A. High-Z High-Z Active H Manual Powerdown
No L X N.A. High-Z High-Z Active L Manual Powerdown
NOTE:
4. Applies only to the ICL3241 and ICL3243.
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
12 FN4805.21
March 1, 2006
The INVALID output always indicates whether or not a valid
RS-232 signal is present at any of the receiver inputs (See
Table 2), giving the user an easy way to determine when the
interface block should power down. In the case of a
disconnected interface cable where all the receiver inputs
are floating (but pulled to GND by the internal receiver pull
down resistors), the INVALID logic detects the invalid levels
and drives the output low. The power management logic
then uses this indicator to power down the interface block.
Reconnecting the cable restores valid levels at the receiver
inputs, INVALID switches high, and the power management
logic wakes up the interface block. INVALID can also be
used to indicate the DTR or RING INDICATOR signal, as
long as the other receiver inputs are floating, or driven to
GND (as in the case of a powered down driver). Connecting
FORCEOFF and FORCEON together disables the
automatic powerdown feature, enabling them to function as
a manual SHUTDOWN input (See Figure 4).
With any of the above control schemes, the time required to
exit powerdown, and resume transmission is only 100µs. A
mouse, or other application, may need more time to wake up
from shutdown. If automatic powerdown is being utilized, the
RS-232 device will reenter powerdown if valid receiver levels
aren’t reestablished within 30µs of the ICL32XX powering
up. Figure 5 illustrates a circuit that keeps the ICL32XX from
initiating automatic powerdown for 100ms after powering up.
This gives the slow-to-wake peripheral circuit time to
reestablish valid RS-232 output levels.
Automatic Powerdown (ICL3221/23/43 Only)
Even greater power savings is available by using the
devices which feature an automatic powerdown function.
When no valid RS-232 voltages (See Figure 6) are sensed
on any receiver input for 30µs, the charge pump and
transmitters powerdown, thereby reducing supply current to
1µA. Invalid receiver levels occur whenever the driving
peripheral’s outputs are shut off (powered down) or when the
RS-232 interface cable is disconnected. The ICL32XX
powers back up whenever it detects a valid RS-232 voltage
level on any receiver input. This automatic powerdown
feature provides additional system power savings without
changes to the existing operating system.
FIGURE 2. POWER DRAIN THROUGH POWERED DOWN
PERIPHERAL
OLD
VCC
POWERED
GND SHDN = GND
VCC
Rx
Tx
VCC
CURRENT
VOUT = VCC
FLOW
RS-232 CHIP
DOWN
UART
FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN
ICL324X
TRANSITION
RX
TX
R2OUTB
R2OUT
T1IN
FORCEOFF = GND
VCC
VCC
TO
R2IN
T1OUT
VOUT = HI-Z
POWERED
OR SHDN = GND, EN = VCC
DETECTOR
DOWN
UART
WAKE-UP
LOGIC
FIGURE 4. CONNECTIONS FOR MANUAL POWERDOWN
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
PWR
FORCEOFF
INVALID
CPU
I/O
FORCEON
ICL3221/23/43
MGT
LOGIC
UART
FIGURE 5. CIRCUIT TO PREVENT AUTO POWERDOWN FOR
100ms AFTER FORCED POWERUP
ICL3221/23/43
FORCEOFF FORCEON
POWER MASTER POWERDOWN LINE
1MΩ
0.1µF
MANAGEMENT
UNIT
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
13 FN4805.21
March 1, 2006
Automatic powerdown operates when the FORCEON input
is low, and the FORCEOFF input is high. Tying FORCEON
high disables automatic powerdown, but manual powerdown
is always available via the overriding FORCEOFF input.
Table 2 summarizes the automatic powerdown functionality.
Devices with the automatic powerdown feature include an
INVALID output signal, which switches low to indicate that
invalid levels have persisted on all of the receiver inputs for
more than 30µs (See Figure 7). INVALID switches high 1µs
after detecting a valid RS-232 level on a receiver input.
INVALID operates in all modes (forced or automatic
powerdown, or forced on), so it is also useful for systems
employing manual powerdown circuitry. When automatic
powerdown is utilized, INVALID = 0 indicates that the
ICL32XX is in powerdown mode.
The time to recover from automatic powerdown mode is
typically 100µs.
Receiver ENABLE Control (ICL3221/22/23/41 Only)
Several devices also feature an EN input to control the
receiver outputs. Driving EN high disables all the inverting
(standard) receiver outputs placing them in a high
impedance state. This is useful to eliminate supply current,
due to a receiver output forward biasing the protection diode,
when driving the input of a powered down (VCC = GND)
peripheral (See Figure 2). The enable input has no effect on
transmitter nor monitor (ROUTB) outputs.
Capacitor Selection
The charge pumps require 0.1µF capacitors for 3.3V
operation. For other supply voltages refer to Table 3 for
capacitor values. Do not use values smaller than those listed
in Table 3. Increasing the capacitor values (by a factor of 2)
reduces ripple on the transmitter outputs and slightly
reduces power consumption. C2, C3, and C4 can be
increased without increasing C1’s value, however, do not
increase C1 without also increasing C2, C3, and C4 to
maintain the proper ratios (C1 to the other capacitors).
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the
amount of ripple on V+ and V-.
Power Supply Decoupling
In most circumstances a 0.1µF bypass capacitor is
adequate. In applications that are particularly sensitive to
power supply noise, decouple VCC to ground with a
capacitor of the same value as the charge-pump capacitor C1.
Connect the bypass capacitor as close as possible to the IC.
Operation Down to 2.7V
ICL32XX transmitter outputs meet RS-562 levels (±3.7V), at
full data rate, with VCC as low as 2.7V. RS-562 levels
typically ensure interoperability with RS-232 devices.
Transmitter Outputs when Exiting
Powerdown
Figure 8 shows the response of two transmitter outputs
when exiting powerdown mode. As they activate, the two
transmitter outputs properly go to opposite RS-232 levels,
with no glitching, ringing, nor undesirable transients. Each
transmitter is loaded with 3kΩ in parallel with 2500pF. Note
that the transmitters enable only when the magnitude of the
supplies exceed approximately 3V.
FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS
0.3V
-0.3V
-2.7V
2.7V
INVALID LEVEL - POWERDOWN OCCURS AFTER 30ms
VALID RS-232 LEVEL - ICL32XX IS ACTIVE
VALID RS-232 LEVEL - ICL32XX IS ACTIVE
INDETERMINATE - POWERDOWN MAY OR
INDETERMINATE - POWERDOWN MAY OR
MAY NOT OCCUR
MAY NOT OCCUR
RECEIVER
INPUTS
TRANSMITTER
OUTPUTS
INVALID
OUTPUT
V+
VCC
0
V-
VCC
0
tINVL tINVH
INVALID
REGION
}
FIGURE 7. AUTOMATIC POWERDOWN AND INVALID
TIMING DIAGRAMS
AUTOPWDN PWR UP
TABLE 3. REQUIRED CAPACITOR VALUES
VCC
(V)
C1
(µF)
C2, C3, C4
(µF)
3.0 to 3.6 0.1 0.1
4.5 to 5.5 0.047 0.33
3.0 to 5.5 0.1 0.47
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
14 FN4805.21
March 1, 2006
Mouse Driveability
The ICL324X have been specifically designed to power a
serial mouse while operating from low voltage supplies.
Figure 9 shows the transmitter output voltages under
increasing load current. The on-chip switching regulator
ensures the transmitters will supply at least ±5V during worst
case conditions (15mA for paralleled V+ transmitters, 7.3mA
for single V- transmitter). The Automatic Powerdown feature
does not work with a mouse, so FORCEOFF and
FORCEON should be connected to VCC.
High Data Rates
The ICL32XX maintain the RS-232 ±5V minimum transmitter
output voltages even at high data rates. Figure 10 details a
transmitter loopback test circuit, and Figure 11 illustrates the
loopback test result at 120kbps. For this test, all transmitters
were simultaneously driving RS-232 loads in parallel with
1000pF, at 120kbps. Figure 12 shows the loopback results
for a single transmitter driving 1000pF and an RS-232 load
at 250kbps. The static transmitters were also loaded with an
RS-232 receiver.
TIME (20µs/DIV)
T1
T2
2V/DIV
5V/DIV
VCC = +3.3V
FORCEOFF
FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING
POWERDOWN
C1 - C4 = 0.1µF
FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CURRENT (PER TRANSMITTER, i.e., DOUBLE
CURRENT AXIS FOR TOTAL VOUT+ CURRENT)
TRANSMITTER OUTPUT VOLTAGE (V)
LOAD CURRENT PER TRANSMITTER (mA)
0246810
-6
-4
-2
0
2
4
6
-5
-3
-1
1
3
5
13579
VOUT+
VOUT -
VCC
VOUT+
VOUT -
T1
T2
T3
VCC = 3.0V
ICL3241/43
FIGURE 10. TRANSMITTER LOOPBACK TEST CIRCUIT
FIGURE 11. LOOPBACK TEST AT 120kbps
FIGURE 12. LOOPBACK TEST AT 250kbps
ICL32XX
VCC FORCEOFF
C1
C2C4
C3
+
+
+
+
1000pF
V+
V-
5K
TIN
ROUT
C1+
C1-
C2+
C2-
RIN
TOUT
+
VCC
0.1µF
VCC
EN
SHDN OR
T1IN
T1OUT
R1OUT
5µs/DIV
VCC = +3.3V
5V/DIV
C1 - C4 = 0.1µF
T1IN
T1OUT
R1OUT
2µs/DIV.
5V/DIV.
VCC = +3.3V
C1 - C4 = 0.1µF
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
15 FN4805.21
March 1, 2006
Interconnection with 3V and 5V Logic
The ICL32XX directly interface with 5V CMOS and TTL logic
families. Nevertheless, with the ICL32XX at 3.3V, and the
logic supply at 5V, AC, HC, and CD4000 outputs can drive
ICL32XX inputs, but ICL32XX outputs do not reach the
minimum VIH for these logic families. See Table 4 for more
information.
TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
SYSTEM
POWER-SUPPLY
VOLTAGE
(V)
VCC
SUPPLY
VOLTAGE
(V) COMPATIBILITY
3.3 3.3 Compatible with all CMOS
families.
5 5 Compatible with all TTL and
CMOS logic families.
5 3.3 Compatible with ACT and HCT
CMOS, and with TTL. ICL32XX
outputs are incompatible with AC,
HC, and CD4000 CMOS inputs.
Typical Performance Curves VCC = 3.3V, TA = 25°C
FIGURE 13. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
FIGURE 14. SLEW RATE vs LOAD CAPACITANCE
FIGURE 15. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FIGURE 16. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
-6
-4
-2
0
2
4
6
1000 2000 3000 4000 50000
LOAD CAPACITANCE (pF)
TRANSMITTER OUTPUT VOLTAGE (V)
1 TRANSMITTER AT 250kbps
VOUT+
VOUT -
1 OR 2 TRANSMITTERS AT 30kbps
LOAD CAPACITANCE (pF)
SLEW RATE (V/µs)
0 1000 2000 3000 4000 5000
5
10
15
20
25
+SLEW
-SLEW
0
5
10
15
20
25
30
45
35
40
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
20kbps
250kbps
120kbps
ICL3221
0
5
10
15
20
25
30
45
35
40
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
20kbps
250kbps
120kbps
ICL3222 - ICL3232
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
16 FN4805.21
March 1, 2006
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ICL3221: 286
ICL3222: 338
ICL3223: 357
ICL3232: 296
ICL324X: 464
PROCESS:
Si Gate CMOS
FIGURE 17. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE
Typical Performance Curves VCC = 3.3V, TA = 25°C (Continued)
0
5
10
15
20
25
30
45
35
40
01000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
20kbps
250kbps
120kbps
ICL324X
SUPPLY CURRENT (mA)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
0.5
1.0
1.5
2.0
SUPPLY VOLTAGE (V)
2.5
3.0
3.5 NO LOAD
ALL OUTPUTS STATIC
ICL3221 - ICL3232
ICL324X
ICL324X
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
17 FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N16 169
Rev. 0 12/93
18 FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3
may have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA
-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E18.3 (JEDEC MS-001-BC ISSUE D)
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.210 -5.33 4
A1 0.015 - 0.39 -4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.845 0.880 21.47 22.35 5
D1 0.005 -0.13 -5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB-0.430 -10.92 7
L 0.115 0.150 2.93 3.81 4
N18 18 9
Rev. 2 11/03
19 FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.3859 0.3937 9.80 10.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N16 167
α0° 8° 0° 8° -
Rev. 1 6/05
20 FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Thin Shrink Small Outline Plastic Packages (TSSOP)
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
0.05(0.002)
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.043 -1.10 -
A1 0.002 0.006 0.05 0.15 -
A2 0.033 0.037 0.85 0.95 -
b0.0075 0.012 0.19 0.30 9
c0.0035 0.008 0.09 0.20 -
D0.193 0.201 4.90 5.10 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E0.246 0.256 6.25 6.50 -
L0.020 0.028 0.50 0.70 6
N16 167
α0o8o0o8o-
Rev. 1 2/02
21 FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Small Outline Plastic Packages (SSOP)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimen-
sion at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H0.25(0.010) BM M
α
0.25
0.010
GAUGE
PLANE
A2
M16.209 (JEDEC MO-150-AC ISSUE B)
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.233 0.255 5.90 6.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N16 167
α0° 8° 0° 8° -
Rev. 3 6/05
22 FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M16.3 (JEDEC MS-013-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.3977 0.4133 10.10 10.50 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N16 167
α0° 8° 0° 8° -
Rev. 1 6/05
23 FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M18.3 (JEDEC MS-013-AB ISSUE C)
18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.4469 0.4625 11.35 11.75 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N18 187
α0° 8° 0° 8° -
Rev. 1 6/05
24 FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004) c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M20.173
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.051 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.252 0.260 6.40 6.60 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N20 207
α0o8o0o8o-
Rev. 1 6/98
25 FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Shrink Small Outline Plastic Packages (SSOP)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
α
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C A
MBS
e
-A-
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H0.25(0.010) B
MM
L
0.25
0.010
GAUGE
PLANE
A2
M20.209 (JEDEC MO-150-AE ISSUE B)
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A0.068 0.078 1.73 1.99
A1 0.002 0.008’ 0.05 0.21
A2 0.066 0.070’ 1.68 1.78
B0.010’ 0.015 0.25 0.38 9
C0.004 0.008 0.09 0.20’
D0.278 0.289 7.07 7.33 3
E0.205 0.212 5.20’ 5.38 4
e 0.026 BSC 0.65 BSC
H0.301 0.311 7.65 7.90’
L0.025 0.037 0.63 0.95 6
N20 207
α0 deg. 8 deg. 0 deg. 8 deg.
Rev. 3 11/02
26 FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AE, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M28.173
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.047 -1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.051 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.378 0.386 9.60 9.80 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N28 287
α0o8o0o8o-
Rev. 0 6/98
27 FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Shrink Small Outline Plastic Packages (SSOP)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess of
“B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H0.25(0.010) BM M
α
0.25
0.010
GAUGE
PLANE
A2
M28.209 (JEDEC MO-150-AH ISSUE B)
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.390 0.413 9.90 10.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N28 287
α0° 8° 0° 8° -
Rev. 2 6/05
28
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4805.21
March 1, 2006
ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243
Small Outline Plastic Packages (SOIC)
α
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H0.25(0.010) BM M
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.6969 0.7125 17.70 18.10 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.01 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N28 287
α0o8o0o8o-
Rev. 0 12/93
