fax id: 5421 CY7C4261V CY7C4271V a SF oor Sc PRELIMINARY 16K/32Kx9 Low Voltage Deep Sync FIFOs Features * 3.3V operation for low power consumption and easy integration into low voitage systems * High-speed, low-power, first-in first-out (FIFO) memories 16K x 9 (CY7C4261V) * 32K x 9 (CY7C4271V) * 0.5 micron CMOS for optimum speed/power * High-speed 67-MHz operation (15 ns read/write cycle times) Low power lecg220 mA Igg=2 mA * Fully asynchronous and simultaneous read and write operation Empty, Full, Half Full, and programmable Almest Empty and Almost Full status flags * Output Enable (OE) pin Independent read and write enable pins * Supports free-running 50% duty cycle clock inputs * Width Expansion Capability * 32-pin PLCC * Pin-compatibie density upgrade from CY7C42X1V family * Pin-compatible 3.3V solution for CY7C4261/71 Functional Description The CY7C4261V/71V are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfac- es. All are 9 bits wide. The CY7C4261V/71V are pin-compati- ble to the CY7C42X1V Synchronous FIFO family. The CY7C4261V/71V can be cascaded to increase FIFO width. Programmable features include Aimost Ful/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buff- ering needs, including high-speed data acquisition, multiprocessor in- terfaces, and communications buffering. These FIFOs have 9-bit input and output ports that are con- trolled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and two write-en- able pins (WENT, WEN2AD). When WENT is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WENT, WEN2/ALD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a free-run- ning read clock (RCL) and two read enable pins (RENT, RENZ). in addition, the CY7C4261V/71V has an output enable pin (OE). The tead (RCLK) and write (WCLK) clocks may be tied together for sin- gle-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Depth expansion is possible using one en- able input for system control, while the other enable is con- trolied by expansion logic to direct the flow of data. Logic Biock Diagram Po. 8 . , ; Pin Configuration INPUT, EGISTER WCLK WENT WEN2/CD PLCC | GAS Top View | | PROGRAM Adah aaS REGISTER aD CONTROL [7 \Z v Tor EF e FLAG = fm PAE eo LOGIC Hi PAF WEN2ED FE RAM ARRAY 16Kx9 WATE 32K x9 READ POINTER POINTER e e TOE RESET RE LOGIC THREE-STATE READ OUTPUT REGISTER CONTROL 4261V-2 4261V-1 itt RCLK RENT RENZ For the most recent information, visit the Cypress web site at www.cypress.com 2-51 -PRELIMINARY CYPRESS CY7C4261V CY7C4271V Functional Description (continued) The CY7C4261V/71V provides four status pins: Empty, Full, Pro- grammable Aimost Empty, and Programmable Almost Full. The At most Empty/Almost Full flags are programmable to single word gran- ulatity. The programmable flags default to Empty+7 and Fult7. The flags are synchronous, i.e., they change state relative to either the read clock (RCLK) or the write clock (WCLK). When entering or exiting the Empty and Almost Empty states, the Selection Guide Current (loc) (mA) CY7C4261V CY7C4271V Density 16K x9 32K x9 Package 32-pin PLCC 32-pin PLCC Maximum Ratings {Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature oo... ce eee eres -65C ta +150C Ambient jemperature t with Power Appiied... vs Supply Voltage to Ground Potential... DC Voitage Applied to Outputs in High Z State... veneeees . ~B5C to +126C 7 O.5V to +3.3V wu O.5V to Veg+0.5V flags are updated exclusively by the RCLK. The flags denoting Almost Full, and Full states are updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags maintain their status for at least one cycle. All configurations are fabricated using an advanced 0.5y CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. 25 DC Input Voltage oo... cette renee ~0.5V to Vect+0.5V Output Current into Outputs (LOW)... eee 20 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) Latch-Up Current... eee rseenereenrene tetas >200 mA Operating Range Ambient Range Temperature Vec Commercial OC to +70C 3.3V +300mV and -600mV industrial 40C to +85C 3.3V + 300mV and -600mV 2-52CY7C4261V CYPRESS PRELIMINARY CY7C4271V Pin Definitions Signal Name | Description | VO Description Do.g Data Inputs | | Data Inputs for 9-bit bus. Qo Data Outputs | Data Outputs for 9-bit bus. WENT Write Enable 1 1! | The only write enable when device is configured to have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when WENT is asserted and FF is HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition of WCLK when WENT is LOW and WEN2/CD and FF are HIGH. WEN2/ED Write Enable 2 1 | If HIGH at reset, this pin operates as a second write enable. !f LOW at reset, this pin Dual Mode Pin Toaq operates as a control to write or read the programmable flag offsets. WENT must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW fo write or read the programmabie flag offsets. RENT, REN2 | Read Enable | | Enables the device for Read operation. Both RENT and REN2 must be asserted to Inputs allow a read operation. WCLK Write Clock ! | The rising edge clocks data into the FIFO when WENT is LOW and WEN2/LD is HIGH ey and the FIFO is not Full. When CD is asserted, WCLK writes data into the programmable flag-off- set register. RCLK Read Clock (| The rising edge clocks data out of the FIFO when RENT and RENZ are LOW and the FiFO | is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-oftset tagister. EF Empty Flag O | When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. FF Full Flag | When FF is LOW, the FIFO is full. FF is synchronized to WCLK. PAE Programmable | O | When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro- Almost Empty grammed into the FIFO. PAE is synchronized to RCLK. PAF Programmable | O | When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed Almost Full into the FIFO, PAF is synchronized to WCLK. RS Reset | | Resets device ta empty condition. A reset is required before an initial read or write operation after power-up. OE Output Enable | | When OE is LOW, the FIFOs data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO's outputs are in High Z (high-impedance) state. Electrical Characteristics Over the Operating Rangel"! ' 704261V/71V-15 7C4261V/71V-25 Parameter Description Test Conditions Min. Max. Min. Max. Unit Vou Output HIGH Voltage Voc = Min.. 2.4 24 Vv lo =-2.0 MA Vor Output LOW Voltage Voc = Min., 0.4 0.4 Vv Io, = 8.0 mA Vin input HIGH Voltage 2.0 Voc 2.0 Vee v Vin Input LOW Voltage -0.5 0.8 ~0.5 0.8 Vv lx Input Leakage Current Voc = Max. -10 +10 ~-10 +10 pA loz Output OFF, OE = Vin, -10 +10 ~10 +10 uA lozy High Z Current Vss < Vo< Voc log4 Active Power Supply Com! 20 20 mA Current ind 25 mA Iga! Average Standby Current Com'i 2 mA ind i mA Notes: 1. See the last page of this specification for Group A subgroup testing information. 2. Input signals switch from OV to 3V with a rise/lall time of fess than 3 ns, clocks and clock enables switch at maximum frequency 20Mhz, while data inputs switch . are unloaded. 3. All inputs = Voco0.2V, except WCLK and RCLK (which are switching at frequency = 20 MHz), All outputs are unloaded 2-53CY7C4261V PRELIMINARY CY7C4271V CYPRESS Capacitance! Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f= 1 MHz, 5 pF Cour Output Capacitance Voc =3.3V 7 pF AC Test Loads and Waveforms4 A1=3309 33V e wr, ALL INPUT PULSES OUTPU , 3.0V c. R2=680Q GND INCLUDING ate JIG AND ~ ~ SCOPE 4261V-4 4261V-5 Equivaient to: THEVENIN EQUIVALENT 200 2 OUTPUT o_wy 6 2.0 Notes: 4. Tested initially and after any design or process changes that may affect these parameters. 5. , =30pF for all AC 1S @XCOPH FOF Top2. 6. CL =5pF tortyyg.CY7C4261V L CYPRESS PRELIMINARY CY7C4271V Switching Characteristics Over the Operating Range 704261 V/71V-15 7C4261V/71V-25 Parameter Description Min. Max. Min. Max. Unit ts Clock Cycle Frequency 66.7 40 MHz ta Data Access Time 2 10 2 15 ns toux Clock Cycle Time 15 25 ns toLKH Clock HIGH Time 6 10 ns touKL Clock LOW Time 6 10 ns tos Data Set-Up Time 4 6 ns tox Data Hold Time 0 1 ns tens Enable Set-Up Time 4 6 ns teny Enable Hold Time 0 1 ns tas Reset Pulse Width!] 15 25 ns 2 tass Reset Set-Up Time 10 15 ns tasr Reset Recovery Time 10 15 ns tasr Reset to Flag and Output Time 15 25 ns towz Output Enable to Output in Low z@] 0 0 ns toe Output Enable to Output Valid 3 8 3 12 ns tow Output Enable to Output in High 2! 3 8 3 12 ns twee Write Clock to Full Flag 10 415 ns trer Read Clock to Empty Flag 10 15 ns tpar Clock to Programmable Almost-Full Flag 10 15 ns trae Clock to Programmable Almost-Full Flag 10 15 ns toxewt Skew Time between Read Clock and Write Clock for 6 10 ns Empty Flag and Full Flag texewe Skew Time between Read Clock and Write Ciock for 15 18 ns Almost-Empty Flag and Almost-Full Flag Notes: 7. Pulse widths less than minimum values are not allowed. 8, Values guaranteed by design, not currently tested. 2-55S- CY7C4261V PRELIMINARY Woy PRESS CY7C4271V Switching Waveforms Write Cycle Timing WCLK Do-Dy7 WENT NO OPERATION NO OPERATION WEN2 (if applicable) FF were 9 tgxews RCLK RENT, RENZ f Read Cycle Timing 4261V-6 teKL teLKH RCLK tenn RENT, REN? NO OPERATION EF Qo -Qiz VALID DATA 4 tskewt 9 WCLK ren \ WEN2 f/ 4261V-7 Notes: 9. tgxews is the minimum time between a rising RCL edge and a tising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. if the time between the rising edge of RCLK and the rising edge of WCLK is less than tgcew. then PF may not change state until the next WCLK rising edge. 10. tga; is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. {t the time between the rising edge of WCLK and the rising edge of RCLK is less than toxewe, then EF may not change state until the next RCLK rising edge. 2-56CY7C4261V j PRELIMINARY CYPRESS CY7C4271V Switching Waveforms (continued) Reset Timing!"! RS WEN2/LD (3! EF,PAE FF. PAF Qo. Qs OE. 0 4261V-3 Notes: 41. The clocks (RCLK, WCLI) can be free-running during reset. 12. Alter reset, the outputs will be LOW if GE = 0 and three-state if DE=1. 13. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/(D LOW during reset will make the pin act as a joad enable for the programmable fiag offsat registers,CY7C4261V IMINARY CYPRESS PRELIMIN CY7C4271V Switching Waveforms (continued) First Data Word Latency after Reset with Read and Write WCLK O09 ~Dg (FIRST VALIO WRITE) WENT ten '4! WEN2 (if applicable) RCLK EF a tit) REN2 oo SEXO toiz toe OE * A2B1V~9 Notes: 14, When texew: 2 minimum specification, tea, (maximum) = toy k + lgxewe- When toeywe < minimum specification, tea, (maximum) = either 2"touK + tgxews OF teLK + texewn- The Latency Timing applies only at the Empty Boundary (EF = LOW). 15. The first word is available the cycle after EF goes HIGH, always.CY7C4261V CY7C4271V Pen. 5s PRELIMINARY Switching Waveforms (continued) Empty Flag Timing WCLK Dy -Dg tos barawnrte xX KKK KR DATA WRITE 2 xXx XX teNH Sk tens tens tENH WEN2 (if applicabley NRK RCLK _/f| 4) gl [_ ter } ! ~ | tens J ENH 114] (< 'rac NS I~ tsxews tRer trer toxews EF RENT, RENZ LOW OE ty m Qo Qg DATA IN OUTPUT REGISTER DATA READ 4261V-10 2-59 ay aCY7C4261V PRELIMINARY : CYPRESS CY7C4271V Switching Waveforms (continued) Full Flag Timing NO WRITE NO WRITE WCLK / \ 7 oN iskews?) tps texewr! DATA WRITE ~ DATA WRITE 0 XXKAXK 3 twer > | I twee twee FF x i WENT o WEN2 (if applicable) rx NANNY NON <-> tENH teny FIENT, tens tens RENZ OE LOW bx- ig ta Qo -Og DATA IN OUTPUT REGISTER DATA READ NEXT DATA READ 4261V-11 Programmable Almost Empty Flag Timing toLKH fouKL wou PONY NY NZ N tens | tenn WENT L/S WEN2 (if applicable) JL tA N \. tens | tenn Note PAE 17 N+ 1 WORDS IN FIFO Note 18 5, 16] AE teskews RCLK tens | tenn VY RENT, NS T GA REND KA 4261V-12 Notes: 16. tgxeywo is the minimum time Detween a rising WCLK and a rising RCLK edge fon PAE to change state during that clock cycie. If the time between the edge of WCLK and the nro ACK: is less than tsxeyp, then PAE may not change state until the next RCLK 47. PAE offset=n. 18. Hareadis preformed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOWCY7C4261V PRELIMINARY CY7C4271V CYPRESS Switching Waveforms (continuec) Programmable Almost Full Flag Timing . " Note ICLKH foLKL 19 WCLK ON ANN IN fen NH me IS. (it appiteable) SL/L TAA Notel20 tens } tenn e tpar FULL - MWORDS PAF FULL ~(M+1)WORDS IN FIFOR IN FIFO tsxews 72! tear 5 RCL NAN YAN YN KY NY \ 7 tens tens | tena REN, " ie if REN2 KR A 4261V-13 Write Programmable Registers e tor. a] teLKH je foLkL welk A MN NANT NV tens ten wets NS L222 tens fe WEN N tos tou PAE OFFSET PAE OFFSET PAF OFFSET PAF OFFSET LSB MSB LSB MSB 4261V-14 Notes: 19. if a write is performed on this rising edge of the write clock, there will be Full (m1} words of the FIFO when PAF goes LOW. 20. PAF offset = m. 21. 16,384 -m words for CY7C4261V, 32,768 ~ m words for CY4271V. 22. texewe is the minimum time between a rising ACLIK and a Tsing WCLIK edge for PAF to change during that Cock cycle. if the time between the rising edge of RCLK de rising edge of WCLKC is less than tayqeyyo. then PAF may not change state until the next WCLK. 2-61CY7C4261V PRELIMINARY 4 Ger: CY7C4271V Switching Waveforms (continued) Read Programmable Registers b< tore ] tcLKH } teuKL tens teNH WEN2/LD XXX Z eM. <7 PAF OFFSET REN2 K MSB, -<# ty O15 XK KK KX YK UNKNOWN y PAE OFFSET LSB X PAE OFFSET MSB 9X PAF Fae 4261V15 2-628 CYPRESS PRELIMINARY CY7C4261V CY7C4271V Architecture The CY7C4261V/71V consists of an array of 16K to 32K words of 9 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, RENT, REN2, WENT, WEN2, FS), and flags (EF PAE, PAF, N. Resetting the FIFO Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs (Qo_) go LOW tage after the rising edge of AS. in order for the FIFO to reset to its default state, a falling edge must occur on RS and the user must not read or write while FS is LOW. All flags are guaranteed to be valid tagr after RS is taken LOW. FIFO Operation When the WENT signal is active LOW, WEN2 is active HIGH, and FF is active HIGH, data present on the Dp_g pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the RENT and REN@ signals are active LOW and EF is active HIGH, data inthe FIFO memory will be presented on the Qg_g outputs. New data will be presented on each rising edge of RCLK while RENT and REN? are active. RENT and REN? must set up tes before RCLK for it to be a valid read function. WENT and WEN2 must occur tens before WCLK for it to be a valid write function. An output enable (OE) pin is provided to three-state the Qo_g out- puts when OE is asserted. When OE is enabled (LOW), data in the output register will be available to the Qo_., outputs after tog. If devic- es are cascaded, the OE function will only output data on the FIFO that is read enabled. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Qo_g outputs even after additional reads occur. Write Enable 1 (WENT) - If the FIFO is configured for pro- grammabie flags, Write Enable 1 (WENT) is the only write en- able control pin. In this configuration, when Write Enable { (WENT) is LOW, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored is the RAM array sequentially and in- dependently of any on-going read operation. Write Enable 2/Load (WEN2/LD) - This is a dual-purpose pin. The FIFO is configured at Reset to have programmable flags or to have two write enabies, which allows for depth expansion. If Write Enable 2/Load (WEN2/LD) is set active HIGH at Reset (RS=LOW), this pin operates as a second write enable pin. If the FIFO is configured to have two write enables, when Write Enable 1 (WEN7) is LOW and Write Enable 2/Load (WEN2/LD) is HIGH, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is storedin the RAM array sequentially and independently of any on-qo- ing read operation. Programming When WEN2/LD is held LOW during Reset, this pin is the load (CD) enable for flag offset programming. in this configuration, WEN2/LD can be used to access the four 8-bit offset registers contained in the CY7C4261V/71V for writing or reading data to these registers. When the device is configured for programmable flags and both WEN2/LD and WENT are LOW, the first LOW-to-HIGH transi- tion of WCLK writes data from the data inputs to the empty offset least significant bit (LSB) register The second, third, and fourth LOW-to-HIGH transitions of WCLK store data in the empty offset mast significant bt (MSB) register, full offset LSB register, and full offset MSB register, respectively, when WEN2/LD and WENT are LOW. The fifth LOW-to-HIGH transition of WCLK while WEN2/-D and WENT are LOW writes data to the empty LSB register again. Figure 1 shows the registers sizes and default values for the various device types. 16K x9 32K x9 Z 0 8 7 0 8 Empty Offset (LSB) Reg. Default Vaiue= 007h 8 5 0 8 6 0 8 7 0 Empty Offset (LSB) Reg Oefauit Value= 007h (MSB) 900000 (MSB) oo0o0da 7 0 Full Offset (LSB) Reg Default Value= 007h Fuil Offset (LS8) Reg Defautt Value= O07h f Y 4261V-16 Figure 1. Offset Register Location and Default Values - Sp 8 5 0 {MSB) 900000 6 0 (MSB) 000000 Itis not necessary to write to all the offset registers at one time. A subset of the offset registers can be written; then by bringing the WEN2/LD input HIGH, the FIFO is returned to normal read and write operation. The next time WEN2/LD is brought LOW, a write op- eration stores data in the next offset register in sequence. The contents of the offset registers can be read to the data outputs when WEN2/CD is LOW and both RENT and REN2 are LOW. LOW-to-HIGH transitions of RCLK read register contents to the data outputs. Writes and reads should not be performed simulta- neously on the offset registers. Programmable Flag (PAE, PAF) Operation Whether the flag offset registers are programmed as de- scribed in Table 7 or the default values are used, the programmable almost-empty flag (PAE) and programmable almost-full flag (PAF) states are determined by their corresponding offset registers and the difference between the read and write pointers.CY7C4261V CYPRESS PRELIMINARY CY7C4271V Table 1. Writing the Offset Registers. The number formed by the empty offset least significant bit register and empty offset most significant bit register is re- CD | WER | weik@l Selection ferred to as nand determines the operation of PAE. PAF is synchro- nized to the LOW-to-HIGH transition of RCLK by one flip-flop and is o 0 Empty Offset (LSB) < LOW when the FIFO contains n or fewer unread words. PAE is set f Empty Offset (MSB) HIGH by the LOW-to-HIGH transition of RCLK when the FIFO con- Full Offset (LSB) tains (n+1) or greater unread words. Fuil Offset (MSB) _ The number formed by the full offset least significant bit regis- ter and full offset most significant bit register is referred to as 0 4 No Operation mand determines the operation of PAF. PAE is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal 1 0 Write Into FIFO to CY7C4261V (16K m) and CY7C4271V (32K m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m. 1 1 - No Operation Table 2. Status Flags Number of Words in FIFO CY7C4261V CY7C4271V FF PAF PAE EF 0 0 H H L L 1 to ne) 1to net H H L H (n+14) to (16384 (m+1)) (n+1) to (32768 - (m+1)) H H H H (16384 m)5l to 16383 (32768 m)!?5l to 32767 H L H H 16384 32768 L L H H Notes: 24, n= Empty Offset (n=7 default value). 25, m= Full Offset (m=7 default value). 2-64 23. The same selection sequence anpias to reading from the registers. RENT and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.SPs Cypress PRELIMINARY CY7C4261V CY7C4271V Width Expansion Configuration Word width may be increased simply by connecting the corre- sponding input controls signals of multiple devices. A compos- ite flag should be created for each of the end-point status flags (EF and FF). The partial status flags (PAE and PAF) cari be detected from any one device. Figure 2 demonstrates a 18-bit word width by using two CY7C4261V/71Vs. Any word width can be attained by add- ing additional CY7C4261V/71Vs. When the CY7C4261V/71V is in a Width Expansion Configu- ration, the Read Enable (RENZ2) control input can be grounded (See Figure 2. in this configuration, the Write Enable 2/Load (WEN2/CD) pin is set to LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets. Flag Operation The CY7C4261V/71V devices provide five flag pins to indicate the condition of the FIFO contents. Empty, Full, PAE, and PAF are synchronous. Full Flag The Full Flag (FF) will go LOW when the device is full. Write opera- tions are inhibited whenever FF is LOW regardless of the state of WENT and WEN2/D. FF is synchronized to WCLK, i.e., it is exclu sively updated by each rising edge of WCLK. Empty Flag The Empty Fiag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of RENT and RENZ. EF is synchronized to RCLK, i.e., itis exclusively updated by each rising edge of RCLK. RESET (RS) RESET (RS) DATAIN(D) ig, | 9, 3 7~T READ CLOCK (RCLK) WRITECLOCK (WCLK) TCAD ENABLE WRITE ENABLE 1(WENT) (RENT) WRITE ENABLE 2/.OAD OUTPUT ENABLE (OE) (WEN2/LD) PROGRAMMABLE(PAE) CY7C4261V/71V CY7C4261V/71V EMPTY FLAG (EF) #1 PROGRAMMABLE(PAF) EMPTY FLAG (EF) #2 FULL FLAG (FF) # 4 ee er EF, l - FF EF 9 , DATAOUT(Q) 19, _ FULL FLAG (FF) # 2 } / 18, c Read Enable 2 (REN2) { Read Enable 2 (REN2) 4263V-17 Figure 2. Block Diagram of 16K x 18/32K x 18 Low Voltage Deep Sync FIFO Memory Used in a Width Expansion Configuration 2-65a CY7C4261V PRELIMINARY CYPRESS CY7C4271V 16Kx9 Low Voltage Deep Sync FIFO ) Ordering Code 5 7 32Kx9 Low Voltage Deep Sync FIFO ) Ordering Code Document #: 38-00655 2-66